4MC68040V PRODUCT INFORMATION MOTOROLA
INTEGER UNIT
The integer unit, which conducts logical and arithmetic operations on the MC68040V, contains a six-stage
integer execution pipeline. The pipeline allows the handling of six separate instructions simultaneously. The
pipeline contains special shadow registers that can begin processing future instructions for conditional
branches while the main pipeline is processing current instructions. This minimizes latency in the change of
instruction flow, improving branch performance. The six stages of the pipeline are:
1. Instruction Fetch—Fetching an instruction from memory.
2. Decode—Converting an instruction into micro-instructions.
3. Effective Address <ea> Calculate—If the instruction calls for data from memory, the location of the
data is calculated.
4. Effective Address <ea> Fetch—Data is fetched from memory.
5. Execute—The data is manipulated during execution.
6. Write-Back—The result of the computation is written back to on-chip caches or external memory.
The write-back stage holds the operand until the opportune moment when no data fetches are required. The
write-back can defer writes indefinitely until either the data memory unit is free or another write is pending
from the execution stage. Holding the data in the write-back stage maximizes system performance by not
interrupting the incoming instruction or data stream.
MEMORY MANAGEMENT UNITS
The MC68040V contains independent instruction and data MMUs. Each MMU contains a 64-entry address
translation cache (ATC) used to keep the most recently used translation. The full addressing range of the
MC68040V is 4 Gbytes (4,294,967,296 bytes). Most MC68040V systems implement a much smaller
physical memory, but by using virtual memory techniques, the system can appear to have a full
4 Gbytes of physical memory available to each user program. Each MMU fully supports demand-paged
virtual-memory operating systems with either 4- or 8-Kbyte page sizes. Each MMU protects supervisor areas
from accesses by user programs and also provides write protection on a page-by-page basis. For maximum
efficiency, each MMU operates in parallel with other processor activities. The MMUs can be disabled for
emulator and debugging support.
ADDRESS TRANSLATION
The ATCs store recently used logical-to-physical address translation information, as page descriptors, for
instruction and data accesses. These caches are 64-entry, four-way, set-associative. Each MMU initiates
address translation by searching for a descriptor containing the address translation information in the ATC. If
the descriptor does not reside in the ATC, the MMU performs external bus cycles through the bus controller
to search the translation tables in physical memory. After being located, the page descriptor is loaded into
the ATC, and the address is correctly translated for the access.
TRANSPARENT TRANSLATION
Four transparent translation registers, two each for instruction and data accesses, are provided on the
MC68LC040 MMU to allow portions of the logical address space to be transparently mapped and accessed
without the need for corresponding entries resident in the ATC. Each register can be used to define a range
of logical addresses from 16 Mbytes to 4 Gbytes with a base address and a mask. All addresses within
these ranges are not mapped and are optionally protected against user or supervisor accesses and write
accesses. Logical addresses in these areas become the physical addresses for memory access. The
transparent translation feature allows rapid movement of large blocks of data in memory or I/O space
without disturbing the context of the on-chip ATCs or incurring delays associated with translation table
searches.