REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
A
Changes in accordance with NOR 5962-R216-92. 92-06-22
Michael A. Frye
B
Updated drawing to current requirements. Editorial changes
throughout. - gap
01-04-04
Raymond Monnin
C Added “Memory” in the SMD title block. Also, boilerplate update and
part of five year review. tcr 07-02-28 Robert M. Heber
THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED.
REV
SHEET
REV
SHEET
REV STATUS REV C C C C C C C C C C C C C C
OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMIC N/A PREPARED BY
Kenneth S. Rice
DEFENSE SUPPLY CENTER COLUMBUS
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Charles Reusing
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
APPROVED BY
Charles Reusing
MICROCIRCUITS, MEMORY, DIGITAL, CMOS,
64K X 4 SRAM (LOW POWER), MONOLITHIC
SILICON
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DRAWING APPROVAL DATE
88-08-04
AMSC N/A
REVISION LEVEL
C SIZE
A CAGE CODE
67268
5962-88545
SHEET
1 OF
14
DSCC FORM 2233
APR 97 5962-E258-07
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-88545
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 2
DSCC FORM 2234
APR 97
1. SCOPE
1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in
accordance with MIL-PRF-38535, appendix A.
1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:
5962-88545 01 L A
Drawing number Device type
(see 1.2.1) Case outline
(see 1.2.2) Lead finish
(see 1.2.3)
1.2.1 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number Circuit function Access time
01 5C256L4 64K X 4 low power CMOS SRAM 35 ns
02 5C256L4 64K X 4 low power CMOS SRAM 45 ns
03 5C256L4 64K X 4 low power CMOS SRAM 55 ns
04 5C256L4 64K X 4 low power CMOS SRAM 70 ns
1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style
L GDIP3-T24 or CDIP4-T24 24 Dual-in-line
X CQCC3-N28 28 Rectangular leadless chip carrier
Y CDFP4-F28 28 Flat package
1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
1.3 Absolute maximum ratings.
Voltage on any input relative to VSS ................................................................................ -0.5 V dc to +7.0 V dc
Voltage applied to outputs .............................................................................................. -0.5 V dc to +6.0 V dc
Storage temperature range ............................................................................................ -65°C to +150°C
Maximum power dissipation (PD) ................................................................................... 1.0 W
Lead temperature (soldering, 10 seconds) ..................................................................... +260°C
Thermal resistance, junction-to-case (θJC) ..................................................................... See MIL-STD-1835
Junction temperature (TJ) .............................................................................................. +150°C 1/
1.4 Recommended operating conditions.
Supply voltage (VCC) ...................................................................................................... 4.5 V dc to 5.5 V dc
Supply voltage (VSS) ...................................................................................................... 0 V dc
Input high voltage (VIH) .................................................................................................. 2.2 V dc to VCC +0.5 V dc
Input low voltage (VIL) .................................................................................................... -0.5 V dc to +0.8 V dc 2/
Case operating temperature range (TC) ......................................................................... -55°C to +125°C
_______
1/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
2/ VIL minimum = -3.0 V dc for pulse width less than 20 ns.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-88545
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 3
DSCC FORM 2234
APR 97
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the
Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-
JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer
Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-
PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying
activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan
may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device.
These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-
PRF-38535 is required to identify when the QML flow option is used.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535, appendix A and herein.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-88545
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 4
DSCC FORM 2234
APR 97
3.2.4 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only.
Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the
internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor
testing shall not be decreased unless approved by the preparing activity for class M. The T RB will ascertain the requirements as
provided by MIL-PRF-38535 for clases Q and V. Samples may be pulled anytime after seal.
3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are
as specified in table I and shall apply over the full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are described in table I.
3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed
in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN
number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device.
3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance
to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification mark in
accordance with MIL-PRF-38535 to identify when the QML flow option is used.
3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an
approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to
listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535,
appendix A and the requirements herein.
3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided
with each lot of microcircuits delivered to this drawing.
3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing.
3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's
facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the
reviewer.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-88545
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 5
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
VCC = 4.5 V to 5.5 V
VSS = 0 V
Group A
subgroups
Device
type
Limits
Unit
unless otherwise specified Min Max
Operating supply current ICC1 t
AVAV = tAVAV (minimum), 1, 2, 3 All 100 mA
1/
VCC = 5.5 V, CE = VIL,
all other inputs at VIL
Standby power supply ICC2 CE ≥ VIH, all other inputs 1, 2, 3 All 25 mA
current, TTL 1/
≤ VIL or ≥ VIH, VCC = 5.5 V,
f = 0 MHz
Standby power supply ICC3 CE ≥ (VCC -0.2 V), f = 0 MHz, 1, 2, 3 All 3 mA
current, CMOS 1/ VCC = 5.5 V, all other inputs
≤ 0.2 V or ≥ (VCC -0.2 V)
Data retention current 1/ ICC4 V
CC = 2.0 V 1, 2, 3 All 900 µA
Input leakage current, IILK V
CC = 5.5 V, 1, 2, 3 All ±10 µA
any input VIN = 0 V to 5.5 V
Off-state output leakage IOLK V
CC = 5.5 V, 1, 2, 3 All ±10 µA
current VIN = 0 V to 5.5 V
Data retention voltage VDR VIN ≤ 0.2 V or ≥ (VCC - 0.2 V), 1, 2, 3 All 2.0 V
CE ≥ (VCC - 0.2 V)
Output high voltage VOH I
OUT = -4.0 mA, VCC = 4.5 V, 1, 2, 3 All 2.4 V
V
IL = 0.8 V, VIH = 2.2 V
Output low voltage VOL I
OUT = 8.0 mA, VCC = 4.5 V, 1, 2, 3 All 0.4 V
V
IL = 0.8 V, VIH = 2.2 V
Input capacitance CIN V
IN = 0 V 4 All 10.0 pF
f = 1.0 MHz, TC = +25°C,
See 4.3.1c
Output capacitance COUT V
IN = 0 V 4 All 12.0 pF
f = 1.0 MHz, TC = +25°C,
See 4.3.1c
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-88545
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 6
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 2/
-55°C ≤ TC ≤ +125°C
VCC = 4.5 V to 5.5 V
VSS = 0 V
Group A
subgroups
Device
type
Limits
Unit
unless otherwise specified Min Max
Chip enable access time tELQV See figure 4 9, 10, 11 01 35 ns
02 45
03 55
04 70
Read cycle time tAVAV See figure 4 3/ 9, 10, 11 01 35 ns
02 45
03 55
04 70
Address access time tAVQV See figure 4 4/ 9, 10, 11 01 35 ns
02 45
03 55
04 70
Output hold after address tAVQX See figure 4 9, 10, 11 All 3.0 ns
change
Chip enable to output tELQX See figure 4 5/, 6/ 9, 10, 11 All 3.0 ns
active
Chip disable to output tEHQZ See figure 4 5/, 6/ 9, 10, 11 01, 02 0 20 ns
inactive 03 0 25
04 0 30
Chip enable to power up tELPU See figure 4 5/ 9, 10, 11 All 0 ns
Chip enable to power down tEHPD See figure 4 5/ 9, 10, 11 01 35 ns
02 45
03 55
04 70
Write cycle time tAVAV See figure 5 9, 10, 11 01 35 ns
02 45
03 55
04 70
Write pulse width tWLWH See figure 5 9, 10, 11 01 30 ns
02 40
03 50
04 55
Chip enable to end of tELEH See figure 5 9, 10, 11 01 30 ns
write 02 40
03 50
04 55
Data setup to end of tDVWH See figure 5 9, 10, 11 01, 02 20 ns
write 03, 04 25
Data hold after end of tWHDX See figure 5 9, 10, 11 All 0 ns
write
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-88545
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 7
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 2/
-55°C ≤ TC ≤ +125°C
VCC = 4.5 V to 5.5 V
VSS = 0 V
Group A
subgroups
Device
type
Limits
Unit
unless otherwise specified Min Max
Address setup to end of tAVWH See figure 5 9, 10, 11 01 30 ns
write 02 40
03 50
04 55
Address setup to tAVWL See figure 5 9, 10, 11 All 0 ns
beginning of write (write cycle number 1)
t
AVEL See figure 5 9, 10, 11 All 0 ns
(write cycle number 2)
Address hold after tWHAV See figure 5 9, 10, 11 All 5.0 ns
end of write
Write enable to output tWLQZ See figure 5 5/, 6/ 9, 10, 11 01, 02 0 20 ns
disable 03 0 25
04 0 30
Output active after tWHQX See figure 5 5/, 6/, 7/ 9, 10, 11 All 0 ns
end of write
Deselect time tEHVCCL See figure 6 5/, 8/ 9, 10, 11 All tAVAV ns
(min)
Recovery time tVCCHEL See figure 6 5/, 8/ 9, 10, 11 All tAVAV ns
(min)
1/ ICC is dependent upon output loading and cycle rate. The specified values apply with output(s) unloaded.
2/ AC measurements assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 V to
3.0 V and output loading of 30 pF load capacitance. Output timing reference is 1.5 V, see figure 3.
3/ For read cycles 1 and 2, WE is high for entire cycle.
4/ Device is continuously selected, CE low.
5/ Parameter if not tested, shall be guaranteed to the limits specified in table I.
6/ Measured ±500 mV from steady state output voltage. Load capacitance is 5.0 pF, see figure 3.
7/ If WE is low when CE goes low, the output remains in the high impedance state.
8/ Supply recovery rate should not exceed 10 µs per volt from VDR to VCC minimum.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-88545
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 8
DSCC FORM 2234
APR 97
Device type All
Case outline L X Y
Terminal number Terminal Symbol
1 A6 NC NC
2 A7 A
6 A
0
3 A8 A
7 A
1
4 A9 A
8 A
2
5 A10 A
9 A
3
6 A11 A
10 A
4
7 A12 A
11 A
5
8 A13 A
12 A
6
9 A14 A
13 A
7
10 A15 A
14 A
8
11 CE A15 A
9
12 VSS CE CE
13 WE NC NC
14 I/O4 V
SS V
SS
15 I/O3 NC WE
16 I/O2 WE I/O1
17 I/O1 I/O4 I/O2
18 A0 I/O3 I/O3
19 A1 I/O2 I/O4
20 A2 I/O1 NC
21 A3 A
0 NC
22 A4 A
1 A
10
23 A5 A
2 A
11
24 VCC A
3 A
12
25 --- A4 A
13
26 --- A5 A
14
27 --- NC A15
28 --- VCC V
CC
FIGURE 1. Terminal connections.
CE WE Mode I/O Power
H X Not selected High Z Standby
L L Write DIN Active
L H Read DOUT Active
H = Logic “1” state
L = Logic “0” state
X = Don’t care
FIGURE 2. Truth table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-88545
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 9
DSCC FORM 2234
APR 97
AC test conditions
Input pulse levels GND to 3.0 V
Input rise fall times 5 ns
Input timing reference
levels 1.5 V
Output reference levels 1.5 V
FIGURE 3. Output load circuit.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-88545
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 10
DSCC FORM 2234
APR 97
NOTES:
1.
WE is high for entire cycle.
2.
CE and WE must transition between VIH (min) to VIL (max) or VIL (max)
to VIH (min) in a monotonic fashion.
3. Device is continuously selected, CE low.
FIGURE 4. Read cycle timing diagrams.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-88545
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 11
DSCC FORM 2234
APR 97
FIGURE 5. Write cycle timing diagrams.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-88545
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 12
DSCC FORM 2234
APR 97
NOTES:
1.
CE and WE must transition between VIH (min) to VIL (max) or VIL (max)
to VIH (min) in a monotonic fashion.
2.
CE and WE must be ≥ VIH during address transitions.
FIGURE 5. Write cycle timing diagrams - Continued.
FIGURE 6. Low VCC data retention cycle.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-88545
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 13
DSCC FORM 2234
APR 97
4. VERIFICATION
4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535,
appendix A.
4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices
prior to quality conformance inspection. The following additional criteria shall apply:
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1015 of MIL-STD-883.
(2) TA = +125°C, minimum.
b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter
tests prior to burn-in are optional at the discretion of the manufacturer.
TABLE II. Electrical test requirements.
MIL-STD-883 test requirements Subgroups
(in accordance with
MIL-STD-883, method 5005,
table I)
Interim electrical parameters
(method 5004) - - -
Final electrical test parameters
(method 5004) 1*, 2, 3, 7*, 8A, 8B, 9, 10, 11
Group A test requirements
(method 5005) 1, 2, 3, 4**, 7, 8A, 8B, 9, 10,
11
Groups C and D end-point
electrical parameters
(method 5005)
2, 3, 7, 8A, 8B
* PDA applies to subgroups 1 and 7.
** See 4.3.1c.
4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-
883 including groups A, B, C, and D inspections. The following additional criteria shall apply.
4.3.1 Group A inspection.
a. Tests shall be as specified in table II herein.
b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
c. Subgroup 4 (CIN/COUT measurement) shall be measured only for the initial test and after process or design changes
which may affect input or output capacitance.
d. Subgroups 7 and 8 shall include verification of the truth table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-88545
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 14
DSCC FORM 2234
APR 97
4.3.2 Groups C and D inspections.
a. End-point electrical parameters shall be as specified in table II herein.
b. Steady-state life test conditions, method 1005 of MIL-STD-883.
(1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1005 of MIL-STD-883.
(2) TA = +125°C, minimum.
(3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-
prepared specification or drawing.
6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be
used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC
5962) should contact DSCC-VA, telephone (614) 692-0544.
6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MIL-
HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by
DSCC-VA.
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 07-02-28
Approved sources of supply for SMD 5962-88545 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate
of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-8854501LA 0EU86 MT5C2564C-35L/883C
0C7V7 CY7C194L-35DMB
3DTT2 P4C1258L-35CMB
3/ OW6208CD3-35
3/ IDT71258L35CB
3/ EDI8465LP35QB
5962-8854501XA 0EU86 MT5C2564EC-35L/883C
0C7V7 CY7C194L-35LMB
3DTT2 P4C1258L-35LMB
3/ OW6208CC3-35
3/ EDI8464LP35LB
5962-8854501YA 0EU86 MT5C2564F-35L/883C
0C7V7 CY7C194L-35KMB
3DTT2 P4C1258L-35FSMB
3/ EDI8465LP35FB
5962-8854502LA 0EU86 MT5C2564C-45L/883C
0C7V7 CY7C194L-45DMB
3DTT2 P4C1258L-45CMB
3/ OW6208CD3-45
3/ IDT71258L45CB
3/ EDI8465LP45QB
5962-8854502XA 0EU86 MT5C2564EC-45L/883C
0C7V7 CY7C194L-45LMB
3DTT2 P4C1258L-45LMB
3/ OW6208CC3-45
3/ EDI8464LP45LB
5962-8854502YA 0EU86 MT5C2564F-45L/883C
0C7V7 CY7C194L-45KMB
3DTT2 P4C1258L-45FSMB
3/ EDI8465LP45FB
Page 1 of 2
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-8854503LA 0EU86 MT5C2564C-55L/883C
0C7V7 CY7C194L-55DMB
3DTT2 P4C1258L-55CMB
3/ OW6208CD3-55
3/ IDT71258L55CB
3/ EDI8465LP55QB
5962-8854503XA 0EU86 MT5C2564EC-55L/883C
0C7V7 CY7C194L-55LMB
3DTT2 P4C1258L-55LMB
3/ OW6208CC3-55
3/ EDI8464LP55LB
5962-8854503YA 0EU86 MT5C2564F-55L/883C
0C7V7 CY7C194L-55KMB
3DTT2 P4C1258L-55FSMB
3/ EDI8465LP55FB
5962-8854504LA 0EU86 MT5C2564C-70L/883C
0C7V7 CY7C194L-70DMB
3DTT2 P4C1258L-70CMB
3/ OW6208CD3-70
3/ IDT71258L70CB
3/ EDI8465LP70QB
5962-8854504XA 0EU86 MT5C2564EC-70L/883C
0C7V7 CY7C194L-70LMB
3DTT2 P4C1258L-70LMB
3/ OW6208CC3-70
3/ EDI8464LP70LB
5962-8854504YA 0EU86 MT5C2564F-70L/883C
0C7V7 CY7C194L-70KMB
3DTT2 P4C1258L-70FSMB
3/ EDI8465LP70FB
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE Vendor name
number and address
0EU86 Austin Semiconductor International L.P.
8701 Cross Park Drive
Austin, TX 78754-4566
0C7V7 QP Semiconductor
2945 Oakmead Village Ct.
Santa Clara, CA 95051-0812
3DTT2 Pyramid Semiconductor Corp
1340 Bordeaux Drive
Sunnyvale, Ca 94089-1005
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