1
FEATURES
APPLICATIONS
DESCRIPTION
APPLICATION CIRCUIT
_
+
IN–
IN+
PWM H–
Bridge
VO+
VO–
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
RI
RI
+
Differential
Input
TPA2005D1
SHUTDOWN
Actual Solution Size
2.5 mm
CS
RI
RI
6 mm
(MicroStar JuniorBGA)
TPA2005D1
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............................................................................................................................................................... SLOS369F JULY 2002 REVISED JULY 2008
1.4-W MONO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER
BGA Package (ZQY)
2
1.4 W Into 8 From a 5 V Supply at 3 mm x 5 mm MSOP PowerPAD™ PackageTHD = 10% (Typ) (DGN)Maximum Battery Life and Minimum Heat TPA2010D1 Available in 1,45 mm × 1,45 mmWCSP (YZF) Efficiency With an 8- Speaker:
Use TPA2006D1 for 1.8 V Logic Compatibility 84% at 400 mW
on Shutdown Pin 79% at 100 mW 2.8-mA Quiescent Current 0.5- µA Shutdown Current
Ideal for Wireless or Cellular Handsets andCapable of Driving an
PDAs8- Speaker (2.5 V V
DD
5.5 V) and a4- Speaker (2.5 V V
DD
4.2 V)Only Three External Components
The TPA2005D1 is a 1.4-W high efficiency filter-freeclass-D audio power amplifier in a MicroStar Junior™ Optimized PWM Output Stage Eliminates
BGA, QFN, or MSOP package that requires onlyLC Output Filter
three external components. Internally Generated 250-kHz Switching
Features like 84% efficiency, -71-dB PSRR at 217Frequency Eliminates Capacitor and
Hz, improved RF-rectification immunity, and 15 mm
2Resistor
total PCB area make the TPA2005D1 ideal for Improved PSRR (-71 dB at 217 Hz) and
cellular handsets. A fast start-up time of 9 ms withWide Supply Voltage (2.5 V to 5.5 V)
minimal pop makes the TPA2005D1 ideal for PDAEliminates Need for a Voltage Regulator
applications. Fully Differential Design Reduces RF
In cellular handsets, the earpiece, speaker phone,Rectification and Eliminates Bypass
and melody ringer can each be driven by theCapacitor
TPA2005D1. The device allows independent gaincontrol by summing the signals from each function Improved CMRR Eliminates Two Input
while minimizing noise to only 48 µV
RMS
.Coupling CapacitorsSpace Saving Package
The TPA2005D1 has short-circuit and thermalprotection. 3 mm × 3 mm QFN package (DRB) 2,5 mm × 2,5 mm MicroStar Junior™
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2MicroStar Junior, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
DISSIPATION RATINGS
TPA2005D1
SLOS369F JULY 2002 REVISED JULY 2008 ...............................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
A
PACKAGE
(1)
PART NUMBER SYMBOL
MicroStar Junior™ (GQY) TPA2005D1GQYR
(2)
PB051MicroStar Junior™ (ZQY)
(3)
TPA2005D1ZQYR
(2)
AAFI-40 ° C to 85 ° C
8-pin QFN (DRB) TPA2005D1DRBR
(2)
BIQ8-pin MSOP (DGN) TPA2005D1DGN(R) BAL
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) The GQY, ZQY, and DRB packages are only available taped and reeled. An R at the end of the part number indicates the devices aretaped and reeled.(3) The GQY is the standard MicroStar Junior™ package. The ZQY is lead-free option, and is qualified for 260 ° lead-free assembly.
over operating free-air temperature range unless otherwise noted
(1)
UNIT
In active mode -0.3 V to 6 VV
DD
Supply voltage
(2)
In SHUTDOWN mode -0.3 V to 7 VV
I
Input voltage -0.3 V to V
DD
+ 0.3 VContinuous total power dissipation See Dissipation Rating TableT
A
Operating free-air temperature -40 ° C to 85 ° CT
J
Operating junction temperature -40 ° C to 85 ° CT
stg
Storage temperature -65 ° C to 150 ° C2.5 V
DD
4.2 V 3.2 (Minimum)R
L
Load resistance
4.2 < V
DD
6 V 6.4 (Minimum)
(1) Stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operatingconditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) For the MSOP (DGN) package option, the maximum V
DD
should be limited to 5 V if short-circuit protection is desired.
MIN NOM MAX UNIT
V
DD
Supply voltage 2.5 5.5 VV
IH
High-level input voltage SHUTDOWN 2 V
DD
VV
IL
Low-level input voltage SHUTDOWN 0 0.8 VR
I
Input resistor Gain 20 V/V (26 dB) 15 k
V
IC
Common mode input voltage range V
DD
= 2.5 V, 5.5 V, CMRR -49 dB 0.5 V
DD
-0.8 VT
A
Operating free-air temperature -40 85 ° C
DERATING T
A
25 ° C T
A
= 70 ° C T
A
= 85 ° CPACKAGE
FACTOR POWER RATING POWER RATING POWER RATING
GQY, ZQY 16 mW/ ° C 2 W 1.28 W 1.04 WDRB 21.8 mW/ ° C 2.7 W 1.7 W 1.4 WDGN 17.1 mW/ ° C 2.13 W 1.36 W 1.11 W
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ELECTRICAL CHARACTERISTICS
V
V
2 158 kW
RI
2 142 kW
RI
2 150 kW
RI
OPERATING CHARACTERISTICS
TPA2005D1
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............................................................................................................................................................... SLOS369F JULY 2002 REVISED JULY 2008
T
A
= 25 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output offset voltage (measured|V
OS
| V
I
= 0 V, A
V
= 2 V/V, V
DD
= 2.5 V to 5.5 V 25 mVdifferentially)
PSRR Power supply rejection ratio V
DD
= 2.5 V to 5.5 V -75 -55 dBV
DD
= 2.5 V to 5.5 V, V
IC
= V
DD
/2 to 0.5 V,CMRR Common mode rejection ratio -68 -49 dBV
IC
= V
DD
/2 to V
DD
- 0.8 V|I
IH
| High-level input current V
DD
= 5.5 V, V
I
= 5.8 V 50 µA|I
IL
| Low-level input current V
DD
= 5.5 V, V
I
= 0.3 V 1 µAV
DD
= 5.5 V, no load 3.4 4.5I
(Q)
Quiescent current V
DD
= 3.6 V, no load 2.8 mAV
DD
= 2.5 V, no load 2.2 3.2I
(SD)
Shutdown current V
(SHUTDOWN)
= 0.8 V, V
DD
= 2.5 V to 5.5 V 0.5 2 µAV
DD
= 2.5 V 770Static drain-source on-stater
DS(on)
V
DD
= 3.6 V 590 m resistance
V
DD
= 5.5 V 500Output impedance in SHUTDOWN V
(SHUTDOWN)
= 0.8 V > 1 k
f
(sw)
Switching frequency V
DD
= 2.5 V to 5.5 V 200 250 300 kHz
Gain
T
A
= 25 ° C, Gain = 2 V/V, R
L
= 8 (unless otherwise noted)
PARAMETER TEST CONDITIOINS MIN TYP MAX UNIT
V
DD
= 5 V 1.18THD + N= 1%, f = 1 kHz, R
L
= 8 V
DD
= 3.6 V 0.58 WV
DD
= 2.5 V 0.26P
O
Output power
V
DD
= 5 V 1.45THD + N= 10%, f = 1 kHz, R
L
= 8 V
DD
= 3.6 V 0.75 WV
DD
= 2.5 V 0.35P
O
= 1 W, f = 1 kHz, R
L
= 8 V
DD
= 5 V 0.18%THD+N Total harmonic distortion plus noise P
O
= 0.5 W, f = 1 kHz, R
L
= 8 V
DD
= 3.6 V 0.19%P
O
= 200 mW, f = 1 kHz, R
L
= 8 V
DD
= 2.5 V 0.20%f = 217 Hz, V
(RIPPLE)
= 200 mV
ppk
SVR
Supply ripple rejection ratio V
DD
= 3.6 V -71 dBInputs ac-grounded with C
i
= 2 µFSNR Signal-to-noise ratio P
O
= 1 W, R
L
= 8 V
DD
= 5 V 97 dBNo weighting 48V
DD
= 3.6 V, f = 20 Hz to 20 kHz,V
n
Output voltage noise µV
RMSInputs ac-grounded with C
i
= 2 µF
A weighting 36CMRR Common mode rejection ratio V
IC
= 1 V
pp
, f = 217 Hz V
DD
= 3.6 V -63 dBZ
I
Input impedance 142 150 158 k
Start-up time from shutdown V
DD
= 3.6 V 9 ms
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PIN ASSIGNMENTS
(A1)
(B1) (A4)
(C4)
(D4)
(SIDE VIEW)
MicroStar Juniort (GQY) PACKAGE
(TOP VIEW)
NC VDD
SHUTDOWN
IN+
IN−
VO−
VDD
VO+
NOTES A. The shaded terminals are used for electrical and thermal connections to the ground plane. All the shaded terminals need to be electrical
connected to ground. No connect (NC) terminals still need a pad and trace.
B. The thermal pad of the DRB and DGN packages must be electrically and thermally connected to a ground plane.
(C1)
(D1)
(B4)
GND
8
SHUTDOWN
NC
IN+
IN−
VO−
GND
VDD
VO+
8-PIN QFN (DRB) PACKAGE
(TOP VIEW)
7
6
5
1
2
3
4
NC − No internal connection
VO−
GND
VDD
VO+
8
7
6
5
1
2
3
4
SHUTDOWN
NC
IN+
IN−
8-PIN MSOP (DGN) PACKAGE
(TOP VIEW)
_
+_
+_
+_
+
150 k
150 k
_
+
_
+
Deglitch
Logic
Deglitch
Logic
Gate
Drive
Gate
Drive
VDD
Short
Circuit
Detect
Startup
& Thermal
Protection
Logic
Ramp
Generator
Biases
and
References
TTL
Input
Buffer
SD
Gain = 2 V/V B4, C4
VDD
A4VO
D4VO+
GND
D1
IN−
C1
IN+
A1
SHUTDOWN
A2, A3, B3, C2, C3, D2, D3
(terminal labels for MicroStar Junior package)
TPA2005D1
SLOS369F JULY 2002 REVISED JULY 2008 ...............................................................................................................................................................
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Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME ZQY, GQY DRB, DGN
IN- D1 4 I Negative differential inputIN+ C1 3 I Positive differential inputV
DD
B4, C4 6 I Power supplyV
O+
D4 5 O Positive BTL outputA2, A3, B3, C2, C3,GND 7 I High-current groundD2, D3V
O-
A4 8 O Negative BTL outputSHUTDOWN A1 1 I Shutdown terminal (active low logic)NC B1 2 No internal connectionThermal Pad Must be soldered to a grounded pad on the PCB.
FUNCTIONAL BLOCK DIAGRAM
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TYPICAL CHARACTERISTICS
Table of Graphs
TEST SET-UP FOR GRAPHS
TPA2005D1
IN+
IN−
OUT+
OUT−
VDD GND
CI
CI
RI
RI
Measurement
Output
+
1 µF
+
VDD
Load 30 kHz
Low Pass
Filter
Measurement
Input
+
Notes:
(1) CI was Shorted for any Common-Mode input voltage measurement
(2) A 33-µH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.
(3) The 30-kHz low-pass filter is required even if the analyzer has a low-pass filter. An RC filter (100 W, 47 nF) is used on
each output for the data sheet graphs.
TPA2005D1
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............................................................................................................................................................... SLOS369F JULY 2002 REVISED JULY 2008
FIGURE
Efficiency vs Output power 1, 2P
D
Power dissipation vs Output power 3Supply current vs Output power 4, 5I
(Q)
Quiescent current vs Supply voltage 6I
(SD)
Shutdown current vs Shutdown voltage 7vs Supply voltage 8P
O
Output power
vs Load resistance 9, 10vs Output power 11, 12THD+N Total harmonic distortion plus noise vs Frequency 13, 14, 15, 16vs Common-mode input voltage 17vs Frequency 18, 19, 20k
SVR
Supply voltage rejection ratio
vs Common-mode input voltage 21vs Time 22GSM power supply rejection
vs Frequency 23vs Frequency 24CMRR Common-mode rejection ratio
vs Common-mode input voltage 25
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0 0.5 1 1.5
P -OutputPower-W
O
0
10
20
30
40
50
60
70
80
90
Efficiency-%
V =4.2V,
R =4 ,33 H
DD
LW m
0
10
20
30
40
50
60
70
80
90
100
0 0.1 0.2 0.3 0.4 0.5 0.6
PO-OutputPower-W
Efficiency-%
VDD =3.6
RL=32 ,33 HW m
RL=16 ,33 HW m
RL=8 ,33 HW m
Class-AB,
RL=8
0
50
100
150
200
250
300
0 0.2 0.4 0.6 0.8 1 1.2
PO - Output Power - W
VDD = 2.5 V,
RL = 8 , 33 µH
VDD = 3.6 V,
RL = 8 , 33 µH
VDD = 5 V,
RL = 8 , 33 µH
Supply Current - mA
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 0.2 0.4 0.6 0.8 1 1.2
-PowerDissipation-WP
D
PO-OutputPower-W
Class-AB,VDD =5V,RL=8 W
Class-AB,
VDD =3.6V,
RL=8 W
VDD =3.6V,
RL=8 W,33 mH
VDD =5V,
RL=8 W,33 mH
V =4.2V,
R =4 ,33 Hm
DD
LW
0
50
100
150
200
250
0 0.1 0.2 0.3 0.4 0.5 0.6
RL = 8 , 33 µH
VDD = 3.6 V
RL = 32 , 33 µH
Supply Current - mA
PO - Output Power - W
2.5 3 3.5 4 4.5 5
VDD - Supply Voltage - V
- Output Power - WPO
RL = 8
f = 1 kHz
Gain = 2 V/V
THD+N = 1%
THD+N = 10%
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
2.5 3 3.5 4 4.5 5 5.5
I(Q) − Quiescent Current − mA
VDD − Supply Voltage − V
No Load
RL = 8 , 33 µH
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
VDD = 2.5 V
VDD = 3.6 V
VDD = 5 V
Shutdown Voltage - V
- Shutdown Current -
I(SD) Aµ
TPA2005D1
SLOS369F JULY 2002 REVISED JULY 2008 ...............................................................................................................................................................
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EFFICIENCY EFFICIENCY EFFICIENCYvs vs vsOUTPUT POWER OUTPUT POWER OUTPUT POWER
Figure 1. Figure 2. Figure 3.
POWER DISSIPATION SUPPLY CURRENT SUPPLY CURRENTvs vs vsOUTPUT POWER OUTPUT POWER OUTPUT POWER
Figure 4. Figure 5. Figure 6.
QUIESCENT CURRENT SHUTDOWN CURRENT OUTPUT POWERvs vs vsSUPPLY VOLTAGE SHUTDOWN VOLTAGE SUPPLY VOLTAGE
Figure 7. Figure 8. Figure 9.
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0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
2.5 3 3.5 4 4.5
V -SupplyVoltage-V
DD
P-OutputPower-W
O
THD+N=10%
THD+N=1%
R =4 ,
f=1kHz,
Gain=2V/V
LW
0
0.2
0.4
0.6
0.8
1
1.2
1.4
4 8 12 16 20 24 28 32
R -LoadResistance-
LW
V =4.2V
DD
V =3.6V
DD
V =2.5V
DD
V =5V
DD
f=1kHz,
THD+N=1%,
Gain=2V/V
P -OutputPower-W
O
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
4 8 12 16 20 24 28 32
R -LoadResistance-
LW
V =4.2V
DD
V =3.6V
DD
V =2.5V
DD
V =5V
DD
P -OutputPower-W
O
f=1kHz,
THD+N=10%,
Gain=2V/V
0.1
30
0.2
0.5
1
2
5
0.01 20.1 1
P -OutputPower-W
O
THD+N-TotalHarmonicDistortion+Noise-%
20
V =2.5V
DD
V =3.6V
DD
V =4.2V
DD
R =4 ,
f=1kHz,
Gain=2V/V
LW
10
0.1
30
0.2
0.5
1
2
5
10
20
0.01 20.1 1
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
5 V
3.6 V
2.5 V
RL = 8 ,
f = 1 kHz,
Gain = 2 V/V
0.1
30
0.2
0.5
1
2
5
10
20
0.01 20.1 1
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
5 V
3.6 V
2.5 V
RL = 16 ,
f = 1 kHz,
Gain = 2 V/V
0.008
10
0.02
0.05
0.1
0.2
0.5
1
2
5
20 100 1 k 20 k
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
50 mW
250 mW
1 W
VDD = 5 V
CI = 2 µF
RL = 8
Gain = 2 V/V
1
2
5
10
0.5
0.2
0.1
0.05
0.02
0.0120 100 1 k 20 k
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
VDD = 3.6 V
CI = 2 µF
RL = 8
Gain = 2 V/V
500 mW 25 mW
125 mW
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.0120 100 1 k 20 k
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
15 mW
VDD = 2.5 V
CI = 2 µF
RL = 8
Gain = 2 V/V
75 mW
200 mW
TPA2005D1
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............................................................................................................................................................... SLOS369F JULY 2002 REVISED JULY 2008
OUTPUT POWER OUTPUT POWER OUTPUT POWERvs vs vsSUPPLY VOLTAGE LOAD RESISTANCE LOAD RESISTANCE
Figure 10. Figure 11. Figure 12.
TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION +NOISE TOTAL HARMONIC DISTORTION + NOISEvs NOISE vsOUTPUT POWER vs OUTPUT POWER OUTPUT POWER
Figure 13. Figure 14. Figure 15.
TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION +NOISE NOISE NOISEvs vs vsFREQUENCY FREQUENCY FREQUENCY
Figure 16. Figure 17. Figure 18.
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0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20k100 1k
f-Frequency-Hz
THD+N-TotalHarmonicDistortion+Noise-%
1W
500mW
250mW
V =4.2V,
R =4 ,
Gain=2V/V
DD
LW
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20k100 1k
THD+N-TotalHarmonicDistortion+Noise-%
f-Frequency-Hz
500mW
250mW
775mW
V =3.6V,
R =4 ,
Gain=2V/V
DD
LW
VDD = 3.6 V
CI = 2 µF
RL = 16
Gain = 2 V/V
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
1
2
5
10
0.5
0.2
0.1
0.05
0.02
0.0120 100 1 k 20 k
15 mW
75 mW
200 mW
20 100
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
1k 20k
200mW
75mW
15mW
V =2.5V,
R =4 ,
Gain=2V/V
DD
LW
f-Frequency-Hz
THD+N-TotalHarmonicDistortion+Noise-%
0.1
1
10
0 0.5 1 1.5 2 2.5 3 3.5
VDD = 2.5 V
VDD = 3.6 V
f = 1 kHz
PO = 200 mW
VIC - Common Mode Input Voltage - V
THD+N - Total Harmonic Distortion + Noise - %
−80
−70
−60
−50
−40
−30
−20
−10
0
20 100 1 k 20 k
f − Frequency − Hz
− Supply Voltage Rejection Ratio − dBkSVR
CI = 2 µF
RL = 8
Vp-p = 200 mV
Inputs ac-Grounded
Gain = 2 V/V
VDD = 5 V
VDD = 3.6 V
VDD =2. 5 V
−80
−70
−60
−50
−40
−30
−20
−10
0
f − Frequency − Hz
− Supply Voltage Rejection Ratio − dBkSVR
20 100 1 k 20 k
Gain = 5 V/V
CI = 2 µF
RL = 8
Vp-p = 200 mV
Inputs ac-Grounded
VDD = 5 V
VDD = 2. 5 V
VDD = 3.6 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f − Frequency − Hz
− Supply Voltage Rejection Ratio − dBkSVR
VDD = 3.6 V
CI = 2 µF
RL = 8
Inputs Floating
Gain = 2 V/V
20 100 1 k 20 k
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VIC - Common Mode Input Voltage - V
f = 217 Hz
RL = 8
Gain = 2 V/V
VDD = 2.5 V
- Supply Voltage Rejection Ratio - dBkSVR
VDD = 3.6 V
VDD = 5 V
TPA2005D1
SLOS369F JULY 2002 REVISED JULY 2008 ...............................................................................................................................................................
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TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION +NOISE NOISE NOISEvs vs vsFREQUENCY FREQUENCY FREQUENCY
Figure 19. Figure 20. Figure 21.
TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION + SUPPLY VOLTAGE REJECTIONNOISE NOISE RATIOvs vs vsFREQUENCY COMMON MODE INPUT VOLTAGE FREQUENCY
Figure 22. Figure 23. Figure 24.
SUPPLY VOLTAGE REJECTION SUPPLY VOLTAGE REJECTIONRATIO SUPPLY VOLTAGE REJECTIO RATIO RATIOvs vs vsFREQUENCY FREQUENCY COMMON-MODE INPUT VOLTAGE
Figure 25. Figure 26. Figure 27.
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Product Folder Link(s): TPA2005D1
C1 - Duty
12.6%
C1 -
Frequency
216.7448 Hz
C1 - Amplitude
512 mV
C1 - High
3.544 V
Voltage - V
t - Time - ms
VDD
VOUT
-150
-100
-50
0 400 800 1200 1600 2000
-150
-100
-50
0
0
f - Frequency - Hz
- Output Voltage - dBVVO
- Supply Voltage - dBVVDD
VDD Shown in Figure 22
CI = 2 µF,
Inputs ac-grounded
Gain = 2V/V
−70
−60
−50
−40
−30
−20
−10
0
f − Frequency − Hz
CMRR − Common Mode Rejection Ratio − dB
20 100 1 k 20 k
VDD = 2.5 V to 5 V
VIC = 1 Vp−p
RL = 8
Gain = 2 V/V
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
RL = 8
Gain = 2 V/V
VIC - Common Mode Input Voltage - V
CMRR - Common Mode Rejection Ratio - dB
VDD = 5 V
VDD = 2.5 V VDD = 3.6 V
TPA2005D1
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............................................................................................................................................................... SLOS369F JULY 2002 REVISED JULY 2008
GSM POWER SUPPLY REJECTION GSM POWER SUPPLY REJECTIONvs vsTIME FREQUENCY
Figure 28. Figure 29.
COMMON-MODE REJECTION RATIO COMMON-MODE REJECTION RATIOvs vsFREQUENCY COMMON-MODE INPUT VOLTAGE
Figure 30. Figure 31.
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APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIER
Advantages of Fully Differential Amplifiers
COMPONENT SELECTION
_
+
IN–
IN+
PWM H–
Bridge
VO+
VO–
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
RI
RI
+
Differential
Input
TPA2005D1
Filter-Free Class D
SHUTDOWN
TPA2005D1
SLOS369F JULY 2002 REVISED JULY 2008 ...............................................................................................................................................................
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The TPA2005D1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifierconsists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that theamplifier outputs a differential voltage on the output that is equal to the differential input times the gain. Thecommon-mode feedback ensures that the common-mode voltage at the output is biased around V
DD
/2 regardlessof the common-mode voltage at the input. The fully differential TPA2005D1 can still be used with a single-endedinput; however, the TPA2005D1 should be used with differential inputs when in a noisy environment, like awireless handset, to ensure maximum noise rejection.
Input-coupling capacitors not required: The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply. For example,if a codec has a midsupply lower than the midsupply of the TPA2005D1, the common-mode feedbackcircuit will adjust, and the TPA2005D1 outputs will still be biased at midsupply of the TPA2005D1. Theinputs of the TPA2005D1 can be biased from 0.5 V to V
DD
- 0.8 V. If the inputs are biased outside of thatrange, input-coupling capacitors are required.Midsupply bypass capacitor, C
(BYPASS)
, not required: The fully differential amplifier does not require a bypass capacitor. This is because any shift in themidsupply affects both positive and negative channels equally and cancels at the differential output.Better RF-immunity:
GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. Thetransmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signalmuch better than the typical audio amplifier.
Figure 32 shows the TPA2005D1 typical schematic with differential inputs and Figure 33 shows the TPA2005D1with differential inputs and input capacitors, and Figure 34 shows the TPA2005D1 with single-ended inputs.Differential inputs should be used whenever possible because the single-ended inputs are much moresusceptible to noise.
Table 1. Typical Component Values
REF DES VALUE EIA SIZE MANUFACTURER PART NUMBER
R
I
150 k (0.5%) 0402 Panasonic ERJ2RHD154VC
S
1µF (+22%, -80%) 0402 Murata GRP155F50J105ZC
I
(1)
3.3 nF (10%) 0201 Murata GRP033B10J332K
(1) C
I
is only needed for single-ended input or if V
ICM
is not between 0.5 V and V
DD
- 0.8 V. C
I
= 3.3 nF (with R
I
= 150 k ) gives ahigh-pass corner frequency of 321 Hz.
Figure 32. Typical TPA2005D1 Application Schematic With Differential Input for a Wireless Phone
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Product Folder Link(s): TPA2005D1
_
+
IN–
IN+
PWM H–
Bridge
VO+
VO–
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
RI
RI
Differential
Input
TPA2005D1
Filter-Free Class D
SHUTDOWN
CI
CI
_
+
IN–
IN+
PWM H–
Bridge
VO+
VO–
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
RI
RI
Single-ended
Input
TPA2005D1
Filter-Free Class D
SHUTDOWN
CI
CI
TPA2005D1
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............................................................................................................................................................... SLOS369F JULY 2002 REVISED JULY 2008
Figure 33. TPA2005D1 Application Schematic With Differential Input and Input Capacitors
Figure 34. TPA2005D1 Application Schematic With Single-Ended Input
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Product Folder Link(s): TPA2005D1
Input Resistors (R
I
)
Gain +2 150 kW
RI
(1)
Decoupling Capacitor (C
S
)
Input Capacitors (C
I
)
fc+1
ǒ2pRICIǓ
(2)
CI+1
ǒ2pRIfcǓ
(3)
TPA2005D1
SLOS369F JULY 2002 REVISED JULY 2008 ...............................................................................................................................................................
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The input resistors (R
I
) set the gain of the amplifier according to equation Equation 1 .
Resistor matching is important in fully differential amplifiers. The balance of the output on the referencevoltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonicdistortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors orbetter to keep the performance optimized. Matching is more important than overall tolerance. Resistor arrays with1% matching can be used with a tolerance greater than 1%.
Place the input resistors close to the TPA2005D1 to limit noise injection on the high-impedance nodes.
For optimal performance the gain should be set to 2 V/V or lower. Lower gain allows the TPA2005D1 to operateat its best, and keeps a high voltage at the input making the inputs less susceptible to noise.
The TPA2005D1 is a high-performance class-D audio amplifier that requires adequate power supply decouplingto ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1µF, placed as close as possible to the device V
DD
lead works best. Placing this decoupling capacitor close to theTPA2005D1 is important for the efficiency of the class-D amplifier, because any resistance or inductance in thetrace between the device and the capacitor can cause a loss in efficiency. For filtering lower-frequency noisesignals, a 10 µF or greater capacitor placed near the audio power amplifier would also help, but it is not requiredin most applications because of the high PSRR of this device.
The TPA2005D1 does not require input coupling capacitors if the design uses a differential source that is biasedfrom 0.5 V to V
DD
- 0.8 V (shown in Figure 32 ). If the input signal is not biased within the recommendedcommon-mode input range, if needing to use the input as a high pass filter (shown in Figure 33 ), or if using asingle-ended source (shown in Figure 34 ), input coupling capacitors are required.
The input capacitors and input resistors form a high-pass filter with the corner frequency, f
c
, determined inequation Equation 2 .
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so thecorner frequency can be set to block low frequencies in this application.
Equation Equation 3 is reconfigured to solve for the input coupling capacitance.
If the corner frequency is within the audio band, the capacitors should have a tolerance of 10% or better,because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below, andcauses pop. Any capacitor in the audio path should have a rating of X7R or better.
For a flat low-frequency response, use large input coupling capacitors (1 µF). However, in a GSM phone theground signal is fluctuating at 217 Hz, but the signal from the codec does not have the same 217 Hz fluctuation.The difference between the two signals is amplified, sent to the speaker, and heard as a 217 Hz hum.
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Product Folder Link(s): TPA2005D1
SUMMING INPUT SIGNALS WITH THE TPA2005D1
Summing Two Differential Input Signals
Gain 1 +VO
VI1 +2 150 kW
RI1 ǒV
VǓ
(4)
Gain 2 +VO
VI2 +2 150 kW
RI2 ǒV
VǓ
(5)
_
+
IN–
IN+
PWM H–
Bridge
VO+
VO–
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
RI2
RI2
+
Differential
Input 1
SHUTDOWN
RI1
RI1
+
Differential
Input 2
Filter-Free Class D
Summing a Differential Input Signal and a Single-Ended Input Signal
Gain 1 +VO
VI1 +2 150 kW
RI1 ǒV
VǓ
(6)
Gain 2 +VO
VI2 +2 150 kW
RI2 ǒV
VǓ
(7)
CI2 +1
ǒ2pRI2 fc2Ǔ
(8)
TPA2005D1
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............................................................................................................................................................... SLOS369F JULY 2002 REVISED JULY 2008
Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sourcesthat need separate gain. The TPA2005D1 makes it easy to sum signals or use separate signal sources withdifferent gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phonewould require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereoheadphones require summing of the right and left channels to output the stereo signal to the mono speaker.
Two extra resistors are needed for summing differential signals (a total of 5 components). The gain for each inputsource can be set independently (see equations Equation 4 and Equation 5 , and Figure 35 ).
If summing left and right inputs with a gain of 1 V/V, use R
I1
= R
I2
= 300 k .
If summing a ring tone and a phone signal, set the ring-tone gain to Gain 2 = 2 V/V, and the phone gain to gain1 = 0.1 V/V. The resistor values would be. . .R
I1
= 3 M , and = R
I2
= 150 k .
Figure 35. Application Schematic With TPA2005D1 Summing Two Differential Inputs
Figure 36 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couplein through IN+ with this method. It is better to use differential inputs. The corner frequency of the single-endedinput is set by C
I2
, shown in equation Equation 8 . To assure that each input is balanced, the single-ended inputmust be driven by a low-impedance source even if the input is not in use.
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CI2 u1
ǒ2p150kW20HzǓ
(9)
CI2 u53pF
(10)
_
+
IN–
IN+
PWM H–
Bridge
VO+
VO–
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
RI2
RI2
Differential
Input 1
Filter-Free Class D
SHUTDOWN
RI1
RI1
Single-Ended
Input 2
CI2
CI2
Summing Two Single-Ended Input Signals
TPA2005D1
SLOS369F JULY 2002 REVISED JULY 2008 ...............................................................................................................................................................
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If summing a ring tone and a phone signal, the phone signal should use a differential input signal while the ringtone might be limited to a single-ended signal. Phone gain is set at gain 1 = 0.1 V/V, and the ring-tone gain is setto gain 2 = 2 V/V, the resistor values would be R
I1
= 3 M , and = R
I2
= 150 k .
The high pass corner frequency of the single-ended input is set by C
I2
. If the desired corner frequency is lessthan 20 Hz.
Figure 36. Application Schematic With TPA2005D1 Summing Differential Input andSingle-Ended Input Signals
Four resistors and three capacitors are needed for summing single-ended input signals. The gain and cornerfrequencies (f
c1
and f
c2
) for each input source can be set independently (see equations Equation 11 throughEquation 14 , and Figure 37 ). Resistor, R
P
, and capacitor, C
P
, are needed on the IN+ terminal to match theimpedance on the IN- terminal. The single-ended inputs must be driven by low impedance sources even if one ofthe inputs is not outputting an ac signal.
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Product Folder Link(s): TPA2005D1
Gain 1 +VO
VI1 +2 150 kW
RI1 ǒV
VǓ
(11)
Gain 2 +VO
VI2 +2 150 kW
RI2 ǒV
VǓ
(12)
CI1 +1
ǒ2pRI1 fc1Ǔ
(13)
CI2 +1
ǒ2pRI2 fc2Ǔ
(14)
CP+CI1 )CI2
(15)
RP+RI1 RI2
ǒRI1 )RI2Ǔ
(16)
_
+
IN–
IN+
PWM H–
Bridge
VO+
VO–
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
RI2
RP
Filter-Free Class D
SHUTDOWN
RI1
Single-Ended
Input 2
CI2
CP
Single-Ended
Input 1
CI1
EFFICIENCY AND THERMAL INFORMATION
qJA +1
Derating Factor +1
0.016 +62.5°CńW
(17)
TAMax +TJMax *qJAPDmax +150 *62.5 (0.2) +137.5°C
(18)
TPA2005D1
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............................................................................................................................................................... SLOS369F JULY 2002 REVISED JULY 2008
Figure 37. Application Schematic With TPA2005D1 Summing Two Single-Ended Inputs
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factorfor the 2,5-mm x 2,5-mm MicroStar Junior package is shown in the dissipation rating table. Converting this to θ
JA
:
Given θ
JA
of 62.5 ° C/W, the maximum allowable junction temperature of 150 ° C, and the maximum internaldissipation of 0.2 W (worst case 5-V supply), the maximum ambient temperature can be calculated with equationEquation 18 .
Equation Equation 18 shows that the calculated maximum ambient temperature is 137.5 ° C at maximum powerdissipation with a 5-V supply; however, the maximum ambient temperature of the package is limited to 85 ° C.Because of the efficiency of the TPA2005D1, it can be operated under all conditions to an ambient temperatureof 85 ° C. The TPA2005D1 is designed with thermal protection that turns the device off when the junctiontemperature surpasses 150 ° C to prevent damage to the IC. Also, using speakers more resistive than 8- dramatically increases the thermal performance by reducing the output current and increasing the efficiency ofthe amplifier.
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BOARD LAYOUT
Component Location
Trace Width
MicroStar Junior™ BGA Layout
0,28
mm
0,38
mm
0,25
mm
SD
NC
IN+
IN−
GND GND
GND
GND GND
GND GND
VDD
VDD
Vo+
Vo−
Solder Mask
Paste Mask
Copper Trace
TPA2005D1
SLOS369F JULY 2002 REVISED JULY 2008 ...............................................................................................................................................................
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Place all the external components close to the TPA2005D1. The input resistors need to be close to theTPA2005D1 input pins so noise does not couple on the high impedance nodes between the input resistors andthe input amplifier of the TPA2005D1. Placing the decoupling capacitor, C
S
, close to the TPA2005D1 is importantfor the efficiency of the class-D amplifier. Any resistance or inductance in the trace between the device and thecapacitor can cause a loss in efficiency.
Make the high current traces going to pins VDD, GND, V
O+
and V
O-
of the TPA2005D1 have a minimum width of0,7 mm. If these traces are too thin, the TPA2005D1's performance and output power will decrease. The inputtraces do not need to be wide, but do need to run side-by-side to enable common-mode noise cancellation.
Use the following MicroStar Junior BGA ball diameters:0,25 mm diameter solder mask0,28 mm diameter solder paste mask/stencil0,38 mm diameter copper trace
Figure 38 shows how to lay out a board for the TPA2005D1 MicroStar Junior BGA.
Figure 38. TPA2005D1 MicroStar Junior BGA Board Layout (Top View)
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Product Folder Link(s): TPA2005D1