Frequency Range
Operating Temperature
Storage Temperature
Overall Frequency Stability
Supply Voltage (Vdd)
Jitter (12KHz - 20MHz)
ABRACON IS
ABRACON IS
ISO 9001 / QS 9000
ISO 9001 / QS 9000
CERTIFIED
CERTIFIED
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
30332
Esperanza, Rancho Santa Margarita, California
92688
tel 949-546-8000 | fax 949-546-8001 | www.abracon.com
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
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ABFM SERIES
STANDARD SPECIFICATIONS:
APPLICATIONS:
• Fiber Channel
• 12Gbit SERDES
• 10Gbit SERDES
• PCI Express
FEATURES:
• Based on a proprietary analog multiplier
• Tri-State Output
• Ultra low Phase Jitter
• 125MHz, 156.25MHz, 187.5MHz, and 212.5MHz applications
• 2.5V to 3.3V +/- 10% operation
• Ceramic SMD, low profile package
rev3.1-8/06
PARAMETERS
150 MHz to 280 MHz
0°C to + 70°C (see options)
- 55°C to + 125°C
± 50 ppm max. (see options)
2.25V - 3.63 V
RMS phase jitter < 0.3pS
period jitter < 20pS peak to peak typical
Low Phase Noise
Aging (PPM/year)
-130 dBc/Hz @ 1kHz Offset from 212.5MHz
-140 dBc/Hz @ 10kHz Offset from 212.5MHz
-145 dBc/Hz @ 100kHz Offset from 212.5MHz
TBD Per Crystal
5.0 x 7.0 x 1.8mm
Supply Current (IDD)[Fout = 212.50MHz]
Output Clock Duty Cycle @ VDD-1.3V
Output High Voltage
Output Low Voltage
Clock Rise time (tr) @ 20/80%
Clock Fall time (tf) @ 80/20%
85mA max.
45% min, 50% typical, 55% max.
VOH = (VDD-1.025V min)
VOL = (VDD-1.620V max)
0.2ns typical, 0.5ns max,
0.2ns typical, 0.5ns max
Supply Current (IDD) [Fout = 212.50MHz]
Output Clock Duty Cycle @ 1.25V
Output Differential Voltage (VOD)
VDD Magnitude Change (∆VOD)
Output High Voltage
Output Low Voltage
Offset Voltage [RL = 100
Ω
]
Offset Magnitude Voltage[RL = 100
Ω
]
Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V]
Output Short Circuit Current (IOSD)
Differential Clock Rise Time (tr) [RL=100
Ω
, CL=10pF]
Differential Clock Fall Time (tf) [RL=100
Ω
, CL=10pF]
55mA typical, 60mA max
45% min, 50% typical, 55% max
247mV min, 355mV typical, 454mV max
-50mV min, 50mV max
VOH = 1.4V typical,1.6V max
VOL = 0.9V min, 1.1V typical
VOS = 1.125V min, 1.2V typical, 1.375V max
∆VOS = 0mV min, 3mV typical, 25mV max
±1µA typical, ±10µA max
-5mA typ, -8mA max.
0.2ns min, 0.5ns typical, 0.7ns max
0.2ns min, 0.5ns typical, 0.7ns max
: PRELIMINARY
ABRACON IS
ABRACON IS
ISO 9001 / QS 9000
ISO 9001 / QS 9000
CERTIFIED
CERTIFIED
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
30332
Esperanza, Rancho Santa Margarita, California
92688
tel 949-546-8000 | fax 949-546-8001 | www.abracon.com
|||||||||||||||
ABFM SERIES
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
Dimensions: inch (mm)
MARKING:
- TUH Frequency: T=First “ten” digit of frequency, U=First “unit” of frequency, H=First “tenth” digit of freq,
Ex: 100 for 10.0MHz; 143 for 14.31818 MHz)
- ABFM ZYX
(Z: Month, A to L; Y: Year, 5 for 2005;
X: Traceability Code)
PIN ASSIGNMENTS:
STANDARD SPECIFICATIONS:
OPTIONS AND PART IDENTIFICATION
(Left blank if standard)
:
PECL & LVDS DRAWING:
Dimensions: inch (mm)
CMOS DRAWING:
ABFMX - Frequency - Temperature - Frequency Stability - Output - Tri-state pin output - Packaging
Packaging option:
T for Tape and Reel (1,000pcs/reel) T5 for Tape and Reel (500pcs/reel)
PIN # NAME DESCRIPTION
1
2
3
4
5
6
Tri-state
NC
GND
Q
Q
V
DD
Tri-state
No Connect
Ground
PECL, LVDS
Complimentary PECL, LVDS
VDD Connection
TRI-STATE PIN OPERATION:
OUTPUT TYPE OPTION PIN 1 LOGIC LEVEL* OUTPUT STATE
P
P1
V
C
PECL
PECL1
LVDS
CMOS
0 (Default)
1
1
0
0
1 (Default)
0
1 (Default)
Enabled
Tri-state
Enabled
Tri-state
Tri-state
Enabled
Tri-state
Enabled
*Connect to VDD from logic level "1", connect to ground for logic level "0".
Stability options:
R for ± 25 ppm max
Vdd options:
PIN # NAME
1
2
3
4
Tri-state
GND/Case
Output
Vdd
Supply Current (IDD)[at 100MHz, load 15pF]
Output Clock Duty Cycle @ 50%VDD
Output High Voltage (VOH) [IOH = -8.5mA]
Output Low Voltage (VOL) [IOL = 8.5mA]
Output Drive Current (IOSD) [VOL = 0.4V, VOH = 2.4V]
Output Clock Rise/Fall time [10% ~ 90% VDD w/10pF load]
Output Clock Duty cycle [Measured @ 50% VDD]
16mA typ., 20mA max.
45% min, 50% typical, 55% max.
2.4 min
0.4V max
8.5mA typ.
1.2nS typical, 1.6nS max.
45% min, 50% typical, 55% max.
Blank (3.3Vdc±10%V)
1 (2.5Vdc±10%V)
rev3.1-8/06
5.0 x 7.0 x 1.8mm
: PRELIMINARY
