AT89C5121-ICSUL - Atmel - Datasheet.Directory

Rev. 4164G–SCR–07/06

Features

•80C51 Core

– 12 or 6 Clocks per Instruction (X1 and X2 Modes)

– 256 Bytes Scr atchpad RAM

– Dual Data Pointer

– Two 16-bit Timer/Counters: T0 and T1

•T83C5121 w it h 16 Kbytes Mask ROM

•T85C5121 w it h 16 Kbytes Cod e RAM

•T89C5121 wit h 16 Kbytes Cod e RAM and 16 Kbytes EEPROM

•On-chip Expanded RAM (XRAM): 256 Bytes

•Versatil e Host Serial Interface

– Full -duplex Enhanc ed UART (EUART) with Dedicated Ba ud Rate Generator (BRG):

Most Standard Speeds up to 230K bits/s at 7.36 MHz

– Output Enable Input

– Multiple Logic Level Shifters Options (1.8V to V CC)

– Autom atic Level Shifter Option

•Multi-protocol Smart Card Interface

– Certi fied with Dedicated Firm wa re According to ISO 7816, EM V2000, GIE-CB, GSM

11.12V and WHQL Standards

– Asy nchronous Protocols T = 0 and T = 1 with Dir ect and Inverse Mod es

– Bau d Rate Generator Support ing All I S O7816 Speeds up to D = 32/F = 372

– Parity Error Det ection and Indica ti on

– Autom ati c Character Repetit ion on Parity Errors

– Programmable Tim eout Detection

– Card Clock Stop High or Low for Card Power-down Mode

– Support Synchronous Card with C4 and C8 Programmable Outputs

– Card Detection and Automatic De- activation Sequence

– Step-up/down Conve rte r wit h Progra mmabl e Voltage Output: 5V, 3V (± 8% at

60 mA) and 1.8V (±8% at 2 0 mA)

– Direct Connection to Smart Car d Terminal s:

Short Circuit Current Limitation

Logic Level Shifters

4 kV ESD Protecti on (MIL/ STD 833 Class 3 )

•Alte rnate Card Support with CLK, I/O a nd RST Accordi ng to GSM 11.12V Standard

•2x I/O Ports: 6 I/O Port1 and 8 I/ O Port3

•2x LED Outputs with Programmable Current Sources: 2, 4, or 10 mA

•Hardware Watchdog

•Reset Outp ut Inc ludes

– Hardware Watchdog Reset

– Power-on Reset (POR)

– Power -f ail Detector (PFD)

•4-level Priority Interrupt System with 7 Sou rces

•7.36 to 16 MHz On-c hip Oscillator with Clock Prescaler

•Absolute CPU Maximal F reque ncy : 1 6 MHz in X1 mode, 8MHz in X2 mode

•Idle and Pow er-down Modes

•Voltage Oper ation: 2.85V to 5.4V

•Low Power Consump ti on

– 8 mA Operat ing Current (at 5.4V and 3.68 MHz )

– 150 mA Maximum Current with Smart Card Power-on (at 16 MHz X1 Mode)

–30 μA Maximum Power-down Current at 3. 0V (without Smart Card)

–100 μA Maximum Power-down Current at 5.4V (without Smart Card)

•Temper ature Range

– Commercial: 0 to +70°C Operating Temperature

– Industrial: -4 0 to +85°C Op erating Temperature

•Packages

– SSOP24

–QFN32

– PLCC52

8-bit

Microcontroller

with Multi-

protocol Smart

Card Interface

T83C5121

T85C5121

T89C5121

AT83C5121

AT85C5121

AT89C5121

A/T8xC5121

4164G–SCR–07/06

Description T8xC5121 is a high performance CMOS ROM/CRAM derivative of the 80C51 CMOS

single chip 8-bit microcontrollers.

T8xC5121 retains the features of the At mel 80C51 with extended ROM capacity (16

Kbytes), 512 bytes of internal RAM, a 4-level interrupt system, two 16-bit timer/counters

(T0/T1), a full d uplex enhanced UART (E UART) with baud rate ge nerat or (BRG) and an

on-chip oscillator.

In addition, the T8xC5121 have, a Multi protocol Smart Card Interface, a dual data

pointer, 2 programmable LED current sources (2-4-10 mA) and a hardware Watchdog.

T89C51 21 Flash RA M version and T85C 5121 Code RAM version can be loaded by In-

System Programm ing (ISP) software residing in the on-chip ROM from a low-cos t e xter-

nal serial EEPROM or from R232 interface.

T8xC 5121 have 2 software-selectable modes of reduced activity for further re duction i n

power consumption.

Block Diagram

Figu re 1. Block Diagram

Notes: 1. Alternate function of Port 1

2. Alternate function of Port 3

3. Only for the Code RAM version

4. Only for PLCC52

Timer 0 INT

RAM

256 x8

RxD

TxD

XTAL2

XTAL1

EUART

CPU

Timer 1

INT1

Ctrl

INT0

C51

CORE

(2)(2) (2)(2)

IB-bus

RST

VSS

VCC

(1):

ROM

Xtal

Osc

XRAM

256

SCIB

CC8

CRST

CPRES

CIO

CC4

CCLK

CVCC

6 I/Os

CRST1

CIO1

CCLK1

(2)

(4)

16K x8 CRAM

16K x8

(2) (2)

8 I/Os

DVCC

Voltage

Reg.

(1)

LED

Drive

Direct

LED0

LED1

(2)

Output

:1-16

Clock

(3)

Prescaler

Watchdog

EVCC

CVSS

PSEN

ALE

DC/DC

Converter

Level

Shifters

POR

PFD

Alternate

Card

BRG

Parallel I/O Ports

A/T8xC5121

4164G–SCR–07/06

Pin D escripti on Fi gure 2. 24-pin SSOP Pinout

Fi gure 3. QF N32 Pinout

P1.1/CC8

P1.4/CCLK

P1.0/CIO

RST

P1.5/CRST

P1.3/CC4

P1.2/CPRES

XTAL1

P3.3/INT1/OE

P3.2/INT0

P3.4/T0

P3.5/CIO1/T1

CVCC

CVSS VCC

EVCC

VSS

P3.0/RxD

P3.1/TxD

13 P3.6/CCLK1/LED0

XTAL2

P3.7/CRST1/LED1

DVCC

N/C

QFN32

Vss

P1.1/CC8

P1.0/CIO

P1.2/CPRES

CVcc

P1.4/CCLK

P3.6/CCLK1/LED0

N/C

XTAL1

P3.7/CRST1/LED1

N/C

XTAL2

P3.5/CIO1/T1

P1.3/CC4

P1.5/CRST

Vcc

CVss

EVcc

N/C

DVcc

P3.4/T0

P3.0/RxD

28 27 26

1211109131415

RST 81617

Vss

P3.1/TxD

N/C

2529303132

N/C

P3.2/INT0

P3.3/INT1/OE

N/C

A/T8xC5121

4164G–SCR–07/06

Fi gure 4. PLCC52 P inout

21 22 26252423 292827 30 31

5 4 3 2 1 6 52 51 50 49 48

CVCC

VSS

DVCC

P0.1/AD1

P0.0/AD0

P0.2/AD2

P0.5/AD5

P0.6/AD6

P0.3/AD3

P0.4/AD4

P0.7/AD7

P3.6/CCLK1/LED0

P3.7/CRST1/LED1

XTAL1

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.2/A10

P2.1/A9

P2.0/A8

P3.0/RxD

P3.1/TxD

P1.5/CRST

P1.4/CCLK

P1.3/CC4

P1.2/CPRES

P1.1/CC8

P1.0/CIO

PSEN

ALE

P2.3/A11

7 47

20 32 33

35 P3.2/INT0

P3.3/INT1/OE

RST

XTAL2

P3.5/CIO1/T1

P3.4/T0

VCC

CVSS

VCC

VSS

EVCC

A/T8xC5121

4164G–SCR–07/06

Signals All the T8xC5121 signals are detailed in Table 1.

The port structure is described in Sec tion “Port Structure Description”.

Table 1. Ports Description

Port Signal

Name Alternate

Internal

Power

Supply ESD Type Description

P1.0 CIO CVCC 4 kV I/O Smar t card interface function

Card I/O.

I/O Input /Output func t io n

P1.0 is a bi-directional I/O port .

IReset co nfiguration

In pu t .

P1.1 CC8 CVCC 4 kV O Smar t card interface function

Card contact 8

OOutput function

P1.1 is a Push-pull port.

IReset co nfiguration

Input

P1.2 CPRES VCC 4 kV I Smar t card interface function

Card presence

I/O Input /Output func t io n

P1.2 is a bi-directional I/O port with internal pull-ups- ( External Pull-up

configuration can be selected).

IReset co nfiguration

Input (high level due to internal pull-up)

P1.3 CC4 CVCC 4 kV O Smar t card interface function

Card contact 4

OOutput function

P1.3 is a Push-pull port.

IReset co nfiguration

Input (high level due to internal pull-up)

P1.4 CCLK CVCC 4 kV O Smart card interface func tion

Card clock

I/O Input /Output func t io n

P1.4 is a a Push-pull port.

OReset co nfiguration

Output at low level

P1.5 CRST CVCC 4 kV O Smar t card interface function

Card reset

I/O Input /Output func t io n

P1.5 is a a Push-pull port.

OReset co nfiguration

Output at low level

A/T8xC5121

4164G–SCR–07/06

P3.0 RxD EVCC IUART function

Receive data input

I/O Input /Output func t io n

P3.0 is a bi-directional I/O port with internal pull-ups.

IReset co nfiguration

In put (hig h level)

P3.1 TxD EVCC OUART function

Transmit data output

OE ac tiv e at lo w or hi gh level dependin g of PMSOEN b its in SIO CON Reg.

I/O Input /Output func t io n

P3.1 is a bi-directional I/O port with internal pull-ups.

ZReset co nfiguration

High impedance du e to PMOS switched OFF

P3.2 INT0 DVCC I

External interrupt 0

INT0 input set IE0 in the TCON register . If bit IT0 in this register is set, bits IE0

are set by a falling edge on INT0. If bit IT0 is cleared, bits IE0 is set by a low

level on INT0.

I/O Input /Output func t io n

P3.2 is a bi-directional I/O port with internal pull-ups.

ITimer 0: Gate input

INT0 serves as external run control for Timer 0 when

selected in TCON register.

IReset co nfiguration

In put (hig h level)

P3.3 INT1 OE EVCC I

External Interrupt 1

INT1 input set OEIT in ISEL Register, IE1 in the TCON register.

If bit IT1 in this register is set, bits OEIT and IE1 are set by a falling edge on

INT1. If bit IT1 is cleared, bits OEIT and IE1 is set by a low level on INT1

UART function

Output enable. A low or high level (depending OELEV bit in

ISEL Register) on this pin disables the PMOS transistors of TxD

(P3.1) and T0 (P3.4 ). This function can be disabled by softw are

I/O Input /Output func t io n

P3.3 is a bi-directional I/O port with internal pull-ups.

ITimer 1 function: Gate input

INT1 serves as external run control for Timer 1 when

selected in TCON register.

IReset co nfiguration

In put (hig h level)

P3.4 T0 EVCC OUART function

OE ac tiv e at low or high level depending of PMSOEN

bits in SIOCON Reg.

Table 1. Ports Description (Continued)

Port Signal

Name Alternate

Internal

Power

Supply ESD Type Description

A/T8xC5121

4164G–SCR–07/06

I/O Input /Output func t io n

P3.4 is a bi-directional I/O port with internal pull-ups.

ITimer 0 function: External clock input

When Timer 0 operates as a counter, a falling edge on the T0 pin

increments the count .

ZReset co nfiguration

High impedance du e to PMOS switched OFF

P3.5 CIO1 DVCC I/O Alternate card function

Card I/O

I/O Input /Output func t io n

P3.5 is a bi-directional I/O port with internal pull-ups.

ITimer 1 function: External clock input

When Timer 1 operates as a counter, a falling edge on the T1 pin

increments the count .

IReset co nfiguration

Input (high level due to internal pull-up)

P3.6 CCLK1 LED0 DVCC OAlternate card function

Card clock

LED function

T he s e pin s ca n be dir ec tl y co nn ecte d t o th e cat hode of stan da r d

LED without ext ernal current limiting resistors. The typical curren t

of each output can be programmed by software to 2, 4 or 10 mA

(LEDCON register).

I/O Input /Output func t io n

P3.6 is a LED port.

IReset co nfiguration

Input at high level

P3.7 CRST1 DVCC OAlternate card function

Card reset

P3.7 CRST1 LED1 DVCC OLED function

T he s e pin s ca n be dir ec tl y co nn ecte d t o th e cat hode of stan da r d

LED without ext ernal current limiting resistors. The typical curren t

of each output can be programmed by software to 2, 4 or 10 mA

(LEDCON register).

I/O Input /Output func t io n

P3.7 is a a LED port.

IReset co nfiguration

Input at high level

Table 1. Ports Description (Continued)

Port Signal

Name Alternate

Internal

Power

Supply ESD Type Description

A/T8xC5121

4164G–SCR–07/06

RST VCC I/O Rese t input

Holding this pin low for 64 oscillator periods while the oscillator

is running resets th e device. The Port pi ns are driven to their reset

co nditi ons when a vo ltag e lower tha n VIL is applied, whether or

not the os cilla tor is running.

This pin has a n internal pull-u p resistor which allows t he de vice to be reset by

connecting a capacitor between this pin and VSS.This capacitor is optional

thanks to the internal POR which output a Reset as long as Vcc has not

reached the POR thr eshold level

Asserting RST when the chip is in Idle mo de or Power-d own mode

return s the chip to normal operation.

The output is active for at least 12 oscillator periods when an internal

rese t occur s.

XTAL1 VCC IInput to the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected

to this pin.

If an e x ternal oscil lator is used, its output is connect ed to this pin.

XTAL2 VCC OOutput of the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected

to this pin.

If an e x ternal oscillator is used, XTAL2 may be left uncon nected.

VCC PWR Supply volt age

VCC is u s ed to power the inter nal vol tage re gula tors and i nternal I/O’s.

LI PWR DC/DC input

LI must be tied to VCC through an external coil (typically 4, 7 μH) and pr ovide

the curr ent for the pump ch arge of the DC/DC converter.

CVCC PWR Car d Sup ply voltage

CVCC is the programmable voltage output for the Card interface.

It must be connected to an external decoupling capaci tor.

DVCC PWR Di gital Sup ply voltage

DVCC is used to supply the digital core and internal I/Os. It is

inte r nall y co nn ect ed to th e outp ut of a 3V regul a to r and must be conn ec te d t o

an ex te r na l de co upli ng capa ci tor.

EVCC VCC PWR Extra supply voltage

EVCC is used to supply the level shifters of UART interface I/O

pins. It must be connected to an external decoupling capacitor.

This reference voltage is generated internally (automatically or not),

or it can be connected t o an e x ternal voltage reference.

CVSS GND DC/DC ground

CVSS is used to sink high shunt currents from the external coil.

VSS GND Ground

Tab le 1. P orts Description (Continued)

Port Signal

Name Alternate

Internal

Power

Supply ESD Type Description

A/T8xC5121

4164G–SCR–07/06

ONLY FOR PLCC52 version

P0[7:0] AD[7:0] VCC I/O Input/Output function Port 0

P0 is an 8-bit open-drain bi-directional I/O port. Port 0 pins that

have 1s written to them float and can be used as high impedance

inputs. To avoid any parasitic current consumption, Floating P0

inputs must be pulled to VCC or VSS.

I/O Address/Data low

Mutiplexed Addr ess/Dat a LSB for extern al access

P2[7:0] A[15:8] VCC I/O Input/Output function Port 2

P2 is an 8-bit open-drain bi-directional I/O port with internal pull-ups

OAddress high

Address Bus MSB for external a ccess

P3.6 WR DVCC OWrite signal

Write signal asserted during external data memory write operation

P3.7 RD DVCC IRead signal

Read signal asserted during external data memory read operation

ALE VCC OAddress latch enable output

The falling edge of ALE strobes the address into external latch

PSEN PSEN VCC OP ro gr a m str o be enable

EA EA VCC IExternal access enable

This pin must be held low to force the device to fetch code from

external pro gram memory startin g at address 0000h. It is latched

during reset and cannot be dyna mically changed during oper ati on.

Tab le 1. P orts Description (Continued)

Port Signal

Name Alternate

Internal

Power

Supply ESD Type Description

A/T8xC5121

4164G–SCR–07/06

Port Structure

Description The different ports structures are described as follows.

Quasi Bi-directional Output

Configuration The default port output configuration for standard I/O ports is the quasi bi-directional out-

put th at is comm on on the 80C5 1 an d mo st o f its de rivati ve s. T his o utp ut ty pe c an b e

used as both an input an d outp ut without the need t o reconfigure the port. This is possi-

ble because when the port out puts a l ogic h igh, it i s weak ly driven, al lowing an externa l

dev ice to p ull th e pi n low . Wh en t he po rt o utput s a lo gic l ow state , it is driv en stron gly

and abl e to sink a fai rly large current . These fe atures are so mewhat s imilar to an ope n

drain output except that there are three pull-up transistors in the quasi bi-directional out-

put that serve different purposes. One of these pull-ups, called the weak pull-up, is

turned o n whenever the po rt latch for the p in contains a lo gic 1. The weak pull-up

so urces a very sm all current th at will pull the pin high if it is left float ing. A secon d pull-

up, called the medium pull-up, is turned on when the port latch for t he pin contains a

logic 1 and the pi n itself is also at a logic 1 level. This pull-up provides the primary

source current for a quasi bi-directional pin that i s outputting a 1. If a pin that has a logic

1 o n it is pull ed low by a n ex ternal d evice , the m edi um pul l-up tu rns o ff, and only the

weak pull-up remains on. In order t o pull the pin low under these conditions, the external

device has to sink enough current to overpower the medium pull-up and take the voltage

on the port pin below its input threshol d.

Figu re 5. Quasi Bi-directional Output Configuration

Pus h-pull Outp ut

Configuration The Push-pull output configur ation has the same pull-down structure as the quasi bi-

dire ction al outp ut m odes, but prov ide s a con tinuou s strong pull- up w hen t he port la tch

contains a logic 1. The Push-pull mod e may be use d when more source curre nt is

needed from a port output. The Push-pull port configuration is shown in Figure 5.

2 CPU

Input

Strong Weak Medium

CLOCK DELAY

Port latch

Data

PMOS

NMOS

A/T8xC5121

4164G–SCR–07/06

Figu re 6. Push-pull Output Configuration

LED Ou tp ut C on f ig urat i on The input only configuration is shown in Figure 7.

Figu re 7. LED Source Current Configuration

Note: The port can be configured in quasi bi-directional mode and the level of current can be programmed by means of LEDCON0

and LE DCON1 r egisters bef ore s wit ching the led on by writing a logical 0 in Port l atch.

Input

Strong

Port latch

Data

PMOS

NMOS

Port Lat ch

Data

Input

Data

LEDx.0

LEDx.1

Weak

2 CPU P

CLOCK DELAY PMOS Strong Medium

NMOS

LED1CTRL

LED2CTRL

A/T8xC5121

4164G–SCR–07/06

SFR Ma pping The Special Function Registers (SFR) of the T8xC5121 belongs to the following

categories:

• C51 core registers: ACC, B, DPH, DPL, PSW, SP

• I/O port registers: P0, P1, P2, P3

• Time r 0 registers: TCON , TH0, TH1, TMOD, TL0, TL1

• Serial I/O port registers: SADDR, SADEN, SBUF, SCON, BRL, BDRCON

• Power and clock control registers: PCON, CKRL, CKCON0, CKCON1, DCCKPS

• Interrupt system registers: IE0, IPL0, IPH0, IE1,IPL1, IP H1, ISEL

• Wa tchdog Timer 0: WDTRST, WDTPRG

• Others : AUXR, AUXR1, RCON

• Smar t C a r d Interfa ce : SCSR , SC CON/ SC ETU0, SCISR/SCETU1, SCI ER/SCIIR,

SCTBUF/SCRBUF, SCGT0/SCWT0, SCGT1/SCWT1, SCICR/SCWT2

• Po rt configuration: SIOCON, LE DCON

A/T8xC5121

4164G–SCR–07/06

Reserved

Tab le 2. SFR Addresses and Reset Values

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h FFh

F0h B

0000 0000 LEDCON

XXXX 00 00 F7h

E8h EFh

E0h ACC

0000 0000 E7h

D8h DFh

D0h PSW

0000 0000 RCON

XXXX OXXX D7h

C8h CFh

C0h C7h

B8h IPL0

XXX0 0000 SADEN

0000 0000 ISEL

0000 0100 DCCKPS

XXXX XX1 1 BFh

B0h P3

1111 1111 IE1

XXXX 0XXX IPL1

XXXX 0XX X IPH1

XXXX 0XXX

0SCWT0 *

1000 0000 0SCWT1 *

0010 0101 0SCWT2 *

0000 0000 IPH0

XXX0 0000

B7h

1SCGT0 *

0000 1100 1SCGT1*

0000 0000 1 SCICR *

0000 0000

A8h IE0

0XX0 0000 SADDR

0000 0000

SCTBUF*

0000 0000 SCSR

XXX0 1000

0 SCCON *

0X000 0 SCISR*

10X0 0000 0 SCIIR*

0X00 0000 CKCON1

XXXX 0XXX

AFh

SCRBUF

0000 000 1SCETU0

0111 0100 1SCETU1

0XXX 1SCIER *

0X00 0000

A0h P2

1111 1111 AUXR1

XXX XXX0 WDTRST

XXXX XXXX WDTPRG

XXXX X0000 A7h

98h SCON

XXX0 0000 SBUF

XXXX XXXX BRL

0000 0000 BDRCON

XXX0 0000 9Fh

90h P1

XX11 1111 SIOCON

00XX 0000 CKRL

XXXX 111X 97h

88h TCON

0000 0000 TMOD

0000 0000 TL0

0000 0000 TL1

0000 0000 TH0

0000 0000 TH1

0000 0000 AUXR

00XX XX00 CKCON0

X0X0 X000 8Fh

80h P0

1111 1111 SP

0000 0111 DPL

0000 0000 DPH

0000 0000 20 PCON

00XX XX00 87h

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

SCRS Bit (SCSR.0) (*)

0SFR value

1SFR value

A/T8xC5121

4164G–SCR–07/06

PowerMonitor T he Powe rMoni tor funct ion su pervis es the ev olutio n of the vo ltag es fee ding the m icro-

controller, and if needed, suspends its activity when the detected value is out of

specification.

It is gua ranteed to start up p roperly whe n T8xC 5121 is po wered up and preven ts code

execution errors when the power supply becomes lower than the functional threshold.

This section describes th e functions of the PowerMonitor.

Description In order to start up and to properly maintain the microcontroller operation, VDD ha s to be

stabil ized in the VDD opera ting range and t he os cillator ha s to be st abilised with a nom i-

nal amplitude compati ble wit h logic threshold.

This control is carried out during three phases which are the power-up, normal operation

and stop. It complies with the following requirements:

• It guarantees an operational Reset when the microcontroller is powered

• and a protection if the power supply goes out from the functional range of the

microcon troller.

Figu re 8. PowerMon itor Block Diagram

Power Monitor Diagr am The target of the Po werMo nitor is to su rvey the power su pply in order to detec t any volt-

age drops which are not in the target spe cification. This PowerMonitor block checks two

kind of situations that occur:

• During the power-up condition, when VDD is reach ing the product specification

• During a steady-state condition, when V DD is stable b ut disturbed by any

undesirable voltage drops.

Figure 9 shows some configurations that can be met by the PowerMonitor.

External

Pow e r Supply

DC to DC

3V Regulator

VDD

VCC

Intern a l RE S E T

Power-fail

Detector

Power-up

Detector

A/T8xC5121

4164G–SCR–07/06

Figu re 9. Power-Up and Steady-state Conditions Monitored

Such device when it is integrated in a microcontroller, forces the CPU in reset mode

when VDD reaches a voltage condition which is out of the specification.

The thresholds and their functi ons are:

•V

PFDP: the output voltage of the regulator has reached a m in imu m functional value

at the powe r -u p . The circuit le a ve s th e RESET mode.

•V

PFDM: the output voltage of the regulator has reached a low threshold functional

value for th e microcontrolle r. An internal RESET is set.

Glitch filt e r ing prevents th e system from RESET when short duration glitches are carried

on VDD power supply.

Th e ele ctri cal pa ra meter s VPFDP, VPFDM, trise, tfall, tG are spec ifie d in th e D Cpara met ers

section.

Power-up

Steady-state Condition

DVCC

Reset

VPFDP

VPFDM

VCC

trise tfall

Power-down

A/T8xC5121

4164G–SCR–07/06

Power Moni toring

and C lo ck

Management

For applications where power consum ption is a critical factor, three power modes are

provided:

• Idle mode

• Po wer-down mod e

• Clock Manag ement (X2 feature and Clock Prescaler)

• 3V Regulator Modes (pulsed or not pulsed)

Idle Mode An i nstruction that sets P CON.0 c auses the last inst ruction to be exec uted bef ore goi ng

into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but

not to the int errupt, Tim er 0, and Serial P ort func ti ons. The CPU st atus is pres erved i n

its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator

and all other reg isters maintain their data during Idle. The port pins hold the logical

state s they had at the time I dle was activated. ALE and P SEN hold at logic high levels.

There are two ways to terminate th e Idle. Activ ati on of any en abled interru pt will cause

PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be s er-

viced, and following RETI the next instruction to be executed will be the one following

the instruction that put the device into idle.

The flag bit GF0 can be used to give an indication if an interrupt occurred during norma l

opera tion o r during a n Idle . F or exam ple, an instruct ion that activa tes Idle ca n also s et

one o r both f lag bit s. Whe n Idle is term inated by an i nterrupt , the inte rrupt se rvice rou-

tine can exam ine the flag bits.

The other way of terminating the Idle mode is with a hardware reset. Since the clock

oscillator is still running, the hardware reset needs to be held active for only two

machine cycl es ( 24 osci ll ato r p e riod s) to co mplete the reset.

Power-down Mode

Ent e ring Powe r-dow n Mod e To save maximum power, a Power-down mode can be invoked by software (refer to

Table 3, PCON register).

In Po wer-down mode, the os cillato r i s stopp ed and the instruct ion tha t invoke d Pow er-

down mode is the last instruction executed. The internal RAM and SFRs retain their

value until the Power-down mode is terminated. VCC can be lowered to save further

powe r. Eith er a ha rdwa re reset or an exte rnal int errupt ca n ca use an e xit fro m Powe r-

down . To p roperly te rmina te Pow er-down, the res et or ext ernal int errupt s hould no t be

ex ecu ted be for e VCC is restored to its normal operating level and m ust be held active

long enough for the osc illat or to res ta rt and stabi lize.

Only external interrupts INT0 and INT1 are useful to exit from Power-down. For that,

interrupt must be enabled and configured as level or edge sensitive interrupt input.

Holding the p in low restarts the os cillator b ut bringing the pi n high com pl etes the exit as

det ailed in F igure 10. W hen b oth inte rrupts are enable d, the oscil lator rest arts as soon

as one of the two inputs is held low and Power-Down exit will be completed when the

first input will be released. In this case the higher priority interrupt service routine is

executed.

O nce the inter rupt i s serv iced, the nex t inst ructio n to be exec uted af ter R ETI w ill be t he

one following the instruction that put it into Power-down mode.

Exit from Power-down Mode Exiting from Power-down by external interrupt does not affect the SFRs and the internal

RAM content.

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4164G–SCR–07/06

The ports status under Power-down is the status which was valid before entering this

mode.

Th e IN T1 i nterrup t is a m ultiple xed i nput (see Inte rrupt para grap h) w ith CP RES (Car d

det ection) and Rxd (U ART Rx) . So these t hree inp uts can b e used to ex it from Pow er-

down mode . The configurations which m ust be set are detailed below:

• Rxd input:

– RXEN (ISE L.0) must be set

– E X1 (I E0 .2 ) mu st b e set

– A low level detected during more than 100 micros econds exit from Power-

down

• C PR ES input:

– PRSEN (ISEL.1) must be set

– EX1 (IEO .2) must be set

– E A (I E0 .7 ) mu st b e set

– In the INT1 interrupt vector, the CPLEV Bit (ISEL.7) must be inverte d

and PRESIT Bit (ISEL.5) must be reset.

Figu re 10. Po wer-down Exit Waveform

Exi ting from Pow er-down by rese t rede fines all the SF Rs, e xiting from Pow er-down by

external interrupt does no affect the SFRs.

Exiting from Power-down by either reset or external interrupt does not affect th e internal

RAM content.

Note: If idle mode is acti vated with Power-down mode (IDL and PD bits set), the exit sequence

is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and

idle mode i s not ent ered.

SCI Control Prior to entering Power-dow n mode, a de-activation of the Smart Card system must be

performed.

LED Contr ol Prior to entering Power-down mode, if t he LED mode output is used, the medium pull-up

must be disconnected by setting the LEDPD bit in the PCON Regist er (PCON 3).

Low Po wer Mode Only in Power-down mode, in order to reduce the power consumption, the user can

choose to select this low-power mode.

The activation reference is the following.

• First select the Low-power mode by setting the LP bit in the AUXR Register (AUXR.

• The act ivation of Power-down can then be done.

INT1

INT0

XTAL1

Power-dow n phase Osc illa tor restart phase Active phaseActive phase

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4164G–SCR–07/06

Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with

external program or data memory. Nevertheless, during internal code execution, ALE

sig nal is still generated.

Only in case of PLCC52 v ersion, in o rder to redu ce EMI , ALE s ignal can be disabl ed by

setting AO bit.

The A O bit is located in AUX R regist er at bit location 0 (Se e Table 4). As soon as A O is

set, ALE is no longer output but remains active during MOVX and MOVC instructions

and external fetche s. During ALE disabling, ALE pin is weakly pulled high.

Power Modes Control

Registers Table 3. PCON Regi ster

PCON (S:87h)

Power Configuration Register

Reset Va lu e = X0XX XX00b

76543210

SMOD1 SMOD0 - - LEDPD GF0 PD IDL

Bit

Number Bit

Mnemonic Description

7SMOD1

Double Baud Rate bit

Set to d ou bl e the B au d Rat e wh en T ime r 1 i s u sed an d mo de 1, 2 o r 3 is se le ct ed in

SCON register.

6SMOD0

SCON Select bit

When cleared, read/write accesses to SCON .7 are to SM0 bit and read/ writ e

accesses to SCON.6 are to SM1 bit.

When set, read/write accesses to SCON.7 are to FE bit and read/write accesses to

SCON.6 are to OVR bit. SCON is Serial Port Control register .

5Reserved

4Reserved

3 LEDPD LED Control Power-Down Mode bits

When cleaned the I/O pull-up is the standard C51 pull-up control. When set the

medium pull-up is disconnected.

2GF0

Gen era l-pu r pos e fla g 0

One use is to indicate wether an i nterrupt occurred during normal operation or

du rin g I dl e mo de.

1PD

Power-down Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Power-down mode.

If IDL and PD are both set, PD takes precedence.

0IDL

Idle Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Idle mode.

If IDL and PD are both set, PD takes precedence.

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Table 4. AUXR Register

AUXR (S:8Eh)

Auxili ar y Re gister

Rese t Value = 00XX XX00b

76543210

- LP - - - - EXTRAM AO

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6LP

Low Power mode selection

Clear to select stan dard mode

Set to select low consumption mode

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

1EXTRAM

EXT RAM select

(ONLY for PLCC52 version)

Clear to map XRAM datas in internal XRAM memory.

S et to map XRAM datas in exte rnal XR AM memo ry.

0AO

ALE Output bit

(ONLY for PLCC52 version)

Clear to restore ALE operation during internal fetches.

Set to disable ALE operation during internal fetches.

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Table 5. IE0 Register

IE0

Interrupt Enable Register (A8h)

Rese t Value = 0XX0 0000b

76543210

EA - - ES ET1 EX1 ET0 EX0

Bit

Number Bit

Mnemonic Description

7EA

Enable All interrupt bit

Clear to disa ble all int errupts.

S et to en ab le all in ter ru p ts.

If EA = 1, each interrupt source is individually enabled or disabled by setting or

clearing its interrupt enable bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4ES

Serial port Enable bit

Clear to disable serial port interrupt.

S et to en able serial por t int er ru pt.

3ET1

Timer 1 overflow interrupt Enable bit

Clear to disa ble Tim er 1 overflow interrupt.

Set to enable T imer 1 overflow interrupt.

2EX1

External interrupt 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

1ET0

Timer 0 overflow interrupt Enable bit

Clear to disa ble Tim er 0 overflow interrupt.

Set to enable T imer 0 overflow interrupt.

0EX0

External interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

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Table 6. ISEL Regi ster

ISEL (S:BAh)

Interrupt Enable Register

Rese t Value = 0X00 0000b

76543210

CPLEV - RXIT PRESIT OELEV OEEN RXEN PRESEN

Bit

Number Bit

Mnemonic Description

7 CPLEV

Card presence detection level

This bit indicates w hich CPRES level will bring a bout an inte rrupt

Set this bit to indicate that Card Presence IT will appear if CPRES is at high

level.

Clear this bit to indicate that Card Presence IT will appear if CPRES is at low

level.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

5 PRESIT Card presence detection interrupt flag

Set by hardware

Must be cleared by software

4RXIT

Received data interrupt flag

Set by hardware

Must be cleared by software

3 OELEV OE/INT1 signal active level

Set this bit to indicate that high level is active.

Clear this bit to indicate that low level is active.

2OEEN

OE /IN T1 inte rru pt dis ab le bit

Clear to disa ble INT1 int errupt

S et to enab le INT 1 interr u pt

1 PRESEN Ca r d pr es ence det e ction int e rr upt en able bi t

Clear to disable the card presence detection interrupt coming from SCIB.

S et to enab le the car d prese nc e detect io n int erru pt com in g from S CIB.

0RXEN

Received data Interrupt enable bit

Clear to disable the RxD interrupt.

S et to enab le the RxD interr up t

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4164G–SCR–07/06

Clock Management In order to optimize the power cons umption and the execution time needed for a specific

task, an internal prescaler feature and a X2 feature have been implemented between

the osc illat or and the CPU.

Fu nctional Block

Diagram Fi gure 11. Clock Generation Diagram

If CKRL<>7 then :

If CKRL = 7 then:

CKRL Prescalor Factor

210

112

014

FOSC

2(7-CKRL)

CKRL = 7

FCLK_Periph

FCLK_CPU

CKCON0

CKRL

FOSC

2x2

Osc.

XTAL1

XTAL2

FCLK CPU

–

FOSC

2x2()

-----------------

2 7 CKRL

–

()

-----------------------------------=

FCLK CPU

–

Fosc

2x2

--------------=

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X2 Feature The T8 xC5121 core needs only 6 clock periods per mach ine cycle. T his feature called

”X2” provides the following advantages :

• Divides frequency crystals by 2 (cheaper cryst als) while keeping same CPU power.

• Sa ves power consum ption while keeping same CPU power (oscillator power

saving).

• Sa ves power consum ption by dynamical ly dividing the operating frequenc y by 2 in

operating and idle modes.

• Increases CP U power by 2 while keeping same crystal frequency.

In order to keep the original C51 com patibility, a divider by 2 is inserted between the

XT AL1 signal and the ma in cloc k i nput of the core (phase generat or). This divi der may

be disabled by software.

Description The clo ck for the who le circuit and perip herals is first divided by t wo before be ing used

by the CPU core and the peripherals.

This allows any cyclic ratio to be acc epted on XTAL1 input. In X2 mode, as this divider is

bypassed, the signals on XTAL1 must have a cyclic ratio from 40 to 60%.

As shown in Figure 11, X2 bit is validated on the rising edge of the XTAL1÷2 to avoid

glitches when switching from X2 to standard mode. Figure 12 shows the switching mode

waveforms.

Figu re 12. M ode Switching Wav eforms

The X2 bit in t he CK CON0 reg ister (se e Table 9) allow s to switc h (if CKRL= 7) from 12

clock periods per instruction to 6 clock p eriods and vice versa.

The T0X2, T1X2, UartX2, and WdX2 bits in the CKCON0 register (see Table 9) and

SC X2 bit in t he CKCON1 regis te r (see Tab le 10) allow to sw itch from standa rd perip h-

eral speed (12 clock periods per peripheral clock c ycle) to fast peripheral speed (6 clock

periods per peripheral clock cycle). T hese bits are acti ve only in X2 mod e.

More i nformation about the X2 mod e c an be found in the app lication no te "How t o T ake

Advantage of the X2 Features in TS80C51 Microcontrol ler?".

XTAL1:2

XTAL1

CPU clock

X2 bit

X2 ModeSTD Mod e STD Mode

FOSC

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Clock Prescaler Before supplyin g the CPU and the peripherals, the main clock is divided by a factor 2 to

30 to reduce the CPU power consumption. This factor is controlled with the CKRL

Table 7. Examples of Factors

Clock Control Registers

Clock Prescaler Reg ister This register is used to reload the clock prescaler of the CPU and peripheral clock.

Table 8. CKRL Register

CKRL - Clock Reload Register (97h)

Reset Value = XXXX 11 1Xb

XTAL (MHz) X2 CPU CKCON0 CKRL Value Prescal er Factor FCLK_CPU, FCLK_Perip h

(MHz)

16 0 (reset mode) 07h 1 8

16 1 (X2 mode) 07h 1 16

16 1 07h 1 16

16 0 07h 1 8

16 0 06h 2 4

16 1 06h 2 8

76543210

- - - - CKRL CKRL CKRL -

Bit

Number Bit

Mnemonic Description

7 - 4 - Reserved

The value read from this bit is indeterminate. Do not set this bit.

3 - 1 CKRL

Clock Reload Register

Prescaler value

XXXX 000Xb: CKRL=7 and Division factor equals 14

XXXX 110Xb: CKRL=6 and factor equals 2

X XXX 111Xb: C KRL= 7 and divisio n facto r equal s 1

Reserved

The value read from this bit is indeterminate. Do not set this bit.

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4164G–SCR–07/06

Table 9. CKCON0 Register

CKCON0 - Clock Contro l Registe r (8Fh)

Rese t Value = X0X0 X000b

76543210

-WDX2- SIX2 - T1X2T0X2X2

Bit

Number Bit

Mnemonic Description

7-Reserved

6WDX2

Watchdog clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this

bit ha s no effec t)

Cleared to select 6 clock periods per peripheral clock c y cle.

Set to select 12 clock periods per peripheral clock cycle.

5-Reserved

4SIX2

Enhanced UART clock (Mode 0 and 2)

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this

bit ha s no effec t)

Cle ar to select 6 cloc k periods per periphe ral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

3-Reserved

2T1X2

Timer 1 clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this

bit ha s no effec t)

Cle ar to select 6 cloc k periods per periphe ral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

1T0X2

Timer 0 clo ck

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this

bit ha s no effec t)

Cle ar to select 6 cloc k periods per periphe ral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

0X2

CPU clock

Clear to select 12 clock periods per ma chine cycle (Standard mode) for CPU

and all the peripherals.

Set to select 6 clock periods per machine cycle (X2 mode) and to enable the

indivi dual peripherals "X2" bits .

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4164G–SCR–07/06

Table 10. CKC ON1 Register

CKCON1 - Clock Contro l Registe r (AFh)

Reset Value = XXXX 0XXXb

76543210

----SCX2---

Bit

Number Bit

Mnemonic Description

7-Reserved

6-Reserved

5-Reserved

4-Reserved

3SCX2

SCIB clock

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cy cle.

2-Reserved

1-Reserved

0-Reserved

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4164G–SCR–07/06

DC/DC Clock The DC/DC block needs a clock with a 50% duty cycle. The frequency mus t also respect

a value between 3.68 MHz and 4 MHz. The first requirement imposes a divider in the

clock path and the second cons traint is solved with the use of a prescale r.

Fi gure 13 . Functional Block Diagram

Clock Control Register T his register is used to reload the clock prescaler of the DC/DC convert er clock.

Table 11. DCCKPS Register

DCCKPS - DC/DC converter Reload Regis ter (BFh)

Reset Value = XXXX XX11b

Clock Prescaler Before supplying the DC/DC block, the oscillator clock is divided by a factor 2 to 5 to

ada pt the cloc k needed by the DC/D C converter. T his facto r is controlled with th e

DCCKPS register.

The presca ler factor must be chosen to match the requirement range which is 4MHz.

Table 12. Exam ple s of Factors

1FCLK_DC/DC

FOSC FOSC

2 to 5

(2 to 5)

DCCKPS

Address BFh

76543210

- - - - - - DCCKPS DCCKPS

Bit

Number Bit

Mnemonic Description

7:2 - Reserved

Do not use write those bits

1:0 DCCKPS

Clock Reload Register

Prescal er v alue

00b: Divi sion factor equals 2

01b: divisi on fac tor equals 3

10b: divisi on fac tor equals 4

11b: division factor equals 5 (r eset value whic h minimize the consump tion)

XTAL (MHz) DCCKPS Value Prescaler

Factor DC/DC Converter CLK (MHz)

800h2 4

12 01h 3 4

14.756 02h 4 3.689

16 02h 4 4

20 03h 5 4

A/T8xC5121

4164G–SCR–07/06

A/T8xC5121

4164G–SCR–07/06

Smart Card Interface Block (SCIB)

Introduction The S CIB provides all signals to directly interface a s mart card. Complianc e with the

ISO7816, EMV’2000, GSM and WHQL standards has been certified.

Both synchronous (e.g. memory card) and asynchronous smart cards (e.g. micropro-

cessor card) are supported. The component supplies the different voltages requested by

the smart card. The power-off sequenc e is directly m anaged by the SCIB.

The card presence switch of the smart card connector is used to detect card insertion or

card remo val. In case of card removal, the SCIB de-activates the smart card using th e

de-activation sequence. An interrupt can be generated when a card is inserted or

removed.

Any malfun ction is reported to th e microcont roller (interrupt + control re gister).

The differen t operating modes are configured by internal registers.

Main Features • Su pport of ISO/IEC781 6

• Charac te r mode

• 1 transmit buffer + 1 receive buffer

• 11 bits ETU counter

• 9 bits guard time counter

• 24 bits wa iting time counter

• Auto-character repetition on error signal detection in transmit mode

• Au to-error signal generation on parity error detection in receive mode

• Power-on and power-off sequence generation

• Manual mode to directly drive the card I/O

A/T8xC5121

4164G–SCR–07/06

Block Diagram The Smart Card Interface Block diagram is shown in Figure 14.

Fi gure 14 . SCIB Block Diagram

Functional Description The architecture of the Sm art Card Interface Block is detailed below.

Barrel Shifter It allows the translation between 1 bit serial data and 8 bits parallel data.

The barrel function is useful for character repetition since the character is still present in

the shifter at the end of th e character transmiss ion.

This shifter is able to shift the data in both directions and to invert the input or output

value in or der to manage both direct and inverse ISO7816-3 convention.

Coupled with the barrel shifter there is a parity checker and generator.

There are 2 regist ers conn ected to this barre l shifter, one for the trans mission a nd one

for the reception.

They act as buffers to relieve the CPU of timing constraints.

SCART FSM (Smart Card Asynchronous Receiver Transmitter Finite State Machine)

Th is is t he c ore of the de sign. I ts purpo se is to co ntro l the ba rrel s hifter. To sequ enc e

correctly the barrel shifter for a reception or a transmission, it uses the signals issued by

B arr e l s h if ter

SCI Registers

Scart

fsm

Interrupt generator

Pow er on

Pow er off

fsm

I/O

mux

IO (in)

IO (o ut)

CLK

RST

C4 (out)

Clk_iso

C8 (out)

CLK1

C4 (in)

C8 (in)

Waitin g time

counter

Guard time

coun

ter

Etu counter

VCARD

INT

Clk_cpu

A/T8xC5121

4164G–SCR–07/06

the different counters. One of the most important counters is the guard time counter that

gives time slots corresponding to the character frame.

It is enabled only in UART mode.

The transition from the receipt mode to the transmit mode is done automatically. Priority

is given to the transmission .

ETU Counter The E TU (Eleme ntary Timing Unit) counter controls the working frequency of the barrel

shifter, in fact, it generat es the enable signal of the barrel shifter.

It is 11 bits wide and t here i s a s pecia l com pens ation mod e ac tivated with the m os t s ig-

nificant bi t that allows non integer ETU value with a working clock equal to the c ard

clock .

But t h e decimal value is limi ted to a half clock cycle. In fact the bit d u ra tion is not fixed. It

takes turns in n clock cycles and n-1 clock cycles. The character duration (10 bits) is

also equal to 10*(n+1/ 2) clock cycles.

This allows to reach the required precision of the character duration specified by the

ISO7816 standard.

exampl e: F = 372 D = 32 = > ETU = 11.62 5 clock cycles.

ETU = (ETU[10-0] -0.5 * COMP)*f with ETU[10-0] = 12, COMP = 1 (bit 7 of SCETU1)

To achieve this clock rate we activated the compensation mode and we programmed

the ETU duration to 12 clock cycles.

The result will be a full characte r duration (10 bits) equal t o 11.5 clock cycles.

Gua rd Time Counter The minimu m time between the leading edge of the start bit of a character and the lead-

ing edge of the st art bi t of the follo wing character transmitted (Guard tim e) is controll ed

by one counter.

It is 9 b its wide and is incremented at the ETU rate.

Fi gure 15 . Guard Time Count er

ETU C ounter

SCGT1 SCGT0

GT[8:0]

Guard Time Counter Timeout

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4164G–SCR–07/06

Waiting Time Counter (WT) The WT counter is a 24 bits down counter which can be loaded with the value contained

in th e SCW T 2, SCW T1, SCW T0 re gisters . Its main p urpos e is tim e ou t sig nal ge nera-

tion. It is 24 b its wide an d is decrem ent ed at the ETU rate . T he ETU co unter acts as a

prescaler (See Figure 16) .

When the WT counter timeout, an interrupt is generated and the SCIB fu nction is

locked: reception and emission are disabled. It can be enabled by resetting the macro or

reloading the counter.

Figu re 16. Waiting Time Counter

The count er is loaded, if WTEN = 0, during the write of SCWT2 register.

This count er is available in both UART a nd manual mode s. But the behaviour depe nds

on the selected mode.

In manual mod e, the WTEN signal controls the start of the c ounter (rising edge) and the

stop o f the counter (falling edge). After a time ou t of the counter, a falling edge on

W TEN, a reload of SC WT 2 and a risin g edge of WTEN are nec ess ary to start aga in the

counter and to release the SCIB macro. The reload of SCWT2 transfers all SCWT0,

SCWT 1 and SC WT2 registers to the WT counter.

In UART mo de t here is an aut oma tic load on the start bit det ection. This a utomatic lo ad

is very usef ul for changing on-the-f ly the Timeout va lue since there is a reg iste r to hold

the load value. This is the case, for example, when in T = 1 a launch is performed on the

BWT Timeout on the start bi t of th e last transmitted ch aracter. But on the receipt o f the

first character an other time out value (CWT) must be used . For this, the new load value

of the waiting time counter must be loaded with CWT before the transmission of the last

character. The reload of SCWT[2-0] with the new va lue occu rs with WTEN = 1.

After a time out of the count er in UART mode, the restart is d one as in manua l mode.

The m axim um interval be twee n th e sta rt leading edge of a ch aracter a nd the s tart l ead-

ing edge of the next character is loaded in the SCWT2, SCWT1, SCWT0 registers.

In T = 1 mode, the CWT (character waiting time) or the BWT (block waiting time) are

loaded in the same registers.

The maxi mum time between tw o consecut ive start bit is WT[23:0] * ETU.

When used to check BWT according to ISO 7816, WT can be set between 971 and

15728651.

ETU Counter WT Counter Timeout

SCWT2 SCWT1 SCWT0

WT[23:0]

Load

WTEN

Start bit

UART

Write_SCWT2

A/T8xC5121

4164G–SCR–07/06

Fi gure 17 . T = 0 Mode

Fi gure 18 . T = 1 Mode

Power-on and Power-off FSM In this state, the machine applies the signals on the smart card in accordance with

ISO7816 standard.

To be able to power-on the SCIB, the card presence is mandatory.

Removal of the sm art card will automatically start the power-off sequence as d escrib ed

in Figure 19.

Fi gure 19 . SCI Deactivation Sequenc e after a Card Extraction

CHAR 1 CHAR 2

< W T

> GT

BLOC 1

CHAR 1 CH AR 2 CHAR n

BLOC 2

CHAR n+1 CH AR n+2 CHAR n+3

< CWT < BWT < CWT

Transmission Reception

VCC

RST

CLK

8 Clock Cycles

A/T8xC5121

4164G–SCR–07/06

Interrupt Gen erat or There are several s ources of interrup tion but the SCIB m ac ro-cell issues onl y o ne inter-

rupt signal: SCIB IT.

Fi gure 20 . SCIB Interrupt So urce s

Thi s signal is hi gh level a ctive. One o f the sources is able to set up the interru pt signa l

and this is the read of the Smart Card Interrupt register by the CPU that clears this

signal.

If during the read of the Sma rt Card In terrupt register an interrupt occurs, the set of the

corresponding bit i nto t he Smart Card Interrupt register and t he set of the interrupt signal

will be delayed after the read access.

Registers There are fourteen registers to control the SCIB macro-cell. They will be described in

the Section “DC/DC Converter”.

Some of the regist er widths a re greater than a byte. Despite the 8 bits access provided

by the BIU, the address mapping of this kind of reg ister respects the follo wing rule:

• The Lowest significant byte register is implemented at the higher address.

This implem entation makes access to the se regi sters easier when using high level pro-

gramm ing language (C,C+ +).

ESCTBI

CIccER

ESCWTI

ESCRI

ESCPI

ECVccER

Transmit buffer

copied to shift register

Output current

out of range

Output voltage

out of range

Timeout on WT

counter

Complete

transmission

Complete

reception

Parity error

detected

SCIB IT

ESCTI

A/T8xC5121

4164G–SCR–07/06

Other Features

Clock The Ck-ISO input must be in the range 1 - 5 MHz acc ording to ISO781 6.

The ISO Clock diagram and the configuration example s are shown in Figure 20.

Fi gure 21 . Clock Diagram of the SCIB Block

Table 13. E xamples of Settings for Clocks

Alternate Card A second card named "A lternate card" can be controlled.

The Clock signal CCLK1 can be adapted to the XTAL frequency. Thanks to the clock

prescaler which can divide the frequency by 1, 2, 4 or 8. The bits ALTKPS0 and

ALTKPS1 in SCSR Register are use d to set this factor.

Xtal ( MHz) X2 CKCON0

FCLK Cpu

+ FCLK Pe riph

( MHz) SCX2 Clk_ iso

(1 to 5 MHz)

40 2 0 2

4 1 (m od e X2) 4 0 4

81 8 1 4

11.05905.529512.7648

14.7456 0 7.3728 1 3.6864

160814

20 0 10 1 5

2 1

Clk_cpu

Clk_iso

SCIB

F4_8MHz

SCX2

CKCON 1.3

Reset value = 1

FCLK_CPU

FCLK_Periph

A/T8xC5121

4164G–SCR–07/06

Fi gure 22 . Alternate Card

Card Presence Input The internal pull-up on Card P resenc e in put can be disconnected in order t o reduce t he

consumption (CPRESRES, bit 3 in PMOD0).

In this case, an external resistor (typical ly 1 MΩ) m us t be externally tied to VCC.

CPRES input can generate an interrupt (see Interrupt syste m section).

The detecti on level can be selected.

SCIB Reset The SC ICR regist er contain s a reset bit. If set, thi s bit generates a reset of the SCI and

its registers. Table 15 shows the SCIB registers that are reseted and their reset value s.

Table 14. Reset Values fo r SCI Registers

SIM,SAM

CARD

Alternate

card

VCC

CRST

CIO

CCLK

CK_IDLE

CCLK1

SCSR Reg.

PR3

SCSR Reg.

ALTKPS0,1 SCCLK1

CK_IDLE

1, 2, 4 or 8

P3.6

Main

card

CPRES

SCICR 0000 0000b

SCCON 0X00 0000b

SCISR 1000 0000b

SCIIR 0X00 0000b

SCIER 0X00 0000b

SCSR XXX0 1000b

SCTBUF 0000 0000b

SCRBUF 0000 0000b

SCETU1, SCETU0 XXX X001b, 0111 0100b (372)

SCGT1, SCGT0 XXXX XXX0b, 0000 1100b (12)

SCWT2, SCWT1, SCWT0 0000 0000b, 0010 0101b, 1000 0000b (9600)

A/T8xC5121

4164G–SCR–07/06

DC/DC Converter The Smart Card supply voltage (CVCC) is gene rated by the integrated DC/DC c onverter.

It is controlled by sev eral registers:

• The register described in Section “SCICR Register” controls the CVCC voltage with

bits CVcc0, CVcc1

• The register described in Secti on “SCCON Register”, switches ON/OFF the DC/DC

converter with bit CARDV CC

• After the selection of the card voltage (CVcc[1:0]), the CARVCC bit is used to switch

on the DC\DC con verter. The CVccOK bit indicates th at the card voltage is within

the voltage range.

• It is mandatory to switch off the CVCC before entering in power-down mode.

A/T8xC5121

4164G–SCR–07/06

Reg iste rs Descr ipt ion Table 15. SCICR Register

SCICR (S:B6h, SCRS = 1)

Smart Card Interface Control Register

Rese t Value = 0000 0000b

76543210

RESET CARDDET CVcc1 CVcc0 UART WTEN CREP CONV

Bit Number Bit Mnemonic Descrip tion

7 RESET Reset

Set this bit to reset the SCIB and its configuration

6CARDDET

Card presence detector sense

Cl ea r t his bi t to i nd ic ate t h e ca rd p res en ce d ete ct or i s o pen ed whe n n o car d

is inserted (CPRES is high).

Set this bit to indicate the card presence detector is closed when no card is

inserted (CPRES is low).

5 - 4 CVcc[1:0]

Card Voltage Selection:

CVcc[1] CVcc[0] CVcc

000V

0 1 1.8V

10 3V

11 5V

3UART

Card UART selection

Clear this bit to use the Card I/O bit to drive the Card I/O pin.

Set this bit to use the Smart Card UART to drive the Card I/O pin.

Also controls the W ait Time Counter as described in Section “Waiting Time

Counter (WT)”

2WTEN

Wait ti me cou nter enable

Clear this bit to stop the counter and enable th e load of the Wait Time

counter hold registers.

Th e hol d regis te r s are load ed wi th S CWT0, SCWT1 a n d S CWT 2 v a lu es

when SCWT2 is written.

Set this bit to start the Wa it Time counter. The counters stop when it

reaches the timeout value.

If the UART bit is set, the W ait T ime counter automatically reloads with the

hold registers whenever a start bit is sent or received.

1 CREP

Character repetition

Clear this bit to disable p arity error detection and indication on the Card I/O

pin in receive mode and to disable character repetition in transmit mode.

Set this bit to enable parity error indication on the Card I/O pin in receive

mode and to set automatic character repetition when a parity error is

indicated in transmit mode. In receive mode, three times error indication is

performed and the parity error flag is set after four times parity error

detection. In transmit mode, up to three times character repetition is

allowed and the parity error flag is set after five times (reset configuration,

can be set at 4 using CREPSET bit in SCSR Register) consecutive parity

error indication.

0CONV

ISO convention

Clear this bit to use the direct convention: b0 bit (LSB) is sent first, the

parity bit is added after b7 bit and a low level on the Card I/O pin represent s

a “0”.

Set this bit to use the inverse convention: b7 bit (LSB) is sent first, the parity

bit is added after b0 bit and a low level on the Card I/O pin represents a “1”.

A/T8xC5121

4164G–SCR–07/06

Table 16. SCC ON Register

SCCON (S:ACh, SCRS = 0)

Smart Card Contacts Register

Rese t Value = 0X00 0000b

76543210

CLK - CARDC8 CARDC4 CARDIO CARDCLK CARDRST CARDVCC

Bit Number Bit Mnemonic Description

7CLK

Card Clock Selection

Clear this bit to use the CardClk bit (CARDCLK) to drive Card CLK pin.

Set this bit to use XTAL signal to drive the Card CLK pin.

Note: in ternal synchronization avo ids an y gli tch on the CLK pin when

switching this bit.

Reserved

The value read from this bit is indeterminate. Do not change this bit or write 0.

5 CARDC8 Card C8

Clear this bit to drive a low level on the Card C8 pin.

Set this bit t o set a high level on th e Card C8 pin.

4 CARDC4 Card C4

Clear this bit to drive a low level on the Card C4 pin.

Set this bit t o set a high level on th e Card C4 pin.

3 CARDIO

Card I/O

When the UART bit is cleare d in SCIC R Reg is te r, the valu e of thi s bit is

driven to the Card I/O pin.

Then this pin can be us ed as a pseudo bi-dir ecti onal I/O when this bit is set.

To be used as an input, this bit must contain a 1.

2CARDCLK

Card CLK

When the CLK bit is cleared in SCCON Register, the value of this bit is driven

to the Card CLK pin.

1 CARDRST

Card RST

Clear this bit to drive a low level on the Card RST pin.

Set this bit to set a high level on the Card RST pin.

Read is not allowed if VCARDOK=0

0 CARDVCC

Card VCC Control

Clear this bit to desactivate the Card interface and set its power-off. The other

bits of SCC register have no ef fect w hile this bit is cleared.

Set this bit to power-on the Card interface. The activation sequence shall be

handled by software.

A/T8xC5121

4164G–SCR–07/06

Table 17. S CISR Register

SCISR (S:ADh, SCRS = 0)

Smart Card UART Interface Status Register

Rese t Value = 1000 0000b

76543210

SCTBE CARDIN CIccOVF CVccOK SCWTO SCTC SCRC SCPE

Bit

Number Bit

Mnemonic Description

7SCTBE

SCIB transmit buffer empty

This bit is set by hardware when the Transmit Buffer is copied to the transmit shift

It is cleared by hardware when SCTBUF is written to.

6 CARDIN

Card presence status

This bit is set when a card is detected (debouncing filter has to be done in

software).

It is cleared otherwise.

5CIccOVF

ICC overflow on card

This bit is set when the current on card is above the limit

It shall be cleared by the hardware .

4CVccOK

Card voltage status

This bit is set when the output voltage is within the voltage range specified by

CV cc field.

It is c leared otherwise.

3SCWTO

Smart card wait Timeout

This bit is set by hardware when the Smart card wait time counter times out.

It shall b e cle ared by the r eload of the counter or by th e reset of the SCIB.

2SCTC

Smart card transmitted character

This bit is set by hardware when the Smart Card UART has transmitted a

character.

It shall be cleared by software after this register has been read.

1SCRC

Smart card received character

This bit is set by hardware when the Smart Card UART has received a character

It is cleared by hardware when SCBUF is read.

0SCPE

Smart card parity error

This bit is set at the same time as SCTI or SCRI if a parity error is detected.

It shall be cleared by software after this register has been read.

A/T8xC5121

4164G–SCR–07/06

Table 18. SCIIR Registe r

SCIIR (S:AEh, SCRS = 0)

Smart Card UART Interrupt

Identification Register (read only)

Rese t Value = 0X00 0000b

76543210

SCTBI - CIccERR CVccERR SCWTI SCTI SCRI SCPI

Bit

Number Bit Mnemonic Description

7SCTBI

SCIB t ra nsmit buffer interrupt

This bit is set by hardware when the Transmit Buffer is copied to the transmit

shift register of th e Smart Card UA RT.

It is cleared by hardware when this register is read.

Reserved

The value read from this bit is indeterminate. Do not change this bit or write 0.

5CIccERR

Card current status

This bit is set when the output current goes out of the current range.

It is cleared by hardware when this register is read.

4 CVccERR

Card voltage statu s

Thi s b it is s et w he n the o ut pu t vol t ag e goe s ou t o f the vol t age r a ng e speci f ie d

by C Vc c fi el d.

It is cleared by hardware when this register is read.

3SCWTI

Smart card wait Timeout interrupt

This bit is set by hardware when the Smart Card Timer 0 times out.

It is cleared by hardware when this register is read.

2SCTI

Smart card transmit interrupt

This bit is set by hardware when the Smart Card UART completes a

character tra nsmission.

It is cleared by hardware when this register is read.

1SCRI

Smart card receive interrupt

This bit is set by hardware when the Smart Card UART completes a

character reception.

It is cleared by hardware when this register is read.

0SCPI

Smart card parity error interrupt

This bit is set at the same time as SCTI or SCRI if a parity error is detected.

It is cleared by hardware when this register is read.

A/T8xC5121

4164G–SCR–07/06

Table 19. S CIER Register

SCIER (S:AEh, SCRS = 1)

Smart Card UART Interrupt Enable Register

Rese t Value = 0X00 0000b

765 4 3210

ESCTBI - CIccER ECVccER ESCWTI ESCTI ESCRI ESCPI

Bit Number Bit

Mnemonic Description

7 ESCTBI Smart Card UART Transmit Buffer Empty Interrupt Enable

Clear this bit to disable the Smart Card UART Transmit Buffer Empty interrupt.

Set this bit to enable the Smart Card UART Transmit Buffer Empty interrupt.

Reserved

The val ue read from this bit is indeterminate. Do not change th is bit .

5CIccER

Card Current Error Interrupt Enable

Clear this bit to disable the Card Current Error interrupt.

Set this bit to enable the Card Current Error interrupt.

4 ECVccER Card Volt age Error Interrupt Enable

Clear this bit to disable the Card Voltage Error interrupt.

Set this bit to enable the Card Voltage Error interrupt.

3 ESCWTI Smart Card Wait Timeout Interrupt Enable

Clear t his b it to disable the Smart Card Wait timeout interrupt.

Set this bit to enable the Smart Card Wait timeout interrupt.

2 ESCTI Smart Card Transmit Interrupt Enable

Clear this bit to disable the Smart Card UART Transmit interrupt.

Set this bit to enable the Smart Card UART Transmit interrupt.

1 ESCRI Smart Card Receive Interrupt Enable

Clear this bit to disable the Smart Card UART Receive interrupt.

Set this bit to enable the Smart Card UART Receive interrupt.

0 ESCPI Sm art Card Parity Error Interrupt Enable

Clear this bit to disable the Smart Card UART Parity Error interrupt.

Set this bit to enable the Smart Card UART Parity Error interrupt.

A/T8xC5121

4164G–SCR–07/06

Table 20. SCSR Regi ster

SCSR (S:ABh) Smart Card Selection Re gister

Rese t Value = XXX0 1000b

Table 21. SCT BUF Register

SCTBUF (S:AA, write-only, S CRS = 0) Smart Card Transmit Buffer Register

Rese t Value = 0000 0000b

76543210

- - - CREPSEL ALTKPS1 ALTKPS0 SCCLK1 SCRS

Bit

Number Bit

Mnemonic Description

7-Reserved

6-Reserved

5-Reserved

4 CREPSEL Char acter repetition selection

Clear this bit to select 5 times repetition before parity error indication

Set this bit to select 4 times repetition before parity error indication

3-2 ALTKPS1

ALTKPS0

Alternate Card Clock p rescaler fac tor

00ALTKPS = 0 : prescaler factor equals 1

01ALTK PS = 1: prescale r factor equals 2

10ALTKPS = 2: prescaler factor equals 4 (reset value)

11ALTKPS = 3: prescaler factor equals 8

1 SCCLK1 Alter na te car d cloc k sele ct io n

Set to select the prescaled clock ( CCLK1)

Clear to select the standar d port configur ation (P3.6)

0 SCRS Smar t ca r d re gis t e r se le cti o n

The SCRS bit select s which set of the SCIB registers is acces sed.

76543210

Bit Number Bit Mnemonic Description

––

Can store a new byte to be transmitted on the I/O pin when SCTBE is set.

Bit ordering on the I/O pin depends on the Convention (see SCICR

A/T8xC5121

4164G–SCR–07/06

Table 22. SCRBUF Register

SCRBUF (S:AA read-only, SCRS = 1)

Smart Card Receive Buffer Register

Rese t Value = 0000 0000b

Table 23. S CETU1 Register

SCETU1 (S:ADh, SCRS = 1)

Smart Card ETU Register 1

Rese t Value = 0XXX X001b

76543210

––––––––

Bit

Number Bit

Mnemonic Description

––

Provides the byte received from the I/O pin when SCRI is set.

Bit ord ering o n the I/O pin depends on the Convention (see SCICR Register).

76543210

COMP ––––ETU10 ETU9 ETU8

Bit

Number Bit

Mnemonic Description

7COMP

Compensation

Clear this bit when no time compensation is needed (i.e. when the ETU to Card

CLK period rat io is clos e to an integer wi th an error less than 1/4 of C ard CL K

period).

Set this bit otherwise and reduce the ETU period by 1 Card CLK cycle for even

bits.

6-3 – Reserved

The val ue read from these bits is inde terminate. D o not c hange these bits .

2-0 ETU[10:8] ETU MSB

Used together with the ETU LSB (see SCETU0 Register).

A/T8xC5121

4164G–SCR–07/06

Table 24. S CETU0 Register

SCETU0 (S:ACh, SCRS = 1)

Smart Card ETU Register 0

Rese t Value = 0111 0100b

Table 25. SCG T1 Regi ster

SCGT1 (S:B5h, SCRS = 1)

Smart Card Transmit Guard Time Register 1

Reset Value = XXXX XXX0b

Table 26. SCG T0 Regi ster

SCGT0 (S:B4h, SCRS = 1)

Smart Card Transmit Guard Time Regist er 0

Rese t Value = 0000 1100b

76543210

ETU7 ETU6 ETU5 ETU4 ETU3 ETU2 ETU1 ETU0

Bit

Number Bit

Mnemonic Description

7-0 ETU[7:0]

ETU LSB

The Elementary Time Unit is (ETU[10:0] - 0.5*COMP)/f, where f is the Card CLK

frequency.

According to ISO7816, ETU[10:0] can be set between 11 and 2047.

The defaul t reset value of ETU[10:0] is 372 (F = 372, D = 1).

76543210

–––––––GT8

Bit

Number Bit

Mnemonic Description

7-1 – Reserved

The val ue read from these bits is inde terminate. D o not c hange these bits .

0GT8

Tran smit Guard Time MSB

Used together with the Transmit Guard Time LSB (see SCGT0 Register).

76543210

GT7GT6GT5GT4GT3GT2GT1GT0

Bit

Number Bit

Mnemonic Description

7-0 GT[7:0]

Tran smit G uard Ti me LSB

The minimum time between two consecutive start bits in transmit mode is

GT[8:0] * ETU.

According to ISO 7816, GT can be set between 11 and 266 (11 to 254+12 ETU).

A/T8xC5121

4164G–SCR–07/06

Table 27. SCWT2 Register

SCWT2 (S:B6h, SCRS = 0)

Smart Card Character/Block Wait Time Register 2

Rese t Value = 0000 0000b

Table 28. SCWT1 Register

SCWT1 (S:B5h, SCRS = 0) Smart Card Character/Block Wait Time Register 1

Rese t Value = 0010 0101b

Table 29. SCWT0 Register

SCWT0 (S:B4h, SCRS = 0)

Smart Card Character/Block Wait Time Register 0

Rese t Value = 1000 0000b

76543210

WT23 WT22 WT21 WT20 WT19 WT18 WT17 WT16

Bit

Number Bit

Mnemonic Description

7-0 WT[23:16] Wait Time Byte 2

Used together with WT[15:0] (see SCWT0 Register).

76543210

WT15 WT14 WT13 WT12 WT11 WT10 WT9 WT8

Bit

Number Bit

Mnemonic Description

7-0 WT[15:8] Wait Time Byte 1

Used together with WT[23:16] and WT[7:0] (see SCWT0 Register).

76543210

WT7 WT6 WT5 WT4 WT3 WT2 WT1 WT0

Bit

Number Bit

Mnemonic Description

7-0 WT[7:0]

Wait Time Byte 0

WT[23:0] is the reload value of the Wait Time counter WTC.

The WTC is a general-purpose T imer 0. It is using the ETU clock and is

controlled by the WTEN bit (see Section “Waiting T ime Counter (WT)”).

When UART bit of SCICR Register is set, the WTC is automatically reloaded at

each start bit of the UART. It is used to check the maximum time between to

consecutive start bits.

A/T8xC5121

4164G–SCR–07/06

Inter r upt S yst em The T8xC5121 has a total of 6 interrupt vectors: four external interrupts (INT0, INT1/OE,

CPRES , RxD), tw o Timer 0 interrupts (Ti mer 0s 0 and 1), serial port interrupt and Smart

Card Interface interrupt. These interrupts are shown in Fig ure 23.

Figu re 23. I n terrupt Control System

Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the Interrupt Enable register (see Figure 32). This register also contains a

global disab le bit, which must be cleared to disable all interru pts at once.

Each in terrupt source can also be individ ually prog rammed to one of four priority levels

by setting or clearing a bit in the Interrupt Priority register (see Figure 36) and in the

Interrupt Priority High register ( see Figure 38). Table 30 s hows the bit values and pri ori ty

levels associa ted with each combination.

Table 30. Pri ority Level Bit Values

Interrupt

Polling

Sequence

TF0

INT0

TF1

IP H0, IPL 0

IE0

Individual

Enable Global

Enable

Low Priority

Interrupt

High Priority

Interrupt

INT1/OE

CPRES

Rxd

RXEN

SCI

RXIT

CPLEV

EX0

ET0

EX1

ET1

ESCI

OEEN

1IE1

PRESEN

OELEV

IT1

IT0

TCO N reg.

TCO N Reg.

PRESIT

The selection bit s

except IT1 (T CON)

are in ISEL Reg.

IPH1, IPL1

IPH.x IP.x Interrupt Level Priority

0 0 0 (Lowest)

01 1

10 2

1 1 3 (Hi ghest)

A/T8xC5121

4164G–SCR–07/06

A low -p riority i nterrupt can be interrupted by a high priority interrupt, but not by anot her

low-p riority inte rrupt. A high-pr iority interru pt can’t be i nterrup te d by a ny other inte rrupt

source.

If two interrupt requests of different priority levels are received simultan eously, the

reques t of higher priority level is serviced. If interrupt re quests of the same priority level

ar e received simul taneous ly, an in terna l polling sequenc e determ ines wh ich requ est is

se rviced. Thu s within ea ch priori ty l evel there i s a seco nd priorit y st ructu re determ ined

by the polling sequence.

Table 31. I n terrupt Vector Addresses

INT1 Interrupt Vector T he INT 1 interrupt is m ul tiplexed with the three follo wing inputs:

•INT1/OE

: Standard 8051 interrupt input

• Rx d: Received data on UART

• CPR ES: Insertion or removall of the main card

The setting conf igurations for each input is detailed below:

INT1/OE Input T his interrupt input is active under the following conditions:

• It must be enabled thanks to OEEN Bit (ISEL Register)

• It can be active on a level or falling edge: thanks to IT1 Bit (TCON Register)

• If level triggering selection is set, the active level 0 or 1 can be selected with OELEV

Bit (ISE L Register)

The Bit IE1 (TCON Reg ister) is set by h ard ware when external interrupt detected. It is

cleared when interrupt is processed.

Rxd Input A seco nd vec tor in terrupt i nput is the rec eption of a character. UART Rx in put c an gen-

erate an interrupt if enabled with Bit RXEN (ISEL.0). The global enable bits EX1 and EA

must also be set.

The n, the Bi t RXI T (ISEL R egister) i s set by ha rdwa re when a low le vel is de te cted o n

P3.0/RXD inp ut.

CPRES Input The t hird input is the detec tion of a level change on CPRE S input (P1.2). This input can

generate an interrupt if enabled with PRESEN (ISEL .1), EX1 ( IE0 .2) and EA (IE0.7) Bit s.

This detection is done according to the level select ed with Bit CPLEV (ISEL.7).

Then the Bit PRESIT (ISEL.5) is set by hardware when the triggering conditions are

met. This Bit must be cleared by software.

Interrupt Source Vector Address

IE0 0003h

TF0 000Bh

IE1 & RxIt & PrIt 0013h

TF1 001Bh

RI & TI 0023h

SCI 0053h

A/T8xC5121

4164G–SCR–07/06

Table 32. IE0 Regist er

Rese t Value = 0XX0 0000b

Bit addressable

76543210

EA - - ES ET1 EX1 ET0 EX0

Bit

Number Bit

Mnemonic Description

7EA

Enable All interrupt bit

Cle ar to disa ble all int e r rupts.

Set to enable al l interrupts.

If EA = 1, each interrupt source is individually enabled or disabled by setting or

clearing its interrupt enable bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4ES

Serial port Ena ble bit

Clear to disable serial port interrupt.

Set to enable serial port interr upt.

3ET1

Timer 1 overflow interrupt Enable bit

Cle ar to di sabl e Timer 1 ov er fl ow in ter rup t.

Set to enable Time r 1 ov erflow in terr upt.

2 EX1 External interrupt 1 Enable bit

Cle ar to disa bl e exter n a l in te r ru pt 1.

Set to enable ex ternal interr upt 1.

1ET0

Timer 0 overflow interrupt Enable bit

Cle ar to di sabl e Timer 0 ov er fl ow in ter rup t.

Set to enable Time r 0 ov erflow in terr upt.

0 EX0 External interrupt 0 Enable bit

Cle ar to disa bl e exter n a l in te r ru pt 0.

Set to enable ex ternal interr upt 0.

A/T8xC5121

4164G–SCR–07/06

Table 33. IE1 Regist er

Reset Value = XXXX 0XXXb

76543210

----ESCI---

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3ESCI

SCI Inte rrupt Ena ble

Clear to disable the SCI interrupt.

Set to enable the SCI interrupt.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

A/T8xC5121

4164G–SCR–07/06

Table 34. TCON Register

TCON (S :88h)

Timer 0/Counter Control Register

Rese t Value = 0000 0000b

76543210

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Bit

Number Bit

Mnemonic Description

7TF1

Timer 1 Overflow flag

Cleared by the hardware when processor vectors to interrupt routine.

Set by the hardware on Timer 0/Counter overflow when Timer 1 register

overflows.

6TR1

Timer 1 Run Control bit

Clear to turn off Timer 0/Counter 1.

Set to turn on Timer 0/Counter 1.

5TF0

Timer 0 Overflow flag

Cleared by the hardware when processor vectors to interrupt routine.

Set by the hardware on Timer 0/Counter overflow when Timer 0 register

overflows.

4TR0

Timer 0 Run Control bit

Clear to turn off Timer 0/Counter 0.

Set to turn on Timer 0/Counter 0.

3IE1

Interrupt 1 Edge flag

Cleare d by the hardware when interrupt is processed if edge-t riggered ( s ee I T1).

Set by the hardware when external interrupt is detected on the INT1 pi n.

2IT1

Interrupt 1 Type Co ntrol bit

Clear to select low level active (level triggered) for ex ternal int errupt 1 (IN T1).

Set to select falling edge active (edge triggered) for external interrupt 1.

1IE0

Interrupt 0 Edge flag

Cleare d by the hardware when interrupt is processed if edge-t riggered ( s ee I T0).

Set by the hardware when external interrupt is detected on INT0 pi n.

0IT0

Interrupt 0 Type Co ntrol bit

Clear to select low level active (level triggered) for ex ternal int errupt 0 (IN T0).

Set to select falling edge active (edge triggered) for external interrupt 0.

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4164G–SCR–07/06

Table 35. I SEL Register

Rese t Value = 0000 0100b

76543210

CPLEV OEIT PRESIT RXIT OELEV OEEN PRESEN RXEN

Bit

Number Bit

Mnemonic Description

7 CPLEV

Card presence detection level

This bit indicates which CPRES level will bring about an interrupt

Set this bit to indicate that Card Presence IT will appear if CPRES is at high

level.

Clear this b it to indicate that Card Presence IT will appear if CPRES is at low

level.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

5 PRESIT Card p resence detection inte rru pt flag

Set by hardware

Mu st be cleared by softw are

4RXIT

Received data interrupt flag

Set by hardware

Mu st be cleared by softw are

3 OELEV OE/INT1 signal active level

Set this bit to indicate that high level is active.

Clear this bit to indicate that low level is active.

2OEEN

OE/I N T1 Inte rru p t Disab le bit

Clear to disabl e INT1 inte rrup t

Set to enable INT1 interrupt

1 PRESEN Card presence d etection Interrupt Enable b it

Clear to disable the card presence detection interrupt coming from SCIB.

Set to enable the card presence detection interrupt coming from SCIB.

0RXEN

Received data Interrupt Enable bit

Clear to disable the RxD interrupt.

Set to enable the RxD i nterr upt (a min imal bit width of 0.1 ms is required to

wake up from Power-Down).

A/T8xC5121

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Table 36. IPL0 Regist er

Rese t Value = XXX0 0000b

Bit addressable

76543210

- - - PSL PT1L PX1L PT0L PX0L

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4 PSL Serial port Priority bit

Refer to PSH for priority level.

3PT1L

Timer 1 ove rflow inte rr upt Prio rity bit

Refer to PT1H for priority level.

2PX1L

External interrupt 1 Priority bit

Refer to PX1H for priority level.

1PT0L

Timer 0 ove rflow inte rr upt Prio rity bit

Refer to PT0H for priority level.

0PX0L

External interrupt 0 Priority bit

Refer to PX0H for priority level.

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Table 37. IPL1 Regist er

Reset Value = XXXX 0XXXb

Bit addressable

76543210

----PSCIL---

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3 PSCIL Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

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Table 38. IPH0 Register

Rese t Value = XXX0 0000b

76543210

- - - PSH PT1H PX1H PT0H PX0H

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4PSH

Serial port Priori t y High bit

PSH PS Priority Level

00Lowest

1 1 Highest

3PT1H

Timer 1 overflow interrupt Priority High bit

PT1H PT1 Priority Level

00Lowest

1 1 Highest

2PX1H

External interrupt 1 Priority High bit

PX1H PX1 Priority Level

00Lowest

1 1 Highest

1PT0H

Timer 0 overflow interrupt Priority High bit

PT0H PT0 Priority Level

00Lowest

1 1 Highest

0PX0H

External interrupt 0 Priority High bit

PX0 HPX0 Priority Level

00Lowest

1 1 Highest

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Table 39. IPH1 Register

Reset Value = XXXX 0XXXb

76543210

----PSCIH---

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3 PSCIH

SCI Inte rrupt Priori t y level most si gni fica nt bit

PSCIH PSCIL Prio ri ty le ve l

00Lowest

1 1 Highest priority

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

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LED Po r ts

Configuration The current source of the LED Ports can be adjusted to 3 different values: 2, 4 or 10 mA.

The LED o utpu t is an al terna te fun ction of P3.6 an P3 .7 an d canno t be u sed w hile the

alternate card function is used.

The control register LEDCON is detailed below.

Registers Definition Tabl e 40. LE DCON Register

Reset Value = XXXX 00 00b

76543210

----LED1[1]LED1[0]LED0[1]LED0[0]

Bit

Number Bit

Mnemonic Description

7 - 4 - Reserved

The value read from this bit is indeterminate. Do not set this bit.

3 - 2 LED1[1,0]

Port LED1 configuration:

LED1[1] LED1[0] Configuration

0 0 Standard C51 port

0 1 2 mA curre nt source when P3.7 is at Low Level

1 0 4 mA curre nt source when P3.7 is at Low Level

1 1 10 mA current source when P3.7 is at Low Level

1 - 0 LED0[1,0]

Port LED0 configuration:

LED0[1] LED0[0] Configuration

0 0 standard C51 port

0 1 2 mA curre nt source when P3.6 is at Low Level

1 0 4 mA curre nt source when P3.6 is at Low Level

1 1 10 mA current source when P3.6 is at Low Level

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Dual Data Pointer T8xC5121 contains a Dual Data Pointer accelerating data memory block moves. The

Standard 80C52 Data Pointer is a 16-bit value that is used to address off-chip data RAM

or peripherals. In T8xC5121, the standard 16-bit data pointer is called DPTR and

loca ted at SF R location 82H a nd 83H. The second Data Pointer named DPTR1 is

located at the same address than the previous one. The DPTR select bit (DPS / bit0)

chooses the active pointer and it is located into the AUXR1 register. It should be s er-

viced in those sections of code that will periodically be executed within the time required

to prevent a WDT reset.

The user s witc hes bet ween da ta po inters b y toggling the LS B of the AUXR1. Th e incre-

ment (INC) is a solution for this. All DPTR-related instructions use the currently selected

DPT R for any activity. Therefore only one instruction is required to switch from a source

to a de stination addres s. Using the Du al Data Point er sa ves code an d resources whe n

moves of blocks need to be accomplished.

The seco nd Data Pointer can be used to address the on-chip XRAM.

Table 41. DPL Register

DPL - Low Byte of DPTR1 (82h)

Rese t value = 0000 0000b

Table 42. DP H Register

DPH - High Byte of DPTR1 (83h)

Rese t value = 0000 0000b

76543210

--------

76543210

--------

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Table 43. AUXR 1 Regi ster

AUXR1 - Dual Pointer Selection Register (A2h)

Reset value = XXXX XXX0b

76543210

-------DPS

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

0DPS

Data pointer 1

Cle ar to sele ct DPTR0 as Data Poin te r.

Set to select DPTR1 as Data Pointer .

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Me m or y Ma na gement

Program Memory All the T8xC 5121 versions implement 16 Kb ytes of ROM memory, 256 Byte s RA M and

256 Bytes XRAM.

The hardware configuration byte and the split of internal memory spaces depends on

the product and is detailed below.

ROM Configuration Byte Table 44. ROM Configuration Byte Hardware Register

The BL JRB depen ds of the produc t version :

•1: ROM mask version

• 0: EEPROM/CRAM versions

This bi t defines if, after reset, ei ther the Customer ROM program or t he B ootload er pro-

gram is executed (for In System programming).

Program ROM Lock Bits The program Lock system protects the on-chip program against software piracy.

The T8xC5121 products are delivered with the highest protection level.

Table 45. T8x C5121 P roducts P rotection Level

P = Prog ramm ed

76543210

-BLJRB-----

Bit

Number Bit

Mnemonic Description

7Reserved

6BLJRB

Bootloader Jump RAM Bit

S et to config ur e User C od e in R O M

Clear t o configure Bootlader in ROM

5-0 Reserved

Pr ogram Lock Bits Protection Desc ription

Security

Level LB1 LB2

3PP

SSOP24 version:

Read function is disabled.But checksum control is still enabled

PLC C5 2 ver sio n:

M OVC instructio n execut ed from external pro gram m emory are disabled

from fetching code bytes from internal memory,

EA i s sa m ple d an d latch ed on r es et.

But checksum control is stil l enab led.

External execution is po ssib le.

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Me m ory Mapping In the products versions, the following internal spaces are defined:

•RAM

•XRAM

• CRAM : 16 KBy tes Pr og r a m RAM Memory

•ROM

The spec ific accesses from/to these memo ries are:

• XRAM: if the bit RPS in RCON (described below) is reset, MOVX instruct ions

address the XRAM space.

• CRAM: if the bit RPS in RCON is set, MOVX instructions address the CRAM

space.

Table 46. RCON Register

Reset Value = XXXX 0XXXb

T89C5121 Flash ROM Ve rsion Three memory blocks are implemented

• An inte r na l se rial EEPROM can be loaded from external with the application

program.

• The ROM me mory contains the Bootloader program. The entry poin t is l ocated at

address F800h. The lower 14K Bytes betwee n address C000 h and F7FFh is, also,

used for the Bootloader program.

• The CRAM is the application program memory. This memory is mapped in the

External RAM spa ce. The bit RPS in RCON (SFR address 0D1h) is set to map the

CRAM space during M OVX instructions

For first programming or an update, the program can be downloaded in the internal

EEPROM (and in the CRAM) fro m an external device:

• Eithe r an external EEPR OM if detected

• or from a host through RS232 serial commun ication.

For this purpose, an In-System Programming (ISP ) is supplied in a Bootloader. This

Bootloa der is program masked in ROM spac e.

The Hardware Byte BLJRB v alue is 0.

As described on page 7, after Reset, the Bootloader program is executed .

76543210

-- RPS

Bit

Number Bit

Mnemonic Description

7-4 - Reserved

The value read from this bit is indeterminate. Do not set this bit.

3RPS

CRAM space map bit

S et to ma p t h e CRAM spa c e during MO VX ins truc tions

Clear to map the Data space during MOVX. This bit has priority over the EXTRAM

bit.

2-0 - Reserved

The value read from this bit is indeterminate. Do not set this bit.

A/T8xC5121

4164G–SCR–07/06

If a serial communication device (as described above: TWI or RS232) is detected, the

program downl oad its content in the internal EEPROM and in CRAM.

Else, t he p rogram is internal ly downloaded from the internal EEPROM into the program

CRAM memory ( 1 6 Kb y tes)

Then, in the two cases, the B ootloader exec ute s a Long Jum p at ad dress 0000h wh ich

initializes the Program counte r at the lower address (0000h) of the executable CR AM.

Fi gure 24 . CRAM with ROM and EEPRO M M emory Mapping s

T85C121 Code RAM Ver sion Two memory blocks are implemented:

• The ROM me mory contains the Bootloader program.

• The CRAM is the Application program memory.

Afte r Rese t, the program is downloa ded, a s described in last paragrap h, from either an

external EEPROM or from an host connected on RS232 serial link into the program

CRAM m em ory of 16 K bytes. Th en t he P rogram Counter is s et at address 00 00h of t he

CRAM space and the program is executed.

16 Kbytes

256 bytes

0000h

3FFFh

CRAM XRAM RAMROM

FFFFh

F800h

C000h

entry point

Bootloader

256 byte s

A/T8xC5121

4164G–SCR–07/06

Fi gure 25 . CRAM and ROM Mappings

T83C5121 wi th Mask ROM

Version I n this version, the customer program is masked in 16 Kbytes ROM.

• The cus tomer program is masked in ROM during the final production phase. The

ROM size will be determined at mask generation process depending of the program

size.

In-System Programming Th e In -Sys tem Pro gram mi ng (IS P) mod e is o nly i mpl eme nted i n th e f ollowi ng pr od uct

versions:

• EEPROM version

• CRAM version

(The ROM product version is masked with the customer program and does not need

ISP mode)

The ISP is used to download an Application program in the device and to ru n it.

The comm uni cation protocols which are implement ed are: UART and TWI.

Hardware Interface The hardware in relation with the two com m unicat ion protocols is detailed below:

• TWI protocol

• Serial protocol

16K bytes

0000h

3FFFh

CRAM XRAM RAMROM

FFFFh

C000h Bootloader

F800h entry point

256 byte s 256 by tes

A/T8xC5121

4164G–SCR–07/06

Figu re 26. Hardware in Relation with the Two Communica tion Protocols

EEPROM Mapping The 16K Bytes EEPROM mappi ng is the foll owing :

The three last bytes are reserved respectively:

• So ftware Security Byte: a ddress 3FFDh

• CRC Bytes: address 3 FFEh and 3FFF h

The use of these bytes is described in the following paragraphs.

Theref ore, the User Program must be mapped f rom 0000h to 3FFCh addres s.

EEPROM external

TWI

DVCC or Ext. VCC (3V)

In ternal EEPROM

AT24C128

VCC

VSS

DVCC or Ext.VCC (3V)

A0 = A1 = 0

wp = 0

SDA

SCL

TWI

Optional

Thanks to internal pull-ups

DVCC

VCC

P2.1

P2.0 (A0 = 1,A1 = 0)

DVss Wp = 1

AT24C128

(default values if not tied)

P3.2/INT0

UART

BOOTLOADER

Address = 01h

Address = 00h

ISP Software Tool

SDA

SCL

P3.7/CRST1

3FFD

3FFE

3FFF

0000h

Reserved address

A/T8xC5121

4164G–SCR–07/06

Bootloader Funct ional

Diagram As described in Section “ ROM Configuration Byte”, page 60a ROM bit B LJRB (Boot

Loader Jump ROM Bit) defines which product version is. The Bootloader program is

mappe d in RO M spac e from addres s C000h up t o FFFFh and t he entry p oint is locat ed

at address F800h.

Figu re 27. Bo otloader Flow ch art

ACK?

E2P R O M at 00

ACK?

E2PROM at 01

Error: No TWI or serial device detected

U Character

received on UART

Serial communication is detected thanks to

Time Elapsed

Internal E2PROM (at 00) is detected

Bootloader

Execution

RESET

ROM program

Execution

BLJRB = 1

ROM Bit

ROM

RAM+ROM RAM+ROM (Pre-prod: Application Program)

F800h

versions:

ROM

0000h

External E2PROM (at 01) is detected

(Prod)

RAM,ROM,EEPROM

A serial code is sent on RD pin (P3.7)

Versions:

SSB & P3.7 test

TWI

ext.bypassed?

bypassed?

SSB & P3.6 test

UART bypassed

bypassed?

Progra m is downloaded from

External EEPROM into internal

An ISP Software can be used from

a PC to program the part.

Atmel FLIP software is available

Progra m is downloaded from

internal EEPROM in CRAM and

executed

EEPROM and CRA M

and executed.

RD port = Erro r code =

22h

Autobaud feature (Table52)

A/T8xC5121

4164G–SCR–07/06

In-S ystem Pr ogr ammi ng

Timings T he download from the inte rna l EEPR OM to CRAM is executed afte r 4 s econds when

operati ng at 12 MHz frequency .

Protection Mechanisms

Tran sfer Chec ks In order to verify th at the tran sfers are free of errors, a CRC check is implemented dur-

ing the download of the program in CRAM.

This test is done at the end of t he 16K spa ce programm ing.

As deta iled in th e next algorithm s:

• in ISP mode, if CRC te st pass, a character Y is returned before the CRLF

characters else a character Z is retuned.

• in download mode, a serial data AA is sent on P3.7 port and CRAM is not executed.

For this purpose, the user program must include in the two last upper bytes (address

3FF Eh an d 3FFFh) the CR C of th e previou s bytes (c alculated from the a ddress 0000h

to 3FFFDh).

The following frames are examples including the CRC in the two last upper bytes:

• FF 03 C0 21 04 00 0 0 08 07 02 08 02 2D DB (CRC = 2DD Bh)

• FF 03 80 21 02 04 00 0 A 03 06 C0 A8 70 01 E3 3D (CRC = E3 3Dh)

• FF 03 C0 21 02 01 0 0 10 02 06 00 00 00 00 05 0 6 00 00 76 55 49 AC (CRC =

49ACh)

The CRC algorithm is the following :

***************************************************************************************************

Uint16 compute_crc (Uint16 W)

{

UcharC;

W&=(Uint16)0x00FF;

for (C=(Uchar)8;C;C--)

{

if ((Uchar)W&(Uchar)1)

{

W>>=1;

W^=(Uint16)0x8408;

}

else

W>>=1;

return W;

Data Bytes

2 By tes CRC

HSB LSB

Addres s: 3FF E ,3FFF

A/T8xC5121

4164G–SCR–07/06

}

void generate_crc_in_frame(void)

{

checksum_tx=(Uint16) FFFFh; /* init of the crc variable */

/* loop which compute for each byte (data_byte) to load */

checksum_tx=compute_crc((Uint16)data_byte^checksum_tx)^(checksum_tx>>8);

/* end of loop */

checksum=~checksum_tx; /* inverts the checksum, so the check will calculate

the CRC of all the datas and */

/* will find a constant value = F0B8

which is the CRC_REF const. of the Bootloader */

write_frame(LOW_BYTE(checksum)); /* writes the LOW_BYTE of the CRC first */

write_frame(HIGH_BYTE(checksum)); /* writes the HIGH_BYTE */

}

***************************************************************************************************

Table 47. Synt hesis of Tra nsfer Protection Me chanism s

Notes: 1. The transfer of SSB Byte is also secured by CRC as the CRC is computed on all the

16K data.

2. If a Bad transfer has occurred in the Internal EEPROM (CRC is bad), as the CRC

check is fina ll y done at the end of CRAM progr am ming, application pro gram will NOT

be executed after any Reset.

Re ad/ Write Protecti on

Lock Byte In orde r to protect the c ontent of the internal EEP ROM , a Sof tware Se curity By te (SSB )

defin es two se curity levels:

• level 0: SSB = 0xFF: Write and Read are allo wed

• level 1: SSB = 0xFE: Write i s disabled

• level 2: SSB = 0xFC: Write and Read are disabled

This SSB Byt e is located at address 3FFDh.

W hen the le vel 2 is s et, the com mand to set level 1 is disabled. The security levels can

only be increased.

Source Target Check

MCU CRAM CRC computed during CRAM Write operation: if error an error code is applied

on P3.7 and Code execution by LJMP000 is not done.

Intern . EEP MCU This Read oper ation is s ecured b y the Writ e sequ ence described above

MCU Intern. EEP Sa m e protec t i on as in fir s t r ow abov e be ca use CRAM is wr itten in seq ue nce

af ter ea ch page program min g of EEP

Ext. EEP MCU Same as above as data are transferred to EEP INT and then to CRAM

A/T8xC5121

4164G–SCR–07/06

The only mea n to remove the security level 2 is to send a Full Chip Erase command.

Table 48. Synt hesis of Security Mechanism s

Configuration Bits The Boot loader tests that TWI compo nents are conn ected as slave componen ts on the

TWI external bus and later in the algorithm if characters are received on the UART input.

This default configuration can be changed , after a first programm ing, in order:

– to disable new programming in download mode from external serial

EEPROM to disable ISP progr amming using UAR T and

– to avoid any conflict with the target hardware on external TWI bus or U ART.

This can be conf igured with t he two higher bits o f the SSB Byte detailed in the previous

paragraph.

The bit 7 is used to bypass (if 0) the External TWI Ackno wledge test.

The bit 6 is used t o bypass (if 0) the UAR T receipt test.

These two bypass modes can be disabled if a level 0 is applied on, respectively, P3.5

and P3.6 pins. This allows to force and use IS P even if the device has be en con figured

as programm ed dev ice.

Source Function Protection

Internal

EEPROM Write The f irst prot ection level of the SS B B y te IN the internal EEPROM prot ects

against ISP W rite comm and

Internal

EEPROM Read The second protection level of the SSB Byte IN the internal EEPROM protects

agains t ISP Read command s

CRAM Write The first pro tection level of the S SB Byt e IN th e internal EEPR O M protects

against ISP W rite comm and in CRAM

CRAM Read The second protection level of the SSB Byte IN the CRAM protects against ISP

Read commands

Da ta B y te s SSB

Address

3FFD

A/T8xC5121

4164G–SCR–07/06

Table 49. Val id So ft w a re Secu rity By te Valu e s

UART Protocol

Overview The se rial protocol used is described below.

Physic al Layer The UAR T is used to tr ansm it information with the following configuration:

• Charac ter: 8-bit data

• Parity: none

• Stop: 1 bit

• Flow control: none

• Ba udrate: autobaud is perfo rmed by the bootloader to comp ute the baudrate

chosen by the host.

Datas and Limits As desc ribed in Section “Tran sfer Checks”, the downl oaded program incl ude the CRC

values in the last two u pper bytes of the 16K bytes space.

An upd ate of a part of the 1 6K program cannot be done because the CRC value would

have to be updated with a value which depends of the actual value of the rest of the

program.

So the Program function of the PC Software Tool include the individual program com-

mands (with 64 data bytes) from address 0000h to address 3FFFh.

Frame Description The Serial Protocol is based on the Intel Hex-type records.

Intel Hex records consist of ASCII characters used to represent hexadecimal values and

are summa rized below:

Table 50. Intel Hex Type Fram e

• Record Mark:

– Record Mark is the sta rt of frame. This field must contain’:’.

• Reclen:

– Reclen specifies that the number of bytes of information or data that fol low

the Record Type field of the re cord.

• Load Offse t:

– Load Offset specifies the 16-bit sta rting load offset of the data bytes,

therefore this field is used only for P rogram Data Record (see Table 51).

SSB Value s Functi ons

FE No bypass and level1 security

FC No bypass and level2 security

BF,BE,BC UART bypass and security le vels

7F,7E,7C External TWI bypass and security levels

3F,3E,3C UA RT and Ext. TW I bypass

Record Mark ‘:’ Reclen Load Offset Record Type Data or Info Checksum

1-byte 1-byte = 40h 2-byte 1-byte 64-byte 1-byte

A/T8xC5121

4164G–SCR–07/06

• Record T ype:

– Record Type specifies the command type. This field is used to interpret the

remaining information within the frame. The encoding for all the current

record types are described in Table 51.

• Data/Info:

– Data/Info is a 64 byte s length field. It consists of 64 byte s encode d as pairs

of hexadecimal digits. The meaning of data depends on the Record Typ e.

• Checksum:

– The two’s complement of the 8-bit bytes that result from converting each pair

of ASCII hexadecimal digits to one byte of binary, and including the Reclen

field to and inclu ding the last byte of the Data/Info fi eld. Therefore, the sum

of all the ASCII pairs in a record after conv erting to binary, from the Reclen

field to and inclu ding the Checksum field, is zero.

Notes: 1. A data byte is represented by two ASCII characters.

2. When th e fi eld Lo ad Offset i s not used, it should be coded as 2 b ytes ( 00h 00h).

Command Description Table 51. Frame Description

Command Command N ame data[ 0] data[1] Command E ffect

00h Program Data Program 64 Data Bytes

01h End Of File - - End of File

03h Write Function

07h

05h

03h

00h

01h

Full Chip Erase

Program SSB level1

Program SSB level2

LJMP(data[2],data[3])

(LJMP0000h)

04h Display Function

Data[0:1] = start address

Data [2:3] = end address

Data[4] = 00h -> Display

data

Data[4] = 01h -> Blank

check

Data[4] = 03h -> Display

CRAM

Di splay Data

05h R ead Function 07h

0Fh 00h

00h Rea d SSB

Read Bootloader Version

06h Direct Load of Baud R ate HSB LS B No t implemented

A/T8xC5121

4164G–SCR–07/06

Autobaud The ISP feature allows a wide range of baud rates in the user application. It is also

adapt able to a wid e ran ge of oscillator fre quencies. This is accomplished by meas uring

the b it-time of a s ingle bit in a recei ved cha racter. Thi s i nformation is then use d to pro-

gra m the baud rate in terms of timer counts based on the oscillator frequ ency. The ISP

feature requires that an initial character (an uppercase U) be sent to the T8xC5121 to

establi sh the baud rate. Table show the autobaud capabi lity.

Protection Mechanisms

Tran sfer Chec ks Table 53. Synthesis of the Communi cation Protec tion Mechan isms

Notes: 1. The transfer of SSB Byte is also secured by CRC as the CRC is computed on all the

16K data.

2. If a bad transfer has occurred in the Internal EEPROM (CRC is bad), as the CRC

check is fina ll y done at the end of CRAM progr am ming, application pro gram will NOT

be executed after any Reset.

Security Table 54. Synthes is of the Security Mechan isms

Tab le 52. A utobaud P erformances

Frequency (MHz)

Baudrate ( kHz) 6.176 8 11.0592 12 14.3 14.7456 16

9600 OK OK OK OK OK OK -

19200 OK - OK OK Ok OK OK

38400 - OK OK OK OK OK

57600 - - OK - OK OK -

115200 -----OK-

Source Target Check

UART ISP MCU Che cks um inc lu de d in c omm an ds i s te st ed w ith c al cu lat ed c he cks um: i f

bad, X echo returned to ISP

MCU CRAM CRC computed during CRAM Write operation: if error an error code is

applied on P3.7. Error code’Z’ is returned to ISP.

MCU Intern. EEP Same protection as above because CRAM is written in sequence after

each page programming of EEP

Source Target Case Protection

UART ISP Intern. EEP Read access SSB level 2 must be set (done, if

selected, at ISP Prog ramming or Ext

EEP Download)

UART ISP CRAM Read access SSB level 2 IN CRAM must be set (SSB

is downloaded from Int EEP after Reset)

UART ISP Intern. EEP Partial Programming

which would not fit

with old CRC

SSB level 1 mu st be set (done, if

selected, at ISP Prog ramming or Ext

EEP Download)

Then the EEP must be, first, erased

before reprogramming.

Programming is done on all the memory

space

A/T8xC5121

4164G–SCR–07/06

UA RT ISP Inter n. EEP P rogramming SSB level 1 must be set (done, if

selected, at ISP Prog ramming or Ext

EEP Donwload)

UART ISP CRAM Program access SSB level 1 IN Int EEP protects as, first,

the Int EE P is programm ed before

CRAM

UART ISP SSB in EEP and

CRAM l evel 2 to level 1 Protected by Bootloader

UART ISP SSB in EEP and

CRAM l evel 1 to level 0 Protected by Bootloader

Source Target Case Protection

A/T8xC5121

4164G–SCR–07/06

Timers/Counters

Introduction The T8xC5121 implements two general-purpose, 16-bit Timer 0s/Counters. Although

they are identified as Timer 0, Timer 1, y ou can independently configure each to operate

in a variety of modes as a Timer 0 or as an event Counter. When operating as a Timer 0,

a Timer 0/Counter runs for a programmed length of time, then issues an interrupt

request. When operating as a Counter, a Timer 0/Counter counts negative transitions

on an ex ternal pin. After a preset number of counts, the Counter issues an interrupt

request.

The Timer 0 registers an d associa ted control registers are impleme nted as add ressable

Sp ecial Fun ction Regist ers (SFRs ). Two o f the S FRs pro vide prog ramm able contro l of

the Timer 0s as follows:

• Tim er 0/Counter mode control register (TMOD) and T imer 0/Counter control register

(TCON) control respectively Timer 0 and Timer 1.

The various operat ing modes of each Timer 0/Counter are described below.

Timer 0/Cou nter

Operations For example, a basic operation is Timer 0 registers T Hx and TLx (x = 0, 1) connected in

cascade to form a 16-bit Timer 0. Setting the run control bit (TRx) in the TCON register

(see Figure 55) turns the Timer 0 on by allowing the selected input to increment TLx.

When TLx overflows it increments THx and when THx overflows it sets the Timer 0 over-

flow fl ag (TFx) in th e TCON re gister. S etting the TR x does not c lear the THx and TLx

Ti mer 0 reg is ters . Time r 0 regi ster s ca n be acc ess ed t o ob tain t he c urr ent coun t or to

enter preset values. They can be read at any time but the TRx bit must be cleared to

preset their values, otherwise the behavior of the Timer 0/Counter is unpredictable.

The C/Tx# control bit selects Timer 0 operation or Counter operation by selecting the

divided-down system clock or the external pin Tx as the source fo r th e cou nted sign al.

The TRx bit must be cleared when changing the operating mode, otherwise the behavior

of the Timer 0/Counter is unpredictable.

For Timer 0 operation (C/Tx# = 0), the Time r 0 register counts the divided-down sy stem

clock. The Timer 0 register incremented once eve ry peripheral cycle.

Exceptions are the Timer 0 2 Baud Rate and Clock-Out modes in which the Timer 0 reg-

ister is incremented by the system clock divide d by two.

For Cou nter ope ration (C/Tx# = 1 ), the Timer 0 re gister cou nts the nega tive transitio ns

on the Tx external input pin. The external input is sampled during every S5P2 state. The

Pr ogram m er’s G uide des crib es the no tat ion for th e st ates in a perip hera l cy cle. W he n

the sample is high in one cycle and low in the next one, the Counter is incremented. The

new c oun t val ue app ears in the re gister d uring t he n ext S3P 1 st ate af ter the transit ion

has be en detected. Since it takes 12 states (24 osc illator periods) to recognize a nega-

tive transition, the maximum count rate is 1 /24 of the oscillator frequency. There are no

restrictions on the duty cycle of the external input signal, but to ensure that a given level

is sampled at least once before it changes, it should be held for at le ast one full pe ri ph-

eral cycle .

A/T8xC5121

4164G–SCR–07/06

Timer 0 Timer 0 functions as either a Timer 0 or an event Counter in four operating modes.

Figure 28 th rough Figu re 31 show the logic configuration of each mode.

Timer 0 is controlled by the four lower bits of the TMOD register (see Figure 56) and bits

0, 1, 4 and 5 of the TCON register (see Figure 55). The TMOD register selects the

method of Timer 0 gating (G ATE 0), Timer 0 or Cou nter operation (T/C0#) and t he oper-

ating mode (M10 a nd M00). The TCON register provides Timer 0 control functions:

overflow flag (TF0), run control bit (TR0), i nterrupt flag (IE 0) and interrupt t ype control bit

(IT0).

For n orma l Time r 0 opera tion (GATE 0 = 0) , setting TR0 al lows T L0 to be incre men ted

by the selected input. Setting GATE0 and TR0 allows external pin INT0 to control T i mer 0

operation.

Timer 0 ov erflow (count rolls over from all 1 s to all 0s) sets the TF0 flag and ge nerates

an interrupt request.

It is important to stop the Ti mer 0/Counter before changi ng mod es.

Mode 0 (13-bit Timer 0) Mode 0 conf igures T imer 0 as a 13-bit Ti mer 0 which i s set up as an 8-bi t T imer 0 (T H0

ister (see Figure 28). The upper three bits of the TL0 register are indeterminate and

shou ld be ignored. Prescale r overflow increments the TH0 register.

Figu re 28. Timer 0/Co unter x (x = 0 o r 1) in Mode 0

Mode 1 (16-bit Timer 0) Mode 1 configures Timer 0 as a 16-bit Timer 0 with t he TH0 and TL0 registers c on-

nected in a cascad e (see Figure 29). The selected input increments th e TL0 register.

TRx

TCON reg

TFx

TCON reg

GATEx

TMOD reg

Overflow Timer 0 x

Interrupt

Request

C/Tx#

TMOD reg

TLx

(5 bits)

THx

(8 bits)

INTx#

FCLK_Periph

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4164G–SCR–07/06

Figu re 29. Timer 0/Co unter x (x = 0 o r 1) in Mode 1

Mode 2 (8-bit Ti mer 0 with

Auto-Reload) Mode 2 configures Timer 0 as an 8-bit Timer 0 (TL0 register) that automatically reloads

from the T H 0 registe r (s ee F igure 30). T L0 overflow sets the T F0 flag in t he T CON reg-

ist er and re loads T L0 with the co ntents o f TH0 , which i s prese t by the softw are. Whe n

the interru pt request is serviced , the hardw are clears TF0. The reload leave s TH0

unc hanged. The nex t reload value m ay b e changed a t any time by writing it to the TH 0

Figu re 30. Timer 0/Co unter x (x = 0 o r 1) in Mode 2

Mode 3 (Two 8-bit Timer 0s) Mode 3 configures Timer 0 so that registers TL0 and TH0 operate as 8-bit Timer 0s (see

Figure 31). This mode is provided for applications requiring an additional 8-bit Timer 0 or

Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in the TMOD register, and

TR0 an d TF0 in the T CON re gister in the norma l manne r. T H0 is locked into a T imer 0

function (counting FUART) and takes over use of the Timer 1 interrupt (TF1) and run con-

trol (TR1) bits. Thus, o peration of Timer 1 is rest ricted when Timer 0 is in mod e 3.

TRx

TCON reg

TFx

TCON reg

GATEx

TMOD reg

Overflow Timer 0 x

Interrupt

Request

C/Tx#

TMOD reg

TLx

(8 bits)

THx

(8 bits)

INTx#

FCLK_Periph

TRx

TCO N reg

TFx

TCO N reg

GATEx

TMOD reg

Overflow Tim e r 0 x

Interrupt

Request

C/Tx#

TMOD reg

TLx

(8 bits)

THx

(8 bits)

INTx#

FCLK_Periph

A/T8xC5121

4164G–SCR–07/06

Figu re 31. Timer 0/Co unter 0 in Mode 3: Two 8-bit Counters

TR0

TCON.4

TF0

TCON.5

INT0

GATE0

TMOD.3

Overflow Timer 0

Interrupt

Request

C/T0#

TMOD.2

TL0

(8 bits)

TR1

TCON.6

TH0

(8 bits) TF1

TCON.7

Overflow Timer 1

Interrupt

Request

FCLK_Periph

A/T8xC5121

4164G–SCR–07/06

Timer 1 Ti mer 1 is id ent ical to T imer 0 e xcep t for M ode 3 w hich i s a ho ld-cou nt mod e. The fol-

lowing com men ts help to understand the differences:

• Time r 1 functions as either a Tim er 0 or an event Counter in th e three operating

modes. Figure 28 through Figure 30 show the logical configuration for modes 0, 1,

and 2. Mode 3 of Timer 1 is a hold-count mode.

• Tim er 1 i s controlled by the four high-order bit s of the TMOD register (see Figure 56)

and bits 2, 3, 6 and 7 of th e TCON register (see Figure 55). The TMOD register

selects the me thod of Timer 0 gating (GATE1), Timer 0 or Counter o peration

(C/T1#) and the operating mode (M11 and M01). The TCON register provides T imer

1 control functions: overf low fl ag (TF1), run control bit (TR1), interrupt flag (I E1) and

the interrupt type control bit (IT1).

• Time r 1 can serve as the Baud Rate Generator for the Serial Port. Mod e 2 is best

suited for this purpose.

• For norm al Ti me r 0 operation (GATE1 = 0), setting TR1 allows TL1 to be

incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1

to control Timer 0 operation.

• Tim er 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag and

generates an interrupt request.

• When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (T F1) and run control bit

(TR1). For this situa tion, use Ti me r 1 only for applications that d o not require an

interrupt (such a s a Baud Rate Generato r for the Se rial Port) and switch Timer 1 in

and out of mode 3 to turn it off and on.

• It is important to stop the Timer 0/Counter befo re changing mo des.

Mode 0 (13-bit Timer 0) M ode 0 configures Timer 1 as a 13-bit Ti mer 0, which is set up as an 8-bit Timer 0 (T H1

ter (see Figure 28). The upper 3 bits of TL1 register are ignored. Prescaler overflow

incremen ts the TH1 register.

Mode 1 (16-bit Timer 0) Mode 1 c onfigures Timer 1 as a 16-bit Ti mer 0 with TH1 and TL1 registers connected in

cascade (s ee Figure 29). The select ed input incremen ts the TL1 register.

Mode 2 (8-bit Ti mer 0 with

Auto-Reload) Mode 2 confi gures Timer 1 as an 8-bit Timer 0 (TL1 register) with automatic reload from

the TH1 register on overflow (see Figure 30). TL1 overflow sets the TF1 flag in the

TCON register and reloads TL1 with the contents of TH1, which is preset by the soft-

ware . The reload leaves TH1 unchanged .

Mode 3 (Halt) Placing Time r 1 in m ode 3 cause s it to h alt a nd hold its count. This c an be used to halt

Timer 1 when the TR1 run control bit is n ot available i.e., when Timer 0 is in m ode 3.

A/T8xC5121

4164G–SCR–07/06

Registers Table 55. TCON Register

TCON (S :88h) - T imer 0/Counter Control Register

Rese t Value = 0000 0000b

76543210

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Bit

Number Bit

Mnemonic Description

7TF1

Timer 1 Overflow flag

Cleared by the hardware when processor vectors to interrupt routine.

Set by the hardware on Timer 0/Counter overflow when Timer 1 register

overflows.

6TR1

Timer 1 Run Control bit

Clear to turn off Timer 0/Counter 1.

Set to turn on Timer 0/Counter 1.

5TF0

Timer 0 Overflow flag

Cleared by the hardware when processor vectors to interrupt routine.

Set by the hardware on Timer 0/Counter overflow when Timer 0 register

overflows.

4TR0

Timer 0 Run Control bit

Clear to turn off Timer 0/Counter 0.

Set to turn on Timer 0/Counter 0.

3IE1

Interrupt 1 Edge flag

Cleare d by the hardware when interrupt is processed if edge-t riggered ( s ee I T1).

Set by the hardware when external interrupt is detected on the INT1 pi n.

2IT1

Interrupt 1 Type Co ntrol bit

Clear to select low level active (level triggered) for ex ternal int errupt 1 (IN T1).

Set to select falling edge active (edge triggered) for external interrupt 1.

1IE0

Interrupt 0 Edge flag

Cleare d by the hardware when interrupt is processed if edge-t riggered ( s ee I T0).

Set by the hardware when external interrupt is detected on INT0 pi n.

0IT0

Interrupt 0 Type Co ntrol bit

Clear to select low level active (level triggered) for ex ternal int errupt 0 (IN T0).

Set to select falling edge active (edge triggered) for external interrupt 0.

A/T8xC5121

4164G–SCR–07/06

Reset Value = 0000 0000b

Tab le 56. TMOD Register

TMOD (S:89h) - Timer 0/Counter Mode Control Registers

76543210

GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

Bit Number Bit Mnemonic Description

7GATE1

Timer 1 Gating Control bit

Clear to enable Timer 1 whenever TR1 bit is set.

Set to enable Timer 1 only while INT1 pin is high and TR1 bit is set.

6C/T1#

Timer 1 Counter/Timer 0 Select bit

Clear for Timer 0 operation: Timer 1 counts the div ided-down syste m cloc k.

Set for Counter operation: Timer 1 counts negative transitions on external pin T1.

5M11

Timer 1 Mode Select bits

M11 M01 O p er a tin g mo de

0 0 Mode 0: 8-bit Timer 0/Counter (TH1) with 5- bit prescaler (TL 1).

0 1 Mode 1: 16-bit Tim er 0/Counter.

1 0 Mode 2: 8-bit auto-reload Time r 0/Counter ( TL1). Reloaded from TH 1 at ov erflow.

1 1 Mode 3:Timer 1 hal te d. Reta ins coun t.

4M01

3GATE0

Timer 0 Gating Control bit

Clear to enable Timer 0 whenever TR0 bit is set.

Set to enable Timer 0/Counter 0 only while IN T0 pin is high and TR0 bit i s set.

2C/T0#

Timer 0 Counter/Timer 0 Select bit

Clear for Timer 0 operation: Timer 0 counts the div ided-down syste m cloc k.

Set for Counter operation: Timer 0 counts negative transitions on external pin T0.

1M10

Timer 0 Mode Select bit

M10 M00 Operat ing m ode

0 0 Mode 0:8-bit Timer 0/Counter (TH0) with 5-bit prescaler (TL0).

0 1 Mo de 1:16-bit Timer 0/Coun ter

1 0 Mo de 2: 8-bit auto-reloa d Timer 0/Counter (TL0). Rel oade d from T H0 at overf low.

1 1 Mo de 3: TL0 is an 8-bit Timer 0/Coun ter.

TH0 is an 8-bit Timer 0 using Timer 1’s TR0 and TF0 bits.

0M00

A/T8xC5121

4164G–SCR–07/06

Table 57. TH0 Regist er

TH0 (S:8Ch) - Timer 0 High Byte Regist er.

Rese t Value = 0000 0000b

Table 58. TL0 Regist er

TL0 (S:8Ah) - Timer 0 Low Byte Register.

Rese t Value = 0000 0000b

Table 59. TH1 Regist er

TH1 (S:8Dh) - Timer 1 High Byte Regist er.

Rese t Value = 0000 0000b

Table 60. TL1 Regist er

TL1 (S:8Bh) - Timer 1 Low Byte Register.

Rese t Value = 0000 0000b

76543210

Bit

Number Bit

Mnemonic Description

7:0 Hi gh Byte of Timer 0

76543210

Bit

Number Bit

Mnemonic Description

7:0 Low Byte of Timer 0

76543210

Bit

Number Bit

Mnemonic Description

7:0 Hi gh Byte of Timer 1

76543210

Bit

Number Bit

Mnemonic Description

7:0 Low Byte of Timer 1

A/T8xC5121

4164G–SCR–07/06

Serial I/O Port The se rial I/O port is ent irely compa tible with the serial I/O port in the 80C52.

It provi des b oth synchr onou s and asynchro nous c ommuni cation modes. I t operat es as

an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex

mode s (Modes 1, 2 and 3). Async hronous transmission and rec eption can occur simul-

taneously and at dif ferent baud rates.

Serial I/O port includes the following enhancements:

• Fram ing error detection and Automatic Address Recognition

• Internal Baud Rate Generator

Fi gure 32 . Serial I/O UART Port Block Diagram

Framing Error Detection Framing bit error detection is provided for the three asynchronous modes. To enable the

framing bit error detection feature, set SMOD0 bit in PCON register.

Fi gure 33 . Framing Error Block Diagram

W hen this feature is enabl ed, the receiver chec ks each incom ing data frame for a valid

stop bit. An invalid stop bit may result f rom noise on the serial l ines or f rom simultaneous

tran smissio n by two C PUs . If a valid st op bit is n ot found, t he Fram ing Error bit (FE) i n

SCON register bit is set.

Softwa re may exa mine FE b it after each reception to ch eck for data erro rs. Once set,

only s oftware or a reset c lear FE bit. Su bsequent ly received fr ames with valid s to p bits

cann ot clear FE bit. W hen FE feature is enabled, RI rises on stop bit instead of the last

data bit (See Figure 34 and Figu re 35).

Write SBUF

RI TI

Transmitter SBUF

Receiver

IB Bus

Mode 0 Tran sm it

Receive

Shift register

Load SBUF

Read SBUF

Interrupt Request

Serial Port

TXD

RXD

SBUF

RITIRB8TB8RENSM2SM1

SM0/FE

IDLPDGF0GF1

POF

SMOD0SMOD1

To UART framing error control

SM0 to UART mode control

Set FE bit if stop bit is 0 (framing error)

A/T8xC5121

4164G–SCR–07/06

Fi gure 34 . UART Timings in Mode 1

Fi gure 35 . UART Timings in Modes 2 and 3

Automatic Address

Recognition The au tomat ic address recognition feature is enabled when the multiproce ssor comm u-

nication feature is enabled (SM2 bit in SCON register is set).

Impl ement ed in hard ware, auto matic add ress recog nition enh ances t he mult iprocessor

communication feature by allowing the serial port to examine the address of each

incoming command frame. Only when the serial port recognizes its own address, the

receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU

is not interrupted by command f rames address ed to other devices.

If desired, you m ay enable the automat ic address recognition feat ure in mode 1. In this

configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the

receive d comm and frame add re ss matche s the device’s address and is terminated by a

valid stop bit.

To support aut om atic addres s rec ognition, a device is identified b y a given address a nd

a broadca st address.

Note: The multiprocessor communication and automatic address recognition features cannot

be enabled i n mod e 0 (i. e., setting SM2 bi t in SCON register in mode 0 has no effect).

Given Address Each device has an individual address that is specified in SADDR register; the SADEN

regi ster is a mask byte that con tains don’t care bi ts (defined by zeros) to for m th e

device’s given address. The don’t care bits provide the flexibility t o addres s one or m ore

sla ve s at a time. The follow ing ex am ple illu str at es how a given address is form ed.

Data Byte

SMOD 0 = X

Stop

Bit

Start

Bit

RXD D7D6D5D4D3D2D1D0

SMOD 0 = 1

SMOD0 = 0

Data Byte Ninth

Bit Stop

Bit

Start

Bit

RXD D8D7D6D5D4D3D2D1D0

SMOD0 = 1

A/T8xC5121

4164G–SCR–07/06

To address a device by its individual address, the SADEN mask byte must be 1111

1111b.

For example:

SADDR0101 0110b

SADEN1111 1100b

Given0101 01XXb

The following is an example of how to use given addresses to address differe nt slaves:

Sla ve A:SADDR1111 0001b

SADEN1111 1010b

Given1111 0X0Xb

Sla ve B:SADDR1111 0011b

SADEN1111 1001b

Given1111 0XX1b

Sla ve C:SADDR1111 0011b

SADEN1111 1101b

Given1111 00X1b

The SADEN by te is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To commu-

nicate with slave A only, the master must send an address where bit 0 is clear (e.g.

1111 0000b).

For slave A, bit 1 is a 0; for slaves B and C, bi t 1 is a don’t care bi t. To c ommunicate with

slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both

set (e.g . 1111 0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0 set,

bit 1 clear, and bit 2 clear (e.g. 1111 0001b).

Broadcas t Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers

with zeros defined as don’t care bits, e.g.:

SADDR0101 0110b

SADEN1111 1100b

SADDR OR SADEN1111 111Xb

The use of don’ t care bits provides flexibility in defining the broadcast add ress, however

in m ost applicat ions, a broa dcast addre ss is FFh. The f ollowing is an e xample of us ing

broadc ast addresses :

Sla ve A:SADDR1111 0001b

SADEN1111 1010b

Given11 11 1X11b,

Sla ve B:SADDR1111 0011b

SADEN1111 1001b

Given1111 1X11B,

Slave C:SADDR = 1111 0010b

SADEN1111 1101b

Given1111 1111b

For slaves A and B, bit 2 is a don’ t care bit; f or slave C, bit 2 is set. To communicate with

all o f the s laves, the m as ter must s end an address FFh. To c om mu nicate with slaves A

and B, but not slave C, the master can send and address FBh.

A/T8xC5121

4164G–SCR–07/06

Reset Addresse s On rese t, the SA DDR , SAD EN re gis ter are in itiali zed to 00h , i.e . the g iven an d broa d-

cast addresses are XXXX XXXXb (all don’t care bits). This ensures that the serial port is

backwards compatible with the 80C51 microcontrollers that do not support automatic

addres s recognition.

UART Output Configuration

Vo l tag e Level The I/O Ports of UART are powered by the EVCC Regulator. The voltage of this r egulator

can be:

• Au tomatically cont rolled by the microcontroller which adapt the power supply level

versu s the OE inpu t vo ltage le ve l.

• Se t at three defined levels (1.8V, 2.3V or 2.8V)

These configura tion s are defin ed w it h the EVAU TO and VEXT 0 ,VEXT1 Bi ts of SIOCON

Out put E nable Fu nct i on T he UAR T outputs (Tx, T0) can be controlled by the Out put Enable input.

The Bit s PMOSEN0 and PMOSEN1 in SIOCON Register are used to control this output.

PMOSEN0

PMOSEN1

(P3.3)

PMOS Comman

(Active at 1)

SFR

Value

A/T8xC5121

4164G–SCR–07/06

UART Control Registers Table 61. SADEN Register

SADEN

Slave Address Mask Register (B9h)

Rese t Value = 0000 0000b

Table 62. SADDR Regi ster

SADDR

Slave Address Register (A9h)

Rese t Value = 0000 0000b

Table 63. S BUF Register

SBUF

Serial Buffer Register (99h)

Reset Value = XXXX XXXXb

76543210

A/T8xC5121

4164G–SCR–07/06

UART Timings The following descri ption will be included in L version:

Mode Selection SM 0 and SM1 bi ts in SC ON r egist er (see T able 67) are used to selec t a mo de am ong

the single synchronous and the three asynchronous mod es accordin g to Table 64.

Table 64. Se rial I/O Port Mode Selectio n

Baud Rate Generator Dependin g on t he m ode and the sou rce sel ectio n, the ba ud rate ca n be gen erated from

either the Timer 1 or the Internal Baud Rate Generator. The Timer 1 can be used in

Mode s 1 and 3 while the Internal B aud Rate Generat or can be used in Modes 0, 1 a nd

The addition of the I nternal B aud Rate Generator allows freeing o f the T imer 1 f or other

purposes in the application. It is highly recommended to use the Internal Baud Rate

Generat or as it al lows higher and more accurate baud rates than with Timer 1.

Baud rate formulas depend on the modes se lected and are given in the following mode

sections.

Timer 1 When using the Timer 1, the Baud Rate is deriv ed from the overflow of the timer. As

shown in Figure 36 the Timer 1 is used in its 8-bit auto-reload mode (detailed in

Section “Tim er 0/Counter Operations”, page 73). SMOD1 bit in PCON register allows

doubling of the generated baud rate.

Figu re 36. Timer 1 Baud Rate Generator Block Diagram

Internal Baud Rate Generator When us ing the Internal Baud Rate Generator, the Baud Rate is derived from the over-

flow of the timer. As shown in Figure 37, the Internal Baud Rate Generator is an 8-bit

auto-reload timer feed by the peripheral clock or by the peripheral clock divided by 6

dependi ng on the SPD bit in BDRCON register (see Table 68). The Internal Baud Rat e

Generat or is enab led by setting BBR bit in BDRCON reg ister. SMO D1 bit in PCO N reg-

ister allows doubling of the generated baud rate.

SM0 SM1 Mode Description Baud Rate

0 0 0 Synch r o no us Sh ift Regis ter Fi xed / Vari able

0 1 1 8-bit UART Variable

10 29-bit UART Fixed

1 1 3 9-bit UART Variable

TR1

TCON.6

GATE1

TMOD.7

Overflow

C/T1#

TMOD.6

TL1

(8 bits)

TH1

(8 bits)

INT1

PER

CLOCK ÷ 6 0

SMOD1

PCON.7

÷ 2 T1

CLOCK To Seria l Por t

A/T8xC5121

4164G–SCR–07/06

Figu re 37. Internal Baud Rate Generator Block Diagram

Sync h r on ous Mode (Mode 0) Mode 0 is a ha lf-duplex, sy nchronous m ode, which is co mmonly used t o e xp and the I/0

cap ab ilities of a dev ice wit h sh ift reg iste rs. The tr an smit d ata (T XD) pin outp uts a s et of

eight clock pulses while the receive data (RXD ) pin transmits or receives a byte of da ta.

The 8 -bit data are transm itted and rec eived lea st-s ignifica nt b it (LSB) firs t. Shifts occur

at a fixed Baud Rate. Figure 38 show s the serial p ort block diagram in Mode 0.

Figu re 38. Se rial I/O Port Block Diagram (Mode 0)

Tran smis sion (Mode 0) To start a transmission mode 0, write to SCON register clearing bits SM0, SM1.

As shown in Figure 3 9, writing the byte to transmit to SBU F register starts the transmis-

sion. Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle

composed of a high level then low level signal on TXD. During the eighth clock cycle the

MSB (D7) is on the RX D pi n. Then, hardwa re drives th e RX D pin h igh and asserts TI to

indicat e the end of the transmission.

Fi gure 39 . Transmission Waveforms (Mode 0)

Overflow

SPD

BDRCON.1

BRG

(8 bits)

BRL

(8 bits)

PER

CLOCK ÷ 6IBRG

CLOCK

BRR

BDRCON.4

SMOD1

PCON.7

÷ 2To Serial Port

BRG

CLOCK

TXD

RXDSBUF Tx SR

SBUF Rx SR

SM1

SCON.6 SM0

SCON.7

Mode Decoder

M3 M2 M1 M0

Mode

Controller

SCON.0

SCON.1

PER

CLOCK Baud Rate

Controller

Wr ite to SBU F

TXD

RXD

D0 D1 D2 D3 D4 D5 D6 D7

A/T8xC5121

4164G–SCR–07/06

Reception (Mode 0) To start a re ceptio n in m ode 0, w rite to S CO N re gister cleari ng S M0, SM1 a nd RI bits

and setting the REN bit.

As sho wn i n Fi gure 40 , Cl ock is pu lsed and t he L SB ( D0 ) is s amp led on the RXD pin .

The D0 bit is th en shifte d into the shift registe r. After ei ght samp ling, the M SB (D7) is

shifted into the shift register, and hardware asserts RI bit to indicate a completed recep-

tion. Software can then read the received byte from SBUF register.

Fi gure 40 . Recepti on Waveforms (Mode 0)

Baud Rate Selection (Mode 0) In mode 0, baud rate can be either fixed or variable.

As show n in Figure 41, the selection is d one us ing M0SRC bit in BD RCON register.

Figure 42 gives the baud rate calculation formulas for each baud rate source.

Fi gure 41 . Baud Rate Sou rce Selection (Mode 0)

Fi gure 42 . Baud Rate Formulas (Mod e 0)

Wr ite to SCON

TXD

RXD

D0 D1 D2 D3 D4 D5 D6 D7

Set REN, Clear RI

M0SRC

BDRCON.0

PER

CLOCK ÷ 6

To Seria l Po

IBRG

CLOCK

Baud_Rate

6(1-SPD) ⋅ 32

⋅ ( 256 -BRL)

2SMOD1

⋅ FPER

BRL = 256

6(1-SPD) ⋅ 32

⋅ Baud_Rate

2SMOD1

⋅ FPER

a. Fixed Form ula b. Variable Formula

Baud_Ra te = 6

FPER

A/T8xC5121

4164G–SCR–07/06

Asynchronous Modes

(Modes 1, 2 and 3) The Serial Port has one 8-bit and two 9-bit asynchronous modes of operation. Figure 43

shows the Serial Port block diagram in such asynchronous modes.

Figu re 43. Se rial I/O Port Block Diagram (Modes 1, 2 and 3)

Mode 1 Mode 1 is a full-duplex, asynchronous mode. The data frame (see Figure 44) consists of

10 bit s: o ne sta rt, eigh t d ata bits and one stop bit . Se rial da ta is tran smitte d on t he TX D

pin and received on the RXD pin. When a data is received, the stop bit is read in the

RB8 bit in SCON register.

Figu re 44. Dat a Frame Format (Mode 1)

Modes 2 and 3 Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 45)

consi sts of 11 bits: one start bit, eight data bits (transmitted and received LS B first), o ne

programm able ninth data bit a nd one stop bit. Serial data is transm itted on the TX D pi n

an d rece iv ed o n th e RXD pi n. O n rece ive, t he n int h b it i s re ad f rom RB 8 bit i n S CO N

regi ster . On tran smit, t he ni nth dat a bi t is w ritten t o TB8 bit in SCO N re gister. Alt erna-

tively, you can use the ninth bit as a co mm and/ data flag.

Figu re 45. Data Frame Format (Modes 2 and 3)

Tran smis sion (Modes 1, 2

and 3) To initi ate a transm ission, write to SCO N register, se tt ing SM0 a nd SM1 bits ac cording

to Tabl e 64 , and s ett ing th e nin th bit by wri tin g to TB8 bit . Then , wri ting t he b yte to be

transm itted to SBUF register starts the transmission.

Reception (Modes 1, 2 and 3) To prepare fo r a reception, write to SCON register, setting SM0 and SM1 bit s according

to Table 64, and setting REN bit. The actual reception is then initiated by a detected

high-to-low transition on the RXD pin.

TB8

SCON.3

IBRG

CLOCK

RXD

TXDSBUF Tx SR

Rx SR

SM1

SCON.6 SM0

SCON.7

Mode Decoder

M3 M2 M1 M0

SCON.0

SCON.1

Mode & Clock

Controller

SBUF Rx RB8

SCON.2

SM2

SCON.4

CLOCK

PER

CLOCK

Mode 1 D0 D1 D2 D3 D4 D5 D6 D7

Start Bit 8-bit Data Stop Bit

Modes 2 and 3 D0 D1 D2 D3 D4 D5 D6 D8

Start Bit 9-bit Data Stop Bit

A/T8xC5121

4164G–SCR–07/06

Fra m in g Er ror De te ct i on

(Modes 1, 2 and 3) Fra ming er ror de tec tion i s p rovi ded f or t he th re e asyn ch ronou s m ode s. T o en abl e th e

framing bit error detection feature, set SMOD0 bit in PCON register as shown in

Figure 46.

W hen this feature is enabl ed, the receiver chec ks each incom ing data frame for a valid

stop bit. An invalid stop bit may result f rom noise on the serial l ines or f rom simultaneous

tra nsmis sion by two device s. If a v alid s top bi t is no t foun d, the so ftw are set s FE bit in

SCON register.

Softwa re may exa mine FE b it after each reception to ch eck for data erro rs. Once set,

only s oftwa re or a chi p reset cle ar F E bit. Subs equen tly received frames with valid st op

bits cannot clear FE bit. When the framing error detection feature is enabled, RI rises on

stop bit instead of the last data bit as detailed in Figure 36.

Fi gure 46 . Framing Error Block Diagram

Baud Rate Selection (Modes 1

and 3) In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Inte rn al Baud

Rate Gen erator and allows different baud rate in reception and transm iss ion.

As shown in Figure 47 the selection is done using RBCK and TBCK bits in BDRCON

Figure 48 gives the ba ud rate calculation formulas for each baud rate source while

Table 65 details Internal Baud Rate Generator configuration for different peripheral

clock freq uencies and giving baud rates closer to the standard baud rates.

Figu re 47. Ba ud Rate Sourc e Selection (Modes 1 and 3)

Fi gure 48 . Baud Rate Formulas (Mod es 1 and 3)

SM0

SMOD0

PCON.6

SM0/FE

SCON.7

Framing Error

Controller FE

RBCK

BDRCON.2

CLOCK To S erial

IBRG

CLOCK

Reception Port 0

TBCK

BDRCON.3

CLOCK To serial

IBRG

CLOCK

Transmission Por

÷ 16÷ 16

Baud_Rate

6(1-SPD) ⋅ 32

⋅ (256 -BRL)

SMOD1

⋅ FPER

BRL = 256

6(1-SPD

)

⋅ 32 ⋅ Baud_Rate

2SMOD1 ⋅ FPER

Baud_Rate

⋅ 32

⋅ (256 -TH1)

2SMOD1

⋅ FPER

TH1 = 256

192

⋅ Baud_Rate

2SMOD1

⋅ FPER

a. BRG Formula b. T1 Formula

A/T8xC5121

4164G–SCR–07/06

Table 65. I nternal Baud Rate Generator Value

Notes: 1. These frequencie s are achieved in X1 mode, FPER = FOSC ÷ 2.

2. These frequencie s are achieved in X2 mode, FPER = FOSC.

Baud Rate Selection (Mode 2) In mo de 2, the bau d ra te can only b e pr ogram med to two fi xed values: 1/ 16 or 1/32 of

the peripheral clock frequency .

As show n in Figure 49, the selection is done using SMO D1 bit in PCON register.

Figure 50 gives the bau d rate calculation formula dependin g on the selection.

Fi gure 49 . Baud Rate Generat or Selection (Mode 2)

Fi gure 50 . Baud Rate Formula (Mo de 2)

Baud Rate

FPER = 6 MHz1FPER = 8 MHz1

SPD SMOD1 BRL Error % SPD SMOD1 BRL Error %

115200--------

57600 - - - - 1 1 247 3.55

38400 1 1 246 2.34 1 1 243 0.16

19200 1 1 236 2.34 1 1 230 0.16

9600 1 1 217 0.16 1 1 204 0.16

4800 1 1 178 0.16 1 1 152 0.16

Baud Rate

FPER = 12 MHz2FPER = 16 MHz2

SPD SMOD1 BRL Error % SPD SMOD1 BRL Error %

115200 - - - - 1 1 247 3.55

57600 1 1 243 0.16 1 1 239 2.12

38400 1 1 236 2.34 1 1 230 0.16

19200 1 1 217 0.16 1 1 204 0.16

9600 1 1 178 0.16 1 1 152 0.16

4800 1 1 100 0.16 1 1 48 0.16

SMOD1

PCON.7

PER

CLOCK ³ 2 ³ 16 To Serial Po

Baud_Rate = 32

2SMOD1 ⋅ FPER

A/T8xC5121

4164G–SCR–07/06

Table 66. B RL (S:91h)

BRL Regi ster

Baud Rate Genera tor Reload Register

Rese t Value = 0000 0000b

76543210

BRL7 BRL6 BRL5 BRL4 BRL3 BRL2 BRL1 BRL0

Bit

Number Bit

Mnemonic Description

7 - 0 BRL7:0 Baud Rate Reload Value.

A/T8xC5121

4164G–SCR–07/06

Reset Value = XXX0 0000b

Tab le 67. S CON Regi ster

SCON (S:98h)

Serial Control Registe

76543210

FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

Bit

Number Bit

Mnemonic Description

Fra ming Er ror bit

To select this function, set SMOD0 bit in PCON register.

Set by hardware to indicate an invalid stop bit.

Must be c leared by software.

SM0

Serial Port Mode bit 0

To select this function, clear SMOD0 bit in PCON register .

Software writes to bits SM0 and SM1 to select the Serial Port operating mode.

Refer to SM1 bit for the mode selections.

6SM1

Serial Port Mode bit 1

To select this function, set SMOD0 bit in PCON register.

Software writes to bits SM1 and SM0 to select the Serial Port operating mode.

SM0 SM1 Mode Description Baud Rate

0 0 0 Shift Register FOSC/1 2 or variable if SRC bit in BDRCON is set

0 1 1 8-bit UART Variable

1 0 2 9-bit UART FOSC/3 2 or FOSC/64

1 1 3 9-bit UART Variable

5SM2

Serial Port Mode bit 2

Software writes t o bit SM2 to enable and disable the multipr ocessor co mmunication and automatic address

recognition features.

Thi s al l ows t he Ser ial P ort t o dif f e rent iat e b et wee n d ata and co mmand f r am es and to reco gn iz e sl av e and b r oad cast

addresses.

4REN

Receiver Enable bit

Clear t o dis able reception in mode 1, 2 and 3, and to enable transmission in mode 0.

Set to enable reception in al l mod es.

3TB8

Transmit b it 8

Modes 0 an d 1: Not used.

Modes 2 an d 3: Software writes the ninth data bit to be transmitted to T B8.

2RB8

Receiver bit 8

Mod e 0: Not us ed .

Mode 1 (SM2 cleared ): Set or cleared by hardware to ref lect the stop bit received.

Modes 2 an d 3 (SM2 s et): Set or cleared by hardw are to r efl ect the ni nth bit received.

1TI

Transmit Interrupt flag

Set by the transmitter after the last data bit is transmitted.

Must be c leared by software.

0RI

Receive Interrupt flag

Set by the rece iver after the stop bit o f a f rame has been received.

Must be c leared by software.

A/T8xC5121

4164G–SCR–07/06

Table 68. BDRCON Register

BDRCON

Baud Rate Control Register (9Bh)

Rese t Value = XXX0 0000b

76543210

- - - BRR TBCK RBCK SPD SRC

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4BRR

Baud Rate Run Control bit

Clear to stop the Baud Rate.

Set to start the Baud Rate.

3TBCK

Transmission Baud rate Generator Selection bit for first UART

Clear to select Timer 1 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

2RBCK

Reception Baud Rate Generator Selection bit for first UART

Clear to select Timer 1 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

1 SPD Baud Rate Speed Control bit for first UART

Clear to select the SLOW Baud Rate Generator when SRC = 1.

Set to select the FAST Baud Rate Generator when SRC = 1.

0SRC

Baud Rate Source select bit in Mode 0 for first UART

Clear to select FOSC/1 2 as the Baud Rat e Generator.

Set to select the internal Baud Rate Generator.

A/T8xC5121

4164G–SCR–07/06

Table 69. S IOCON Register

Serial Input Output Confi guration Register

Rese t Value = 00XX 000 0b

76543210

PMSOEN1 PMSOEN0 - - CPRES

RES EVAUTO VEXT0 VEXT1

Bit

Number Bit

Mnemonic Description

7 - 6 PMOSEN1

PMOSEN0

Output Enable function on Txd/P3.1 and T0/P3.4:

PMSOEN1 PMSOEN0

0 0 PMOS is always off (reset value)

0 1 PMOS is always driven according to P3.1 or P3.4 value

1 0 PMOS is driven only when O E is high

1 1 PMOS is driv en on ly when OE is lo w

5 - 4 - Reserved

The value read from this bit is indeterminate. Do not set this bit.

3CPRES

RES

Card Presence pull-up resistor

0 Internal pull-up is connecte d

1 Internal pull-up is disconnected

2EVAUTO

EVCC Auto setup

Set to enable the Automatic mode of EVCCregulator

Clear to disable the Automatic mode of EV CC regulator

1 - 0 VEXT0

VEXT1

EVCC vol tage configur ation:

VEXT0 VEXT1

0 0 Power -down, E VCC is external (rese t value)

01EV

CC = 1.8V

10EV

CC = 2.3V

11EV

CC = 2.7V

A/T8xC5121

4132C–SCR–07/06

Hardware Watchdog

Timer The WDT is intended as a recovery method in situations where the CPU may be sub-

jected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer

R eSeT (WD TRST) S FR. The WDT is b y defau lt disabl ed from e xiting rese t. To en able

the WDT, user m ust write 01 EH and 0 E1H in se quenc e to the W DTRS T, SFR locatio n

0A6 H. When WDT is enab led, it will increm ent every machine cycle while the oscillator

is running and there is no way to disable the WDT except through reset ( either hardware

reset or WDT overflow reset). When WDT overflows, it wi ll dri ve an output RESET H IGH

pulse at the RST-pin.

Using the WDT To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR

location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH

and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it

reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will

increment every machine cycle while the oscillator is running. This means the user must

reset the WDT at least every 16383 machine cycle. To reset the WDT the user must

write 01E H and 0E1H to WDT RST. WDT RST is a write only reg ister. The WDT c ounter

cannot be read or written. When WDT overflows, it wil l generate an output RESET pulse

at the RST-pin. The RESET pulse duration i s 96 x T C L K PE RI PH , where TCLK PERIPH= 1/ FCLK

PERIPH. To make the best use of the WDT, it s hould be serviced in those sections of c ode

that will periodically be e xecu ted within the tim e required to p re vent a WDT reset.

To have a more powerful WDT, a 27 counter has been added to extend the Time-out

capability, ranking from 16 ms to 2s @ FOSCA = 12 MHz. To manage this feature, refer to

WDTPRG register description, Table 70. The WDTPRG register should be configured

before the WDT activation sequence, and can not be modified until next reset.

Table 70. WDT RST Register

WD TRST - Watchdog Res et Register (0A6h)

Reset Value = XXXX XXXXb

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in

sequence.

76543210

--------

A/T8xC5121

4132C–SCR–07/06

Table 71. WDT PRG Regist er

WDTPRG - Watchdog Timer Out Register (0A7h)

Reset Value = XXXX X000

WDT during Power-down

and Idle In Powe r- down mo de t he osc illato r s top s, w hich me ans the WDT al so s tops . Wh ile in

Power-do wn mo de th e user does not need to service the WDT . There are 2 m et hods of

exiting Power-down mode: by a hardware reset or via a level activated external interrupt

which is enab led prior to entering Power-down mode. When P ower-down is exited with

hardware reset, servicing the WDT should occur as it normally should whenever the

T8 xC5121 i s reset. Exi ting Powe r-down with an interrup t is signif ic antly d ifferent. The

interrupt is held low lo ng enough for the oscillator to st abilize. When the interrupt is

brought high, the int errupt is serviced. To prevent the WDT from resetting the device

while the interrupt pin is held low, the WDT is not started until the int errupt is pulled high.

It is suggested that the WDT be reset during the interrupt service routine.

To ensure that the WDT does not overflow wi thin a f ew states of exiting of powerdown, it

is better to reset the WDT just before entering powerdown.

In the Idle m ode, t he oscillator continues to run. To preve nt th e W DT from res etting the

T8xC5121 while in Idle mode, the user should always set up a timer that will periodically

exit Idle, service the WDT, and re-enter Idle m ode.

76543210

- - - - - S2 S1 S0

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is undetermined. Do not try to set this bit.

2S2WDT Time-out select bit 2

1S1WDT Time-out select bit 1

0S0WDT Time-out select bit 0

S2 S1 S0 Selected Time-out

000 (2

14 - 1) machine cycles, 16. 3 ms @ FOSCA =12 MHz

001 (2

15 - 1) machine cyc les, 32.7 ms @ FOSCA=12 MHz

010 (2

16 - 1) machine cycles, 65. 5 ms @ FOSCA=1 2 MH z

011 (2

17 - 1) machine cycles, 131 ms @ FOSCA=12 MHz

100 (2

18 - 1) machine cycles, 262 ms @ FOSCA=12 MHz

101 (2

19 - 1) machine cycles, 542 ms @ FOSCA=12 MHz

110 (2

20 - 1) machine cycles, 1.05 ms @ FOSCA=12 MHz

111 (2

21 - 1) machine cycles, 2.09 ms @ FOSCA=12 MHz

A/T8xC5121

4164G–SCR–07/06

Electrical Characteristics

Ab solu te Maximum Rating s

DC Parameters TA = -40°C to +85°C; VSS = 0 V; VCC = 2.85V to 5.4V; F = 7.36 to 16 MHz

Table 72. Core DC Parameters (XTAL, RST, P0, P2, AL E, PSEN, EA)

Ambiant Temperature Under Bias ......................-25°C to 85°C

Sto r ag e Tem p e ra t ur e....... ..... ..... .. ..... ..... ..... . -65°C to + 150°C

Voltage on VCC to VSS........................................-0.5V to + 6.0V

Voltage on Any Pin to VSS.......................... -0.5V to VCC + 0.5V

Note: Stresses at or above those listed under “ Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other condi-

tions above those indicated in the operational

sections of this specification is not implied. Exposure

to absolute maximum rating conditions may affect

device reli ability.

Symbo l Paramete r Min Ty p Max Unit Te st Cond it io ns

VIL Input Low Voltage -0.5 0.2 VCC - 0.1 V

VIH Input High Voltage

ex cept XTAL1, RST .2 VCC + .9 VCC + 0.5 V

VIH1 Input High Vo ltage,

XTAL1, RST 0.7 VCC VCC + 0.5 V

VOL Output Low Voltage,

Port 0 and 2 0.45 V IOL = 1.6 mA

VOH Ou tput H igh Volt age ,

Port 0 and 2 0.9 x VCC VI

OH = -40 µA

DICC Digital Supply Output

Current 610 mAC

L = 100 nF

DVCC Digital Supply

Voltage 2.5 2 .9 3.0 V CL = 100 nF

DIcc=10mA

Icc Normal Power Down

mode 80 100 µA 25°C

Icc Pulsed Power Down

mode 20 30 µA 50°C Vcc=3V

Iccop Po wer Supply

current Iccop = 0.25 Freq (MHz) +4 mA

IccIDLE = 0.03 Freq (MHz) +5 mA

VCC = 5.4V and

Bootloader

execution

VPFDP Power-fail high lev el

threshold 2 .55 V

VPFDM Power-fail low level

threshold 2 .45 V

tGPow er Fa il glitc h

time 50 ns

trise, tfall VDD rise and fall

time 1 μs 600 sec.

A/T8xC5121

4164G–SCR–07/06

The operating conditions for ICC Tests are the foll owing:

Fi gure 51 . I CC Test Condition, Active Mode

Fi gure 52 . ICC Test Condition, Idle Mode

Fi gure 53 . ICC Test Condition, Power-down Mode

VCC

ICC

(NC)

CLOCK SIGN AL

All other pins are disconnected.

RST

XTAL2

XTAL1

VSS

VCC

PLC C52 configuration

VCC

RST EA

XTAL2

XTAL1

VSS

VCC

ICC

(NC)

VCC

All other pins are disconnected.

VCC

PLC C52 configuration

CLOCK SIGNAL

VCC

RST EA

XTAL2

XTAL1

VSS

VCC

ICC

(NC)

VCC

All other pins are disconnected.

VCC

PLCC52 configuration

VCC

100

A/T8xC5121

4164G–SCR–07/06

Table 73. Se rial Interface DC parameters (P3.0, P3.1, P3.3 and P3.4)

Table 74. LED outputs DC Parameters (P3.6 and P3.7)

Symbol Parameter Min Typ Max Unit Test Conditions

VIL Inpu t Low Voltage

-0.5

0.4

0.5

EVCC = 1.8V

EVCC = 2.3V

EVCC = 2.8V

External EVcc

A utom ati c EVcc

VIH Inpu t H igh Voltage

1.4

1.6

2.0

0.7 x E VCC EVCC

2.3

2.8

3.3

EVCC +

0.5

EVCC = 1.8V

EVCC = 2.3V

EVCC = 2.8V

External EVCC

A utom ati c EVcc

VOL Output Low

Voltage 0.4 V IOL = 1.2 mA

VOH Output High

Voltage

1.6

1.8

2.2

0.8 x E VCC

1.8

2.3

2.7

EVCC

EVCC = 1. 8V IOH = 1 μA

EVCC = 2.3V

EVCC = 2. 8V IOH = 10μA

External EVCC

EICC Ex tra Supply

Current +3 mA CL = 10 0 nF

EVCC Extra Supply

Voltage

1.6

2.1

2.6

1.6

1.7

2.2

2.7

1.8

2.3

2.8

VCC

CL = 100 nF, 1 .8V

CL = 100 nF, 2.3V

CL = 100 nF, 2 .8V

External EVCC

A utom ati c EVcc

Ts Sampling time Automatic EVcc

Symbol Parameter Min Typ Max Unit Test Conditions

IOL

Output Low

Current, P3.6 and

P3.7 LED modes

2 mA configuration

4 mA configuration

10 mA configuration

(TA = -20°C to +50°C, VCC -

VOL = 2V ± 20%)

101

A/T8xC5121

4164G–SCR–07/06

Table 75. Smart Card 5V Interface DC Parameters

Note: 1. Capacitor = 10 µF, X7 R type. Ma ximum ESR value is 250 mohm, Inductor = 4.7 µH.

Table 76. S mart Card 3V Int erface DC Parameters

Note: 1. Capacitor = 10 µF, X7 R type. Ma ximum ESR value is 250 mohm, Inductor = 4.7 µH.

Table 77. Smart Card 1.8 V Interface DC Parameters

Note: 1. Capacitor = 10 µF, X7 R type. Ma ximum ESR value is 250 mohm, Inductor = 4.7 µH.

Symbol Parameter Min Typ Max Unit Test Conditions

CICC Card Supply

Current 60 121

105

102 mA VCC = 5.4V

VCC = 4V

VCC = 2.85V

CVCC Card Supply

Voltage 4.6 5.4 V CIcc = 60 mA

CVCC Ripple on CVcc 200 mV 0<CIcc<60 mA

CVCC Spikes on CV cc 4.6 5.4 V

Max i. charge 20 n A.s

Max . duration 400 ns

Max . variation CIcc 100 m A

(1)

TVHLl CVcc to 0 750 μsCIcc = 0

CVcc = 5V to 0.4V (1)

Symbol Parameter Min Typ Max Unit Test Conditions

CICC Card S upply

Current 60 110

110 mA VCC = 5.4V

VCC = 4V

VCC = 2.85V

CVCC Car d Sup ply

Voltage 2.76 3.24 V CIcc = 60 mA

CVCC Ripple on CVcc 200 mV 0<CIcc<60 mA

CVCC Spikes on CVcc 2.76 3.24 V Max. charge 10 ns

Max. duratio n 400 n s

Max. variati on CIc c 50 mA

TVHLl CVcc to 0 750 μsCIcc = 0

CV cc = 5V to 0.4V (1)

Symbo l Para me t e r M in Typ Max Unit Te st Cond it io ns

CICC Card Supply

Current 20 109

100

82 mA VCC = 5.4V

VCC = 4V

VCC = 2.85V

CVCC Card Supply

Voltage 1.68 1.92 V CIcc = 20 mA

CVCC Spikes on CVcc 1.68 1.92 V

TVHLl CVcc to 0 750 μsCIcc = 0

CVcc = 5V to 0.4V (1)

102

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4164G–SCR–07/06

Table 78. Smart Card Clock DC Parameters (Port P1.4)

Note: 1. The voltage on CLK should remain between -0.3V and CVCC + 0.3V during dynamic

operation.

Table 79. A lte rnate Card Clock DC parameters (Port P3.6): 5V tolerant

Note: 1. The voltage on CLK should remain between -0.3V and VCC + 0.3V during dynamic

operation.

Symbol Parameter Min Typ Max Unit Test Conditions

VOL Ou tput Lo w

Voltage 0(1)

0(1) 0.2 x CVCC

0.4 VI

OL = 20 μΑ (1.8,3 V)

IOL = 50 μA (5V)

IOL Ou tput Lo w

Current 15 mA

VOH Output High

Voltage

0.7 x CVCC

CVCC - 0. 5

CVCC

IOH = 2 0 μA (1.8V)

IOH = 2 0 μA (3V)

IOH = 5 0 μA (5V)

IOH Output High

Current 15 mA

tR tFRise and Fall time 16

22.5

50 ns

CIN = 30 pF(5 V)

CIN = 30 pF(3 V)

CIN = 30 pF(1 .8V)

Voltage Stability -0.25

CVCC-0.5

0.4 x CVCC

CVCC +

0.25

VLow level

High level

Symbol Parameter Min Typ Max Unit Test Conditions

VOL Ou tput Lo w

Voltage 0 (1)

0(1) 0.2 x DVCC

0.5 VI

OL = 20 μA

IOL = -200 μA

VOH Output High

Voltage 0.7 x DVCC DVCC (1) V IOH = 2 0 μA

tR tFRise and Fa ll

times 18 ns CIN = 30 pF

103

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4164G–SCR–07/06

Table 80. S mart Card I/O DC Parameters (P1.0)

Note: 1. The voltage on RST should remain between -0.3V and CVCC + 0.3V during dynamic

operation.

Table 81. Alterna te Card I/O DC Paramet ers (P3.5) : 5V tolerant

Note: 1. The voltage on I/O should remain between -0.3V and DVCC + 0.3V during dynamic

operation.

Symbol Parameter Min Typ Max Unit Test Conditions

VIL In p ut Low Voltage 0(1)

0(1)

0.5

0.15 x

CVCC

IL = 500 μA

IIL = 20 μA

IIL Input Low Current 500 μA

VIH In p ut High Voltage 0.7 x CVCC CVCC VI

IH = -20 μA

IIH Input High Current -20 / +20 μA

VOL Ou tput Lo w

Voltage 0(1) 0.4

0.4

0.3 VIOL = 1μA (5V )

IOL = 1 mA (3V)

IOL = 1 mA (1.8V)

IOL Ou tput Lo w

Current 15 mA

VOH Output High

Voltage 0.8 x CVCC CVCC (1) V IOH = 2 0 μA (5V,3V,1.8V)

IOH Output High

Current 15 mA

tR tFRise and Fa ll

times 0.8 μsC

IN = 30 pF Output

Symbol Parameter Min Typ Max Unit Test Conditions

VIL In p ut Low Voltage -0.3 0.2 x DV CC VI

IL = 1 mA

VIH In p ut High Voltage 0.7 x DVCC DVCC + 0.3 V IIH = -20 μA

VOL Ou tput Lo w

Voltage 0(1) 0.3 V IOL = 1000 μA

VOH Output High

Voltage 0.7 x DVCC DVCC (1) V IOH = 2 0 μA

tR tFRise and Fa ll

delays 1μsC

IN = 30 pF

104

A/T8xC5121

4164G–SCR–07/06

Table 82. Smart Card RST, CC4, CC8, DC Parameters (Port P1.5, P1.3, P1.1)

Note: 1. The voltage on RST should remain between -0.3V and CVCC + 0.3V during dynamic

operation.

Table 83. Alterna te Card RST DC Param eters (Port P3.7) : 5V tol erant

Note: 1. The voltage on RST should remain between -0.3V and DVCC + 0.3V during dynamic

operation.

Table 84. Card Presence DC Pa rameters (P1.2)

Symbol Parameter Min Typ Max Unit Test Conditions

VOL Out put Low Voltage 0(1)

0(1)

0.12 x

CVCC

0.4 VIOL = 20 μΑ

IOL = 5 0 μΑ

IOL Output Low Current 15 mA

VOH Output High V o lt age CVCC - 0.5

0.8 x C VCC

CVCC

CVCC (1) VI

OH = 50 μΑ

IOH = 20 μΑ

IOH Output High Current 15 mA

tR tFRise and Fall delays 0.8 μsC

IN = 30 pF

Voltage stability -0.25

CVCC-0.5

0.4 x CVCC

CVCC +

0.25

Low level

High level

Symbol Parameter Min Typ Max Unit Test Conditions

VOL Output L ow Voltage 0 (1) 0.2 x DVCC VI

OL = 200 μΑ

VOH Output High Voltage 0.8 x DVCC

0.8 x D VCC

DVCC (1)

DVCC VIOH = 20 μΑ (1.8V)

IOH = 200 μΑ (3V)

tR tFRise and Fall delays 400 μsC

IN = 30 pF

Symbol Parameter Min Typ Max Unit Test Conditions

IOL1 CPRES weak pull-

up ou tput current 31025μAP1.2 = 1, short to VSS

(i nte r na l pu ll-up enab led)

105

A/T8xC5121

4164G–SCR–07/06

Typical Application

Figure 54. Typic al Application Diagram

Notes: 1. C4 and C5 must be placed near IC and have l ow ESR (<250mΩ)

2. Straight and short connect ions avoid any loop between:

- CVSS and VSS

- CVCC and C4, C5

3. VCC connection of the mas ter card must be placed as follows:

4. Curre nt i s li m it ed to 10 mA.

5. CCLK should be routed far from CRST, CIO, CC4, CC8 and armored by ground plane.

10µF

VCC

RxD

TxD

VCC

TxD

RxD

XTAL1 XTAL2

CPRES

CRST

CCLK

CC4

CC8

CIO

CVCC(1)(2)(3)

VSS I/O

CLK(5)

RST

4.7 µF

VSS

RTS

VSS

INT1/OE

VSS

100nF

VSS

DVCC

EVCC

100nF

VSS

DVCC(4) LED0

LED1

C1 C2 C3

4.7 µH

VSS VSS

I/O

RST

CLK

Alternate

Card

CIO1

CRST1

CCLK1

VCC

1Mohm

(optional resistor )

or VCC

Serial Interface

CVSS

22 pF

VSS

Vcc

Positive

Detection

Mode

Resonator

or Quartz w ith s tandard

capacitors

100nF

P1.2

P1.0

P1.1

P1.3

P1.4

P3.5

P3.7

P3.6

10 kohm

82 pF

VSS

CVCC

P3.6

P3.7

P3.4

P3.3

P3.1

P3.0

P1.5

VCC to card VCC

VSS

C4, C5

106

A/T8xC5121

4164G–SCR–07/06

6. Distance between Device pads and Smart Card connector must be less than 4

centimeters.

7. C6,C7 should be as close as possible to the Smart Card connector to reduce noise

and interferences.

107

A/T8xC5121

4164G–SCR–07/06

Ordering Information

Note: 1. Contact Atmel for availability.

Part Number Code Memory

Size (Bytes) Supply Voltage Temperature

Rang e Max Frequency Package Pack ing Product

Marking

T83C5121xxx-

ICSIL 16K ROM 2.85 - 5.4V Industrial 16 MHz SSOP24 Stick 83C5121-IL

T83C5121xxx-

ICRIL 16K ROM 2.85 - 5.4V Industrial 16 MHz SSOP24 Tape & Re el 83C5121-IL

T83C5121xxx-

S3SIL 16K ROM 2.85 - 5.4V Industrial 16 MHz PLCC52(1) Stick 83C5121-IL

T83C5121xxx-

S3RIL 16K ROM 2.85 - 5.4V Industrial 16 MHz PLCC52(1) Tape & Reel 83C5121-IL

T85C5121-ICSIL 16K RAM 2.85 - 5.4V Industrial 16 MHz SSOP24 Stick 85C5121-IL

T85C 5121-ICRIL 16K RAM 2.85 - 5. 4V Industrial 16 MHz SSOP24 Tape & Re el 85C5121-IL

T85C5121-S3SIL 16K RAM 2.85 - 5.4V Industrial 16 MHz PLCC52 Stick 85C5121-IL

T85C5121-S3RIL 16K RAM 2.85 - 5.4V Industrial 16 MHz PLCC52 Tape & Reel 85C5121-IL

T89C5121-ICSIL 16K Flash RAM 2.85 - 5.4V Industrial 16 MHz SSOP24 Stick 89C5121-IL

T89C 5121-ICRIL 16K Flash RAM 2.85 - 5.4V Industr ial 16 MHz SSOP24 Tape & Re el 89C5121-IL

AT83C5121xxx-

ICSUL 16K ROM 2.85 - 5.4V In dustrial &

Green 16 MHz SSOP24 S ti ck 8 3C5121-UL

AT83C5121xxx-

ICRUL 16K ROM 2.85 - 5.4V Industrial &

Green 16 MHz SSOP24 Tape & Reel 83C5 121-UL

AT83C5121xxx-

PUTUL 16K ROM 2.85 - 5.4V In dustrial &

Green 16 MHz QFN32 Tray 83C5121-UL

AT83C5121xxx-

PURUL 16K ROM 2.85 - 5.4V Industrial &

Green 16 MHz QFN32 Tray 83C5121-UL

AT83C5121xxx-

S3SUL 16K ROM 2.85 - 5.4V Industrial &

Green 16 MHz PLCC52(1) Stick 83C5121-UL

AT83C5121xxx-

S3RUL 16K ROM 2.85 - 5.4V Industrial &

Green 16 MHz PLCC52(1) Tape & Reel 83C5121-UL

AT85C5121-

ICSUL 16K RAM 2.85 - 5.4V Industrial &

Green 16 MHz SSOP24 S ti ck 8 5C5121-UL

AT85C5121-

ICRUL 16K RAM 2.85 - 5.4V Industrial &

Green 16 MHz SSOP24 Tape & Reel 85C5 121-UL

AT85C5121-

S3SUL 16K RAM 2.85 - 5.4V Industrial &

Green 16 MHz PLCC52 S tick 85C5121-UL

AT85C5121-

S3RUL 16K RAM 2.85 - 5.4V Industrial &

Green 16 MHz PLCC52 Tape & Reel 85C5121-UL

AT89C5121-

ICSUL 16K Flash RAM 2.85 - 5.4V Industrial &

Green 16 MHz SSOP24 S ti ck 8 9C5121-UL

AT89C5121-

ICRUL 16K Flash RAM 2.85 - 5.4V Industrial &

Green 16 MHz SSOP24 Tape & Reel 89C5 121-UL

108

A/T8xC5121

4164G–SCR–07/06

Pac kag e Dra win g s

SSOP24

109

A/T8xC5121

4164G–SCR–07/06

PLCC52

110

A/T8xC5121

4164G–SCR–07/06

QFN32

111

A/T8xC5121

4164G–SCR–07/06

Document Revision History for T8xC5121

Changes from 4164B -

06/02 to 4164C - 07/03 1. P orts description update.

2. Added Bootloader Au tobaud table.

3. Modified ICC test conditions Fig ure 51.

4. Added ICCOP powe r supply current characteristics.

5. Added ICCO pulsed power down m ode c urrent characteristics.

6. Modified Smart card characteristics : VCC/CVCC mixed.

Changes from 4164C -

07/03 to 4164D - 12/03 1. Changed value of EMV to EMV200 0. Section “F eatures ”, page 1.

Changes from 4164D -

12/03 to 4164E - 01/04 1. DVcc Min/Max values changed, page 96.

2. Alternate Card Pads are 5V tolerant, pag e 99.

Changes from 4164E -

01/04 to 4164F 11/05 1. Added green product ordering information.

Changes from 4164F

11/05 to 4164F 07/06 1. Added QF N32 package to ordering information.

i4164G–SCR–07/06
A/T8xC5121
Table of 
Contents Features ................................................................................................. 1
Description ............................................................................................ 2
Block Diagram  ...................................................................................... 2
Pin Description  ..................................................................................... 3
Signals...................................................................................................................5
Port Structure Description ....................................................................................10
SFR Mapping  ....................................................................................... 12
PowerMonitor ...................................................................................... 14
Description.......................................................................................................... 14
PowerMo n itor Diagra m.......... .......... ......... ........................ .................................. 14
Power Monitoring and Clock Management ...................................... 16
Idle Mode............................................................................................................ 16
Power-down Mode.............................................................................................. 16
Clock Manag ement.............................................................................  22
Functional Block Diag ram................................................................................... 22
X2 Featu r e............................. .......... ......... .......................... .......... .......................23
Clock Prescaler....................................................................................................24
Clock Control Registers...................................................................................... 24
DC/DC Clock  ................. ...................................................................... 27
Clock Control Register........................................................................................ 27
Clock Prescaler................................................................................................... 27
Smart Card Interface Block (SCIB)  ................................................... 29
Introduction......................................................................................................... 29
Main Features..................................................................................................... 29
Blo ck Diag r a m......... ..................................................................... ......... .......... ....30
Functional Descriptio n........................................................................................ 30
Other Features.....................................................................................................35
DC/DC Converter... .... ................. ................. ................ ................. ................ .......37
Registers Descriptio n. ..... .......... ......... ................. ................ ................. ................38
Interrupt System ................................................................................. 47
INT1 Interrupt Vector.......................................................................................... 48
LED Ports Configuration .................................................................... 57
Registers Defi n ition.. ..................................................................... ...................... 57
Dual Da ta Pointer .......... ............................ ......... .......... ......... ......... ..... 58

ii
4164G–SCR–07/06
A/T8xC5121
Memory Management ......................................................................... 60
Pro gram Memory................................................................................................ 60
In-System Pro gramming..................................................................................... 63
Protection Mec hanism s . ........................................... .......................................... 66
Autobaud............................................................................................................ 71
Pro tection M echanism s ............................. ..................................................... .... 71
Timers/Counters ................................................................................. 73
Introduction......................................................................................................... 73
Timer 0/Counter Operations....................... ................... ..................... ................ 73
Timer 0.................................................................................................................74
Timer 1.................................................................................................................77
Registers............................................................................................................. 78
Serial I/O Port ...................................................................................... 81
Fra mi n g Erro r  De te cti o n...... ............................................................................... 81
Automatic Add ress Recogni tion................................ .......................... ................ 82
UART Output Configuration................................................................................ 84
UART Control Registers..................................................................................... 85
UART Timings ..................................................................................... 86
Mode Selec tion........................ ............................................ ............................... 86
Baud Rate Generator... ................... .................. ........................... ................... .... 86
Asynchronous Modes (Modes 1, 2 and 3)..... ......... ............ ....... ....... ............ .......89
Hardware Watchdog Timer ................................................................ 96
Using the WDT ................................................................................................... 96
WDT during Power-down and Idle..................... ..................................... ............ 97
Electrical Char act eristics ...... .......... ......... ......... .......... ......... .............. 98
Absolute Maxi mu m Ratin g s .. ..... ........................................................................ 98
DC Parameters................................................................................................... 98
Typical Applicati on ................ .......... ......... ......... .......... ......... ............ 105
Ordering Information........................................................................  107
Package Drawings............................................................................  108
SSOP24..... ............ ......... ........................................ .......... ................................ 108
PLCC52.............................................................................................................109
QFN32...............................................................................................................110
Document Revision History for T8xC5121.....................................  111
Changes from 4164 B -06/02 to 4164C  - 07/0 3........................... ...................... 111
Changes from 4164 C - 07/03 to 4164D - 12/03 ................... .................... ......... 111
Changes from 4164 D - 12/03 to 4164E - 01/04. ............................................... 111

iii 4164G–SCR–07/06

A/T8xC5121

Changes from 4164 E - 01/04 to 4 164F 11/ 05 ................................. ................. 111

Changes from 4164 F 11/05 to 4164F 07/06........................ ............................. 111

Table of Cont ents .................................................................................. i

Pr inted o n rec ycled paper.

4164G–SCR–07/06

are th e tr a de ma rk s of At m el Corporatio n or its s u bs id iaries. O ther terms an d pr o du c t nam es m a y be tr a de m ar k s of othe r s.

Disclaimer: The information in this doc ument is provided in connection with A tmel products. No l icense, express or implied, by estoppel o r otherwise,to anyintellectu-

alproperty right is granted by this doc ument or in connec tion with the s ale of A tmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-TIONS OF

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TION) ARISING OUTOF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAM-

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authorized, or warranted for usea s components in applications intended to support or sustainlife.

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