PCA9624BS,118"" - NXP SEMICONDUCTORS

1. General description

The PCA9624 is an I2C-bus controlled 8-bit LED driver optimized for voltage switch

dimming and blinking 100 mA Red/Green/Blue/Amber (RGBA) LEDs. Each LED output

has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller that

operates at 97 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the

LED to be set to a specific brightness value. An additional 8-bit resolution (256 steps)

group PWM controller has both a fixed frequency of 190 Hz and an adjustable frequency

between 24 Hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 %

to 99.6 % that is used to either dim or blink all LEDs with the same value.

Each LED output can be off, on (no PWM control), set at its individual PWM controller

value or at both ind ivi dual an d group PWM controller values. The PCA9624 oper ates with

a supply voltage range of 2.3 V to 5.5 V and the 100 mA open-drain outputs allow

voltages up to 40 V.

The PCA9624 is one of the first LED controller devices in a new Fast-mode Plus (Fm+)

family. Fm+ devices offer higher frequency (up to 1 MHz) and more densely populated

bus operatio n (u p to 40 00 pF).

The active LOW Output Enable input pin (OE) blinks all the LED output s and can be u sed

to externally PWM the outputs, which is useful when multiple devices need to be dimmed

or blinked together without using software control.

Software programmable LED Group and three Sub Call I2C-bus addresses allow all or

defined groups of PCA9624 devices to respond to a common I2C-bus address, allowing

for example, all red LEDs to be turned on or off at the same time or marq ue e ch as ing

effect, thus minimizing I2C-bus commands. Seven hardware address pins allow up to

126 devices on the same bus.

The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9624

through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to

their default state causing the outputs to be set HIGH (LED off). This allows an easy and

quick way to reconfigure all device registers to the same condition.

The PCA9624 and PCA9634 software is identical and if the PCA9624 on-chip 100 mA

NAND FETs do not provide enough current or voltage to drive the LEDs, then the

PCA9634 with larger current or higher voltage external drivers can be used.

PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

Rev. 3 — 6 September 2012 Product data sheet

Product data sheet Rev. 3 — 6 September 2012 2 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

2. Features and benefits

8 LED drivers. Each output programmable at:

Off

On

Programmable LED brightness

Programmable group dimming/blinking mixed with individual LED brightness

1 MHz Fast-mode Plus compatible I2C-bus interface with 30 mA high drive capability

on SDA output for driving high capacitive buses

256-step (8-bit) linear programmable brightness per LED output varying from fully off

(default) to maximum brightness using a 97 kHz PWM signal

256-step group brightness control allows general dimming (using a 190 Hz PWM

signal) from fully off to maximum brightness (default)

256-step group blinkin g with freq ue ncy pr ogram mab le from 24 Hz to 10.73 s and duty

cycle from 0 % to 99.6 %

Eight open-drain outputs can sink between 0 mA to 100 mA and are tolerant to a

maximum off state voltage of 40 V. No input function.

Output state change programmable on the Acknowledge or the STOP Command to

update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).

Active LOW Output Enable (OE) input pin allows for hardware blinking and dimming of

the LEDs

7 hardware address pins allow 126 PCA9624 devices to be connected to the same

I2C-bus and to be individually programmed

4 software programmable I2C-bus addresses (one LED Group Call address and three

LED Sub Call addresses) allow groups of devices to be addressed at th e same time in

any combination (for example, one register used for ‘All Call’ so that all the PCA9624s

on the I2C-bus can be addressed at the same time and the second register used for

three different addresses so that 1⁄3 of all devices on the bus can be addressed at the

same time in a group). Software enable and disable for I2C-bus address.

Software Reset feature (SWRST Call) allows the device to be reset through the

I2C-bus

25 MHz internal oscillator requires no external components

Internal power- on res et

Noise filter on SDA/SCL inputs

No glitch on power-up

Supports hot insertion

Low standby current

Operating power supply voltage (VDD) range of 2.3 V to 5.5 V

5.5 V tolerant inputs on non-LED pins

40 C to +85 C operation

ESD protection exceeds 2000 V HBM per JESD22- A114 and 1000 V CDM per

JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Packages offered: TSSOP24, HVQFN24

Product data sheet Rev. 3 — 6 September 2012 3 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

3. Applications

RGB or RGBA LED drivers

LED status information

LED displays

LCD backlights

Keypad backlights for cellular phones or handheld devices

4. Ordering information

5. Block diagram

Table 1. Ordering information

Type number Topside mark Package

Name Description Version

PCA9624BS 9624 HVQFN24 plastic thermal enhanced very thin quad flat package;

no leads; 24 terminals; body 4 40.85 mm SOT616-3

PCA9624PW PCA9624PW TSSOP24 plastic thin shrink small outline package; 24 leads;

body width 4.4 mm SOT355-1

Remark: Only one LED output shown for clarity.

Fig 1. Block diagram of PCA9624

A0 A1 A2 A3 A4 A5 A6

002aad591

C-BUS

CONTROL

INPUT FILTER

PCA9624

POWER-ON

RESET

SCL

SDA

LED

STATE

SELECT

PWM

BRIGHTNESS

CONTROL

GRPFREQ

MUX/

CONTROL

'0' – permanently OFF

'1' – permanently ON

LEDn

190 Hz

24.3 kHz

97 kHz

25 MHz

OSCILLATOR

FET

DRIVER

Product data sheet Rev. 3 — 6 September 2012 4 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 2. Pin configuration for TSSOP Fig 3. Pin configuration for HVQFN24

VDD

SDA

SCL

VSS

LED7

LED6

LED5

LED4

VSS

LED0

LED1

LED2

LED3

VSS

PCA9624PW

002aad593

002aad594

PCA9624BS

Transparent top view

LED6

LED0

LED1

LED7

VSS VSS

A4 OE

A3 A5

A2 A6

LED2

LED3

VSS

LED4

LED5

VSS

VDD

SDA

SCL

terminal 1

index area

613

514

4 15

3 16

2 17

118

Table 2. Pin description

Symbol Pin Type Description

TSSOP24 HVQFN24

VSS 1, 7, 12, 13, 18 4, 9, 22, 10, 15 [1] power supply supply ground

A0 2 23 I address input 0

A1 3 24 I address input 1

A2 4 1 I address input 2

A3 5 2 I address input 3

A4 6 3 I address input 4

LED0 8 5 O LED driver 0

LED1 9 6 O LED driver 1

LED2 10 7 O LED driver 2

LED3 11 8 O LED driver 3

LED4 14 11 O LED driver 6

LED5 15 12 O LED driver 7

LED6 16 13 O LED driver 8

LED7 17 14 O LED driver 9

OE 19 16 I active LOW output enable

A5 20 17 I address input 5

A6 21 18 I address input 6

SCL 22 19 I serial clock line

SDA 23 20 I/O serial data line

VDD 24 21 power supply supply voltage

Product data sheet Rev. 3 — 6 September 2012 5 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

[1] HVQFN24 package supply ground is connected to both VSS pins and exposed center pad. VSS pins must

be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board

level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad

on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the

PCB in the thermal pad region.

7. Functional description

Refer to Figure 1 “Block dia gram of PCA9624”.

7.1 Device addresses

Following a START condition, the bus master mus t ou tpu t th e ad dr es s of th e slav e it is

accessing.

There are a maximum of 128 possible programmable addresses using the 7 hardware

address pins. Two of these addresses, Software Reset and LED All Call, cannot be used

because their default power-up state is ON, leaving a maximum of 126 addresses. Using

other reserved addresses, as well as any other Sub Call address, will reduce the total

number of possible addresses even further.

7.1.1 Regular I2C-bus slave address

The I2C-bus slave address of the PCA9 62 4 is shown in Figure 4. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW.

Remark: Using reserved I2C-bus addresses will interfere with other devices, but only if

the devices are on the bus and/or the bus will be open to other I2C-bus systems at some

later date. In a closed system where the designer controls the address assignment these

addresses can be used since the PCA9624 treats them like any other address. The

LED All Call, Software Rest and PCA9 564 or PCA9665 slave address (if on the bus) can

never be used for individual device addresses.

•PCA9624 LED All Call address (1110 000) and Sof tware Reset (0000 01 10) which are

active on start-up

•PCA9564 (0000 000) or PCA9665 (1110 000) slave address which is active on

start-up

•‘reserved for future use’ I2C- bus addresses (0000 011, 1111 1XX)

•slave devices that use the 10-bit addressing scheme (1111 0XX)

•slave devices that are designed to respond to the General Call address (0000 000)

•High-speed mode (Hs-mode) master code (0000 1XX)

Fig 4. Slave address

R/W

002aab319

A6 A5 A4 A3 A2 A1 A0

hardware selectable

slave address

Product data sheet Rev. 3 — 6 September 2012 6 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

The last bit of the addre ss byte defines the op eration to be per formed. When set to logic 1

a read is selected, while a logic 0 selects a write operation.

7.1.2 LED All Call I2C-bus address

•Default power-up value (ALLCALLADR register): E0h or 1110 000

•Programmable through I2C-bus (volatile programming)

•At power-up, LED All Call I2C-bus address is ena bled. PCA9624 se nds an ACK whe n

E0h (R/W = 0) or E1h (R/W = 1) is sent by the master.

See Section 7.3.8 “ALLCALLADR, LED All Call I2C-bus address” for more detail.

Remark: The default LED All Call I2C-bus address (E0h or 1110 000) must not be used as

a regular I2C-bus slave address since this address is enabled at power-up. All the

PCA9624s on the I2C-bus will acknowledge the address if sent by the I2C-bus master.

7.1.3 LED Sub Call I2C-bus addresses

•3 different I2C-bus addresses can be used

•Default power-up values:

–SUBADR1 register: E2h or 1110 001

–SUBADR2 register: E4h or 1110 010

–SUBADR3 register: E8h or 1110 100

•Programmable through I2C-bus (volatile programming)

•At power-up, Sub Call I2C-bus addresses are disabled. PCA9624 does not send an

ACK when E2h (R/W =0) or E3h (R/W= 1), E4h (R/W = 0) or E5h (R/W =1), or

E8h (R/W = 0) or E9h (R/W = 1 ) is sen t by th e ma st er.

See Section 7.3.7 “SUBADR1 to SUBADR3, I2C-bus su ba dd r ess 1 to 3” for more detail.

Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus

slave addresses as long as they are disabled.

7.1.4 Software Reset I2C-bus address

The address shown in Figure 5 is used when a re set of the PCA9624 needs to be

performed by the master. The Software Reset address (SWRST Call) must be used with

R/W = logic 0. If R/W = logic 1, the PCA9624 does not acknowledge the SWRST. See

Section 7.6 “Software reset” for more detail.

Remark: The Software Reset I2C-bus address is a rese rved address and ca nnot be used

as a regular I2C-bus slave address or as an LED All Call or LED Sub Call address.

Fig 5. Software Reset address

002aab416

0000011

R/W

Product data sheet Rev. 3 — 6 September 2012 7 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

7.2 Control register

Following the successful acknowledgement of the slave address, L ED All Call address or

LED Sub Call address, the bus master will send a byte to the PCA9624, which will be

stored in the Control register.

The lowest 5 bits are used as a pointer to determine which register will be accessed

(D[4:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options

(AI[2:0]).

When the Auto-Increment flag is set (AI2 = logic 1), the five low order bits of the Control

program the registers sequentially. Four different types of Auto-Increme nt ar e po ssible,

depending on AI1 and AI0 values.

Remark: Other combinations not shown in Table 3 (AI[2:0] = 001, 010, and 011) are

reserved and must not be used for proper device operation.

AI[2:0] = 000 is used when the same register must be accessed several times during a

single I2C-bus communication, for exa mple, changes the brightness of a single LED. Dat a

is overwritten each time the register is accessed during a write operation.

AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example,

power-up programming.

AI[2:0] = 101 is used when the 16 LED drivers must be individually programmed with

different values during the same I2C-bus communication, for example, changing color

setting to another color setting.

reset state = 80h

Remark: The Control register does not apply to the Software Reset I2C-bus address.

Fig 6. Control register

Table 3. Auto-Increment options

AI2 AI1 AI0 Function

0 0 0 no Auto-Increment

1 0 0 Auto-Increment for al l registers. D[4:0] roll over to 00h after the last

1 0 1 Auto-Increment for individual brightness registers only. D[4:0] roll over to

02h after the last register (11h) is accessed.

1 1 0 Auto-Increment fo r global control registers only. D[4:0] roll over to 0Ah’

after the last register (0Bh) is accessed.

1 1 1 Auto-Increment for individual and global control registers only. D[4:0] roll

over to 02h after the last register (0Bh) is accessed.

002aac147

AI2 AI1 AI0 D4 D3 D2 D1 D0

Auto-Increment flag

Auto-Increment options

Product data sheet Rev. 3 — 6 September 2012 8 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

AI[2:0] = 110 is used when the LED drivers must be globally programmed with different

settings during the same I2C-bus communication, for example, global brightness or

blinking change.

AI[2:0] = 111 is used when individual and global changes must be performed during the

same I2C-bus communication, for exam ple, ch angi ng a color and global brightness at the

same time.

Only the 5 least signific an t bits D[4:0] are affected by the AI[2:0] bits.

When the Control register is written, the register entry point determined by D[4:0] is the

first register that will be addres sed (read or write operation), and can be anywhere

between 0 0000 and 1 0001 (as defined in Table 4). When AI[2] = 1, the Auto-Increment

flag is set and the rollover value at which the register increment stop s and goes to the next

one is determined by AI[2:0]. See Table 3 for rollover values. For example, if the Control

hexadecimal):

04 …0B 02 …0B 02 …0B 02 …0B 02 … as long

as the master keeps sending or reading data.

7.3 Register definitions

[1] Only D[4:0] = 0 0000 to 1 0001 are allowed and will be acknowledged. D[4:0] = 1 0010 to 1 1111 are reserved and will not be

acknowledged.

[2] When writing to the Control register, bit 4 must be programmed with logic 0 for proper device operation.

Table 4. Register summary[1][2]

00h 0 0 0 0 0 MODE1 read/write Mode register 1

01h 0 0 0 0 1 MODE2 read/write Mode register 2

02h 0 0 0 1 0 PWM0 read/write brightness control LED0

03h 0 0 0 1 1 PWM1 read/write brightness control LED1

04h 0 0 1 0 0 PWM2 read/write brightness control LED2

05h 0 0 1 0 1 PWM3 read/write brightness control LED3

06h 0 0 1 1 0 PWM4 read/write brightness control LED4

07h 0 0 1 1 1 PWM5 read/write brightness control LED5

08h 0 1 0 0 0 PWM6 read/write brightness control LED6

09h 0 1 0 0 1 PWM7 read/write brightness control LED7

0Ah 0 1 0 1 0 GRPPWM read/write group duty cycle control

0Bh 0 1 0 1 1 GR PF REQ read/write group frequency

0Ch 0 1 1 0 0 LEDOUT0 read/write LED output state 0

0Dh 0 1 1 0 1 LEDOUT1 read/write LED output state 1

0Eh 01110SUBADR1 read/writeI

2C-bus subaddress 1

0Fh 01111SUBADR2 read/writeI

2C-bus subaddress 2

10h 10000SUBADR3 read/writeI

2C-bus subaddress 3

11h 1 0 0 0 1 ALLCALLADR read/write LED All Call I2C-bus address

Product data sheet Rev. 3 — 6 September 2012 9 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

7.3.1 Mode register 1, MODE1

[1] It takes 500 s max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. T imings

on LEDn outputs are not guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the

500 s window.

[2] No blinking or dimming is possible when the oscillator is off.

7.3.2 Mode register 2, MODE2

[1] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9624.

Applicable to registers from 02h (PWM0) to 08h (LEDOUT) only.

[2] Remark: If you change these bits from their default values, the device will not perform as expected.

Table 5. MODE1 - Mode regis te r 1 (address 00h) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 AI2 read only 0 Register Auto-Increment disabled.

1* Register Auto-Increment enabled.

6 AI1 read only 0* Auto-Increment bit 1 = 0 .

1 Auto-Increment bit 1 = 1.

5 AI0 read only 0* Auto-Increment bit 0 = 0 .

1 Auto-Increment bit 0 = 1.

4 SLEEP R/W 0 Normal mode[1].

1* Low power mode. Oscillator off[2].

3 SUB1 R/W 0* PCA9624 does not respo nd to I2C-bus subaddress 1.

1 PCA9624 responds to I2C-bus subaddress 1.

2 SUB2 R/W 0* PCA9624 does not respo nd to I2C-bus subaddress 2.

1 PCA9624 responds to I2C-bus subaddress 2.

1 SUB3 R/W 0* PCA9624 does not respo nd to I2C-bus subaddress 3.

1 PCA9624 responds to I2C-bus subaddress 3.

0 ALLCALL R/W 0 PCA9624 does not respond to LED All Call I2C-bus

address.

1* PCA9624 responds to LED All Call I2C-bus address.

Table 6. MODE2 - Mode regis te r 2 (address 01h) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 - read only 0* reserved

6 - read only 0* reserved

5 DMBLNK R/W 0* group control = dimming.

1 group control = blinking.

4 INVRT R/W 0* reserved; write must always be a logic 0

3 OCH R/W 0* outputs change on STOP command[1]

1 outputs change on ACK

2 - R/W 1* reserved; write must always be a logic 1[2]

1 - R/W 0* reserved; write must always be a logic 0[2]

0 - R/W 1* reserved; write must always be a logic 1[2]

Product data sheet Rev. 3 — 6 September 2012 10 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

7.3.3 PWM0 to PWM7, individual brightness control

A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through

256 linear steps from 00h (0 % duty cycle = LED output off) to FFh

(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs

programmed with LDRx = 10 or 11 (LEDOUT0 to LEDOUT3 registers).

(1)

7.3.4 GRPPWM, group duty cycle control

When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed

frequency signa l is supe rim p os ed with the 97 kHz individual brightness control signal.

GRPPWM is then used as a global brightness control allowing the LED outputs to be

dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.

General brightness for the 16 outputs is controlled through 256 linear steps from 00h

(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3

registers).

When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers

define a global blinking pattern, where GRPFREQ contains the blinking period (from

24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).

(2)

Table 7. PWM0 to PWM7 - PWM registers 0 to 7 (address 02h to 09h) bit description

Legend: * default value.

Address Register Bit Symbol Access Value Description

02h PWM0 7:0 IDC0[7:0] R/W 0000 0000* PWM0 Individual Duty Cycle

03h PWM1 7:0 IDC1[7:0] R/W 0000 0000* PWM1 Individual Duty Cycle

04h PWM2 7:0 IDC2[7:0] R/W 0000 0000* PWM2 Individual Duty Cycle

05h PWM3 7:0 IDC3[7:0] R/W 0000 0000* PWM3 Individual Duty Cycle

06h PWM4 7:0 IDC4[7:0] R/W 0000 0000* PWM4 Individual Duty Cycle

07h PWM5 7:0 IDC5[7:0] R/W 0000 0000* PWM5 Individual Duty Cycle

08h PWM6 7:0 IDC6[7:0] R/W 0000 0000* PWM6 Individual Duty Cycle

09h PWM7 7:0 IDC7[7:0] R/W 0000 0000* PWM7 Individual Duty Cycle

duty cycle IDCx 7:0

256

---------------------------

Table 8. GRPPWM - Group brightness control register (address 0Ah) bit descriptio n

Legend: * default value

Address Register Bit Symbol Access Value Description

0Ah GRPPWM 7:0 GDC[7:0] R /W 11111111 GRPPWM re gister

duty cycle GDC 7:0

256

--------------------------

Product data sheet Rev. 3 — 6 September 2012 11 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

7.3.5 GRPFREQ, group frequency

GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3

registers).

Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)

to FFh (10.73 s).

(3)

7.3.6 LEDOUT0 and LEDOUT1, LED driver output state

LDRx = 00 — LED driver x is off (default power-up state ).

LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking

not controlled ).

LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx

LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be

controlled through its PWMx register and the GRPPWM registers.

Table 9. GRPFREQ - Group Frequency re gister (address 0Bh) bit description

Legend: * default value.

Address Register Bit Symbol Access Value Description

0Bh GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000* GRPFREQ register

global blinking period GFRQ 7:01+

----------------------------------------s=

Table 10. LEDOUT0 to LEDOUT1 - LED driver output state register (address 0Ch to 0Dh)

bit description

Legend: * default value.

Address Register Bit Symbol Access Value Description

0Ch LEDOUT0 7:6 LDR3 R/W 00* LED3 output state control

5:4 LDR2 R/W 00* LED2 output state control

3:2 LDR1 R/W 00* LED1 output state control

1:0 LDR0 R/W 00* LED0 output state control

0Dh LEDOUT1 7:6 LDR7 R/W 00* LED7 output state control

5:4 LDR6 R/W 00* LED6 output state control

3:2 LDR5 R/W 00* LED5 output state control

1:0 LDR4 R/W 00* LED4 output state control

Product data sheet Rev. 3 — 6 September 2012 12 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

7.3.7 SUBADR1 to SUBADR3, I2C-bus subaddress 1 to 3

Subaddresses are programmable through the I2C-bus. Default power-up va lues are E2h,

E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up

(the corresponding SUBx bit in MODE1 register is equal to 0).

Once subaddresses have been programmed to their right values, SUBx bits need to be

set to logic 1 in order to have the device acknowledging these addresses (MODE1

Only the 7 MSBs representing the I2C-bus subaddress are valid. The LSB in SUBADRx

When SUBx is set to logic 1, the corresponding I2C-bus subaddress can be used during

either an I2C-bus re ad or writ e se qu en ce .

7.3.8 ALLCALLADR, LED All Call I2C-bus address

The LED All Call I2C-bus address allows all the PCA9624s on the bus to be programmed

at the same time (ALLC A LL bit in re gist er MOD E 1 m ust be eq ua l to 1 (p ow er -u p de fa ult

state)). This address is programmable through the I2C-bus and can be used during either

an I2C-bus read or write sequence. The register address can also be programmed as a

Sub Call.

Only the 7 MSBs representing the All Call I2C-bus address are valid. The LSB in

ALLCALLADR register is a read-only bit (0).

If ALLCALL bit = 0, the device does n ot acknowledge the ad dress programmed in register

ALLCALLADR.

Table 11. SUBADR1 to SUBADR3 - I2C-bus subad dress registers 0 to 3 (address 0Eh to

10h) bit description

Legend: * default value.

Address Register Bit Symbol Access Value Description

0Eh SUBADR1 7:1 A1[7:1] R/W 1110 001* I2C-bus subaddress 1

0 A1[0] R only 0* reserved

0Fh SUBADR2 7:1 A2[7:1] R/W 1110 010* I2C-bus subaddress 2

0 A2[0] R only 0* reserved

10h SUBADR3 7:1 A3[7:1] R/W 1110 100* I2C-bus subaddress 3

0 A3[0] R only 0* reserved

Table 12. ALLCALLADR - LED All Call I2C-bus address register (address 11h )

bit description

Legend: * default value.

Address Register Bit Symbol Access Value Description

11h ALLCALLADR 7:1 AC[7:1] R/W 1110 000* ALLCALL I2C-bus

address register

0 AC[0] R only 0* reserved

Product data sheet Rev. 3 — 6 September 2012 13 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

7.4 Active LOW output enable input

The active LOW output enable (OE) pin, allows to e nable or disable all the LED output s at

the same time.

•When a LOW level is applied to OE pin, all the LED outputs are ena bled.

•When a HIGH level is applied to OE pin, all the LED outputs are high-impedance.

The OE pin can be used as a synchron izat i on si gnal to switch on/off several PCA9624

devices at the same time . T his requir es an external clock reference that provides blinking

period and the duty cycle.

The OE pin can also be used as an e xterna l dim ming con tr ol signal. T he fr equen cy o f th e

external clock must be high enough not to be seen by the human eye, and the duty cycle

value determines the brightness of the LEDs.

Remark: Do not use OE as an external blinking control signal when internal global

blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undefined

blinking pattern. Do not use OE as an externa l dimming control signal when internal global

dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an undefined

dimming pattern.

Remark: During power-down, slow decay of volt age supplies may keep LEDs illuminated.

Consider disabling LED outputs using HIGH level applied to OE pin.

7.5 Power-on reset

When power is applied to VDD, an internal power-on reset holds the PCA9624 in a reset

condition until VDD has reached VPOR. At this point, the re set condition is released and the

PCA9624 registers and I2C-bus state machine are initialized to their default states (all

zeroes) causing all the chann els to be deselected. Thereaf ter , V DD must be lowered below

0.2 V to reset the device.

7.6 Software reset

The Software Reset Call (SWRST Call) allows all the devices in the I2C-bus to be reset to

the power-up st ate value through a specific formatted I2C-bus comman d. To be performe d

correctly, it implies that the I2C-bus is functional and that there is no device hanging the

bus.

The SWRST Call function is defined as the following:

1. A START command is sent by the I2C-bus master.

2. The reserved SWRST I2C-bus address ‘0000 011’ with the R/W bit set to ‘0’ (write) is

sent by the I2C-bus master.

3. The PCA9624 device(s) acknowledge(s) after seeing the SWRST Call address

‘0000 0110’ (06h) o nly. If the R/W bit is set to ‘1’ (read), no acknowled ge is returned to

the I2C-bus master.

4. Once the SWRST Call address has been sent and acknowledged, the master sends

2 bytes w ith 2 sp ecif ic valu es (SWRST da ta byte 1 and byte 2):

a. Byte 1 = A5h: the PCA9624 acknowledges this value only. If byte 1 is not equal to

A5h, the PCA9624 does not acknowledge it.

Product data sheet Rev. 3 — 6 September 2012 14 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

b. Byte 2 = 5Ah: the PCA9624 acknowledges this value only. If byte 2 is not equal to

5Ah, then the PCA9624 does not acknowledge it.

If more than 2 bytes of data are sent, the PCA9624 does not acknowledge any more.

5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and

correctly acknowledged, the master sends a STOP command to end the

SWRST Call: the PCA9624 then resets to the default value (power-up value) and is

ready to be addressed again within the specified bus free time (tBUF).

The I2C-bus master must interpret a non- acknowledge from th e PCA9624 (at any time) a s

a ‘SWRST Call Abort’. The PCA9624 does not initiate a reset of its registers. This

happens only when the format of the SWRST Call sequence is not correct.

7.7 Individual brightness control with group dimming/blinking

A 97 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used

to control individually the brightness for each LED.

On top of this signal, one of the following si gnals can be super imposed (this sig nal can be

applied to the 4 LED outputs):

•A lower 190 Hz fixe d fr eq ue n cy sign a l with prog ra m ma b le du ty cyc le (8 bits,

256 steps) is used to provide a global br ightness control.

•A programmable frequency signal from 24 Hz to 1⁄10.73 Hz (8 bits, 256 steps) with

programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking

control.

Minimum pulse width for LEDn Brightness Control is 40 ns.

Minimum pulse width for Group Dimming is 20.48 s.

When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group D imming signal will have 2 pulses of

the LED Brightness Control signal (pulse width = N 40 ns, with ‘N’ defined in PWMx register).

This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 4 (8 pulses).

Fig 7. Brightness + Group Dimming signals

123456789101112 507508509510511512 1234567891011

Brightness Control signal (LEDn)

M × 256 × 2 × 40 ns

with M = (0 to 255)

(GRPPWM Register)

N × 40 ns

with N = (0 to 255)

(PWMx Register)

256 × 40 ns = 10.24 μs

(97.6 kHz)

1234567812345678

Group Dimming signal

resulting Brightness + Group Dimming signal

256 × 2 × 256 × 40 ns = 5.24 ms (190.7 Hz)

002aab417

Product data sheet Rev. 3 — 6 September 2012 15 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

8. Characteristics of the I2C-bus

The I2C-bus is for 2 -way, 2-line communication between differe nt ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bi t is transferred durin g each clock pulse . The data o n the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 8).

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HI GH is defined as the STAR T condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P) (see Figure 9).

8.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 10).

Fig 8. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 9. Definition of START and STOP conditions

mba608

SDA

SCL P

STOP condition

START condition

Product data sheet Rev. 3 — 6 September 2012 16 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

8.3 Acknowledge

The number of data bytes transferre d be twe en the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addresse d must gener ate an acknowledg e af ter the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocke d ou t of th e sla ve tr an smitter. The device that acknowledges has to

pull down the SDA line during the acknowledge cl ock pulse , so that the SDA line is st able

LOW during the HIGH period of the acknowledge related clock pulse; set-up time a nd hold

time must be taken into account.

A master receiver must signal an end of data to the transmitter by not gener ating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter mus t leave the data line HIGH to enable the master to generate a ST OP

condition.

Fig 10. System configuration

002aaa966

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

I2C-BUS

MULTIPLEXER

SLAVE

Fig 11. Acknowledgement on the I2C-bus

002aaa987

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

Product data sheet Rev. 3 — 6 September 2012 17 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

9. Bus transactions

(1) See Table 4 for register definition.

Fig 12. Write to a specific register

A5 A4 A3 A2 A1 A0 0 AS A6

slave address

START condition R/W

acknowledge

from slave

002aac148

data for register D[4:0](1)

X X D4 D3 D2 D1 D0X

control register

Auto-Increment flag

Auto-Increment options

acknowledge

from slave

acknowledge

from slave

STOP

condition

Fig 13. Write to all registers using the Auto-Increment feature

A5 A4 A3 A2 A1 A0 0 AS A6

slave address

START condition R/W

acknowledge

from slave

002aac149

MODE1 register

0 0 0 0 0 0 01

control register

Auto-Increment on

Auto-Increment

on all registers

acknowledge

from slave

acknowledge

from slave

STOP

condition

(cont.)

MODE1

selection

MODE2 register

acknowledge

from slave

SUBADR3 register

acknowledge

from slave

ALLCALLADR register

acknowledge

from slave

Fig 14. Multiple writes to Individual Brightness registers only using the Auto-Increment feature

A5 A4 A3 A2 A1 A0 0 AS A6

slave address

START condition R/W

acknowledge

from slave

002aad597

PWM0 register

0 1 0 0 0 1 01

control register

Auto-Increment on

increment

on Individual

brightness

registers only

acknowledge

from slave

acknowledge

from slave

STOP

condition

(cont.)

PWM0

selection

PWM1 register

acknowledge

from slave

PWM6 register

acknowledge

from slave

PWM7 register

acknowledge

from slave

PWM0 register

acknowledge

from slave

PWMx register

acknowledge

from slave

Product data sheet Rev. 3 — 6 September 2012 18 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

Fig 15. Read all registers using the Auto-Increme nt feature

A5 A4 A3 A2 A1 A0 0 AS A6

slave address

START condition R/W

acknowledge

from slave

002aac151

0 0 0 0 0 0 01

control register

Auto-Increment on

Auto-Increment

on all registers

acknowledge

from slave

(cont.)

MODE1

selection

data from MODE1 register

acknowledge

from master

ReSTART

condition

A5 A4 A3 A2 A1 A0 1 AA6

slave address

R/W

acknowledge

from slave

data from MODE2 register

acknowledge

from master

data from PWM0

acknowledge

from master

data from

ALLCALLADR register

acknowledge

from master

data from

MODE1 register

acknowledge

from master

(cont.)

data from last read byte

not acknowledge

from master

STOP

condition

(1) In this example, several PCA9624s are used and the same sequence (A) (above) is sent to each of them.

(2) ALLCALL bit in MODE1 register is equal to 1 for this example.

(3) OCH bit in MODE2 register is equal to 1 for this example.

Fig 16. LED All Call I2C-bus address programming and LED All Call sequence example

A5 A4 A3 A2 A1 A0 0 AS A6

slave address(1)

START condition R/W

acknowledge

from slave

002aad598

X X 1 1 0 1 1X

control register

Auto-Increment on

acknowledge

from slave

ALLCALLADR

0 1 0 1 0 1 X1

new LED All Call I2C address(2)

STOP

condition

acknowledge

from slave

0 1 0 1 0 1 0 AS 1

LED All Call I2C address

START condition R/W

acknowledge

from the

4 devices

X X 0 1 0 0 0X

control register

acknowledge

from the

4 devices

LEDOUT

1 0 1 0 1 0 10

LEDOUT register (LED fully ON)

STOP

condition

acknowledge

from the

4 devices

the 8 LEDs are on at the acknowledge(3)

sequence (A)

sequence (B)

Product data sheet Rev. 3 — 6 September 2012 19 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

10. Application design-in information

(1) OE requires pull-up resistor if control signal from the master is open-drain.

I2C-bus address = 0010 101x.

Remark: During power-down, slow decay of voltage supplies may keep LEDs illuminated. Consider disabling LED outputs

using HIGH level applied to OE pin.

Fig 17. Typical application

PCA9624

LED0

LED1

SDA

SCL

VDD = 2.5 V, 3.3 V or 5.0 V

I2C-BUS/SMBus

MASTERSDA

SCL

10 kΩ

LED2

LED3

VDD

VSS

10 kΩ(1)

up to 40 V

LED4

LED5

LED6

LED7

002aad599

VSS

up to 40 V

Product data sheet Rev. 3 — 6 September 2012 20 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

10.1 Junction temperature calculation

A device junction temperature can be calculated when the ambient temperature or the

case temperature is known.

When the ambient temperature is known, the junction temperature is calculated using

Equation 4 and the ambient tem p er at ur e , junc tio n to amb i en t ther ma l res i stance and

power dissipation.

(4)

where:

Tj = junction temperature

Tamb = ambient temperature

Rth(j-a) = junction to ambient thermal resistance

Ptot = (device) total power dissipation

When the case temperature is known, the junction temperature is calculated using

Equation 5 and the case temperature, junction to case thermal resistance and power

dissipation.

(5)

where:

Tj = junction temperature

Tcase = case temperature

Rth(j-c) = junction to case thermal resistance

Ptot = (device) total power dissipation

Here are two examples regarding how to calculate the junction temperatu re using junction

to case and junction to ambient thermal resistance. In the first example (Section 10.1.1),

given the operating condition and the junction to ambient thermal resistance, the junction

temperature of PCA9624PW, in the TSSOP24 package, is calculated for a system

operating cond itio n in 50 C1 ambient temperature. In the second example

(Section 10.1.2), based on a specific customer application requir ement where only the

case temperature is known, applying the junction to case thermal resistance equation, th e

junction temperature of the PCA9624PW, in the TSSOP24 package, is calculated.

1. 50 C is a typical temperature inside an enclosed system. The designers should feel free, as needed, to perform their own

calculation using the examples.

TjTamb Rth j-aPtot

+=

TjTcase Rth j-cPtot

+=

Product data sheet Rev. 3 — 6 September 2012 21 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

10.1.1 Example 1: Tj calculation of PCA9624DR, in TSSOP24 package, when Tamb

is known

Rth(j-a) = 108 C/W

Tamb = 50 C

LED output low voltage (LED VOL) = 0.5 V

LED output current per channel = 80 mA

Number of outputs = 8

IDD(max) = 10 mA

VDD(max) = 5.5 V

I2C-bus clock (SCL) maximum sink current = 25 mA

I2C-bus data (SDA) maximum sink current = 25 mA

1. Find Ptot (device total power dissipation):

–output total power = 80 m A 80.5 V = 320 mW

–chip core power consumption = 10 mA 5.5 V = 55 mW

–SCL power dissipation = 25 mA 0.4 V = 10 mW

–SDA power dissipation = 25 mA 0.4 V = 10 mW

Ptot = (320 + 5 5 + 10 + 10) mW = 395 mW

2. Find Tj (junction temperature):

Tj = (Tamb +R

th(j-a) Ptot) = (50 C + 108 C/W 39 5 mW) = 92.7 C

10.1.2 Example 2: Tj calculation where only Tcase is known

This example uses a customer’s specific application of the PCA9624PW, 8-channel LED

controller in the TSSOP24 package, where only the case temperature (Tcase) is known.

Tj = Tcase + Rth(j-c) Ptot, where:

Rth(j-c) = 30 C/W

Tcase (measured) = 94.6 C

VOL of LED ~ 0.5 V

IDD(max) = 10 mA

VDD(max) = 5.5 V

LED output voltage LOW = 0.5 V

LED output current:

60 mA on 1 port = (60 mA 1)

50 mA on 6 ports = (50 mA 6)

40 mA on 1 port = (40 mA 1)

I2C-bus maximum sink current on clock line = 25 mA

I2C-bus maximum sink current on da ta line = 25 mA

Product data sheet Rev. 3 — 6 September 2012 22 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

1. Find Ptot (device total power dissipation)

–output current (60 mA 1 port); output power (60 mA 10.5 V) = 30 mW

–output current (50 mA 6 ports); output power (50 mA 60.5 V) = 150 mW

–output current (40 mA 1 port); output power (40 mA 10.5 V) = 20 mW

Output total power = 200 mW

–chip core power consumption = 10 mA 5.5 V = 55 mW

–SCL power dissipation = 25 mA 0.4 V = 10 mW

–SDA power dissipation = 25 mA 0.4 V = 10 mW

Ptot (device total power dissipation) = 275 mW

2. Find Tj (junction temperature):

Tj = Tcase + Rth(j-a)  Ptot = 94.6 C + 30 C/W  275 mW = 102.85 C

11. Limiting values

[1] Each bit must be limited to a maximum of 100 mA and the total package limited to 800 mA due to internal

busing limits. The pull-up (current limiting) resistor must be of sufficient size (W) and value () to guarantee

that the 100 mA limit is not exceeded on any output.

[2] Refer to Section 10.1 for calculation.

Table 13. Limiting va lues

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +6.0 V

VI/O voltage on an input/output pin VSS 0.5 5.5 V

Vdrv(LED) LED driver voltage VSS 0.5 40 V

IO(LEDn) output current on pin LEDn - 100 mA

IOL(tot) total LOW-level output current LED driver outputs;

VOL =0.5V [1] 800 - mA

ISS ground supply current per VSS pin - 800 mA

Ptot total power dissipation Tamb =25C-1.8W

Tamb =85C - 0.72 W

P/ch power dissipation per channel Tamb =25C-100mW

Tamb =85C-45mW

Tjjunction temperature [2] - +125 C

Tstg storage temperature 65 +150 C

Tamb ambient temperature operating 40 +85 C

Product data sheet Rev. 3 — 6 September 2012 23 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

[1] This value signifies package’s ability to handle more than 100 mA per output driver . The device’s maximum

current rating per output is 100 mA.

12. Thermal characteristics

[1] Calculated in accordance with JESD 51-7.

Table 14. TSSOP24 ver sus HVQFN24 power dissipation and output curren t capability

Measurement TSSOP24 HVQFN24

Tamb = 25 C

maximum power

dissipation

(chip + output drivers)

926 mW 2220 mW

maximum power

dissipation

(output drivers only)

851 mW 2150 mW

maximum drive current

per channel [1] [1]

Tamb = 60 C

maximum power

dissipation

(chip + output drivers)

602 mW 1440 mW

maximum power

dissipation

(output drivers only)

527 mW 1365 mW

maximum drive current

per channel [1] [1]

Tamb = 80 C

maximum power

dissipation

(chip + output drivers)

417 mW 1000 mW

maximum power

dissipation

(output drivers only)

342 mW 925 mW

maximum drive current

per channel [1]

851 mW

8-bit 0.5 V

--------------------------------

212.75 mA=

2150 mW

8-bit 0.5 V

--------------------------------

537.5 mA=

527 mW

8-bit 0.5 V

--------------------------------

131.8 mA=

1365 mW

8-bit 0.5 V

--------------------------------

341.25 mA=

342 mW

8-bit 0.5 V

--------------------------------

85.5 mA=

925 mW

8-bit 0.5 V

--------------------------------

231.3 mA=

Table 15. Th ermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from junction to ambient TSSOP24 [1] 108 C/W

HVQFN24 [1] 45 C/W

Rth(j-c) thermal resistance from junction to case TSSOP24 [1] 30 C/W

HVQFN24 [1] 19.6 C/W

Product data sheet Rev. 3 — 6 September 2012 24 of 37

NXP Semiconductors PCA9624

8-bit Fm+ I2C-bus 100 mA 40 V LED driver

13. Static characteristics

[1] VDD must be lowered to 0.2 V in order to reset part.

[2] Each bit must be limited to a maximum of 100 mA and the total package limited to 800 mA due to internal busing limits.

Table 16. Static characteristics

VDD =