PCA9624 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 6 September 2012 13 of 37
NXP Semiconductors PCA9624
8-bit Fm+ I2C-bus 100 mA 40 V LED driver
7.4 Active LOW output enable input
The active LOW output enable (OE) pin, allows to e nable or disable all the LED output s at
the same time.
•When a LOW level is applied to OE pin, all the LED outputs are ena bled.
•When a HIGH level is applied to OE pin, all the LED outputs are high-impedance.
The OE pin can be used as a synchron izat i on si gnal to switch on/off several PCA9624
devices at the same time . T his requir es an external clock reference that provides blinking
period and the duty cycle.
The OE pin can also be used as an e xterna l dim ming con tr ol signal. T he fr equen cy o f th e
external clock must be high enough not to be seen by the human eye, and the duty cycle
value determines the brightness of the LEDs.
Remark: Do not use OE as an external blinking control signal when internal global
blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undefined
blinking pattern. Do not use OE as an externa l dimming control signal when internal global
dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an undefined
dimming pattern.
Remark: During power-down, slow decay of volt age supplies may keep LEDs illuminated.
Consider disabling LED outputs using HIGH level applied to OE pin.
7.5 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9624 in a reset
condition until VDD has reached VPOR. At this point, the re set condition is released and the
PCA9624 registers and I2C-bus state machine are initialized to their default states (all
zeroes) causing all the chann els to be deselected. Thereaf ter , V DD must be lowered below
0.2 V to reset the device.
7.6 Software reset
The Software Reset Call (SWRST Call) allows all the devices in the I2C-bus to be reset to
the power-up st ate value through a specific formatted I2C-bus comman d. To be performe d
correctly, it implies that the I2C-bus is functional and that there is no device hanging the
bus.
The SWRST Call function is defined as the following:
1. A START command is sent by the I2C-bus master.
2. The reserved SWRST I2C-bus address ‘0000 011’ with the R/W bit set to ‘0’ (write) is
sent by the I2C-bus master.
3. The PCA9624 device(s) acknowledge(s) after seeing the SWRST Call address
‘0000 0110’ (06h) o nly. If the R/W bit is set to ‘1’ (read), no acknowled ge is returned to
the I2C-bus master.
4. Once the SWRST Call address has been sent and acknowledged, the master sends
2 bytes w ith 2 sp ecif ic valu es (SWRST da ta byte 1 and byte 2):
a. Byte 1 = A5h: the PCA9624 acknowledges this value only. If byte 1 is not equal to
A5h, the PCA9624 does not acknowledge it.