HEF4040B 12-stage binary ripple counter Rev. 06 -- 25 November 2009 Product data sheet 1. General description The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. The clock input is highly tolerant of slow rise and fall times due to its Schmitt trigger action. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (-40 C to +85 C) temperature range. 2. Features Tolerant of slow clock rise and fall time Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the full industrial temperature range -40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Applications Frequency dividing circuits Time delay circuits Control counters 4. Ordering information Table 1. Ordering information All types operate from -40 C to +85 C. Type number Package Name Description Version HEF4040BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4040BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4040B NXP Semiconductors 12-stage binary ripple counter 5. Functional diagram CP MR 10 T 12-STAGE COUNTER 11 CD 9 7 6 5 3 2 4 13 12 14 15 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 001aad589 Fig 1. Functional diagram FF 2 Q FF 1 Q CP FF 12 Q T Q CD T T Q Q CD CD MR Q1 Q0 Q11 001aae615 Fig 2. Logic diagram 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 CP input MR input Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 001aad587 Fig 3. Timing diagram HEF4040B_6 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 06 -- 25 November 2009 2 of 13 HEF4040B NXP Semiconductors 12-stage binary ripple counter 6. Pinning information 6.1 Pinning HEF4040B Q11 1 16 VDD Q5 2 15 Q10 Q4 3 14 Q9 Q6 4 13 Q7 Q3 5 12 Q8 Q2 6 11 MR Q1 7 10 CP VSS 8 9 Q0 001aae614 Fig 4. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description VSS 8 ground supply voltage Q0 to Q11 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 parallel output CP 10 clock input (HIGH-to-LOW edge-triggered) MR 11 master reset input (active HIGH) VDD 16 supply voltage HEF4040B_6 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 06 -- 25 November 2009 3 of 13 HEF4040B NXP Semiconductors 12-stage binary ripple counter 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O IDD VI < -0.5 V or VI > VDD + 0.5 V Min Max -0.5 +18 V - 10 mA -0.5 VDD + 0.5 V - 10 mA input/output current - 10 mA supply current - 50 mA Tstg storage temperature -65 +150 C Tamb ambient temperature total power dissipation Ptot P power dissipation VO < -0.5 V or VO > VDD + 0.5 V Unit -40 +85 C DIP16 package [1] - 750 mW SO16 package [2] - 500 mW - 100 mW per output [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. 8. Recommended operating conditions Table 4. Recommended operating conditions Symbol Parameter Min Typ Max Unit VDD supply voltage Conditions 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air -40 - +85 C t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V 9. Static characteristics Table 5. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH VIL HIGH-level input voltage LOW-level input voltage Conditions |IO| < 1 A |IO| < 1 A VDD Tamb = -40 C Tamb = 85 C Unit Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V HEF4040B_6 Product data sheet Tamb = 25 C (c) NXP B.V. 2009. All rights reserved. Rev. 06 -- 25 November 2009 4 of 13 HEF4040B NXP Semiconductors 12-stage binary ripple counter Table 5. Static characteristics ...continued VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter Conditions Tamb = -40 C VDD Min VOH VOL IOH IOL HIGH-level output voltage |IO| < 1 A LOW-level output voltage HIGH-level output current LOW-level output current input leakage current IDD supply current CI Tamb = 85 C Min Min Max Unit Max 5V 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 V -1.7 - -1.4 - -1.1 - mA |IO| < 1 A VO = 2.5 V 5V VO = 4.6 V 5V -0.52 - -0.44 - -0.36 - mA VO = 9.5 V 10 V -1.3 - -1.1 - -0.9 - mA VO = 13.5 V 15 V -3.6 - -3.0 - -2.4 - mA VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V ILI Max Tamb = 25 C 15 V 3.6 - 3.0 - 2.4 - mA 15 V - 0.3 - 0.3 - 1.0 A 5V - 20 - 20 - 150 A 10 V - 40 - 40 - 300 A 15 V - 80 - 80 - 600 A - - - - 7.5 - - pF IO = 0 A input capacitance 10. Dynamic characteristics Table 6. Dynamic characteristics VSS = 0 V; Tamb = 25 C; unless otherwise specified; for test circuit see Figure 6. Symbol Parameter Conditions tPHL HIGH to LOW propagation delay CP Q0 see Figure 5 Qn Qn + 1 MR Qn see Figure 5 tPLH LOW to HIGH propagation delay CP Q0 see Figure 5 Extrapolation formula[1] Min Typ Max Unit 5V 78 ns + (0.55 ns/pF)CL - 105 210 ns 10 V 34 ns + (0.23 ns/pF)CL - 45 90 ns 15 V 27 ns + (0.16 ns/pF)CL - 35 70 ns VDD 5V [2] (0.55 ns/pF)CL - 35 70 ns 10 V [2] (0.23 ns/pF)CL - 15 30 ns 15 V [2] (0.16 ns/pF)CL - 10 20 ns 5V 63 ns + (0.55 ns/pF)CL - 90 180 ns 10 V 29 ns + (0.23 ns/pF)CL - 40 80 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns 5V 58 ns + (0.55 ns/pF)CL - 85 170 ns 10 V 29 ns + (0.23 ns/pF)CL - 40 80 ns 22 ns + (0.16 ns/pF)CL - 30 60 ns 5V [2] (0.55 ns/pF)CL - 35 70 ns 10 V [2] (0.23 ns/pF)CL - 15 30 ns 15 V [2] (0.16 ns/pF)CL - 10 20 ns 15 V Qn Qn + 1 HEF4040B_6 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 06 -- 25 November 2009 5 of 13 HEF4040B NXP Semiconductors 12-stage binary ripple counter Table 6. Dynamic characteristics ...continued VSS = 0 V; Tamb = 25 C; unless otherwise specified; for test circuit see Figure 6. Symbol tt Parameter transition time pulse width tW Conditions see Figure 5 recovery time CP input HIGH; minimum width; see Figure 5 maximum frequency fmax MR input; see Figure 5 CP input; see Figure 5 Min 10 ns + (1.00 ns/pF)CL 10 V 15 V Typ Max Unit - 60 120 ns 9 ns + (0.42 ns/pF)CL - 30 60 ns 6 ns + (0.28 ns/pF)CL - 20 40 ns 5V 50 25 - ns 10 V 30 15 - ns 15 V 20 10 - ns 5V 40 20 - ns 10 V 30 15 - ns 15 V 20 10 - ns 5V MR input HIGH; minimum width; see Figure 5 trec Extrapolation formula[1] VDD [3] 5V 40 20 - ns 10 V 30 15 - ns 15 V 20 10 - ns 5V 10 20 - MHz 10 V 15 30 - MHz 15 V 25 50 - MHz [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF) [2] For loads other than 50 pF at the nth output, use the slope given. [3] tt is the same as tTHL and tTLH. Table 7. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol PD Parameter dynamic power dissipation VDD Typical formula for PD (W) where: 5V PD = 400 x fi + (fo x CL) x VDD 10 V PD = 2000 x fi + (fo x CL) x VDD 15 V PD = 5200 x fi + (fo x CL) x VDD2 2 fi = input frequency in MHz, 2 fo = output frequency in MHz, CL = output load capacitance in pF, VDD = supply voltage in V, (fo x CL) = sum of the outputs. HEF4040B_6 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 06 -- 25 November 2009 6 of 13 HEF4040B NXP Semiconductors 12-stage binary ripple counter 11. Waveforms VI VM MR input VSS 1/fmax tW trec VI VM CP input VSS tPHL tPLH VOH Q0 or Qn output VOL tW tPHL VM tTLH tPLH tPHL tTHL VOH Qn + 1 output VM VOL 001aaj763 Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Transition times: transition time (tt) = HIGH LOW (tTHL) or LOW HIGH (tTLH) transition times. Measurement points are given in Table 8, test circuit in Figure 6 and test data in Table 9 Fig 5. Waveforms showing propagation delays for MR to Qn and CP to Q0, minimum MR and CP pulse widths Table 8. Measurement points Supply voltage Input Output VDD VI VM VM 5 V to 15 V VDD or VSS 0.5VDD 0.5VDD HEF4040B_6 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 06 -- 25 November 2009 7 of 13 HEF4040B NXP Semiconductors 12-stage binary ripple counter tW VI 90 % negative pulse VM VM 10 % 0V VI tf tr tr tf 90 % positive pulse VM VM 10 % 0V tW 001aaj781 a. Input waveforms VDD VI VO G DUT CL RT 001aag182 b. Test circuit Test data is given in Table 9. Definitions test circuit: DUT = Device Under Test; CL = load capacitance, including the jig and probe capacitance; RL = load resistance, which should be equal to the output impedance of the pulse generator. Fig 6. Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load VDD VI tr, tf CL 5 V to 15 V VSS or VDD 20 ns 50 pF HEF4040B_6 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 06 -- 25 November 2009 8 of 13 HEF4040B NXP Semiconductors 12-stage binary ripple counter 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 7. EUROPEAN PROJECTION Package outline SOT38-4 (DIP16) HEF4040B_6 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 06 -- 25 November 2009 9 of 13 HEF4040B NXP Semiconductors 12-stage binary ripple counter SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) HEF4040B_6 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 06 -- 25 November 2009 10 of 13 HEF4040B NXP Semiconductors 12-stage binary ripple counter 13. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4040B_6 20091125 Product data sheet - HEF4040B_5 Modifications: * Section 2 "Features", t/V values updated. HEF4040B_5 20090709 Product data sheet - HEF4040B_4 HEF4040B_4 20090304 Product data sheet - HEF4040B_CNV_3 HEF4040B_CNV_3 19950101 Product specification - HEF4040B_CNV_2 HEF4040B_CNV_2 19950101 Product specification - - HEF4040B_6 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 06 -- 25 November 2009 11 of 13 HEF4040B NXP Semiconductors 12-stage binary ripple counter 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. Definition [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 14.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4040B_6 Product data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 06 -- 25 November 2009 12 of 13 HEF4040B NXP Semiconductors 12-stage binary ripple counter 16. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 November 2009 Document identifier: HEF4040B_6