MC74HC573ADW - Motorola / Freescale Semiconductor



SEMICONDUCTOR TECHNICAL DATA

1REV 6

 Motorola, Inc. 1995

10/95

  

 

High–Performance Silicon–Gate CMOS

The MC54/74HC573A is identical in pinout to the LS573. The devices are

compatible with standard CMOS outputs; with pullup resistors, they are

compatible with LSTTL outputs.

These latches appear transparent to data (i.e., the outputs change

asynchronously) when Latch Enable is high. When Latch Enable goes low,

data meeting the setup and hold time becomes latched.

The HC573A is identical in function to the HCT373A but has the data

inputs on the opposite side of the package from the outputs to facilitate PC

board layout.

The HC573A is the noninverting version of the HC563.

•Output Drive Capability: 15 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 µA

•In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

•Chip Complexity: 218 FETs or 54.5 Equivalent Gates

LOGIC DIAGRAM

DATA

INPUTS

LATCH ENABLE

OUTPUT ENABLE

2 19

PIN 20 = VCC

PIN 10 = GND

NONINVERTING

OUTPUTS

ÎÎÎÎÎÎÎÎÎÎ

Design Criteria

ÎÎÎÎ

Value

ÎÎÎ

Units

ÎÎÎÎÎÎÎÎÎÎ

Internal Gate Count*

ÎÎÎÎ

54.5

ÎÎÎ

ea.

ÎÎÎÎÎÎÎÎÎÎ

Internal Gate Propagation Delay

ÎÎÎÎ

1.5

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Internal Gate Power Dissipation

ÎÎÎÎ

5.0

ÎÎÎ

µW

ÎÎÎÎÎÎÎÎÎÎ

Speed Power Product

ÎÎÎÎ

0.0075

ÎÎÎ

*Equivalent to a two–input NAND gate.



PIN ASSIGNMENT

OUTPUT

ENABLE

GND

D3 5

VCC

LATCH

ENABLE

FUNCTION TABLE

Inputs Output

Output Latch

Enable Enable D Q

L H H H

L H L L

L L X No Change

H X X Z

X = Don’t Care

Z = High Impedance

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ORDERING INFORMATION

MC54HCXXXAJ

MC74HCXXXAN

MC74HCXXXADW

Ceramic

Plastic

SOIC

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

MC54/74HC573A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 1.5 to VCC + 1.5

ÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎÎ

± 20

ÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

± 35

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

± 75

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

ÎÎÎÎÎÎ

750

500

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

(Ceramic DIP)

ÎÎÎÎÎÎ

260

300

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: –10 mW/

C from 65

to 125

Ceramic DIP: –10 mW/

C from 100

to 125

SOIC Package: –7 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

1000

500

400

ÎÎÎ

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

1.5

3.15

4.2

ÎÎÎÎ

1.5

3.15

4.2

ÎÎÎÎ

1.5

3.15

4.2

ÎÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

0.5

1.35

1.8

ÎÎÎÎ

0.5

1.35

1 8

ÎÎÎÎ

0.5

1.35

1.8

ÎÎÎ

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

6.0 mA

|Iout|

7.8 mA

ÎÎÎÎ

4.5

6.0

ÎÎÎ

3.98

5.48

ÎÎÎÎ

3.84

5.34

ÎÎÎÎ

3.7

5.2

ÎÎÎ

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

6.0 mA

|Iout|

7.8 mA

ÎÎÎÎ

4.5

6.0

ÎÎÎ

0.26

ÎÎÎÎ

0.33

ÎÎÎÎ

0.4

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎÎ

6.0

ÎÎÎ

± 0.1

ÎÎÎÎ

± 1.0

ÎÎÎÎ

± 1.0

ÎÎÎ

µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND

(Vin or V out)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC54/74HC573A

High–Speed CMOS Logic Data

DL129 — Rev 6 3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

IOZ

ÎÎÎÎÎÎÎÎÎ

Maximum Three–State Leakage

Current

ÎÎÎÎÎÎÎÎÎ

Output in High–Impedance State

Vin = VIL or VIH

Vout = VCC or GND

ÎÎÎÎ

6.0

ÎÎÎ

– 0.5

ÎÎÎÎ

– 5.0

ÎÎÎÎ

– 10

ÎÎÎ

µA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply

Current (per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

IIoutI = 0 µA

ÎÎÎÎ

6.0

ÎÎÎ

4.0

ÎÎÎÎ

160

ÎÎÎ

µA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Input D to Q

(Figures 1 and 5)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

150

ÎÎÎÎ

190

ÎÎÎÎ

225

ÎÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Latch Enable to Q

(Figures 2 and 5)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

160

ÎÎÎÎ

200

ÎÎÎÎ

240

ÎÎÎ

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

150

ÎÎÎÎ

190

ÎÎÎÎ

225

ÎÎÎ

ÎÎÎÎ

tPZL,

tPZH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

150

ÎÎÎÎ

190

ÎÎÎÎ

225

ÎÎÎ

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 1 and 5)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

Cout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Three–State Output Capacitance (Output in High–Impedance State)

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Enabled Output)*

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Enabled Output)*

*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Fig.

ÎÎÎ

VCC

Volts

ÎÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Fig.

ÎÎÎ

VCC

Volts

ÎÎÎÎÎ

– 55 to 25

ÎÎÎÎÎ

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Fig.

ÎÎÎ

VCC

Volts

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Input D to Latch Enable

ÎÎÎ

2.0

4.5

6.0

ÎÎÎ

9.0

ÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Latch Enable to Input D

ÎÎÎ

2.0

4.5

6.0

ÎÎÎ

5.0

ÎÎÎ

5.0

ÎÎÎ

5.0

ÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Latch Enable

ÎÎÎ

2.0

4.5

6.0

ÎÎÎ

110

ÎÎ

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall Times

ÎÎÎ

2.0

4.5

6.0

ÎÎÎ

1000

500

400

ÎÎÎ

1000

500

400

ÎÎÎ

ÎÎ

1000

500

400

ÎÎÎ

MC54/74HC573A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

SWITCHING WAVEFORMS

VCC

GND

INPUT D

10%

50%

90%

10%

50%

90%

tTLH

tPLH tPHL

tTHL

OUTPUT

ENABLE

50%

1.3 V 90%

10%

tPZL tPLZ

tPZH tPHZ

3.0 V

GND

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

1 k

Ω

Figure 1. Figure 2.

Figure 3. Figure 4.

VCC

GND

50%

LATCH

ENABLE

tPLH tPHL

Figure 5. Test Circuit

Figure 6. Test Circuit

EXPANDED LOGIC DIAGRAM

LE Q

D0 219 Q0

LE Q

D1 318 Q1

LE Q

D2 417 Q2

LE Q

D3 516 Q3

LE Q

D4 615 Q4

LE Q

D5 714 Q5

LE Q

D6 813 Q6

LE Q

D7 912 Q7

LATCH ENABLE

OUTPUT ENABLE

VCC

GND

VCC

GND

50%

VALID

tSU th

INPUT D

LATCH

ENABLE

MC54/74HC573A

High–Speed CMOS Logic Data

DL129 — Rev 6 5 MOTOROLA

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

ISSUE E

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ISSUE E

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D–04

ISSUE E

NOTES:

1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE

POSITION AT SEATING PLANE, AT MAXIMUM

MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

3. DIMENSIONS A AND B INCLUDE MENISCUS.

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A23.88 25.15 0.940 0.990

B6.60 7.49 0.260 0.295

C3.81 5.08 0.150 0.200

D0.38 0.56 0.015 0.022

F1.40 1.65 0.055 0.065

G2.54 BSC 0.100 BSC

H0.51 1.27 0.020 0.050

J0.20 0.30 0.008 0.012

K3.18 4.06 0.125 0.160

L7.62 BSC 0.300 BSC

M0 15 0 15

N0.25 1.02 0.010 0.040

_ _ _ _

1 10

SEATING

PLANE

HGK

NJM

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

J20 PL

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A25.66 27.171.010 1.070

B6.10 6.600.240 0.260

C3.81 4.570.150 0.180

D0.39 0.550.015 0.022

G2.54 BSC0.100 BSC

J0.21 0.380.008 0.015

K2.80 3.550.110 0.140

L7.62 BSC0.300 BSC

M0 15 0 15

N0.51 1.010.020 0.040

_ __ _

E1.27 1.770.050 0.070

–A–

SEATING

PLANE

D20 PL

–T–

0.25 (0.010) T

F1.27 BSC0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.150

(0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.13

(0.005) TOTAL IN EXCESS OF D DIMENSION

AT MAXIMUM MATERIAL CONDITION.

–A–

–B–

0.010 (0.25) B S

D20X

0.010 (0.25)

P10X

18X K

–T–

SEATING

PLANE

RX 45

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A12.65 12.95 0.499 0.510

B7.40 7.60 0.292 0.299

C2.35 2.65 0.093 0.104

D0.35 0.49 0.014 0.019

F0.50 0.90 0.020 0.035

G1.27 BSC 0.050 BSC

J0.25 0.32 0.010 0.012

K0.10 0.25 0.004 0.009

M0 7 0 7

P10.05 10.55 0.395 0.415

R0.25 0.75 0.010 0.029

_ _ _ _

MC54/74HC573A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

How to reach us:

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MC54/74HC573A/D

*MC54/74HC573A/D*

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