W24512A
64K × 8 HIGH SPEED CMOS STATIC RAM
Publication Release Date: March 1999
- 1 - Revision A7
GENERAL DESCRIPTION
The W24512A is a high speed, low power CMOS static RAM organized as 65536 × 8 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
•High speed access time: 15/20/25/35 nS (max.)
•Low power consumption:
−Active: 500 mW (typ.)
•Single +5V power supply
•Fully static operation
•All inputs and outputs directly TTL compatible
•Three-state outputs
•Available packages: 32-pin 300 mil SOJ,
skinny DIP, 450 mil SOP, and standard type
one TSOP
PIN CONFIGURATIONS
V
A8
A9
WE
1
2
3
4
5
24
25
26
27
28
NC
A7
A6
A5
A12
A4
A3
A2
A1
6
7
8
9
20
21
22
23
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
10
11
12
13
16 17
18
19
A0
I/O2
I/O3
I/O1
14
15
I/O4
A13
V
A14
NC
32
31
30
29
A15
CS2
DD
SS
1
2
3
4
5
6
7
8
9
V
DD
32-pin
TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
A13
A11
A9
A8
WE
CS2
A15
NC
NC
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
A0
A1
A2
A3
10
11
12
13
14
15
16
BLOCK DIAGRAM
A0
.
CS1
A15
WE
I/O1
I/O8
OE
CORE
V
V
.
.
DATA I/O
ARRAY
DECODER CORE
CS2
.
CONTROL
DD
SS
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0−A15 Address Inputs
I/O1−I/O8 Data Inputs/Outputs
CS1
, CS2 Chip Select Inputs
WE
Write Enable Input
OE
Output Enable Input
VDD Power Supply
VSS Ground
NC No Connection
W24512A
- 2 -
TRUTH TABLE
CS
1
CS2
OE
WE
MODE I/O1
−
I/O8 VDD CURRENT
HXXX Not Selected High Z ISB, ISB1
XLX X Not Selected High Z ISB, ISB1
LHHH Output Disable High Z IDD
LHLHRead Data Out IDD
LHXLWrite Data In IDD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Supply Voltage to VSS Potential -0.5 to +7.0 V
Input/Output to VSS Potential -0.5 to VDD +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150 °C
Operating Temperature 0 to +70 °C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Operating Characteristics
(VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C)
PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT
Input Low Voltage VIL --0.5 -+0.8 V
Input High Voltage VIH -+2.2 -VDD +0.5 V
Input Leakage Current ILI VIN = VSS to VDD -10 -+10 µA
Output Leakage
Current ILO VI/O = VSS to VDD
CS1
= VIH or CS2 = VIL or
OE
= VIH or
WE
= VIL
-10 -+10 µA
Output Low Voltage VOL IOL = +8.0 mA - - 0.4 V
Output High Voltage VOH IOH = -4.0 mA 2.4 - - V
Operating Power IDD
CS1
= VIL, CS2 = VIH 15 - - 200 mA
Supply Current I/O = 0 mA, Cycle = min. 20 160
Duty = 100% 25 160
35 - - 140
Standby Power
Supply Current ISB
CS1
= VIH or CS2 = VIL
Cycle = min., Duty = 100% - - 30 mA
ISB1
CS1
≥ VDD -0.2V or
CS2 ≤ 0.2V - - 10 mA
Note: Typical characteristics are at VDD = 5V, TA = 25° C.
W24512A
Publication Release Date: March 1999
- 3 - Revision A7
CAPACITANCE
(VDD = 5V, TA = 25° C, f = 1 MHz)
PARAMETER SYM. CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 8pF
Input/Output Capacitance CI/O VOUT = 0V 10 pF
Note: These parameters are sampled but not 100% tested.
THERMAL RESISTANCE
PARAMETER SYM. CONDITIONS MAX. UNIT
Junction to Case Thermal Resistance θJC A. F. R. = 1m/sec, TA = 25° C 20 °C/W
Junction to Ambient Thermal
Resistance θJA A. F. R. = 1m/sec, TA = 25° C 60 °C/W
Note: These parameters are only applied to "TSOP" and "SOJ" package types.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V
Output Load CL = 30 pF, IOH/IOL = -4 mA/8 mA
AC Test Loads and Waveform
90% 90%
5 nS
10%
5 nS 10%
R1 480 ohm
5V
OUTPUT R2
255 ohm
30 pF
Including
Jig and
Scope
3.0V
0V
5V
OUTPUT
R1 480 ohm
5 pF
Including
Jig and
Scope
R2
255 ohm
(For T
CLZ1, CLZ2, OLZ, CHZ1, CHZ2, OHZ, WHZ, OW
TTTT T T T )
W24512A
- 4 -
AC Characteristics, continued
(VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C)
Read Cycle
PARAMETER SYM. W24512A-15 W24512A-25 W24512A-25 W24512A-35 UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time TRC 15 -20 -25 -35 -nS
Address Access Time TAA -15 -20 -25 -35 nS
Chip Select Access Time CS1 TACS1 -15 -20 -25 -35 nS
CS2 TACS2 -15 -20 -25 -35 nS
Output Enable to Output Valid TAOE -7-10 -12 -17 nS
Chip Selection to Output in Low Z CS1 TCLZ1* 3-3-3-3-nS
CS2 TCLZ2* 3-3-3-3-nS
Output Enable to Output in Low Z TOLZ* 0-0-0-0-nS
Chip Deselection to Output in CS1 TCHZ1* -7-10 -12 -17 nS
High Z CS2 TCHZ2* -7-10 -12 -17 nS
Output Disable to Output in High Z TOHZ* -7-1-12 -17 nS
Output Hold from Address Change TOH 3-3-3-3-nS
* These parameters are sampled but not 100% tested.
Write Cycle
PARAMETER SYM. W24512A-15 W24512A-25 W24512A-25 W24512A-35 UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time TWC 15 -20 -25 -35 -nS
Chip Selection to End of Write CS1 TCW1 13 -17 -18 -20 -nS
CS2 TCW2 13 -17 -18 -20 -nS
Address Valid to End of Write TAW 13 -17 -18 -20 -nS
Address Setup Time TAS 0-0-0-0-nS
Write Pulse Width TWP 10 -12 -15 -18 -nS
Write Recovery Time CS1,WE TWR1 0-0-0-0-nS
CS2 TWR2 0-0-0-0-nS
Data Valid to End of Write TDW 9-10 -12 -15 -nS
Data Hold from End of Write TDH 0-0-0-0-nS
Write to Output in High Z TWHZ* -8-10 -12 -15 nS
Output Disable to Output in High Z TOHZ* -8-10 -12 -15 nS
Output Active from End of Write TOW 0-0-0-0-nS
* These parameters are sampled but not 100% tested.
W24512A
Publication Release Date: March 1999
- 5 - Revision A7
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
T
T
TT
D
OH AA
RC
OH
OUT
Read Cycle 2
(Chip Select Controlled)
CS1
CS2
D
T
T
T
TT
T
ACS1
ACS2
CLZ1
CLZ2
CHZ1
CHZ2
OUT
Read Cycle 3
(Output Enable Controlled)
Address
T
OE
CS1
CS2
D
T
T
TT
T
TT
T
T
T
T
OH
CHZ1
CHZ2 OHZ
AA
RC
AOE
CLZ1ACS1
ACS2
CLZ2
OLZ
OUT
W24512A
- 6 -
Timing Waveforms, continued
Write Cycle 1
(
OE
Clock)
Address
OE
CS1
CS2
WE
D
D
T
T(1, 4)
OUT
IN
OHZ
WC
TWR1
TCW1
TCW2
TAW TWP TWR2
TAS
TDW TDH
Write Cycle 2
(
OE
= VIL Fixed)
Address
CS1
CS2
WE
D
D
T
T
T
T
TT
T
T
T
T
T
(2) (3)
T
T
WC
CW1 WR1
CW2
AW
WP WR2
OW
WHZ (1, 4)
DW DH
OH
AS
OUT
IN
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
W24512A
Publication Release Date: March 1999
- 7 - Revision A7
ORDERING INFORMATION
PART NO. ACCESS
TIME (nS) OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (mA)
PACKAGE
W24512AK-15 15 200 10 300 mil skinny DIP
W24512AK-20 20 160 10 300 mil skinny DIP
W24512AK-25 25 160 10 300 mil skinny DIP
W24512AK-35 35 140 10 300 mil skinny DIP
W24512AJ-15 15 200 10 300 mil SOJ
W24512AJ-20 20 160 10 300 mil SOJ
W24512AJ-25 25 160 10 300 mil SOJ
W24512AJ-35 35 140 10 300 mil SOJ
W24512AS-15 15 200 10 450 mil SOP
W24512AS-20 20 160 10 450 mil SOP
W24512AS-25 25 160 10 450 mil SOP
W24512AS-35 35 140 10 450 mil SOP
W24512AT-15 15 200 10 standard type one TSOP
W24512AT-20 20 160 10 standard type one TSOP
W24512AT-25 25 160 10 standard type one TSOP
W24512AT-35 35 140 10 standard type one TSOP
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
W24512A
- 8 -
PACKAGE DIMENSIONS
32-pin SOJ
D
H
B
b
e
e
116
17
32
E
Y
A
A
A
Seating Plane
c
L
S
θ
Symbol Dimension in mmDimension in Inches
Min. Nom. Max. Min. Nom. Max.
A
A
A
B
b
c
D
E
e
e
H
L
S
Y
0.140
0.020
0.095 0.100 0.105
0.0320.0280.026
0.0220.0180.016
0.0140.010
0.008
0.8350.825
0.305
0.3000.295
0.0560.0500.044
0.2870.2670.247
0.3450.3350.325
0.080
0.045
0.004
0 10
0.815
3.556
0.508
2.413 2.540 2.667
0.8130.7110.660
0.559
0.4570.406
0.356
0.2540.203
21.20920.955
7.7477.6207.493
1.4221.2701.118
7.2906.7826.274
8.7638.509
8.255
2.032
1.143
0.102
0°10°
20.701
θ
__
__
__
__
__
__
__
__
__
__
__
__
__
__
__
__
__
__ __
__
__
__
1
2
1
e
e
1
2
1
32-pin SO Wide Body
1
17
32
16
ye
D
S
Seating Plane
b
A
A
EH
L
L
E
E
1
c
e1
1
e
A
2
See Detail F
Detail F
1. Dimension D Max. & S include mold flash
or tie bar burrs.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Dimension D & E include mold mismatch
and are determined at the mold parting line.
.
Notes:
4. Controlling dimension: Inches.
5. General appearance spec should be based
on final visual inspection spec.
0.200.15
0.0080.006
Symbol Min. Nom. Max. Max.
Nom.
Min.
Dimension in Inches Dimension in mm
A
b
c
D
e
HE
L
y
A
A
LE
1
2
E
0.012 0.31
0.118 3.00
0.004
0.101
0.014
0.106
0.016
0.111
0.020
2.57
0.36
0.10
2.69
0.41
2.82
0.51
0.047
0.004
010
0.805
0.055
0.817
0.063 1.19
20.45
1.40
20.75
1.60
0.556
0.5560.546 14.3814.1213.87
10
0
0.10
11.43
11.30
11.18
0.4500.4450.440
0.58 0.79 0.99
0.023 0.031 0.039
1.12 1.27 1.420.044 0.050 0.056
S0.91
0.036
θ
W24512A
Publication Release Date: March 1999
- 9 - Revision A7
Package Dimensions, continued
32-pin TSOP
A
A
A
2
1
L
L1Y
c
E
H
D
D
b
e
M
0.10(0.004)
θ
Min. Nom. Max. Min. Nom. Max.
Symbol
A
A
b
c
D
E
e
L
L
Y
1
1
2
A
HD
Note:
Controlling dimension: Millimeter
Dimension in Inches
0.047
0.006
0.041
0.039
0.037
0.007 0.008 0.009
0.005 0.006 0.007
0.720 0.724 0.728
0.311 0.315 0.319
0.780 0.787 0.795
0.020
0.016 0.020 0.024
0.031
0.000 0.004
13 5
0.002
1.20
0.05 0.15
1.051.00
0.95
0.17
0.12
18.30
7.90
19.80
0.40
0.00
1
0.20 0.23
0.15 0.17
18.40 18.50
8.00 8.10
20.00 20.20
0.50
0.50 0.60
0.80
0.10
3 5
Dimension in mm
θ
__ __ __ __
__ __
__ __
__ __
__
__
__
__
____
32-pin P-DIP Skinny (300 mil)
eA
A
a
c
E
Base Plane
Mounting Plane
1
A
1
e
L
A
S
1
E
D
1
B
B
1
2
16
17
32
1. Dimension D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
6. General appearance spec. should be based on
final visual inspection spec.
1.631.47
0.0640.058
Notes:
Symbol Min. Nom. Max. Max.Nom.Min.
Dimension in Inches Dimension in mm
0.060 1.52
0.200 5.08
0.015
0.145
0.016
0.150
0.018
0.155
0.022
3.68
0.41
0.38
3.81
0.46
3.94
0.56
0.008
0.120
0.470
0.010
0.130
0.014
0.140
0.20
3.05
0.25
3.30
0.36
3.56
11.94
2.29 2.54 2.790.090 0.100 0.110
A
B
c
D
e
A
L
S
A
A1
2
E
B1
1
e
E1
a0
0.065 1.65
0.450
0.430 10.92 11.43
15°
0°
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
1.60 1.62 40.64 41.15
0.286
0.295
0.290
0.315
0.294
0.335
7.26
7.49
7.36
8.00
7.46
8.50
15
W24512A
- 10 -
VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A7 Mar. 1999 -Arrange access time for 15/20/25/35 nS
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792647
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2730 Orchard Parkway, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
Note: All data and specifications are subject to change without notice.
