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FEATURES
DESCRIPTION
UC1543 , , UC1544UC2543 , UC2544UC3543 , UC3544
SLUS188A – APRIL 1997 – REVISED FEBRUARY 2007
Power Supply Supervisory Circuit
Both over- and under-voltage sensing circuits can beexternally programmed for minimum time duration of•Includes Over-Voltage, Under-Voltage, and
fault before triggering. All functions contain openCurrent Sensing Circuits
collector outputs which can be used independently or•Internal 1% Accurate Reference
wire-or’ed together, and although the SCR trigger isdirectly connected only to the over-voltage sensing•Programmable Time Delays
circuit, it may be optionally activated by any of the•SCR “Crowbar” Drive of 300 mA
other outputs, or from an external signal. The O.V.•Remote Activation Capability
circuit also includes an optional latch and externalreset capability.•Optional Over-Voltage Latch•Uncommitted Comparator Inputs for Low
The UC1544/2544/3544 devices have the addedVoltage Sensing (UC1544 Series Only)
versatility of completely uncommitted inputs to thevoltage sensing comparators so that levels less than2.5 V may be monitored by dividing down the internalreference voltage. The current sense circuit may beThe monolithic integrated circuits contain all the
used with external compensation as a linear amplifierfunctions necessary to monitor and control the output
or as a highgain comparator. Although nominally setof a sophisticated power supply system.
for zero input offset, a fixed threshold may be addedOver-voltage (O.V.) sensing with provision to trigger
with an external resistor. Instead of current limiting,an external SCR “crowbar” shutdown; an
this circuit may also be used as an additional voltageundervoltage (U.V.) circuit which can be used to
monitor.monitor either the output or to sample the input line
The reference generator circuit is internally trimmedvoltage; and a third op amp/comparator usable for
to eliminate the need for external potentiometers andcurrent sensing (C.L.) are all included in this device,
the entire circuit may be powered directly from eithertogether with an independent, accurate reference
the output being monitored or from a separate biasgenerator.
voltage.
BLOCK DIAGRAM
NOTE:
For each terminal, first number refers to 1543 series, second to 1544 series.*On 1543 series, this function is internally connected to VREF.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1997–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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Connection Diagrams
PACKAGE PIN FUNCTION PACKAGE PIN FUNCTION
FUNCTION FUNCTIONPIN PIN
N/C N/C
SCR Trigger SCR Trigger
Remote Activate Remote Activate
Reset Reset
O.V. Indicate O.V. Indicate
N/C N/C
O.V. Delay O.V. Delay
O.V. Input
N/C
N/C
U.V. Input
U.V. Delay U.V. Delay
U.V. Indicate U.V. Indicate
C.L. INV. Input C.L. INV. Input
C.L. N.I. Input C.L. N.I. Input
Offset/Comp Offset/Comp
C.L. Output C.L. Output
Ground Ground
VREF VREF
19 19
VIN VIN
20 20
O.V. N.I. Input
O.V. INV. Input
U.V. N.I. Input
U.V. INV. Input
DIL-18, SOIC-18(TOP VIEW)
J or N, DW Package
DIL-16, SOIC-16(TOP VIEW)
J or N, DW Package
(AlsoWPackagefortheUC1543Only)
UC1544
UC2544
UC3544
UC1543
UC2543
UC3543
1
2
3
4
5
6
7
8
9 10
11
12
13
14
15
16
17
18 VIN
VREF
Ground
C.L.Output
Offset/Comp
C.L.N.I.Input
C.L.INV.Input
U.V.Indicate
U.V.Delay
SCR Trigger
Remote Activate
Reset
O.V.Indicate
O.V.Delay
O.V.N.I.Input
O.V.Inv.Input
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16 VIN
VREF
Ground
C.L.Output
Offset/Comp
C.L.N.I.Input
C.L.INV.Input
U.V.Indicate
SCR Trigger
Remote Activate
Reset
O.V.Indicate
O.V.Delay
O.V.Input
U.V.Input
U.V.Delay
U.V.N.I.Input
U.V.Inv.Input
12 1211 11
10 10
13 13
14 14
15 15
16 16
17 17
18 18
8 8
9 9
7 7
5 5
4 4
3 3
2 2
6 6
1 1
19 19
20 20
PLCC-20, LCC-20
(TOP VIEW)
Qor L Package
PLCC-20, LCC-20
(TOP VIEW)
Qor L Package
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
ABSOLUTE MAXIMUM RATINGS
(1)
UC1543 , , UC1544UC2543 , UC2544UC3543 , UC3544
SLUS188A – APRIL 1997 – REVISED FEBRUARY 2007
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
V
IN
Input supply voltage 40
VSense inputs, voltage range 0 to VINSCR trigger current
(2)
-600 mAIndicator output voltage 40 VIndicator output sink current 50 mAPower dissipation (package limitation) 1000 mWUC1543, UC1544 -55 to 125T
J
Operating temperature range UC2543, UC2544 -25 to 85
°CUC3543, UC3544 0 to 70T
stg
Storage temperature range -65 to 150
(1) Currents are positive-into, negative-out of the specified terminal.(2) At higher input voltages, a dissipation limiting resistor, RG, is required.
2
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ELECTRICAL CHARACTERISTICS
UC1543 , , UC1544UC2543 , UC2544UC3543 , UC3544
SLUS188A – APRIL 1997 – REVISED FEBRUARY 2007
Unless otherwise stated, these specifications apply for T
A
= -55°C to 125°C for theUC1543 and UC1544; -25°C to 85°C forthe UC2543 and UC2544; and 0°C to 70°C for the UC3543 and UC3544. Electrical tests are performed with V
IN
= 10 V and2-k Ωpull-up resistors on all indicator outputs. All electrical specifications for the UC1544, UC2544, and UC3544 devices aretested with the inverting over-voltage input and the non-inverting under-voltage input externallyconnected to the 2.5 Vreference. T
A
= T
J
.
UC1543/UC1544/UC2543/
UC3543/UC3544UC2544PARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
T
J
= 25°C to T
MAX
4.5 40 4.5 40V
IN
Input voltage range VT
MIN
to T
MAX
4.7 40 4.7 40V
IN
= 40 V, output open,
7 10 7 10T
J
= 25°CI
CC
Supply current mAT
MIN
≤T
J
≤T
MAX
15 15
Reference Section
T
J
= 25°C 2.48 2.5 2.52 2.45 2.50 2.55V
OUT
Output voltage VOver temperature range 2.45 2.55 2.40 2.60Line regulation V
IN
= 5 to 30 V 1 5 1 5
mVLoad regulation I
REF
= 0 to 10 mA 1 10 1 10Short circuit current V
REF
= 0 -10 -20 -40 -12 -20 -40 mATemperature stability 50 50 ppm/°C
SCR Trigger Section
Peak output current V
IN
= 5V, RG = 0, VO = 0 -100 -300 -600 -100 -300 -600 mAPeak output voltage V
IN
= 15 V, I
O
= -100 mA 12 13 12 13
VOutput OFF voltage V
IN
= 40 V 0 0.1 0 0.1Remote activate current R/A Pin = GND -0.4 -0.8 -0.4 -0.8 mARemote activate voltage R/A Pin Open 2 6 2 6 VReset current Reset = GND, R/A = GND -0.4 -0.8 -0.4 -0.8 mAReset voltage Reset open, R/A = GND 2 6 2 6 VOutput current rise time R
L
= 50, T
J
= 25°C, C
D
= 0 400 400 mA/ µsProp. delay from R/A R
L
= 50, T
J
= 25°C, C
D
= 0 300 300
nsProp. delay from O/V input R
L
= 50, T
J
= 25°C, C
D
= 0 500 500
Comparator Section
Input threshold (Input T
J
= 25°C 2.45 2.50 2.55 2.40 2.50 2.60voltage rising on O.V. and VOver temperature range 2.40 2.60 2.35 2.65falling on U.V.)Input hysteresis 25 25 mVInput bias current Sense input = 0 V -0.3 -1.0 -0.3 -1.0 µADelay saturation 0.2 0.5 0.2 0.5
VDelay high level 6 7 6 7Delay charging current V
O
= 0 -200 -250 -300 -200 -250 -300 µAIndicate saturation I
L
= 10 mA 0.2 0.5 0.2 0.5 VIndicate leakage V
IND
= 40 V 0.01 1.0 0.01 1.0 µAInput over drive = 200 mV,
400 400 nsT
J
= 25°C, C
D
= 0Propagation delay
Input over drive = 200 mV,
10 10 msT
J
= 25°C, C
D
= 1 µF
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TYPICAL CHARACTERISTICS
UC1543 , , UC1544UC2543 , UC2544UC3543 , UC3544
SLUS188A – APRIL 1997 – REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)Unless otherwise stated, these specifications apply for T
A
= -55°C to 125°C for theUC1543 and UC1544; -25°C to 85°C forthe UC2543 and UC2544; and 0°C to 70°C for the UC3543 and UC3544. Electrical tests are performed with V
IN
= 10 V and2-k Ωpull-up resistors on all indicator outputs. All electrical specifications for the UC1544, UC2544, and UC3544 devices aretested with the inverting over-voltage input and the non-inverting under-voltage input externallyconnected to the 2.5 Vreference. T
A
= T
J
.
Current Limit Section
Input voltage range 0 VIN -3V 0 VIN -3V VInput Bias Current Offset pin open, V
CM
= 0 -0.3 -1.0 -0.3 -1.0 µAOffset pin open, V
CM
= 0 0 10 0 10Input offset voltage mV10k from offset pin to GND 80 100 120 80 100 120CMRR 0 ≤V
CM
≤12 V, V
IN
= 15 V 60 70 60 70Offset pin open, V
CM
= 0
dBV,AVOL 72 80 72 80R
L
= 10 k Ωto 15 k Ω,V
OUT
= 1 to 6 VOutput saturation I
L
= 10 mA 0.2 0.5 0.2 0.5 VOutput leakage V
IND
= 40 V 0.01 1.0 0.01 1.0 µASmall signal bandwidth A
V
= 0dB, T
J
= 25°C 5 5 MHzV
OVERDRIVE
= 100 mV,Propagation delay 200 200 nsT
J
= 25°C
Figure 1. Figure 2.
4
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APPLICATION INFORMATION
Current limit input threshold,
1000
1
TH
VR
=
Peak current to load,
2
2 3
O
TH
P
SC SC
V
VR
IR R R R
æ ö
@ + ç ÷
+
è ø
Short circuit current,
TH
SC
SC
V
IR
=
Low output voltage limit,
2 5 4 5 6
5 6
O( low )
. ( R R R )
VR R
+ +
=+
High output voltage limit,
2 5 4 5 6
6
O( high )
. ( R R R )
VR
+ +
=
SCR trigger power limiting resistor,
5
0 2
IN
G
V
R.
-
>
UC1543 , , UC1544UC2543 , UC2544UC3543 , UC3544
SLUS188A – APRIL 1997 – REVISED FEBRUARY 2007
The values for the external components are determined as follows:
C
S
is determined by the current loop dynamics
Voltage sensing delay, t
D
= 10,000C
d
Figure 7. Typical Application
6
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-8774001EA ACTIVE CDIP J 16 1 TBD Call TI Call TI
5962-8774001FA ACTIVE CFP W 16 25 TBD A42 N / A for Pkg Type
5962-8774002VA OBSOLETE CDIP J 18 TBD Call TI Call TI
UC1543J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
UC1543J883B ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
UC1543L ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
UC1543L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
UC1543W883B ACTIVE CFP W 16 25 TBD A42 N / A for Pkg Type
UC1544J OBSOLETE CDIP J 18 TBD Call TI Call TI
UC1544J883B OBSOLETE CDIP J 18 TBD Call TI Call TI
UC1544L OBSOLETE LCCC FK 20 TBD Call TI Call TI
UC1544L883B OBSOLETE LCCC FK 20 TBD Call TI Call TI
UC2543DW NRND SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC2543DWG4 NRND SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC2543J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
UC2543N NRND PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UC2543NG4 NRND PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UC2544DW NRND SOIC DW 18 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC2544DWG4 NRND SOIC DW 18 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC2544J OBSOLETE CDIP J 18 TBD Call TI Call TI
UC2544N NRND PDIP N 18 20 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UC2544NG4 NRND PDIP N 18 20 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UC3543J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 9-May-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UC3543N NRND PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UC3543NG4 NRND PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UC3544J OBSOLETE CDIP J 18 TBD Call TI Call TI
UC3544N NRND PDIP N 18 20 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UC3544NG4 NRND PDIP N 18 20 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1543, UC1544, UC2543, UC2543M, UC3543, UC3543M, UC3544 :
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