©2017 Integrated Device Technology, Inc.
DECEMBER 2017
DSC 3741/13
1
HIGH-SPEED 3.3V
1K X 8 DUAL-PORT
STATIC RAM
IDT71V30S/L
Features
◆High-speed access
– Commercial: 25/35/55ns (max.)
– Industrial 35ns (max.)
◆Low-power operation
– IDT71V30S
—Active: 375mW (typ.)
—Standby: 5mW (typ.)
– IDT71V30L
—Active: 375mW (typ.)
—Standby: 1mW (typ.)
Functional Block Diagram
NOTES:
1. IDT71V30: BUSY outputs are non-tristatable push-pulls.
2. INT outputs are non-tristable push-pull output structure.
◆On-chip port arbitration logic
◆Interrupt flags for port-to-port communication
◆Fully asynchronous operation from either port
◆Battery backup operation, 2V data retention (L Only)
◆TTL-compatible, single 3.3V ±0.3V power supply
◆Industrial temperature range (-40OC to +85OC) is available
for selected speeds
◆Green parts available, see ordering information
I/O
Control
Address
Decoder MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
I/O
Control
R/
W
L
CE
L
OE
L
BUSY
L
A
9L
A
0L
3741 drw 01
I/O
0L
-I/O
7L
CE
L
OE
L
R/W
L
INT
L
BUSY
R
I/O
0R
-I/O
7R
A
9R
A
0R
INT
R
CE
R
OE
R
(2)
(1) (1)
(2)
R/
W
R
CE
R
OE
R
10
10
R/W
R
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
2
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. Package body is approximately 10mm x 10mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate the orientation of the actual part-marking.
Pin Configurations(1,2,3)
Description
The IDT71V30 is a high-speed 1K x 8 Dual-Port Static RAM. The
IDT71V30 is designed to be used as a stand-alone 8-bit Dual-Port
SRAM.
Both devices provide two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 375mW of power. Low-power (L) ver-
sions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
The IDT71V30 devices are packaged in 64-pin STQFPs.
INDEX
IDT71V30TF
PP64
(4)
64-Pin STQFP
Top View
(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
17
18
19
20
32
31
30
29
28
27
26
25
24
23
22
21
49
50
51
52
63
62
61
60
59
58
57
56
55
54
53
64
I/O
6R
N/C
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
OE
R
N/C
N/C
I/O
2L
A
0L
OE
L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
N/C
N/C
3741 drw 03
N/C
N/C
N/C
INT
L
BUSY
L
R/W
L
CE
L
V
CC
V
CC
CE
R
R/W
R
BUSY
R
INT
R
N/C
N/C
N/C
I/O
3L
N/C
I/O
4L
I/O
5L
I/O
6L
I/O
7L
N/C
GND
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
N/C
I/O
4R
I/O
5R
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
3
Absolute Maximum Ra tings(1)
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.
3 . This is the absolute maximum junction temperature for the device. No DC Bias.
NOTE:
1. At Vcc < 2.0V input leakages are undefined. Supply CurrentVIN > VCC -0.2V or < 0.2V
Capacitance(1) (TA = +25OC, f=1.0MHz)
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Symbol Rating Com'l & Ind Unit
V
TERM
(2)
Terminal Vo ltag e
wi th Res p e c t to GND -0.5 to + 4.60 V
T
BIAS
Temperature
Und e r B ias -55 to +125
o
C
T
STG
Storage
Temperature -65 to + 150
o
C
T
JN
(3)
J unc tion Te mp e rature +150
o
C
I
OUT
DC Outp ut
Current 50 mA
3741 tb l 01
Symbol Parameter Conditions
(2)
Max. Unit
C
IN
Inp ut Cap a c itanc e V
IN
= 3dV 9 pF
C
OUT
(3)
Output Cap a c itanc e V
OUT
= 3dV 10 pF
3741 tbl 04
Symbol Parameter Test Conditions
71V30S 71V30L
UnitMin. Max. Min. Max.
|I
LI
| Input Le ak age
Current
(1)
V
CC
= 3.6V,
V
IN
= 0V to V
CC
___
10
___
5µA
|I
LO
| Output Leakage
Current CE = V
IH
,
V
OUT
= 0V to V
CC
___
10
___
5µA
V
OL
Outp ut Lo w Voltag e
(I/O
0
-I/O
7
)I
OL
= 4mA
___
0.4
___
0.4 V
V
OH
Output High Vo ltag e I
OH
= -4mA 2.4
___
2.4
___
V
3741 t bl 05
Recommended
DC Oper ating Conditions
Maximum Operating
Temperature and Supply Voltage(1,2)
NOTE:
1. VIL (min.) = -1.5V for pulse width less than 20ns.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers,
contact your sales office.
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supp ly Vo ltage 3.0 3.3 3.6 V
GND Ground 0 0 0 V
V
IH
Input Hi g h Voltag e 2. 0
____
V
CC
+0.3V V
V
IL
Input Lo w Vo l tag e -0.3(1)
____
0.8 V
3741 tbl 02
Grade Ambient
Temperature GND Vcc
Commercial 0
O
C to + 70
O
C0V 3.3V
+
0.3
Industrial -40
O
C to +85
O
C0V 3.3V
+
0.3
3741 tbl 03
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
4
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization but not production tested.
Data Retention Characteristics (L V ersion Only)
DC Electrical Characteristics Over the Operating
Tempera ture and Supply Voltage Range(1,6,7) (VCC = 3.3V ± 0.3V)
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 70mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t RC.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to chip enable Truth Table I.
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Symbol Parameter Test Condition
71V30L
UnitMin. Typ.
(1)
Max.
V
DR
V
CC
fo r Data Re tenti on 2. 0
____ ____
V
I
CCDR
Data Re te ntio n Curre nt
V
CC
= 2
V,
CE > V
CC
-0.2V
Ind.
____
100 1000 µA
Com'l.
____
100 500
t
CDR
(3)
Chi p De se le c t to Data Re te ntio n Ti me V
IN
> V
CC
-0. 2V o r V
IN
< 0. 2V 0
____ ____
ns
t
R
(3)
Op e ratio n Re cov e ry Time t
RC
(2)
____ ____
ns
3741 tb l 07
Symbol Parameter Test Condition Version
71V30X25
Com'l Only
71V30X35
Com'l & Ind 71V30X55
Com'l Only
Unit
Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max.
I
CC
Dynamic Operating Current
(Both Ports Active) CE
L
and
CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(3)
COM'L S
L75
75 150
120 75
75 145
115 75
75 135
105 mA
IND S
L
___
___
___
___
___
75
___
145
___
___
___
___
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
CE
L
and
CE
R
= V
IL
,
f = f
MAX
(3)
COM'L S
L20
20 50
35 20
20 50
35 20
20 50
35 mA
IND S
L
___
___
___
___
___
20
___
50
___
___
___
___
I
SB2
Standby Current
(One Port - TTL Level
Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(3)
COM'L S
L30
30 105
75 30
30 100
70 30
30 90
60 mA
IND S
L
___
___
___
___
___
30
___
100
___
___
___
___
I
SB3
Full Standby Current (Both
Ports - CMOS Level Inputs) CE
L
and CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
COM'L S
L1.0
0.2 5.0
3.0 1.0
0.2 5.0
3.0 1.0
0.2 5.0
3.0 mA
IND S
L
___
___
___
___
___
1.0
___
5.0
___
___
___
___
I
SB4
Full Standby Current
(One Port - CMOS
Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f=f
MAX
(3)
COM'L S
L30
30 90
75 30
30 85
70 30
30 75
60 mA
IND S
L
___
___
___
___
___
30
___
85
___
___
___
___
3741 tbl 06
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
5
AC Test Conditions Data Retention Waveform
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part number indicates power rating (S or L).
4. Industrial temperature: for specific speeds, packages and power contact your sales office.
Figure 2. Output Test Load
(For tHZ, tLZ, tWZ and tOW)
* Including scope and jig.
Figure 1. AC Output Test Load
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(3,4)
Inp ut Puls e Le v e ls
Inp ut Ris e /Fall Time s
Inp ut Timing Re fere nce Leve ls
Outp ut Refere nce Levels
Outp ut Lo ad
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
3741 tbl 08
V
CC
CE
3.0V 3.0V
DATA RETENTION MODE
t
CDR
V
IH
V
IH
V
DR
V
DR
≥2.0V
3741 drw 04
t
R
,
590Ω
30pF
435Ω
DATA
OUT
590Ω
435Ω5pF
DATA
OUT
3741 drw 05
3.3V 3.3V
BUSY
INT
71V30X25
Com'l Only 71V30X35
Com'l & Ind 71V30X55
Com'l Only
UnitSymbol Parameter Min. Max. Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 25
____
35
____
55
____
ns
t
AA
Address Access Time
____
25
____
35
____
55 ns
t
ACE
Chip Enable Access Time
____
25
____
35
____
55 ns
t
AOE
Output Enable Access Time
____
12
____
20
____
25 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
0
____
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,2)
____
12
____
15
____
30 ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
50
____
50
____
50 ns
3741 tbl 09
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
6
Timing Waveform of Read Cycle No. 1, Either Side(1)
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in case where the opposite is port is completing a write operation to same the address location. For simultaneous read operations BUSY has
no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side(3)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is desserted first, OE or CE.
3. R/W = VIH and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, and tBDD.
ADDRESS
DATA
OUT
t
RC
t
OH
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
3741 drw 06
t
BDD
(2,3)
BUSY
OUT
CE
t
ACE
t
AOE
t
HZ
t
LZ
t
PD
VALID DATA
t
PU
50%
OE
DATA
OUT
CURRENT
CC
I
SS
I50%
3741 drw 07
(4)
(1)
(1) (2)
(2)
(4)
t
LZ
t
HZ
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
7
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
4. 'X' in part number indicates power rating (S or L).
5. Industrial temperatures: for specific speeds, packages and powers contact your sales office.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(4,5)
Symbol Parameter
71V30X25
Com'l Only 71V30X35
Com'l & Ind 71V30X55
Com'l Only
Unit
Min. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 25
____
35
____
55
____
ns
t
EW
Chip Enable to End-of-Write 20
____
30
____
40
____
ns
t
AW
Address Valid to End-of-Write 20
____
30
____
40
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WP
Write Pulse Width 20
____
30
____
40
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 12
____
20
____
20
____
ns
t
HZ
Output High-Z Time
(1,2)
____
12
____
15
____
30 ns
t
DH
Data H old Time
(3)
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
15
____
15
____
30 ns
t
OW
Output Active from End-of-Write
(1,2,3)
0
____
0
____
0
____
ns
3741 tbl 10
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
8
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
Timing Wa veform of Write Cycle No. 1,(R/W Controlled Timing)(1,5,8)
t
WC
ADDRESS
OE
CE
R/W
DATA
OUT
DATA
IN
t
AS
t
WR
t
OW
t
DW
t
DH
t
AW
t
WP
(2)
t
HZ
(4) (4)
t
WZ
t
HZ
3741 drw 08
(6)
(7)
(7)
(7)
(3)
tWC
ADDRESS
CE
R/W
DATA IN
tAS tEW tWR
tDW tDH
tAW
3741 drw 09
(6) (2) (3)
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
9
t
WC
t
WP
t
DW
t
DH
t
BDD
t
DDD
t
BDA
t
WDD
ADDR
"B"
DATA
OUT"B"
DATA
IN"A"
ADDR
"A"
MATCH
VALID
MATCH
VALID
BUSY
"B"
3741 drw 10
(1)
t
APS
R/W
"A"
NOTES:
1. To ensure that the earlier of the two ports wins.
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Timing Wav eform of Write with Port-to-Port Read with BUSY(1,2,3,4)
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6,7)
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read with BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the Write Cycle is inhibited on Port “B” during contention on Port “A”.
5. To ensure that the Write Cycle is completed on Port “B” after contention on Port “A”.
6. 'X' in part number indicates power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
71V30X25
Com'l Only 71V30X35
Com'l & Ind 71V30X55
Com'l Only
UnitSymbol Parameter Min. Max. Min. Max. Min. Max.
BUSY TIMING (M/S= V
IH
)
t
BAA
BUSY Access Time from Address Match
____
20
____
20
____
30 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
20
____
20
____
30 ns
t
BAC
BUSY Access Time from Chip Enable
____
20
____
20
____
30 ns
t
BDC
BUSY Disable Time from Chip Enable
____
20
____
20
____
30 ns
t
WH
Write Hold After BUSY
(5)
20
____
30
____
40
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
50
____
60
____
80 ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
35
____
45
____
65 ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
30
____
30
____
45 ns
3741 tbl 11
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
10
NOTES:
1. tWH must be met for BUSY.
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
Timing Waveform of BUSY Arbitration Controlled Address Match Timing(1)
Timing Wa veform of Write with BUSY(3)
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
BUSY
'B'
3741 drw 11
R/W
'A'
t
WP
t
WH
t
WB
R/W
'B' (2)
(1)
,
tAPS
ADDR
'A' AND 'B' ADDRESSES MATCH
tBAC tBDC
CE'B'
CE'A'
BUSY'A'
3741 drw 12
(2)
BUSY
'B'
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
t
APS
ADDR
'A'
ADDR
'B'
t
RC OR
t
WC
3741 drw 13
(2)
t
BAA
t
BDA
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
11
INT Clears
Timing Waveform of Interrupt Mode(1)
INT Sets
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table II.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,2)
71V30X25
Com'l Only 71V30X35
Com'l & Ind 71V30X55
Com'l Only
UnitSymbol Parameter Min. Max. Min. Max. Min. Max.
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
INS
Interrupt Set Time
____
25
____
25
____
45 ns
t
INR
Interrupt Reset Time
____
25
____
25
____
45 ns
3741 tbl 12
t
INS
ADDR
'A'
INT
'B'
INTERRUPT ADDRESS
t
WC
t
AS
R/W
'A'
t
WR
3741 drw 14
(3)
(3)
(2)
(4)
t
RC
INTERRUPT CLEAR ADDRESS
ADDR
'B'
OE
'B'
t
INR
INT
'A'
3741 drw 15
t
AS
(3)
(3)
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
12
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT71V30. BUSYX outputs on the
IDT71V30 are non-tristatable push-pull.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result.
BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Tables
Table I — Non-Contention Read/Write Control(4)
NOTES:
1. A0L – A9L ≠ A0R – A9R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t WDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
Table III — Address BUSY Arbitration
T able II — Interrupt Flag(1,4)
Left or Right Port
(1)
FunctionR/WCE OE D
0-7
X H X Z Port Disab led and in Power-Down Mode, I
SB2
or I
SB4
XHX Z
CE
R =
CE
L =
V
IH
,
Power-Down Mode, I
SB1
or I
SB3
LLXDATA
IN
D ata o n Po rt Writte n Into Me mo ry
(2)
HLLDATA
OUT
Data in Memory Output on Port
(3)
H L H Z High Impedance Outputs
3741 tbl 13
Left Port Right Port
FunctionR/W
L
CE
L
OE
L
A
9L
-A
0L
INT
L
R/W
R
CE
R
OE
R
A
9R
-A
0R
INT
R
LLX3FFXXXX X L
(2)
S e t Rig h t INT
R
Flag
XXXXXXLL3FFH
(3
)
Re s et Ri g h t INT
R
Flag
XXX X L
(3)
LLX3FEXSet Left INT
L
Flag
XLL3FEH
(2)
XXX X XReset Left INT
L
Flag
3 741 t bl 14
Inputs Outputs
Function
CE
L
CE
R
A
OL
-A
9L
A
OR
-A
9R
BUSY
L
(1)
BUSY
R
(1)
X X NO MATCH H H Normal
H X MATCH H H Normal
X H MATCH H H Normal
L L MATCH (2) (2) Write Inhi bit
(3)
3741 tbl 15
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
13
Functional Description
The IDT71V30 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT71V30 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not
selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
3FE (HEX), where a write is defined as the CE = R/W = VIL per Truth
Table II. The left port clears the interrupt by accessing address location
3FE access with CER = OER = VIL, R/W is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port writes to
memory location 3FF (HEX) and to clear the interrupt flag (INTR), the
right port must access the memory location 3FF. The message (8 bits)
at 3FE or 3FF is user-defined, since it is an addressable SRAM location.
If the interrupt function is not used, address locations 3FE and 3FF are not
used as mail boxes, and are part of the random access memory. Refer
to Table II for the interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “Busy”. The BUSY pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
The use of BUSY logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation.
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
14
Ordering Inform ation
NOTES:
1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office.
2. Green parts available. For specific speeds, packages and powers contact your sales office.
LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02
A
Power 99
Speed A
Package A
Process/
Temperature
Range
Blank
I(1
)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
TF 64-pin STQFP (PP64)
3741 drw 20
S
L Standard Power
Low Power
71V30 8K (1K x 8-Bit) Synchronous Dual-Port RAM
Speed in nanoseconds
Commercial Only
Commercial & Industrial
Commercial Only
XXXXX
Device
Type
G(2
)
Green
25
35
55
Tube or Tray
Tape and Reel
A A
Blank
8
Datasheet Document History
12/9/98: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
6/15/99: Changed drawing format
8/3/99: Page 2 Fixed typographical error
9/1/99: Removed Preliminary
11/12/99: Replaced IDT logo
1/17/01: Pages 1 and 2 Moved all of "Description" to page 2 and adjusted page layouts
Page 3 Increased storage temperature parameters
Clarified TA parameter
Page 4 DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±200mV to 0mV in notes
3/14/05: Page 1 Added green availability to features
Page 17 Added green indicator to ordering information
Page 1 & 17 Replaced old TM logo with new TM logo
7/16/07: Page 3 Added Junction Temperature spec values to the Absolute Maximum Rating table
Added footnote 3 for additional clarification of Junction Temperature
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
15
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
Datasheet Document History (con't)
10/23/08: Page 14 Removed "IDT" from orderable part number
11/25/09: Page 4 In order to correct the DC Chars table for the 71V30L35 speed grade and to the Data Retention Chars table, I Temp
values have been added to each table respectively. In addition, all of the AC tables and the ordering information also
now reflect this I temp correction
06/22/15: Page 2 Removed IDT in reference to fabrication
Page 2 & 14 The package code PP64-1 changed to PP64 to match standard package codes
Page 14 Added Tape and Reel indicator to Ordering Information
07/23/15: Entire datasheet Removed the 55ns Industrial speed offering. 55ns speed only offered in commercial grade
Product Discontinuation Notice - PDN# SP-17-02
Last time buy expires June 15, 2018
12/20/17:
