ADC12138CIWMX/NOPB - NATIONAL SEMICONDUCTOR

ADC12130, ADC12132, ADC12138

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ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D

Converters with MUX and Sample/Hold

Check for Samples: ADC12130,ADC12132,ADC12138

1FEATURES DESCRIPTION

NOTE: Some device/package combinations are

2• Serial I/O (MICROWIRE, SPI and QSPI obsolete and are described and shown here for

Compatible) reference only. See our web site for product

• Power Down Mode availability.

• Programmable Acquisition Time The ADC12130, ADC12132 and ADC12138 are 12-

• Variable Digital Output Word Length and bit plus sign successive approximation Analog-to-

Format Digital converters with serial I/O and configurable

input multiplexer. The ADC12132 and ADC12138

• No Zero or Full Scale Adjustment Required have a 2 and an 8 channel multiplexer, respectively.

• 0V to 5V Analog Input Range with Single 5V The differential multiplexer outputs and ADC inputs

Power Supply are available on the MUXOUT1, MUXOUT2, A/DIN1

and A/DIN2 pins. The ADC12130 has a two channel

APPLICATIONS multiplexer with the multiplexer outputs and ADC

inputs internally connected. The ADC12130 family is

• Pen-Based Computers tested and specified with a 5 MHz clock. On request,

• Digitizers these ADCs go through a self calibration process that

• Global Positioning Systems adjusts linearity, zero and full-scale errors to typically

less than ±1 LSB each.

KEY SPECIFICATIONS The analog inputs can be configured to operate in

• Resolution 12-bit plus sign various combinations of single-ended, differential, or

pseudo-differential modes. A fully differential unipolar

• 12-Bit plus sign conversion time 8.8 μs (max) analog input range (0V to +5V) can be

• 12-Bit plus sign throughput time 14 μs (max) accommodated with a single +5V supply. In the

• Integral Linearity Error ±2 LSB (max) differential modes, valid outputs are obtained even

when the negative inputs are greater than the positive

• Single Supply 3.3V or 5V ±10% because of the 12-bit plus sign output data format.

• Power Consumption The serial I/O is configured to comply with NSC

– +3.3V 15 mW (max) MICROWIRE. For voltage references, see the

– +3.3V power down 40 μW (typ) LM4040, LM4050 or LM4041.

– +5V 33 mW (max)

– +5V power down 100 μW (typ)

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADC12130, ADC12132, ADC12138

SNAS098G –MARCH 2000–REVISED MARCH 2013

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ADC12138 Simplified Block Diagram

Connection Diagrams

Top View Top View

Figure 1. 16-Pin MDIP and Figure 2. 20-Pin SSOP Package

Wide Body SOIC Packages See Package Number DB0020A

See Package Number NFG0016E and DW0016B

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SNAS098G –MARCH 2000–REVISED MARCH 2013

Top View

Figure 3. 28-Pin MDIP, SSOP and

Wide Body SOIC Packages

See Package Numbers N28B, DB0028A, and DW0028B

Some of these product/package combinations are obsolete and are shown here for reference only. Check the TI

web site for availability.

PIN DESCRIPTIONS

Pin Name Pin Description

Analog Inputs to the MUX (multiplexer). A channel input is selected by the address information at the DI pin, which

is loaded at the rising edge of SCLK into the address register (see Table 2 and Table 3). The voltage applied to

CH0 thru CH7 these inputs should not exceed VA+ or go below VA- or below GND. Exceeding this range on an unselected

channel may corrupt the reading of a selected channel.

COM Analog input pin that is used as a pseudo ground when the analog multiplexer is single-ended.

MUXOUT1 Multiplexer Output pins. If the multiplexer is used, these pins should be connected to the A/DIN pins, directly or

MUXOUT2 through an amplifier and/of filter.

Converter Input pins. MUXOUT1 is usually tied to A/DIN1. MUXOUT2 is usually tied to A/DIN2. If external circuitry

A/DIN1 is placed between MUXOUT1 and A/DIN1, or MUXOUT2 and A/DIN2, it may be necessary to protect these pins

A/DIN2 against voltage overload. The voltage at these pins should not exceed VA+or go below AGND (see Figure 64).

Data Output pin. This pin is an active push/pull output when CS is low. When CS is high, this output is TRI-STATE.

The conversion result (DB0–DB12) and converter status data are clocked out at the falling edge of SCLK on this

DO pin. The word length and format of this result can vary (see Table 1). The word length and format are controlled by

the data shifted into the multiplexer address and mode select register (see Table 4).

Serial Data Input pin. The data applied to this pin is shifted at the rising edge of SCLK into the multiplexer address

DI and mode select register. Table 2 through Table 4 show the assignment of the multiplexer address and the mode

select data.

This pin is an active push/pull output which indicates the status of the ADC12130/2/8.A logic low on this pin

EOC indicates that the ADC is busy with a conversion, Auto Calibration, Auto Zero or power down cycle. The rising edge

of EOC signals the end of one of these cycles

A logic low is required at this pin to program any mode or to change the ADC's configuration as listed in Mode

Programming (Table 4). When this pin is high, the ADC is placed in the read data only mode. While in the read data

only mode, bringing CS low and pulsing SCLK will only clock out the data stored in the ADCs output shift register.

CONV The data at DI will be ignored. A new conversion will not be started and the ADC will remain in the mode and/or

configuration previously programmed. Read data only cannot be performed while a conversion, Auto Cal or Auto

Zero are in progress.

Product Folder Links: ADC12130 ADC12132 ADC12138

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PIN DESCRIPTIONS (continued)

Pin Name Pin Description

Chip Select input pin. When a logic low is applied to this pin, the rising edge of SCLK shifts the data at the DI input

into the address register and brings DO out of TRI-STATE. With CS low, the falling edge of SCLK shifts the data

resulting from the previous ADC conversion out at the DO output, with the exception of the first bit of data. When

CS is low continuously, the first bit of the data is clocked out on the rising edge of EOC (end of conversion). When

CS is toggled, the falling edge of CS always clocks out the first bit of data. CS should be brought low while SCLK is

low. The falling edge of CS interrupts a conversion in progress and starts the sequence for a new conversion.

CS When CS is brought low during a conversion, that conversion is prematurely terminated and the data in the output

latches may be corrupted. Therefore, when CS is brought low during a conversion in progress, the data output at

that time should be ignored. CS may also be left continuously low. In this case, it is imperative that the correct

number of SCLK pulses be applied to the ADC in order to remain synchronous. After the ADC supply power is

applied, the device expects to see 13 clock pulses for each I/O sequence. The number of clock pulses the ADC

expects is the same as the digital output word length. This word length can be modified by the data shifted in at the

DO pin. Table 4 details the data required.

Data Output Ready pin. This pin is an active push/pull output which is low when the conversion result is being

DOR shifted out and goes high to signal that all the data has been shifted out.

Serial Data Clock input. The clock applied to this input controls the rate at which the serial data exchange occurs.

The rising edge loads the information at the DI pin into the multiplexer address and mode select shift register. This

address controls which channel of the analog input multiplexer (MUX) is selected and the mode of operation for the

ADC. With CS low, the falling edge of SCLK shifts the data resulting from the previous ADC conversion out on DO,

SCLK with the exception of the first bit of data. When CS is low continuously, the first bit of the data is clocked out on the

rising edge of EOC (end of conversion). When CS is toggled, the falling edge of CS always clocks out the first bit of

data. CS should be brought low when SCLK is low. The rise and fall times of the clock edges should not exceed

1μs.

Conversion Clock input. The clock applied to this input controls the successive approximation conversion time

CCLK interval and the acquisition time. The rise and fall times of the clock edges should not exceed 1 μs.

Positive analog voltage reference input. In order to maintain accuracy, the voltage range of VREF (VREF = VREF+−

VREF+ VREF−) is 1.0 VDC to 5.0 VDC and the voltage at VREF+ cannot exceed VA+. See Figure 63 for recommended

bypassing.

The negative analog voltage reference input. In order to maintain accuracy, the voltage at this pin must not go

VREF-below GND or exceed VREF+. (See Figure 63).

Power Down pin. When PD is high the ADC is powered down; when PD is low the ADC is powered up, or active.

PD The ADC takes a maximum of 700 μs to power up after the command is given.

These are the analog and digital power supply pins. VA+and VD+are not connected together on the chip. These

VA+pins should be tied to the same supply voltage and bypassed separately (see Figure 63). The operating voltage

VD+range of VA+ and VD+ is 3.0 VDC to 5.5 VDC.

DGND The digital ground pin (see Figure 63).

AGND The analog ground pin (see Figure 63).

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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Absolute Maximum Ratings (1)(2)

Positive Supply Voltage

(V+= VA+=VD+) 6.5V

Voltage at Inputs and Outputs

except CH0–CH7 and COM −0.3V to V++0.3V

Voltage at Analog Inputs

CH0–CH7 and COM GND −5V to V++5V

|VA+−VD+| 300 mV

Input Current at Any Pin (3) ±30 mA

Package Input Current (3) ±120 mA

Package Dissipation at TA= 25°C (4) 500 mW

ESD Susceptibility (5)

Human Body Model 1500V

Soldering Information

PDIP Packages (10 seconds) 260°C

SOIC Package (6)

Vapor Phase (60 seconds) 215°C

Infrared (15 seconds) 220°C

Storage Temperature −65°C to +150°C

(1) All voltages are measured with respect to GND, unless otherwise specified.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(3) When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA+ or VD+), the current at that pin should be

limited to 30 mA. The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power

supplies with an input current of 30 mA to four.

(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature,

TA. The maximum allowable power dissipation at any temperature is PD= (TJmax −TA)/θJA or the number given in the Absolute

Maximum Ratings, whichever is lower. For this device, TJmax = 150°C.

(5) The human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin.

(6) See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post

1986 Texas Instruments Linear Data Book for other methods of soldering surface mount devices.

Operating Ratings (1)(2)

Operating Temperature Range TMIN ≤TA≤TMAX

−40°C ≤TA≤+85°C

Supply Voltage (V+= VA+=VD+) +3.0V to +5.5V

|VA+−VD+| ≤100 mV

VREF+ 0V to VA+

VREF−0V to (VREF+−1V)

VREF (VREF+−VREF−) 1V to VA+

VREF Common Mode Voltage Range

[(VREF+) −(VREF−)] / 2 0.1 VA+ to 0.6 VA+

A/DIN1, A/DIN2, MUXOUT1

and MUXOUT2 Voltage Range 0V to VA+

ADC IN Common Mode Voltage Range

[(VIN+) −(VIN−)] / 2 0V to VA+

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND, unless otherwise specified.

Product Folder Links: ADC12130 ADC12132 ADC12138

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Package Thermal Resistance

Part Number Thermal Resistance (θJA)

ADC12130CIN 53°C/W

ADC12130CIWM 70°C/W

ADC12132CIMSA 134°C/W

ADC12132CIWM 64°C/W

ADC121038CIN 40°C/W

ADC121038CIMSA 97°C/W

ADC12138CIWM 50°C/W

Some of these product/package combinations are obsolete and are shown here for reference only. Check the TI

web site for availability.

Converter Electrical Characteristics

The following specifications apply for (V+= VA+=VD+ = +5V, VREF+ = +4.096V, and fully differential input with fixed 2.048V

common-mode voltage) or (V+= VA+=VD+ = 3.3V, VREF+ = 2.5V and fully-differential input with fixed 1.250V common-mode

voltage), VREF−= 0V, 12-bit + sign conversion mode(1), source impedance for analog inputs, VREF−and VREF+≤25Ω, fCK = fSK

= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA= TJ= TMIN to TMAX;all other

limits TA= TJ= 25°C. (2)(3)(4)

Units

Parameter Test Conditions Typical (5) Limits (6) (Limits)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 12 + sign Bits (min)

ILE Integral Linearity Error After Auto Cal (7) (8) ±1/2 ±2 LSB (max)

DNL Differential Non-Linearity After Auto Cal ±1.5 LSB (max)

Positive Full-Scale Error After Auto Cal (7) (8) ±1/2 ±3.0 LSB (max)

Negative Full-Scale Error After Auto Cal (7)(8) ±1/2 ±3.0 LSB (max)

After Auto Cal (9)(8)

Offset Error ±1/2 ±2 LSB (max)

VIN(+) = VIN(−) = 2.048V

(1) The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device.

Therefore, the output data from these modes are not an indication of the accuracy of a conversion result.

(2) Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+

or 5V below GND will not damage this device. However, errors in conversion can occur (if these diodes are forward biased by more than

50 mV) if the input voltage magnitude of selected or unselected analog input go above VA+ or below GND by more than 50 mV. As an

example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.55 VDC to ensure accurate conversions.

(3) To ensure accuracy, it is required that the VA+ and VD+ be connected together to the same power supply with separate bypass

capacitors at each V+pin.

(4) With the test condition for VREF (VREF+−VREF−) given as +4.096V, the 12-bit LSB is 1.0 mV. For VREF = 2.5V, the 12-bit LSB is 610 μV.

(5) Typical figures are at TJ= TA= 25°C and represent most likely parametric norm.

(6) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).

(7) Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes

through positive full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero

(see Figure 5 and Figure 6).

(8) The ADC12130 family's self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-

calibration process will result in a maximum repeatability uncertainty of 0.2 LSB.

(9) The human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin.

Product Folder Links: ADC12130 ADC12132 ADC12138

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Converter Electrical Characteristics (continued)

The following specifications apply for (V+= VA+=VD+ = +5V, VREF+ = +4.096V, and fully differential input with fixed 2.048V

common-mode voltage) or (V+= VA+=VD+ = 3.3V, VREF+ = 2.5V and fully-differential input with fixed 1.250V common-mode

voltage), VREF−= 0V, 12-bit + sign conversion mode(1), source impedance for analog inputs, VREF−and VREF+≤25Ω, fCK = fSK

= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA= TJ= TMIN to TMAX;all other

limits TA= TJ= 25°C. (2)(3)(4)

Units

Parameter Test Conditions Typical (5) Limits (6) (Limits)

DC Common Mode Error After Auto Cal (10) ±2 LSB (max)

TUE Total Unadjusted Error After Auto Cal (7)(11) (12) ±1 LSB

Multiplexer Chan-to-Chan Matching V+= +5V ±10%, VREF = +4.096V ±0.05 LSB

Power Supply Sensitivity Offset Error ±0.5 LSB

+ Full-Scale Error ±0.5 LSB

−Full-Scale Error ±0.5 LSB

Integral Linearity Error ±0.5 LSB

UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS

fIN = 1 kHz, VIN = 5 VPP, VREF+= 5.0V 69.4 dB

S/(N+D) Signal-to-Noise Plus Distortion Ratio fIN = 20 kHz, VIN = 5 VPP, VREF+= 5.0V 68.3 dB

fIN = 40 kHz, VIN = 5 VPP, VREF+ = 5.0V 65.7 dB

−3 dB Full Power Bandwidth VIN = 5 VPP, where S/(N+D) drops 3 dB 31 kHz

DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS

fIN = 1 kHz, VIN = ±5V, VREF+= 5.0V 77.0 dB

S/(N+D) Signal-to-Noise Plus Distortion Ratio fIN = 20 kHz, VIN = ±5V, VREF+= 5.0V 73.9 dB

fIN = 40 kHz, VIN = ±5V, VREF+= 5.0V 67.0 dB

−3 dB Full Power Bandwidth VIN = ±5V, where S/(N+D) drops 3 dB 40 kHz

REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS

CREF Reference Input Capacitance 85 pF

A/DIN1 and A/DIN2 Analog Input

CA/D 75 pF

Capacitance

A/DIN1 and A/DIN2 Analog Input VIN = +5.0V or VIN = 0V ±0.1 μA

Leakage Current

GND −0.05 V (min)

CH0–CH7 and COM Input Voltage (VA+) + 0.05 V (max)

CCH CH0–CH7 and COM Input Capacitance 10 pF

CMUXOUT MUX Output Capacitance 20 pF

On Channel = 5V and −0.01 μA

Off Channel = 0V

Off Channel Leakage (13)

CH0–CH7 and COM Pins On Channel = 0V and 0.01 μA

Off Channel = 5V

On Channel = 5V and 0.01 μA

Off Channel = 0V

On Channel Leakage (13)

CH0–CH7 and COM Pins On Channel = 0V and −0.01 μA

Off Channel = 5V

MUXOUT1 and MUXOUT2 Leakage VMUXOUT = 5.0V or VMUXOUT = 0V 0.01 μA

Current VIN = 2.5V and

RON MUX On Resistance 850 1900 Ω(max)

VMUXOUT = 2.4V

VIN = 2.5V and

RON Matching Channel to Channel 5 %

VMUXOUT = 2.4V

(10) The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels

shorted together.

(11) Offset or Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value

of the code transitions between −1 to 0 and 0 to +1 (see Figure 7).

(12) Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.

(13) Channel leakage current is measured after the channel selection.

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Converter Electrical Characteristics (continued)

The following specifications apply for (V+= VA+=VD+ = +5V, VREF+ = +4.096V, and fully differential input with fixed 2.048V

common-mode voltage) or (V+= VA+=VD+ = 3.3V, VREF+ = 2.5V and fully-differential input with fixed 1.250V common-mode

voltage), VREF−= 0V, 12-bit + sign conversion mode(1), source impedance for analog inputs, VREF−and VREF+≤25Ω, fCK = fSK

= 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA= TJ= TMIN to TMAX;all other

limits TA= TJ= 25°C. (2)(3)(4)

Units

Parameter Test Conditions Typical (5) Limits (6) (Limits)

Channel-to-Channel Crosstalk VIN = 5 VPP, fIN = 40 kHz −72 dB

MUX Bandwidth 90 kHz

DC and Logic Electrical Characteristics

The following specifications apply for (V+= VA+=VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V

common-mode voltage) or (V+= VA+=VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-

mode voltage), VREF−= 0V, 12-bit + sign conversion mode(1), source impedance for analog inputs, VREF−and VREF+≤25Ω,

fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA= TJ= TMIN to TMAX;

all other limits TA= TJ= 25°C. (2)(3)(4)

V+= VA+ = V+= VA+ =

Typical Units

Parameter Test Conditions VD+ = 3.3V VD+ = 5V

(5) (Limits)

Limits (6) Limits (6)

CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS

VIN(1) Logical “1” Input Voltage VA+=VD+=V++10% 2.0 2.0 V (min)

VIN(0) Logical “0” Input Voltage VA+=VD+=V+−10% 0.8 0.8 V (max)

IIN(1) Logical “1” Input Current VIN = V+0.005 1.0 1.0 μA (max)

IIN(0) Logical `“0” Input Current VIN = 0V −0.005 −1.0 −1.0 μA (min)

DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS

VA+=VD+=V+−10%, 2.4 2.4 V (min)

IOUT =−360 μA

VOUT(1) Logical “1” Output Voltage VA+=VD+=V+−10%, 2.9 4.25 V (min)

IOUT =−10 μA

VA+=VD+=V+−10%

VOUT(0) Logical “0” Output Voltage 0.4 0.4 V (max)

IOUT = 1.6 mA

VOUT = 0V −0.1 −3.0 −3.0 μA (max)

IOUT TRI-STATE Output Current VOUT = V+−0.1 3.0 3.0 μA (max)

+ISC Output Short Circuit Source Current VOUT = 0V −14 mA

−ISC Output Short Circuit Sink Current VOUT = VD+ 16 mA

(1) The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device.

Therefore, the output data from these modes are not an indication of the accuracy of a conversion result.

(2) Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+

or 5V below GND will not damage this device. However, errors in conversion can occur (if these diodes are forward biased by more than

50 mV) if the input voltage magnitude of selected or unselected analog input go above VA+ or below GND by more than 50 mV. As an

example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.55 VDC to ensure accurate conversions.

(3) To ensure accuracy, it is required that the VA+ and VD+ be connected together to the same power supply with separate bypass

capacitors at each V+pin.

(4) With the test condition for VREF (VREF+−VREF−) given as +4.096V, the 12-bit LSB is 1.0 mV. For VREF = 2.5V, the 12-bit LSB is 610 μV.

(5) Typical figures are at TJ= TA= 25°C and represent most likely parametric norm.

(6) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).

Product Folder Links: ADC12130 ADC12132 ADC12138

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DC and Logic Electrical Characteristics (continued)

The following specifications apply for (V+= VA+=VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V

common-mode voltage) or (V+= VA+=VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-

mode voltage), VREF−= 0V, 12-bit + sign conversion mode(1), source impedance for analog inputs, VREF−and VREF+≤25Ω,

fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA= TJ= TMIN to TMAX;

all other limits TA= TJ= 25°C. (2)(3)(4)

V+= VA+ = V+= VA+ =

Typical Units

Parameter Test Conditions VD+ = 3.3V VD+ = 5V

(5) (Limits)

Limits (6) Limits (6)

POWER SUPPLY CHARACTERISTICS

Awake (Active) 1.5 2.5 mA (max)

CS = HIGH, Powered Down, 600 μA

ID+ Digital Supply Current CCLK on

CS = HIGH, Powered Down, 20 μA

CCLK off

Awake (Active) 3.0 4.0 mA (max)

CS = HIGH, Powered Down, 10 μA

IA+ Positive Analog Supply Current CCLK on

CS = HIGH, Powered Down, 0.1 μA

CCLK off

CS = HIGH, Powered Down, 70 μA

CCLK on

IREF Reference Input Current CS = HIGH, Powered Down, 0.1 μA

CCLK off

AC Electrical Characteristics

The following specifications apply for (V+= VA+=VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V

common-mode voltage) or (V+= VA+=VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-

mode voltage), VREF−= 0V, 12-bit + sign conversion mode(1), source impedance for analog inputs, VREF−and VREF+≤25Ω,

fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA= TJ= TMIN to TMAX;

all other limits TA= TJ= 25°C. (2)

Parameter Test Conditions Typical (3) Limits (4) Units (Limits)

10 5MHz (max)

fCK Conversion Clock (CCLK) Frequency 1 MHz (min)

10 5MHz (max)

fSK Serial Data Clock SCLK Frequency 0 Hz (min)

40 % (min)

Conversion Clock Duty Cycle 60 % (max)

40 % (min)

Serial Data Clock Duty Cycle 60 % (max)

44(tCK)44(tCK)(max)

tCConversion Time 12-Bit + Sign or 12-Bit 8.8 μs (max)

(1) The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device.

Therefore, the output data from these modes are not an indication of the accuracy of a conversion result.

(2) Timing specifications are tested at the TTL logic levels, VOL = 0.4V for a falling edge and VOL = 2.4V for a rising edge. TRI-STATE

output voltage is forced to 1.4V.

(3) Typical figures are at TJ= TA= 25°C and represent most likely parametric norm.

(4) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).

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AC Electrical Characteristics (continued)

The following specifications apply for (V+= VA+=VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V

common-mode voltage) or (V+= VA+=VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-

mode voltage), VREF−= 0V, 12-bit + sign conversion mode(1), source impedance for analog inputs, VREF−and VREF+≤25Ω,

fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA= TJ= TMIN to TMAX;

all other limits TA= TJ= 25°C. (2)

Parameter Test Conditions Typical (3) Limits (4) Units (Limits)

6(tCK)6(tCK)(min)

7(tCK)(max)

6 Cycles Programmed 1.2 μs (min)

1.4 μs (max)

10(tCK)10(tCK)(min)

11(tCK)(max)

10 Cycles Programmed 2.0 μs (min)

2.2 μs (max)

tAAcquisition Time (5) 18(tCK)18(tCK)(min)

19(tCK)(max)

18 Cycles Programmed 3.6 μs (min)

3.8 μs (max)

34(tCK)34(tCK)(min)

35(tCK)(max)

34 Cycles Programmed 6.8 μs (min)

7.0 μs (max)

4944(tCK)4944(tCK)(max)

tCAL Self-Calibration Time 988.8 μs (max)

76(tCK)76(tCK)(max)

tAZ Auto Zero Time 15.2 μs (max)

2(tCK)2(tCK)(min)

3(tCK)(max)

Self-Calibration or Auto Zero

tSYNC Synchronization Time from DOR 0.40 μs (min)

0.60 μs (max)

DOR High Time when CS is Low 9(tSK)9(tSK)(max)

tDOR Continuously for Read Data and Software 1.8 μs (max)

Power Up/Down 8(tSK)8(tSK)(max)

tCONV CONV Valid Data Time 1.6 μs (max)

(5) If SCLK and CCLK are driven from the same clock source, then tAis 6, 10, 18 or 34 clock periods minimum and maximum.

AC Electrical Characteristics

The following specifications apply for (V+= VA+=VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V

common-mode voltage) or (V+= VA+=VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-

mode voltage), VREF−= 0V, 12-bit + sign conversion mode(1), source impedance for analog inputs, VREF−and VREF+≤25Ω,

fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA= TJ= TMIN to TMAX;

all other limits TA= TJ= 25°C. (2) (Continued)

(1) The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device.

Therefore, the output data from these modes are not an indication of the accuracy of a conversion result.

(2) Timing specifications are tested at the TTL logic levels, VOL = 0.4V for a falling edge and VOL = 2.4V for a rising edge. TRI-STATE

output voltage is forced to 1.4V.

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AC Electrical Characteristics (continued)

The following specifications apply for (V+= VA+=VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V

common-mode voltage) or (V+= VA+=VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-

mode voltage), VREF−= 0V, 12-bit + sign conversion mode(1), source impedance for analog inputs, VREF−and VREF+≤25Ω,

fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA= TJ= TMIN to TMAX;

all other limits TA= TJ= 25°C. (2) (Continued) Units

Parameter Test Conditions Typical (3) Limits (4) (Limits)

Hardware Power-Up Time, Time from PD

tHPU 500 700 μs (max)

Falling Edge to EOC Rising Edge

Software Power-Up Time, Time from Serial

tSPU 500 700 μs (max)

Data Clock Falling Edge to EOC Rising Edge

Access Time Delay from CS Falling Edge to

tACC 25 60 ns (max)

DO Data Valid

Set-Up Time of CS Falling Edge to Serial Data

tSET-UP 50 ns (min)

Clock Rising Edge

Delay from SCLK Falling Edge to CS Falling

tDELAY 05ns (min)

Edge

t1H, t0H Delay from CS Rising Edge to DO TRI-STATE RL= 3k, CL= 100 pF 70 100 ns (max)

DI Hold Time from Serial Data Clock Rising

tHDI 515 ns (max)

Edge

DI Set-Up Time from Serial Data Clock Rising

tSDI 510 ns (min)

Edge

DO Hold Time from Serial Data Clock Falling 35 65 ns (max)

tHDO RL= 3k, CL= 100 pF

Edge 5ns (min)

Delay from Serial Data Clock Falling Edge to

tDDO 50 90 ns (max)

DO Data Valid

DO Rise Time, TRI-STATE to High DO Rise 10 40 ns (max)

tRDO RL= 3k, CL= 100 pF

Time, Low to High 10 40 ns (max)

DO Fall Time, TRI-STATE to Low DO Fall 15 40 ns (max)

tFDO RL= 3k, CL= 100 pF

Time, High to Low 15 40 ns (max)

Delay from CS Falling Edge to DOR Falling

tCD 45 80 ns (max)

Edge

Delay from Serial Data Clock Falling Edge to

tSD 45 80 ns (max)

DOR Rising Edge

CIN Capacitance of Logic Inputs 20 pF

COUT Capacitance of Logic Outputs 20 pF

(3) Typical figures are at TJ= TA= 25°C and represent most likely parametric norm.

(4) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).

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Figure 4. Transfer Characteristic

Figure 5. Simplified Error Curve vs. Output Code without Auto Calibration or Auto Zero Cycles

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Figure 6. Simplified Error Curve vs. Output Code after Auto Calibration Cycle

Figure 7. Offset or Zero Error Voltage

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Typical Performance Characteristics

The following curves apply for 12-bit + sign mode after Auto Calibration unless otherwise specified.

Linearity Error Change Linearity Error Change

vs. Clock Frequency vs. Temperature

Figure 8. Figure 9.

Linearity Error Change Linearity Error Change

vs. Reference Voltage vs. Supply Voltage

Figure 10. Figure 11.

Full-Scale Error Change Full-Scale Error Change

vs. Clock Frequency vs. Temperature

Figure 12. Figure 13.

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Typical Performance Characteristics (continued)

The following curves apply for 12-bit + sign mode after Auto Calibration unless otherwise specified.

Full-Scale Error Change Full-Scale Error Change

vs. Reference Voltage vs. Supply Voltage

Figure 14. Figure 15.

Offset or Zero Error Change Offset or Zero Error Change

vs. Clock Frequency vs. Temperature

Figure 16. Figure 17.

Offset or Zero Error Change Offset or Zero Error Change

vs. Reference Voltage vs. Supply Voltage

Figure 18. Figure 19.

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Typical Performance Characteristics (continued)

The following curves apply for 12-bit + sign mode after Auto Calibration unless otherwise specified.

Analog Supply Current Digital Supply Current

vs. Temperature vs. Clock Frequency

Figure 20. Figure 21.

Digital Supply Current Linearity Error Change

vs. Temperature vs. Temperature

Figure 22. Figure 23.

Full-Scale Error Change Full-Scale Error Change

vs. Temperature vs. Supply Voltage

Figure 24. Figure 25.

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Typical Performance Characteristics (continued)

The following curves apply for 12-bit + sign mode after Auto Calibration unless otherwise specified.

Offset or Zero Error Change Offset or Zero Error Change

vs. Temperature vs. Supply Voltage

Figure 26. Figure 27.

Analog Supply Current Digital Supply Current

vs. Temperature vs. Temperature

Figure 28. Figure 29.

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Typical Dynamic Performance Characteristics

The following curves apply for 12-bit + sign mode after Auto Calibration unless otherwise specified.

Bipolar Spectral Response Bipolar Spectral Response

with 1 kHz Sine Wave Input with 10 kHz Sine Wave Input

Figure 30. Figure 31.

Bipolar Spectral Response Bipolar Spectral Response

with 20 kHz Sine Wave Input with 30 kHz Sine Wave Input

Figure 32. Figure 33.

Bipolar Spectral Response Bipolar Spectral Response

with 40 kHz Sine Wave Input with 50 kHz Sine Wave Input

Figure 34. Figure 35.

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Typical Dynamic Performance Characteristics (continued)

The following curves apply for 12-bit + sign mode after Auto Calibration unless otherwise specified.

Bipolar Spurious Free Unipolar Signal-to-Noise Ratio

Dynamic Range vs. Input Frequency

Figure 36. Figure 37.

Unipolar Signal-to-Noise Unipolar Signal-to-Noise

+ Distortion Ratio + Distortion Ratio

vs. Input Frequency vs. Input Signal Level

Figure 38. Figure 39.

Unipolar Spectral Response Unipolar Spectral Response

with 1 kHz Sine Wave Input with 10 kHz Sine Wave Input

Figure 40. Figure 41.

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Typical Dynamic Performance Characteristics (continued)

The following curves apply for 12-bit + sign mode after Auto Calibration unless otherwise specified.

Unipolar Spectral Response Unipolar Spectral Response

with 20 kHz Sine Wave Input with 30 kHz Sine Wave Input

Figure 42. Figure 43.

Unipolar Spectral Response Unipolar Spectral Response

with 40 kHz Sine Wave Input with 50 kHz Sine Wave Input

Figure 44. Figure 45.

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Test Circuits

Figure 46. DO “TRI-STATE” (t1H, t0H) Figure 47. DO except “TRI-STATE”

Figure 48. Leakage Current

Timing Diagrams

Figure 49. DO Falling and Rising Edge

Figure 50.

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SCLK

tACC

tSD

tHDO tDDO

2.4V2.4V 2.4V

0.4V

tSET-UP

tCD

0 1 2 3 4 n

DOR

EOC

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Figure 51. DI Data Input Timing

Figure 52. DO Data Output Timing Using CS

Figure 53. DO Data Output Timing with CS Continuously Low

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Note: DO output data is not valid during this cycle.

Figure 54. ADC12138 Auto Cal or Auto Zero

Figure 55. ADC12138 Read Data without Starting a Conversion Using CS

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Figure 56. ADC12138 Read Data without Starting a Conversion with CS Continuously Low

Figure 57. ADC12138 Conversion Using CS with 16-Bit Digital Output Format

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Figure 58. ADC12138 Conversion with CS Continuously Low and 16-Bit Digital Output Format

Figure 59. ADC12138 Software Power Up/Down Using CS with 16-Bit Digital Output Format

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Figure 60. ADC12138 Software Power Up/Down with CS Continuously Low and 16-Bit Digital Output

Format

Note: Hardware power up/down may occur at any time. If PD is high while a conversion is in progress that conversion

will be corrupted and erroneous data will be stored in the output shift register.

Figure 61. ADC12138 Hardware Power Up/Down

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ADC

VA+

+5.0V

VD+

VREF+

VREF-

+4.096V

DGNDAGND

ANALOG INPUT VOLTAGE

GROUND REFERENCE

ANALOG

INPUT

VOLTAGE

ASSIGNED

(+) INPUT

ANALOG

INPUT

VOLTAGE ASSIGNED

(-) INPUT

0.01 uF **

0.1 uF 10 uF *

0.01 uF **

0.1 uF 10 uF *

0.01 uF **

0.1 uF 10 uF *

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Figure 62. ADC12138 Configuration Modification—Example of a Status Read

*Tantalum

**Monolithic Ceramic or better

Figure 63. Recommended Power Supply Bypassing and Grounding

Figure 64. Protecting the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 Analog Pins

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Format and Set-Up Tables

Table 1. Data Out Formats(1)

DB DB DB DB DB DB DB

DO Formats DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 10 11 12 13 14 15 16

17 X X X X Sign MSB 10 9 8 7 6 5 4 3 2 1 LSB

Bits

MSB

First 13 Sing MSB 10 9 8 7 6 5 4 3 2 1 LSB

Bits

with

Sign 17 LSB 1 2 3 4 5 6 7 8 9 10 MSB Sign X X X X

Bits

LSB

First 13 LSB 1 2 3 4 5 6 7 8 9 10 MSB Sign

Bits

16 0000MSB10987654321LSB

Bits

MSB

First 12 MSB 10 9 8 7 6 5 4 3 2 1 LSB

with- Bits

out 16

Sign LSB12345678910MSB0000

Bits

LSB

First 12 LSB 1 2 3 4 5 6 7 8 9 10 MSB

Bits

(1) X = High or Low state.

Table 2. ADC12138 Multiplexer Addressing

Analog Channel Addressed and Assignment ADC Input Multiplexer Output

MUX Address with A/DIN1 tied to MUXOUT1 and A/DIN2 tied Polarity Channel Assignment

to MUXOUT2 Assignment Mode

CH CH CH CH CH CH CH CH

DI0 DI1 DI2 DI3 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2

0 1 2 3 4 5 6 7

LLLL+−+−CH0 CH1

L L L H + −+−CH2 CH3

L L H L + −+−CH4 CH5

L L H H + −+−CH6 CH7 Differential

L H L L −+−+ CH0 CH1

L H L H −+−+ CH2 CH3

L H H L −+−+ CH4 CH5

L H H H −+−+ CH6 CH7

H L L L + −+−CH0 COM

H L L H + −+−CH2 COM

H L H L + −+−CH4 COM

H L H H + −+−CH6 COM Single-Ended

H H L L + −+−CH1 COM

H H L H + −+−CH3 COM

H H H L + −+−CH5 COM

H H H H + −+−CH7 COM

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Table 3. ADC12130 and ADC12132 Multiplexer Addressing(1)

Analog Channel Addressed and Assignment ADC Input Polarity Multiplexer Output Channel

MUX Address with A/DIN1 tied to MUXOUT1 and A/DIN2 tied Assignment Assignment Mode

to MUXOUT2

DI0 DI1 CH0 CH1 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2

L L + −+−CH0 CH1 Differential

L H −+−+ CH0 CH1

H L + −+−CH0 COM Single-Ended

H H + −+−CH1 COM

(1) ADC12130 do not have A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 pins.

Table 4. Mode Programming(1)

ADC12138 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DO Format

Mode Selected

ADC12130 (next Conversion

(Current)

and DI0 DI1 DI2 DI3 DI4 DI5 Cycle)

ADC12132

See Table 2 or Table 3 L L L L 12 Bit Conversion 12 or 13 Bit MSB First

See Table 2 or Table 3 L L L H 12 Bit Conversion 16 or 17 Bit MSB First

See Table 2 or Table 3 L H L L 12 Bit Conversion 12 or 13 Bit LSB First

See Table 2 or Table 3 L H L H 12 Bit Conversion 16 or 17 Bit LSB First

L L L L H L L L Auto Cal No Change

L L L L H L L H Auto Zero No Change

L L L L H L H L Power Up No Change

L L L L H L H H Power Down No Change

L L L L H H L L Read Status Register No Change

L L L L H H L H Data Out without Sign No Change

H L L L H H L H Data Out with Sign No Change

L L L L H H H L Acquisition Time—6 CCLK Cycles No Change

L H L L H H H L Acquisition Time—10 CCLK Cycles No Change

H L L L H H H L Acquisition Time—18 CCLK Cycles No Change

H H L L H H H L Acquisition Time—34 CCLK Cycles No Change

L L L L H H H H User Mode No Change

Test Mode

H X X X H H H H No Change

(CH1–CH7 become Active Outputs)

(1) The ADC powers up with no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12-bit + sign conversion, power up, 12- or 13-bit MSB

First, and user mode.

X = Don't Care

Table 5. Conversion/Read Data Only Mode Programming(1)

CS CONV PD Mode

L L L See Table 4 for Mode

L H L Read Only (Previous DO Format). No Conversion.

H X L Idle

X X H Power Down

(1) X = Don't Care

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Table 6. Status Register

Status Bit DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8

Location

Status Bit PU PD Cal 12 or 13 16 or 17 Sign Justification Test Mode

Device Status DO Output Format Status

Function “High” “High” “High” Not used “High” “High” “High” When “High” When

indicates a indicates a indicates an indicates a indicates a indicates the conversion “High” the

Power Up Power Auto Cal 12 or 13 bit 16 or 17 bit that the result will be device is in

Sequence Down Sequence format format sign bit is output MSB test mode.

is in Sequence is in included. first. When When

progress is in progress When “Low” the “Low” the

progress “Low” the result will be device is in

sign bit is output LSB user mode.

not first.

included.

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APPLICATION INFORMATION

NOTE: Some of the device/package combinations are obsolete and are shown and described here for

reference only. Please see the TI web site for availability.

1.0 DIGITAL INTERFACE

1.1 Interface Concepts

The example in Figure 65 shows a typical sequence of events after the power is applied to the ADC12130/2/8:

Figure 65. Typical Power Supply Power Up Sequence

The first instruction input to the ADC via DI initiates Auto Cal. The data output on DO at that time is meaningless

and is completely random. To determine whether the Auto Cal has been completed, a read status instruction

should be issued to the ADC. Again the data output at that time has no significance since the Auto Cal procedure

modifies the data in the output shift register. To retrieve the status information, an additional read status

instruction should be issued to the ADC. At this time the status data is available on DO. If the Cal signal in the

status word is low, Auto Cal has been completed. Therefore, the next instruction issued can start a conversion.

The data output at this time is again status information.

To keep noise from corrupting the conversion, status can not be read during a conversion. If CS is strobed and is

brought low during a conversion, that conversion is prematurely ended. EOC can be used to determine the end

of a conversion or the ADC controller can keep track in software of when it would be appropriate to communicate

to the ADC again. Once it has been determined that the ADC has completed a conversion, another instruction

can be transmitted to the ADC. The data from this conversion can be accessed when the next instruction is

issued to the ADC.

Note, when CS is low continuously it is important to transmit the exact number of SCLK cycles, as shown in the

timing diagrams. Not doing so will desynchronize the serial communication to the ADC. (See 1.3 CS Low

Continuously Considerations.)

1.2 Changing Configuration

The configuration of the ADC12130/2/8 on power up defaults to 12-bit plus sign resolution, 12- or 13-bit MSB

First, 10 CCLK acquisition time, user mode, no Auto Cal, no Auto Zero, and power up mode. Changing the

acquisition time and turning the sign bit on and off requires an 8-bit instruction to be issued to the ADC. This

instruction will not start a conversion. The instructions that select a multiplexer address and format the output

data do start a conversion. Figure 66 describes an example of changing the configuration of the ADC12130/2/8.

During I/O sequence 1, the instruction at DI configures the ADC to do a conversion with 12-bit +sign resolution.

Notice that, when the 6 CCLK Acquisition and Data Out without Sign instructions are issued to the ADC, I/O

sequences 2 and 3, a new conversion is not started. The data output during these instructions is from conversion

N, which was started during I/O sequence 1. The Figure 62 describes in detail the sequence of events necessary

for a Data Out without Sign, Data Out with Sign, or 6/10/18/34 CCLK Acquisition time mode selection. Table 4

describes the actual data necessary to be loaded into the ADC to accomplish this configuration modification. The

next instruction, shown in Figure 66, issued to the ADC starts conversion N+1 with 16-bit format and 12 bits of

resolution formatted MSB first. Again the data output during this I/O cycle is the data from conversion N.

The number of SCLKs applied to the ADC during any conversion I/O sequence should vary in accord with the

data out word format chosen during the previous conversion I/O sequence. The various formats and resolutions

available are shown in Table 1.InFigure 66, since 16-bit without sign MSB first format was chosen during I/O

sequence 4, the number of SCLKs required during I/O sequence 5 is sixteen. In the following I/O sequence the

format changes to 12-bit without sign MSB first; therefore the number of SCLKs required during I/O sequence 6

changes accordingly to 12.

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1.3 CS Low Continuously Considerations

When CS is continuously low, it is important to transmit the exact number of SCLK pulses that the ADC expects.

Not doing so will desynchronize the serial communications to the ADC. When the supply power is first applied to

the ADC, it will expect to see 13 SCLK pulses for each I/O transmission. The number of SCLK pulses that the

ADC expects to see is the same as the digital output word length. The digital output word length is controlled by

the Data Out (DO) format. The DO format maybe changed any time a conversion is started or when the sign bit

is turned on or off. The table below details out the number of clock periods required for different DO formats:

DO Format Number of SCLKs Expected

SIGN OFF 12

12-Bit MSB or LSB First SIGN ON 13

SIGN OFF 16

16-Bit MSB or LSB first SIGN ON 17

If erroneous SCLK pulses desynchronize the communications, the simplest way to recover is by cycling the

power supply to the device. Not being able to easily resynchronize the device is a shortcoming of leaving CS low

continuously.

The number of clock pulses required for an I/O exchange may be different for the case when CS is left low

continuously vs. the case when CS is cycled. Take the I/O sequence detailed in Figure 65 as an example. The

table below lists the number of SCLK pulses required for each instruction:

Instruction CS Low Continuously CS Strobed

Auto Cal 13 SCLKs 8 SCLKs

Read Status 13 SCLKs 8 SCLKs

12-Bit + Sign Conv 1 13 SCLKs 8 SCLKs

12-Bit + Sign Conv 2 13 SCLKs 13 SCLKs

1.4 Analog Input Channel Selection

The data input at DI also selects the channel configuration (see Table 2,Table 3, and Table 4). In Figure 66 the

only times when the channel configuration could be modified would be during I/O sequences 1, 4, 5 and 6. Input

channels are reselected before the start of each new conversion. Shown below is the data bit stream required at

DI during I/O sequence number 4 in Figure 66 to set CH1 as the positive input and CH0 as the negative input for

the different ADC versions.

Part DI Data(1)

Number DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7

ADC12130andADC12132 L H L L H L X X

ADC12138 L H L L L L H L

(1) X can be a logic high (H) or low (L).

1.5 Power Up/Down

The ADC may be powered down by taking the PD pin HIGH or by the instruction input at DI (see Table 4,

Table 5,Figure 59,Figure 60, and Figure 61). When the ADC is powered down in this way, the ADC conversion

circuitry is deactivated but the digital I/O circuitry is kept active.

Hardware power up/down is controlled by the state of the PD pin. Software power-up/down is controlled by the

instruction issued to the ADC. If a software power up instruction is issued to the ADC while a hardware power

down is in effect (PD pin high) the device will remain in the power-down state. If a software power down

instruction is issued to the ADC while a hardware power up is in effect (PD pin low), the device will power down.

When the device is powered down by software, it may be powered up by either issuing a software power up

instruction or by taking PD pin high and then low. If the power down command is issued during a conversion, that

conversion is interrupted, so the data output after power up cannot be relied upon.

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Figure 66. Changing the ADC's Conversion Configuration

1.6 User Mode and Test Mode

An instruction may be issued to the ADC to put it into test mode, which is used by the manufacturer to verify

complete functionality of the device. During test mode CH0–CH7 become active outputs. If the device is

inadvertently put into the test mode with CS continuously low, the serial communications may be

desynchronized. Synchronization may be regained by cycling the power supply voltage to the device. Cycling the

power supply voltage will also set the device into user mode. If CS is used in the serial interface, the ADC may

be queried to see what mode it is in. This is done by issuing a “read STATUS register” instruction to the ADC.

When bit 9 of the status register is high, the ADC is in test mode; when bit 9 is low the ADC, is in user mode. As

an alternative to cycling the power supply, an instruction sequence may be used to return the device to user

mode. This instruction sequence must be issued to the ADC using CS. The following table lists the instructions

required to return the device to user mode. Note that this entire sequence, including both Test Mode and User

Mode values, should be sent to recover from the test mode.

DI Data(1)

Instruction DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7

TEST MODE H X X X H H H H

Reset L L L L H H H L

Test Mode L L L L H L H L

Instructions L L L L H L H H

USER MODE L L L L H H H H

Power Up L L L L H L H L

Set DO with or without Sign H or L L L L H H L H

Set Acquisition Time H or L H or L L L H H H L

Start a Conversion H or L H or L H or L H or L L H or L H or L H or L

(1) X = Don't Care

The power up, data with or without sign, and acquisition time instructions should be resent after returning to the

user mode. This is to ensure that the ADC is in the required state before a conversion is started.

1.7 Reading the Data Without Starting a Conversion

The data from a particular conversion may be accessed without starting a new conversion by ensuring that the

CONV line is taken high during the I/O sequence. See Figure 55 and Figure 56.Table 5 describes the operation

of the CONV pin. It is not necessary to read the data as soon as DOR goes low. The data will remain in the

output register ifCS is brought high right after DOR goes high. A single conversion may be read as many times

as desired before CS is brought low.

1.8 Brown Out Conditions

When the supply voltage dips below about 2.7V, the internal registers, including the calibration coefficients and

all of the other registers, may lose their contents. When this happens the ADC will not perform as expected or

not at all after power is fully restored. While writing the desired information to all registers and performing a

calibration might sometimes cause recovery to full operation, the only sure recovery method is to reduce the

supply voltage to below 0.5V, then reprogram the ADC and perform a calibration after power is fully restored.

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2.0 THE ANALOG MULTIPLEXER

For the ADC12138, the analog input multiplexer can be configured with 4 differential channels or 8 single ended

channels with the COM input as the zero reference or any combination thereof (see Figure 67). The difference

between the voltages at the VREF+and VREF−pins determines the input voltage span (VREF). The analog input

voltage range is 0 to VA+. Negative digital output codes result when VIN−> VIN+. The actual voltage at VIN−or VIN+

cannot go below AGND. 8 Single-Ended Channels

4 Differential with COM

Channels as Zero Reference

Figure 67. Input Multiplexer Options

Differential Single-Ended

Configuration Configuration

A/DIN1 and A/DIN2 can be assigned as the + or −input

A/DIN1 is + input

A/DIN2 is −input

Figure 68. MUXOUT connections for multiplexer option

CH0, CH2, CH4, and CH6 can be assigned to the MUXOUT1 pin in the differential configuration, while CH1,

CH3, CH5, and CH7 can be assigned to the MUXOUT2 pin. In the differential configuration, the analog inputs

are paired as follows: CH0 with CH1, CH2 with CH3, CH4 with CH5 and CH6 with CH7. The A/DIN1 and A/DIN2

pins can be assigned positive or negative polarity.

With the single-ended multiplexer configuration, CH0 through CH7 can be assigned to the MUXOUT1 pin. The

COM pin is always assigned to the MUXOUT2 pin. A/DIN1 is assigned as the positive input; A/DIN2 is assigned

as the negative input. (See Figure 68).

The Multiplexer assignment tables for these ADCs (Table 2 and Table 3) summarize the aforementioned

functions for the different versions of ADCs.

2.1 Biasing for Various Multiplexer Configurations

Figure 69 is an example of device connections for single-ended operation. The sign bit is always low. The digital

output range is 0 0000 0000 0000 to 0 1111 1111 1111. One LSB is equal to 1 mV (4.1V/4096 LSBs).

Product Folder Links: ADC12130 ADC12132 ADC12138

ADC1213X

VA+

LM4040-2.5

(LM4041-1.2)

430:

+5.0V

(+3.3V)

VD+

VREF+

VREF-

+2.5V

(+1.25V)

DGNDAGND

ANALOG INPUT VOLTAGE

GROUND REFERENCE

CH0

CH1

CH2

CH7

COM

ANALOG INPUT

VOLTAGE RANGE

0V to 5V

(0V to 2.5V)

12-BITS SIGNED ASSIGNED

(+) INPUT

ASSIGNED

(-) INPUT

600:R1

(DEPENDS UPON

ACQUISITION TIME)

0.01 uF 0.1 uF 10 uF

ADC1213X

VA+0.01 uF 0.1 uF 10 uF

LM4040-4.1

(LM4040-2.5)

+5.0V

(+3.3V)

VD+

VREF+

VREF-

+2.048V

(+2.5)

DGNDAGND

ANALOG INPUT VOLTAGE

GROUND REFERENCE

CH0

CH1

CH2

CH7

COM

ASSIGNED

(+) INPUT

ASSIGNED

(-) INPUT

ANALOG INPUT

VOLTAGE RANGE

0 TO 4.096V

(0V TO 2.5V)

12-BITS UNSIGNED 0.01 uF 0.1 uF 10 uF

0.01 uF 0.1 uF 10 uF

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Figure 69. Single-Ended Biasing

For pseudo-differential signed operation, the circuit of Figure 70 shows a signal AC coupled to the ADC. This

gives a digital output range of −4096 to +4095. With a 2.5V reference, 1 LSB is equal to 610 μV. Although the

ADC is not production tested with a 2.5V reference, when VA+and VD+are +5.0V, linearity error typically will not

change more than 0.1 LSB (see the curves in Typical Performance Characteristics). With the ADC set to an

acquisition time of 10 clock periods, the input biasing resistor needs to be 600Ωor less. Notice though that the

input coupling capacitor needs to be made fairly large to bring down the high pass corner. Increasing the

acquisition time to 34 clock periods (with a 5 MHz CCLK frequency) would allow the 600Ωto increase to 6k,

which would set the high pass corner at 26 Hz. Increasing R, to 6k would allow R2to be 2k with a 1 μF coupling

capacitor.

Figure 70. Pseudo-Differential Biasing with the Signal Source AC Coupled Directly into the ADC

An alternative method for biasing pseudo-differential operation is to use the +2.5V from the LM4040 to bias any

amplifier circuits driving the ADC as shown in Figure 71. The value of the resistor pull-up biasing the LM4040-2.5

will depend upon the current required by the op amp biasing circuitry.

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ADC1213X

VA+

LM4041-ADJ

+5.0V

VD+

VREF+

VREF-

+2.048V

DGNDAGND

ANALOG INPUT VOLTAGE

GROUND REFERENCE

CH0

CH1

CH2

CH7

COM

ASSIGNED

(+) INPUT

ASSIGNED

(-) INPUT

+5.0V

ANALOG

INPUT

VOLTAGE

ANALOG INPUT

VOLTAGE RANGE

2.5V +/- 2.048V

12-BITS SIGNED

LM4040-2.5

1M 1k

0.01 uF 0.1 uF 10 uF

ADC1213X

VA+

LM4040-2.5

(LM4041-1.2)

+5.0V

(+3.3V)

VD+

VREF+

VREF-

+2.5V

(+1.25V)

DGNDAGND

ANALOG INPUT VOLTAGE

GROUND REFERENCE

CH0

CH1

CH2

CH7

COM

ASSIGNED

(+) INPUT

ASSIGNED

(-) INPUT

ANALOG

INPUT

VOLTAGE

ANALOG INPUT

VOLTAGE RANGE

0V to 5V

(0V to 2.5V)

12-BITS SIGNED

0.01 uF 0.1 uF 10 uF

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In the circuit of Figure 71, some voltage range is lost since the amplifier will not be able to swing to +5V and

GND with a single +5V supply. Using an adjustable version of the LM4041 to set the full scale voltage at exactly

2.048V and a lower grade LM4040D-2.5 to bias up everything to 2.5V as shown in Figure 72 will allow the use of

all the ADC's digital output range of −4096 to +4095 while leaving plenty of head room for the amplifier.

Fully differential operation is shown in Figure 73. One LSB for this case is equal to (4.1V/4096) = 1 mV.

Figure 71. Alternative Pseudo-Differential Biasing

Figure 72. Pseudo-Differential Biasing without the Loss of Digital Output Range

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ADC1213X

VA+

LM4040-4.1

(LM4040-2.5)

+5.0V

(+3.3V)

VD+

VREF+

VREF-

+4.1V

(+2.5V)

DGNDAGND

ANALOG INPUT VOLTAGE

GROUND REFERENCE

CH0

CH2

CH4

CH6

CH1

CH3

CH4

CH7

ANALOG INPUT VOLTAGE RANGE

0.45V to 4.55V

(0.4V to 2.9V) ASSIGNED

(+) INPUT

ANALOG INPUT VOLTAGE RANGE

0.45V to 4.55V

(0.4V to 2.9V) ASSIGNED

(-) INPUT

FULLY DIFFERENTIAL

12-BIT PLUS SIGN

0.01 uF 0.1 uF 10 uF

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Figure 73. Fully Differential Biasing

3.0 REFERENCE VOLTAGE

The difference in the voltages applied to the VREF+and VREF−defines the analog input span (the difference

between the voltage applied between two multiplexer inputs or the voltage applied to one of the multiplexer

inputs and analog ground) over which 4095 positive and 4096 negative codes exist. The voltage sources driving

VREF+and VREF−must have very low output impedance and noise. The circuit in Figure 74 is an example of a

very stable reference appropriate for use with the device.

*Tantalum

Figure 74. Low Drift Extremely

Stable Reference Circuit

The ADC12130/2/8 can be used in either ratiometric or absolute reference applications. In ratiometric systems,

the analog input voltage is proportional to the voltage used for the ADC's reference voltage. When this voltage is

the system power supply, the VREF+pin is connected to VA+and VREF−is connected to ground. This technique

relaxes the system reference stability requirements because the analog input voltage and the ADC reference

voltage move together. This maintains the same output code for given input conditions. For absolute accuracy,

where the analog input voltage varies between very specific voltage limits, a time and temperature stable voltage

source can be connected to the reference inputs. Typically, the reference voltage magnitude will require an initial

adjustment to null reference voltage induced full-scale errors.

Below are recommended references along with some key specifications.

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Part Number Output Voltage Tolerance Temperature Coefficient

LM4041CI-Adj ±0.5% ±100ppm/°C

LM4040AI-4.1 ±0.1% ±100ppm/°C

LM4120AI-4.1 ±0.2% ±50ppm/°C

LM4121AI-4.1 ±0.2% ±50ppm/°C

LM4050AI-4.1 ±0.1% ±50ppm/°C

LM4030AI-4.1 ±0.05% ±10ppm/°C

LM4040AI-4.1 ±0.1% ±3.0ppm/°C

Circuit of Figure 74 Adjustable ±2ppm/°C

The reference voltage inputs are not fully differential. The ADC12130/2/8 will not generate correct conversions or

comparisons if VREF+is taken below VREF−. Correct conversions result when VREF+and VREF−differ by 1V or more

and remain at all times between ground and VA+. The VREF common mode range, (VREF++ VREF−)/2, is restricted

to (0.1 × VA+) to (0.6 × VA+). Therefore, with VA+= 5V, the center of the reference ladder should not go below

0.5V or above 3.0V. Figure 75 is a graphic representation of the voltage restrictions on VREF+and VREF−.

Figure 75. VREF Operating Range

4.0 ANALOG INPUT VOLTAGE RANGE

The ADC12130/2/8's fully differential ADC generate a two's complement output that is found by using the

equation shown below:

for (12-bit) resolution the Output Code =

(1)

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Round off to the nearest integer value between −4096 to 4095 if the result of the above equation is not a whole

number.

Examples are shown in the table below:

VREF+VREF−VIN+VIN−Code Output Digital

+2.5V +1V +1.5V 0V 0,1111,1111,1111

+4.096V 0V +3V 0V 0,1011,1011,1000

+4.096V 0V +2.499V +2.500V 1,1111,1111,1111

+4.096V 0V 0V +4.096V 1,0000,0000,0000

5.0 INPUT CURRENT

At the start of the acquisition window (tA) a charging current flows into or out of the analog input pins (A/DIN1 and

A/DIN2) depending upon the input voltage polarity. The analog input pins are CH0–CH7 and COM when A/DIN1

is tied to MUXOUT1 and A/DIN2 is tied to MUXOUT2. The peak value of this input current will depend upon the

actual input voltage applied, the source impedance and the internal multiplexer switch on resistance. With

MUXOUT1 tied to A/DIN1 and MUXOUT2 tied to A/DIN2 the internal multiplexer switch on resistance is typically

1.6 kΩ. The A/DIN1 and A/DIN2 mux on resistance is typically 750Ω.

6.0 INPUT SOURCE RESISTANCE

For low impedance voltage sources (<600Ω), the input charging current will decay, before the end of the S/H's

acquisition time of 2 μs (10 CCLK periods with fCK = 5 MHz), to a value that will not introduce any conversion

errors. For high source impedances, the S/H's acquisition time can be increased to 18 or 34 CCLK periods. For

less ADC accuracy and/or slower CCLK frequencies the S/H's acquisition time may be decreased to 6 CCLK

periods. To determine the number of clock periods (Nc) required for the acquisition time with a specific source

impedance for the various resolutions the following equations can be used:

12 Bit + Sign NC= [RS+ 2.3] × fCK × 0.824

Where fCK is the conversion clock (CCLK) frequency in MHz and RSis the external source resistance in kΩ. As

an example, operating with a resolution of 12 Bits + sign, a 5 MHz clock frequency and maximum acquisition

time of 34 conversion clock periods the ADC's analog inputs can handle a source impedance as high as 6 kΩ.

The acquisition time may also be extended to compensate for the settling or response time of external circuitry

connected between the MUXOUT and A/DIN pins.

An acquisition starts at a falling edge of SCLK and ends at a rising edge of CCLK (see timing diagrams). If SCLK

and CCLK are asynchronous, one extra CCLK clock period may be inserted into the programmed acquisition

time for synchronization. Therefore, with asynchronous SCLK and CCLK, the acquisition time will change from

conversion to conversion.

7.0 INPUT BYPASS CAPACITANCE

External capacitors (0.01 μF–0.1 μF) can be connected between the analog input pins, CH0–CH7, and analog

ground to filter any noise caused by inductive pickup associated with long input leads. These capacitors will not

degrade the conversion accuracy.

8.0 NOISE

The leads to each of the analog multiplexer input pins should be kept as short as possible. This will minimize

input noise and clock frequency coupling that can cause conversion errors. Input filtering can be used to reduce

the effects of the noise sources.

9.0 POWER SUPPLIES

Noise spikes on the VA+and VD+supply lines can cause conversion errors; the comparator will respond to the

noise. The ADC is especially sensitive to any power supply spikes that occur during the Auto Zero or linearity

correction. The minimum power supply bypassing capacitors recommended are low inductance tantalum

capacitors of 10 μF or greater paralleled with 0.1 μF monolithic ceramic capacitors. More or different bypassing

may be necessary depending upon the overall system requirements. Separate bypass capacitors should be used

for the VA+and VD+supplies and placed as close as possible to these pins.

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10.0 GROUNDING

The ADC12130/2/8's performance can be maximized through proper grounding techniques. These include the

use of separate analog and digital areas of the board with analog and digital components and traces located only

in their respective areas. Bypass capacitors of 0.01 µF and 0.1 µF surface mount capacitors and a 10 µF are

recommended at each of the power supply pins for best performance. These capacitors should be located as

close to the bypassed pin as practical, especially the smaller value capacitors.

11.0 CLOCK SIGNAL LINE ISOLATION

The ADC12130/2/8's performance is optimized by routing the analog input/output and reference signal

conductors as far as possible from the conductors that carry the clock signals to the CCLK and SCLK pins.

Maintaining a separation of at least 7 to 10 times the height of the clock trace above its reference plane is

recommended.

12.0 THE CALIBRATION CYCLE

A calibration cycle needs to be started after the power supplies, reference, and clock have been given enough

time to stabilize after initial turn-on. During the calibration cycle, correction values are determined for the offset

voltage of the sampled data comparator and any linearity and gain errors. These values are stored in internal

RAM and used during an analog-to-digital conversion to bring the overall full-scale, offset, and linearity errors

down to the specified limits. Full-scale error typically changes ±0.4 LSB over temperature and linearity error

changes even less; therefore, it should be necessary to go through the calibration cycle only once after power up

if the Power Supply Voltage and the ambient temperature do not change significantly (see the curves in the

Typical Performance Characteristics).

13.0 THE Auto Zero CYCLE

To correct for any change in the zero (offset) error of the ADC, the Auto Zero cycle can be used. It may be

desirable to do an Auto Zero cycle whenever the ambient temperature or the power supply voltage change

significantly. (See the curves, Figure 17 and Figure 19, in the Typical Performance Characteristics.)

14.0 DYNAMIC PERFORMANCE

Many applications require the converter to digitize AC signals, but the standard DC integral and differential

nonlinearity specifications will not accurately predict the converter's performance with AC input signals. The

important specifications for AC applications reflect the converter's ability to digitize AC signals without significant

spectral errors and without adding noise to the digitized signal. Dynamic characteristics such as signal-to-noise

(S/N), signal-to-noise + distortion ratio or S/(N + D), effective bits, full power bandwidth, aperture time and

aperture jitter are quantitative measures of the converter's capability.

An ADC's AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal

waveform is applied to the ADC's input, and the transform is then performed on the digitized waveform. S/(N + D)

and S/N are calculated from the resulting FFT data, and a spectral plot may also be obtained. Typical values for

S/N are shown in Converter Electrical Characteristics, and spectral plots of S/(N + D) are included in Typical

Performance Characteristics.

The ADC's noise and distortion levels will change with the frequency of the input signal, with more distortion and

noise occurring at higher signal frequencies. This can be seen in the S/(N + D) versus frequency curves. These

curves will also give an indication of the full power bandwidth (the frequency at which the S/(N + D) or S/N drops

3 dB).

Effective number of bits can also be useful in describing the ADC's noise and distortion performance. An ideal

ADC will have some amount of quantization noise, determined by its resolution, and no distortion, which will yield

an optimum S/(N + D) ratio given by the following equation:

S/(N + D) = (6.02 × n + 1.76) dB

where

• "n" is the ADC's resolution in bits (2)

The effective bits of an actual ADC can be found by:

n(effective) = ENOB = (S/(N + D) - 1.76) / 6.02 (3)

Product Folder Links: ADC12130 ADC12132 ADC12138

ABC

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

MUXOUT1

A/DIN1

MUXOUT2

A/DIN2

DGND

VD+

CCLK

SCLK

EOC

AGND

VREF+

VREF-

VA+

DOR

CONV RS-232

Interface

+4.096V

+5V

D Q

CLK

7474

1/6 74HC04 1/4 DS14C89

1/4 DS14C89

1/4 DS14C88

+5V

5 MHz

DTR

RTS

CTS

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As an example, this device with a differential signed 5V, 1 kHz sine wave input signal will typically have a S/(N +

D) of 77 dB, which is equivalent to 12.5 effective bits.

15.0 AN RS232 SERIAL INTERFACE

Shown on the following page is a schematic for an RS232 interface to any IBM and compatible PCs. The DTR,

RTS, and CTS RS232 signal lines are buffered via level translators and connected to the ADC12138's DI, SCLK,

and DO pins, respectively. The D flip-flop is used to generate the CS signal.

Note: VA+, VD+, and VREF+on the ADC12138 each have 0.01 μF and 0.1 μF chip caps, and 10 μF tantalum caps. All

logic devices are bypassed with 0.1 μF caps.

Figure 76. RS232 Serial Interface Schematic

The assignment of the RS232 port is shown below

B7 B6 B5 B4 B3 B2 B1 B0

Input Address 3FE X X X CTS X X X X

COM1 Output Address 3FC X X X 0 X X RTS DTR

A sample program, written in Microsoft QuickBasic, is shown on the next page. The program prompts for data

mode select instruction to be sent to the ADC. This can be found from the Mode Programming table shown

earlier. The data should be entered in “1”s and “0”s as shown in the table with DI0 first. Next, the program

prompts for the number of SCLK cycles required for the programmed mode select instruction. For instance, to

send all “0”s to the ADC, selects CH0 as the +input, CH1 as the −input, 12-bit conversion, and 13-bit MSB first

data output format (if the sign bit was not turned off by a previous instruction). This would require 13 SCLK

periods since the output data format is 13 bits.

The ADC powers up with No Auto Cal, No Auto Zero, 10 CCLK Acquisition Time, 12-bit conversion, data out with

sign, power up, 12- or 13-bit MSB First, and user mode. Auto Cal, Auto Zero, Power Up and Power Down

instructions do not change these default settings. The following power up sequence should be followed:

1. Run the program

2. Prior to responding to the prompt apply the power to the ADC12138

3. Respond to the program prompts

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It is recommended that the first instruction issued to the ADC12138 be Auto Cal (See 1.1 Interface Concepts).

Code Listing:

'variables DOL=Data Out word length, DI=Data string for the DI input,

' DO=ADC result string

'SET CS# HIGH

OUT &H3FC, (&H2 OR INP (&H3FC) 'set RTS HIGH

OUT &H3FC, (&HFE AND INP(&H3FC) 'SET DTR LOW

OUT &H3FC, (&HFD AND INP (&H3FC) 'SET RTS LOW

OUT &H3FC, (&HEF AND INP(&H3FC)) 'set B4 low

LINE INPUT “DI data for ADC12138 (see Mode Table on data sheet)”; DI$

INPUT “ADC12138 output word length (12,13,16 or 17)”; DOL

'SET CS# HIGH

OUT &H3FC, (&H2 OR INP (&H3FC) 'set RTS HIGH

OUT &H3FC, (&HFE AND INP(&H3FC) 'SET DTR LOW

OUT &H3FC, (&HFD AND INP (&H3FC) 'SET RTS LOW

'SET CS# LOW

OUT &H3FC, (&H2 OR INP (&H3FC) 'set RTS HIGH

OUT &H3FC, (&H1 OR INP(&H3FC) 'SET DTR HIGH

OUT &H3FC, (&HFD AND INP (&H3FC) 'SET RTS LOW

DO$=“ ” 'reset DO variable

OUT &H3FC, (&H1 OR INP(&H3FC) 'SET DTR HIGH

OUT &H3FC, (&HFD AND INP(&H3FC)) 'SCLK low

FORN=1TO8

Temp$ = MID$(DI$, N, 1)

IF Temp$=“0” THEN

OUT &H3FC, (&H1 OR INP(&H3FC))

ELSE OUT &H3FC, (&HFE AND INP(&H3FC))

END IF 'out DI

OUT &H3FC, (&H2 OR INP(&H3FC)) 'SCLK high

IF (INP(&H3FE) AND 16) = 16 THEN

DO$ = DO$ + “0”

ELSE

DO$ = DO$ + “1”

END IF 'Input DO

OUT &H3FC, (&H1 OR INP(&H3FC) 'SET DTR HIGH

OUT &H3FC, (&HFD AND INP(&H3FC)) 'SCLK low

NEXT N

IF DOL > 8 THEN

FOR N=9 TO DOL

OUT &H3FC, (&H1 OR INP(&H3FC) 'SET DTR HIGH

OUT &H3FC, (&HFD AND INP(&H3FC)) 'SCLK low

OUT &H3FC, (&H2 OR INP(&H3FC)) 'SCLK high

IF (INP(&H3FE) AND &H1O) = &H1O THEN

DO$ = DO$ + “0”

ELSEDO$ = DO$ + “1”

END IF

NEXT N

END IF

OUT &H3FC, (&HFA AND INP(&H3FC)) 'SCLK low and DI high

FOR N = 1 TO 500

NEXT N

PRINT DO$

INPUT “Enter “C” to convert else “RETURN” to alter DI data”; s$

IF s$ = “C” OR s$ = “c” THEN

GOTO 20

ELSE

GOTO 10

END IF

END

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REVISION HISTORY

Changes from Revision F (March 2013) to Revision G Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 42

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PACKAGE OPTION ADDENDUM

www.ti.com 17-Nov-2018

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ADC12130CIWM/NOPB ACTIVE SOIC DW 16 45 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC12130

CIWM

ADC12130CIWMX/NOPB ACTIVE SOIC DW 16 1000 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC12130

CIWM

ADC12138CIMSA/NOPB LIFEBUY SSOP DB 28 47 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC12138

CIMSA

ADC12138CIMSAX/NOPB LIFEBUY SSOP DB 28 2000 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC12138

CIMSA

ADC12138CIWM/NOPB LIFEBUY SOIC DW 28 26 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 ADC12138

CIWM

ADC12138CIWMX/NOPB LIFEBUY SOIC DW 28 1000 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 ADC12138

CIWM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

PACKAGE OPTION ADDENDUM

www.ti.com 17-Nov-2018

Addendum-Page 2

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADC12130CIWMX/NOPB SOIC DW 16 1000 330.0 16.4 10.9 10.7 3.2 12.0 16.0 Q1

ADC12138CIMSAX/NOPB SSOP DB 28 2000 330.0 16.4 8.4 10.7 2.4 12.0 16.0 Q1

ADC12138CIWMX/NOPB SOIC DW 28 1000 330.0 24.4 10.8 18.4 3.2 12.0 24.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADC12130CIWMX/NOPB SOIC DW 16 1000 367.0 367.0 38.0

ADC12138CIMSAX/NOPB SSOP DB 28 2000 367.0 367.0 38.0

ADC12138CIWMX/NOPB SOIC DW 28 1000 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 2

GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

DW 16 SOIC - 2.65 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

4040000-2/H

www.ti.com

PACKAGE OUTLINE

TYP

10.63

9.97

2.65 MAX

14X 1.27

16X 0.51

0.31

8.89

TYP

0.33

0.10

0 - 8 0.3

0.1

(1.4)

0.25

GAGE PLANE

1.27

0.40

NOTE 3

10.5

10.1

BNOTE 4

7.6

7.4

4220721/A 07/2016

SOIC - 2.65 mm max heightDW0016A

SOIC

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

116

0.25 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 1.500

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

(9.3)

14X (1.27)

R0.05 TYP

16X (2)

16X (0.6)

4220721/A 07/2016

SOIC - 2.65 mm max heightDW0016A

SOIC

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

OPENING

SOLDER MASK METAL

SOLDER MASK

DEFINED

LAND PATTERN EXAMPLE

SCALE:7X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

R0.05 TYP

16X (2)

16X (0.6)

14X (1.27)

(9.3)

4220721/A 07/2016

SOIC - 2.65 mm max heightDW0016A

SOIC

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:7X

SYMM

www.ti.com

PACKAGE OUTLINE

26X 0.65

8.45

28X 0.38

0.22

8.2

7.4 TYP

SEATING

PLANE

0.05 MIN

0.25

GAGE PLANE

0 -8

2 MAX

B5.6

5.0

NOTE 4

10.5

9.9

NOTE 3

0.95

0.55

(0.15) TYP

SSOP - 2 mm max heightDB0028A

SMALL OUTLINE PACKAGE

4214853/B 03/2018

14 15

0.15 C A B

PIN 1 INDEX AREA

SEE DETAIL A

0.1 C

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-150.

A 15

DETAIL A

TYPICAL

SCALE 1.500

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

28X (1.85)

28X (0.45)

26X (0.65)

(7)

(R0.05) TYP

SSOP - 2 mm max heightDB0028A

SMALL OUTLINE PACKAGE

4214853/B 03/2018

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SYMM

14 15

15.000

METAL

SOLDER MASK

OPENING METAL UNDER

SOLDER MASK SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

28X (1.85)

28X (0.45)

26X (0.65)

(7)

(R0.05) TYP

SSOP - 2 mm max heightDB0028A

SMALL OUTLINE PACKAGE

4214853/B 03/2018

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

SYMM

14 15

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