W71NW20GF3FW MULTI-CHIP PACKAGE (MCP) MEMORY 1.8V 2G-BIT (16M-WORD x 8-BIT) SLC NAND FLASH MEMORY & 1.8V 1G-BIT (256K- WORD x 8 BANK x 32-BIT) LOW POWER DDR2 (LPDDR2) SDRAM -1- Publication Release Date: June 09, 2015 Preliminary - Revision C W71NW20GF3FW Table of Contents 1 GENERAL DESCRIPTION .............................................................................................................. 3 2 FEATURES...................................................................................................................................... 3 3 BALL CONFIGURATION................................................................................................................. 4 3.1 162-Ball Description for W29N02GZ NAND Flash Memory .................................................... 5 3.2 162-Ball Description for W97AH2KK Low Power DDR2 SDRAM ........................................... 5 4 Block Diagram ................................................................................................................................. 8 5 Package Specification ..................................................................................................................... 9 5.1 VFBGA162Ball (8x10.5mm^2, Ball pitch:0.5mm, O=0.3mm) .................................................. 9 6 MCP ORDERING INFORMATION ................................................................................................ 10 7 Revision History ............................................................................................................................. 11 Table of Table Table 3-1 W29N02GZ VFBGA-162 Ball Description ............................................................................... 5 Table 3-2 W97AH2KK VFBGA-162 Ball Description .............................................................................. 7 Table 7-1 Revision History .................................................................................................................... 11 Table of Figure Figure 3-1 W71NW20GF3FW, 162 Ball VFBGA Package (Top View, balls facing down) ..................... 4 Figure 4-1 W71NW20GF3FW MCP Flash & LPDDR2 SDRAM Block Diagram ..................................... 8 Figure 5-1 162 Ball VFBGA 8x10.5mm Package .................................................................................... 9 Figure 6-1 MCP Ordering Information ................................................................................................... 10 -2- Publication Release Date: June 09, 2015 Preliminary - Revision C W71NW20GF3FW 1 GENERAL DESCRIPTION The W71NW series is a Multi-Chip Package (MCP) memory product family that consists of a 1.8V NAND Flash Memory device and a 1.8V Low Power SDRAM device in one convenient Thin VFBGA package. W71NW20GF3FW consists of: * W29N02GZ - 1.8V 2G-Bit x8-BIT NAND Flash Memory * W97AH2KK - 1.8V 1G-Bit x32-BIT Low Power DDR2 SDRAM * 162 Ball VFBGA - Dimension 8x10.5x1.0mm, ball pitch 0.50-mm, ball diameter 0.30mm 2 FEATURES W29N02GZ NAND Flash Memory * Basic Features - Density : 2Gbit (Single chip solution) - Vcc : 1.7V to 1.95V - Bus width : x8 - Operating temperature Industrial: -40C to 85C * Single-Level Cell (SLC) technology. * Organization - Density: 2G-bit/256M-byte - Page size 2,112 bytes (2048 + 64 bytes) - Block size 64 pages (128K + 4K bytes) * Highest Performance - Read performance (Max.) Random read: 25us Sequential read cycle: 25ns - Write Erase performance Page program time: 250us(typ.) Block erase time: 2ms(typ.) - Endurance 100,000 Erase/Program Cycles(2) - 10-years data retention * Command set - Standard NAND command set - Additional command support Copy Back Two-plane operation - Contact Winbond for OTP feature - Contact Winbond for block Lock feature * Lowest power consumption - Read: 25mA(typ.3V),T.B.D(typ.1.8V) - Program/Erase: 10mA(typ.1.8V) - CMOS standby: 10uA(typ.) Note: 1. W97AH2KK Low Power DDR2 SDRAM * VDD1 = 1.7~1.95V * VDD2/VDDCA/VDDQ = 1.14V ~ 1.30V * Data width: x32 * Clock rate: up to 533MHz * Four-bit prefetch DDR architecture * Eight internal banks for concurrent operation * Programmable READ and WRITE latencies (RL/WL) * Programmable burst lengths: 4, 8, or 16 * Per Bank Refresh * Partial Array Self-Refresh(PASR) * Deep Power Down Mode (DPD Mode) * Programmable output buffer driver strength * Data mask (DM) for write data * Clock Stop capability during idle periods * Double data rate for data output * Differential clock inputs * Bidirectional differential data strobe * Interface: HSUL_12 * JEDEC LPDDR2-S4B compliance * Operating Temperature Range -40 ~ 85 C Endurance specification is based on 1bit/528 byte ECC (Error Correcting Code). -3- Publication Release Date: June 09, 2015 Preliminary - Revision C W71NW20GF3FW 3 BALL CONFIGURATION 1 2 3 4 5 6 7 8 9 10 NC NC WP/ CLE VCC IO4 IO7 VCC NC NC NC VCC NC ALE RE/ IO5 NC NC GND NC NC IO1 IO3 WE/ R/B IO6 NC IO0 IO2 CE/ NC NC GND NC DNU VDD2 VDD1 DQ31 DQ29 DQ26 NC VDD1 VSS DNU VSS VSSQ VDDQ DQ25 VSSQ VDDQ VSS VDD2 ZQ VDDQ DQ30 DQ27 DQS3_t DQS3_c VSSQ VSSCA CA9 CA8 DQ28 DQ24 DM3 VDDCA CA6 CA7 VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ A B C D E F G H DQ15 VDDQ VSSQ J K VDD2 CA5VREF(CA) DQS1_c DQS1_t DQ10 DQ9 DQ8 VSSQ L VDDCA VSS CK_c VSSCA NC CK_t DM1 VDDQ M VSSQ VDDQ VDD2 VSS VREF(DQ) N CKE NC NC CS_n NC NC CA4 CA3 CA2 DM0 VDDQ P DQS0_c DQS0_t DQ5 DQ6 DQ7 VSSQ DQ2 DQ1 DQ3 VDDQ R VSSQ DQ4 T VSSCA VDDCA CA1 DQ19 DQ23 DM2 DQ0 VDDQ VSSQ U VSS VDD2 CA0 VDDQ DQ17 DQ20 DQS2_t DQS2_c VSSQ VDD1 VSS NC VSS VSSQ VDDQ DQ22 VSSQ VDDQ NC NC NC NC NC V W VDD2 VDD1 DQ16 DQ18 DQ21 NC Y LPDDR2 NAND NC NC NOT CONNECTED Figure 3-1 W71NW20GF3FW, 162 Ball VFBGA Package (Top View, balls facing down) -4- Publication Release Date: June 09, 2015 Preliminary - Revision C W71NW20GF3FW 3.1 162-Ball Description for W29N02GZ NAND Flash Memory Ball NO. BALL NAME I/O A3 WP# I Write Protect C4 WE# I Write Enable B4 ALE I Address Latch Enable A4 CLE I Command Latch Enable D4 CE# I Chip Enable B5 RE# I Read Enable C5 R/B# I Ready/#Busy D2 IO0 I/O Data Input Output 0 C2 IO1 I/O Data Input Output 1 D3 IO2 I/O Data Input Output 2 C3 IO3 I/O Data Input Output 3 A6 IO4 I/O Data Input Output 4 B6 IO5 I/O Data Input Output 5 C6 IO6 I/O Data Input Output 6 A7 IO7 I/O Data Input Output 7 B2,A5,A8 VCC Power Supply NAND E1,B9 VSSn Ground NAND E3,F3 DNU Do Not Use Multiple NC FUNCTION No Connection Table 3-1 W29N02GZ VFBGA-162 Ball Description 3.2 162-Ball Description for W97AH2KK Low Power DDR2 SDRAM BALL NO. BALL NAME I/O P1 CS_n I Chip Select N1 CKE I Clock Enable L3 CLK_c I CK_t and CK_c are differential clock inputs M3 CLK_t I CK_t and CK_c are differential clock inputs U3 CA0 I DDR Command/Address Input 9 T3 CA1 I DDR Command/Address Input R3 CA2 I DDR Command/Address Input R2 CA3 I DDR Command/Address Input R1 CA4 I DDR Command/Address Input K2 CA5 I DDR Command/Address Input FUNCTION -5- Publication Release Date: June 09, 2015 Preliminary - Revision C W71NW20GF3FW BALL NO. BALL NAME I/O J2 CA6 I DDR Command/Address Input J3 CA7 I DDR Command/Address Input H3 CA8 I DDR Command/Address Input H2 CA9 I DDR Command/Address Input N5 DM0 I Input Data Mask L5 DM1 I Input Data Mask T7 DM2 I Input Data Mask H7 DM3 I Input Data Mask P5 DQS0_c I/O Data Strobe (Bi-directional, Differential) P6 DQS0_t I/O Data Strobe (Bi-directional, Differential) K5 DQS1_c I/O Data Strobe (Bi-directional, Differential) K6 DQS1_t I/O Data Strobe (Bi-directional, Differential) U9 DQS2_c I/O Data Strobe (Bi-directional, Differential) U8 DQS2_t I/O Data Strobe (Bi-directional, Differential) G9 DQS3_c I/O Data Strobe (Bi-directional, Differential) G8 DQS3_t I/O Data Strobe (Bi-directional, Differential) T8 DQ0 I/O Data Inputs/Output R8 DQ1 I/O Data Inputs/Output R7 DQ2 I/O Data Inputs/Output R9 DQ3 I/O Data Inputs/Output R6 DQ4 I/O Data Inputs/Output P7 DQ5 I/O Data Inputs/Output P8 DQ6 I/O Data Inputs/Output P9 DQ7 I/O Data Inputs/Output K9 DQ8 I/O Data Inputs/Output K8 DQ9 I/O Data Inputs/Output K7 DQ10 I/O Data Inputs/Output J6 DQ11 I/O Data Inputs/Output J9 DQ12 I/O Data Inputs/Output J7 DQ13 I/O Data Inputs/Output J8 DQ14 I/O Data Inputs/Output H8 DQ15 I/O Data Inputs/Output W7 DQ16 I/O Data Inputs/Output U6 DQ17 I/O Data Inputs/Output W8 DQ18 I/O Data Inputs/Output T5 DQ19 I/O Data Inputs/Output FUNCTION -6- Publication Release Date: June 09, 2015 Preliminary - Revision C W71NW20GF3FW BALL NO. BALL NAME I/O U7 DQ20 I/O Data Inputs/Output W9 DQ21 I/O Data Inputs/Output V8 DQ22 I/O Data Inputs/Output T6 DQ23 I/O Data Inputs/Output H6 DQ24 I/O Data Inputs/Output F8 DQ25 I/O Data Inputs/Output E9 DQ26 I/O Data Inputs/Output G7 DQ27 I/O Data Inputs/Output H5 DQ28 I/O Data Inputs/Output E8 DQ29 I/O Data Inputs/Output G6 DQ30 I/O Data Inputs/Output E7 DQ31 I/O Data Inputs/Output G3 ZQ I/O Reference Pin for Output Drive Strength Calibration F1,V1,E6,W6 VDD1 Core Power Supply 1 K1,G2,U2,E5,W5,M7 VDD2 Core Power Supply 2 G5,U5,L6,M6,N6,F7, V7,H9,T9,F10,J10,R1 0,V10 VDDQ J1,L1,T2 VDDCA G1,U1,L2,V2,F5,F2,V 5,M8 VSS J5,M5,R5,F6,V6,F9,V 9,G10,H10,K10,P10, T10,U10 VSSQ H1,M1,T1 VSSCA K3 VREF(CA) Reference Voltage for CA Command and Control Input Receiver M9 VREF(DQ) Reference Voltage for DQ Input Receiver FUNCTION I/O Power Supply Input Receiver Power Supply Ground I/O Ground Ground for CA Input Receivers Table 3-2 W97AH2KK VFBGA-162 Ball Description -7- Publication Release Date: June 09, 2015 Preliminary - Revision C W71NW20GF3FW 4 Block Diagram Figure 4-1 W71NW20GF3FW MCP Flash & LPDDR2 SDRAM Block Diagram -8- Publication Release Date: June 09, 2015 Preliminary - Revision C W71NW20GF3FW 5 Package Specification 5.1 VFBGA162Ball (8x10.5mm^2, Ball pitch:0.5mm, O=0.3mm) Figure 5-1 162 Ball VFBGA 8x10.5mm Package -9- Publication Release Date: June 09, 2015 Preliminary - Revision C W71NW20GF3FW 6 MCP ORDERING INFORMATION W 71 NW 2 0 G F 3 F W Winbond Standard Product W: Winbond Product Family 71: MCP Product Voltage NW: 1.8V ONFI NAND Flash Product Density 2: 2Gb NAND I/O bits 0: 8 bit Flash Generation G= WEC 4X Technology Node RAM Density F= 1Gb LPDDR2 RAM Option Information 3: 4X Technology *32 Package Type F: 162 Balls VFBGA Grade & Temperature W: Industrial: -40C to +85C Figure 6-1 MCP Ordering Information - 10 - Publication Release Date: June 09, 2015 Preliminary - Revision C W71NW20GF3FW 7 Revision History VERSION DATE A 07/15/2014 B 11/26/2014 3 Corrected W29N02GZ BUS Width to x8 06/09/2015 3 10 N/A Added new W29N02GZ description Temperature Grade Correction Added updated W29N02GZ Datasheet C PAGE DESCRIPTION New Create Preliminary Table 7-1 Revision History Preliminary Designation The "Preliminary" designation on a Winbond datasheet indicates that the product is not fully characterized. The specifications are subject to change and are not guaranteed. Winbond or an authorized sales representative should be consulted for current information before using this product. Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 11 - Publication Release Date: June 09, 2015 Preliminary - Revision C W29N02GW/Z W29N02GW/Z 2G-BIT 1.8V NAND FLASH MEMORY 1 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z Table of Contents 1. GENERAL DESCRIPTION ............................................................................................................... 7 2. FEATURES ....................................................................................................................................... 7 3. PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 8 3.1 Pin Descriptions .................................................................................................................... 8 4. PIN DESCRITPIONS ........................................................................................................................ 9 4.1 Chip Enable (#CE)................................................................................................................ 9 4.2 Write Enable (#WE) .............................................................................................................. 9 4.3 Read Enable (#RE) .............................................................................................................. 9 4.4 Address Latch Enable (ALE) ................................................................................................ 9 4.5 Command Latch Enable (CLE) ............................................................................................ 9 4.6 Write Protect (#WP).............................................................................................................. 9 4.7 Ready/Busy (RY/#BY) .......................................................................................................... 9 4.8 Input and Output (I/Ox) ......................................................................................................... 9 5. BLOCK DIAGRAM .......................................................................................................................... 10 6. MEMORY ARRAY ORGANIZATION .............................................................................................. 11 6.1 Array Organization (x8) ...................................................................................................... 11 6.2 Array Organization (x16) .................................................................................................... 12 7. MODE SELECTION TABLE ........................................................................................................... 13 8. COMMAND TABLE......................................................................................................................... 14 9. DEVICE OPERATIONS .................................................................................................................. 15 9.1 READ operation .................................................................................................................. 15 9.2 9.3 9.4 9.1.1 PAGE READ (00h-30h) ........................................................................................................ 15 9.1.2 TWO PLANE READ (00h-00h-30h) ...................................................................................... 15 9.1.3 RANDOM DATA OUTPUT (05h-E0h) ................................................................................... 17 9.1.4 READ ID (90h) ...................................................................................................................... 18 9.1.5 READ PARAMETER PAGE (ECh) ....................................................................................... 19 9.1.6 READ STATUS (70h) ........................................................................................................... 21 9.1.7 READ STATUS ENHANCED (78h) ...................................................................................... 22 9.1.8 READ UNIQUE ID (EDh) ...................................................................................................... 24 PROGRAM operation ......................................................................................................... 25 9.2.1 PAGE PROGRAM (80h-10h) ................................................................................................ 25 9.2.2 SERIAL DATA INPUT (80h) ................................................................................................. 25 9.2.3 RANDOM DATA INPUT (85h) .............................................................................................. 26 9.2.4 TWO PLANE PAGE PROGRAM .......................................................................................... 26 COPY BACK operation....................................................................................................... 28 9.3.1 READ for COPY BACK (00h-35h) ........................................................................................ 28 9.3.2 PROGRAM for COPY BACK (85h-10h) ................................................................................ 28 9.3.3 TWO PLANE READ for COPY BACK ................................................................................... 29 9.3.4 TWO PLANE PROGRAM for COPY BACK .......................................................................... 29 BLOCK ERASE operation .................................................................................................. 33 9.4.1 BLOCK ERASE (60h-D0h) ................................................................................................... 33 9.4.2 TWO PLANE BLOCK ERASE .................................................................................................. 34 9.5 RESET operation................................................................................................................ 35 Release Date: May 19, 2015 2 Preliminary - Revision 0.3 W29N02GW/Z 9.5.1 9.6 9.7 9.8 9.9 RESET (FFh) ........................................................................................................................ 35 FEATURE OPERATION..................................................................................................... 36 9.6.1 GET FEATURES (EEh) ........................................................................................................ 39 9.6.2 SET FEATURES (EFh) ......................................................................................................... 40 ONE TIME PROGRAMMABLE (OTP) area ....................................................................... 41 WRITE PROTECT .............................................................................................................. 42 BLOCK LOCK ..................................................................................................................... 44 10. ELECTRICAL CHARACTERISTICS............................................................................................... 45 10.1 Absolute Maximum Ratings (1.8V) ..................................................................................... 45 10.2 Operating Ranges (1.8V) ................................................................................................... 45 10.3 Device power-up timing ...................................................................................................... 46 10.4 DC Electrical Characteristics (1.8V) ................................................................................... 47 10.5 AC Measurement Conditions (1.8V) ................................................................................... 48 10.6 AC timing characteristics for Command, Address and Data Input (1.8V) .......................... 49 10.7 AC timing characteristics for Operation (1.8V) ................................................................... 50 10.8 Program and Erase Characteristics ................................................................................... 51 11. TIMING DIAGRAMS ....................................................................................................................... 52 12. INVALID BLOCK MANAGEMENT .................................................................................................. 61 12.1 Invalid blocks ...................................................................................................................... 61 12.2 Initial invalid blocks ............................................................................................................. 61 12.3 Error in operation ................................................................................................................ 62 12.4 Addressing in program operation ....................................................................................... 63 13. REVISION HISTORY ...................................................................................................................... 64 3 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z List of Tables Table 3-1 Pin Descriptions ............................................................................................................................ 8 Table 6-1 Addressing .................................................................................................................................. 11 Table 6-2 Addressing .................................................................................................................................. 12 Table 7-1 Mode Selection ........................................................................................................................... 13 Table 8-1 Command Table ......................................................................................................................... 14 Table 9-1 Device ID and configuration codes for Address 00h .................................................................. 18 Table 9-2 ONFI identifying codes for Address 20h ..................................................................................... 18 Table 9-3 Parameter Page Output Value .................................................................................................... 21 Table 9-4 Status Register Bit Definition ...................................................................................................... 22 Table 9-5 Features ...................................................................................................................................... 36 Table 9-6 Feature Address 80h .................................................................................................................. 37 Table 9-7 Feature Address 81h .................................................................................................................. 38 Table 10-1 Absolute Maximum Ratings ...................................................................................................... 45 Table 10-2 Operating Ranges ..................................................................................................................... 45 Table 10-3 DC Electrical Characteristics .................................................................................................... 47 Table 10-4 AC Measurement Conditions .................................................................................................... 48 Table 10-5 AC timing characteristics for Command, Address and Data Input ........................................... 49 Table 10-6 AC timing characteristics for Operation .................................................................................... 50 Table 10-7 Program and Erase Characteristics .......................................................................................... 51 Table 12-1 Valid Block Number .................................................................................................................. 61 Table 12-2 Block failure .............................................................................................................................. 62 Table 16-1 History Table ............................................................................................................................. 64 4 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z List of Figures Figure 6-1 Array Organization ..................................................................................................................... 11 Figure 6-2 Array Organization ..................................................................................................................... 12 Figure 9-1 Page Read Operations .............................................................................................................. 15 Figure 9-2 Two Plane Read Page (00h-00h-30h) Operation ...................................................................... 16 Figure 9-3 Random Data Output ................................................................................................................. 17 Figure 9-4 Two Plane Random Data Read (06h-E0h) Operation ............................................................... 17 Figure 9-5 Read ID ...................................................................................................................................... 18 Figure 9-6 Read Parameter Page ............................................................................................................... 19 Figure 9-7 Read Status Operation .............................................................................................................. 21 Figure 9-8 Read Status Enhanced (78h) Operation ................................................................................... 23 Figure 9-9 Read Unique ID ......................................................................................................................... 24 Figure 9-10 Page Program.......................................................................................................................... 25 Figure 9-11 Random Data Input ................................................................................................................. 26 Figure 9-12 Two Plane Page Program ....................................................................................................... 27 Figure 9-13 Program for copy back Operation............................................................................................ 30 Figure 9-14 Copy Back Operation with Random Data Input....................................................................... 30 Figure 9-15 Two Plane Copy Back ............................................................................................................. 31 Figure 9-16 Two Plane Copy Back with Random Data Input ..................................................................... 31 Figure 9-17 Two Plane Program for copy back .......................................................................................... 32 Figure 9-18 Block Erase Operation ............................................................................................................. 33 Figure 9-19 Two Plane Block Erase Operation........................................................................................... 34 Figure 9-20 Reset Operation....................................................................................................................... 35 Figure 9-21 Get Feature Operation ............................................................................................................. 39 Figure 9-22 Set Feature Operation ............................................................................................................. 40 Figure 9-23 Erase Enable ........................................................................................................................... 42 Figure 9-24 Erase Disable .......................................................................................................................... 42 Figure 9-25 Program Enable ....................................................................................................................... 42 Figure 9-26 Program Disable ...................................................................................................................... 43 Figure 9-27 Program for Copy Back Enable ............................................................................................... 43 Figure 9-28 Program for Copy Back Disable .............................................................................................. 43 Figure 10-1 Power ON/OFF sequence ....................................................................................................... 46 Figure 11-1 Command Latch Cycle ............................................................................................................ 52 Figure 11-2 Address Latch Cycle ................................................................................................................ 52 Figure 11-3 Data Latch Cycle ..................................................................................................................... 53 Figure 11-4 Serial Access Cycle after Read ............................................................................................... 53 Figure 11-5 Serial Access Cycle after Read (EDO) .................................................................................... 54 Figure 11-6 Read Status Operation ............................................................................................................ 54 Figure 11-7 Page Read Operation .............................................................................................................. 55 Figure 11-8 #CE Don't Care Read Operation ............................................................................................. 55 Figure 11-9 Random Data Output Operation .............................................................................................. 56 Figure 11-10 Read ID .................................................................................................................................. 57 Figure 11-11 Page Program........................................................................................................................ 57 Figure 11-12 #CE Don't Care Page Program Operation ............................................................................ 58 Figure 11-13 Page Program with Random Data Input ................................................................................ 59 5 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z Figure 11-14 Copy Back ............................................................................................................................. 59 Figure 11-15 Block Erase............................................................................................................................ 60 Figure 11-16 Reset ..................................................................................................................................... 60 Figure 12-1 Flow chart of create initial invalid block table .......................................................................... 62 Figure 12-2 Bad block Replacement........................................................................................................... 63 6 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 1. GENERAL DESCRIPTION The W29N02GW/Z (2G-bit) NAND Flash memory provides a storage solution for embedded systems with limited space, pins and power. It is ideal for code shadowing to RAM, solid state applications and storing media data such as, voice, video, text and photos. The device operates on a single 1.7V to 1.95V power supply with active current consumption as low as 13mA at 1.8V and 10uA for CMOS standby current. The memory array totals 276,824,064bytes, and organized into 2,048 erasable blocks of 135,168 bytes (135,168 words). Each block consists of 64 programmable pages of 2,112-bytes (1056 words) each. Each page consists of 2,048-bytes (1024 words) for the main data storage area and 64-bytes (32words) for the spare data area (The spare area is typically used for error management functions). The W29N02GW/Z supports the standard NAND flash memory interface using the multiplexed 8-bit (16bit) bus to transfer data, addresses, and command instructions. The five control signals, CLE, ALE, #CE, #RE and #WE handle the bus interface protocol. Also, the device has two other signal pins, the #WP (Write Protect) and the RY/#BY (Ready/Busy) for monitoring the device status. 2. FEATURES * Basic Features - Density : 2Gbit (Single chip solution) - Vcc : 1.7V to 1.95V - Bus width : x8 x16 - Operating temperature Industrial: -40C to 85C * Single-Level Cell (SLC) technology. * Organization - Density: 2G-bit/256M-byte - Page size 2,112 bytes (2048 + 64 bytes) 1,056 words (1024 + 32 words) - Block size 64 pages (128K + 4K bytes) 64 pages (64K + 2K words) * Highest Performance - Read performance (Max.) Random read: 25us Sequential read cycle: 25ns - Write Erase performance Page program time: 250us(typ.) Block erase time: 2ms(typ.) - Endurance 100,000 Erase/Program Cycles(2) - 10-years data retention * Command set - Standard NAND command set - Additional command support Copy Back Two-plane operation - Contact Winbond for OTP feature - Contact Winbond for block Lock feature * Lowest power consumption - Read: 25mA(typ.3V),T.B.D(typ.1.8V) - Program/Erase: 10mA(typ.1.8V) - CMOS standby: 10uA(typ.) * Space Efficient Packaging - Contact Winbond for stacked packages/KGD Note: 1. Endurance specification is based on 1bit/528 byte ECC (Error Correcting Code). 7 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 3. PACKAGE TYPES AND PIN CONFIGURATIONS 3.1 Pin Descriptions PIN NAME I/O #WP I Write Protect ALE I Address Latch Enable #CE I Chip Enable #WE I Write Enable RY/#BY O Ready/Busy #RE I Read Enable CLE I Command Latch Enable I/O[0-7] I/O[0-15] I/O Vcc Supply FUNCTION Data Input/Output (x8,x16) Power supply Vss Supply DNU - Do Not Use. Ground N.C - No Connect Table 3-1 Pin Descriptions Note: 1. Connect all Vcc and Vss pins to power supply or ground. Do not leave Vcc or Vss disconnected. 8 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 4. PIN DESCRITPIONS 4.1 Chip Enable (#CE) #CE pin enables and disables device operation. When #CE is high the device is disabled and the I/O pins are set to high impedance and enters into standby mode if not busy. When #CE is set low the device will be enabled, power consumption will increase to active levels and the device is ready for Read and Write operations. 4.2 Write Enable (#WE) #WE pin enables the device to control write operations to input pins of the device. Such as, command instructions, addresses and data that are latched on the rising edge of #WE. 4.3 Read Enable (#RE) #RE pin controls serial data output from the pre-loaded Data Register. Valid data is present on the I/O bus after the tREA period from the falling edge of #RE. Column addresses are incremented for each #RE pulse. 4.4 Address Latch Enable (ALE) ALE pin controls address input to the address register of the device. When ALE is active high, addresses are latched via the I/O pins on the rising edge of #WE. 4.5 Command Latch Enable (CLE) CLE pin controls command input to the command register of the device. When CLE is active high, commands are latched into the command register via I/O pins on the rising edge of #WE. 4.6 Write Protect (#WP) #WP pin can be used to prevent the inadvertent program/erase to the device. When #WP pin is active low, all program/erase operations are disabled. 4.7 Ready/Busy (RY/#BY) RY/#BY pin indicates the device status. When RY/#BY output is low, it indicates that the device is processing either a program, erase or read operations. When it returns to high, those operations have completed. RY/#BY pin is an open drain. 4.8 Input and Output (I/Ox) I/Ox bi-directional pins are used for the following; command, address and data operations. 9 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 5. BLOCK DIAGRAM Status Register #CE ALE CLE #RE #WE #WP Command Resister Column Decoder Cache Register Data Register I/O Control I/Ox Address Register NAND Flash Array Logic Control High Voltage Generator Row Decoder RY/#BY Figure 5-1 NAND Flash Memory Block Diagram 10 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 6. MEMORY ARRAY ORGANIZATION 6.1 Array Organization (x8) 2112 bytes 2112 bytes DQ7 Cache Register 2048 64 2048 64 Data Register 2048 64 2048 64 DQ0 1page = (2k+64bytes) 1block = (2k+64bytesx64 pages = (128k+4k)byte 1plane = (128k+4k)bytex1024blocks = 1056Mb 1device = 1056M x2planes = 2112Mb 1024 blocks Per plane 1 block 1 block 2048 blocks Per device Plane of even numbered blocks Plane of- odd numbered blocks Figure 6-1 Array Organization I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 A7 A6 A5 A4 A3 A2 A1 A0 L L L L A11 A10 A9 A8 cycle A19 A18 A17 A16 A15 A14 A13 A12 4th cycle A27 A26 A25 A24 A23 A22 A21 A20 5th cycle L L L L L L L A28 1st cycle 2nd cycle 3rd Table 6-1 Addressing Notes: 1. "L" indicates a low condition, which must be held during the address cycle to insure correct processing. 2. A0 to A11 during the 1st and 2nd cycles are column addresses. A12 to A28 during the 3rd, 4th and 5th cycles are row addresses. 3. A18 is plane address 4. The device ignores any additional address inputs that exceed the device's requirement. 11 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 6.2 Array Organization (x16) 1056 words 1056 words DQ15 Cache Register 1024 32 1024 32 Data Register 1024 32 1024 32 DQ0 1page = (1k+32words) 1block = (1k+32wordsx64 pages = (64k+2k)words 1plane = (64k+2k)wordsx1024blocks = 1056Mb 1device= 1056M x2planes = 2112Mb 1024 blocks Per plane 1 block 1 block 2048 blocks Per device Plane of even numbered blocks (0,2,4,6...,1020,1022) Plane of- odd numbered blocks (1,3,5,7...,1021,1023) Figure 6-2 Array Organization I/O[15:8] I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 1st cycle L A7 A6 A5 A4 A3 A2 A1 A0 2ndcycle L L L L L L A10 A9 A8 3rd cycle L A18 A17 A16 A15 A14 A13 A12 A11 4th cycle L A26 A25 A24 A23 A22 A21 A20 A19 5th cycle L L L L L L L L A27 Table 6-2 Addressing Notes: 1. "L" indicates a low condition, which must be held during the address cycle to insure correct processing. 2. A0 to A10 during the 1st and 2nd cycles are column addresses. A11 to A27 during the 3rd, 4th and 5th cycles are row addresses. 3. A17 is plane address 4. The device ignores any additional address inputs that exceed the device's requirement. 12 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 7. MODE SELECTION TABLE MODE CLE ALE #CE #WE #RE #WP Read mode Command input H L L H X Address input L H L H X Program Command input H L L H H Erase mode Address input L H L H H Data input L L L H H Sequential Read and Data output L L L H During read (busy) X X X X H X During program (busy) X X X X X H During erase (busy) X X X X X H Write protect X X X X X L Standby X X H X X 0V/Vcc X Table 7-1 Mode Selection Notes: 1. "H" indicates a HIGH input level, "L" indicates a LOW input level, and "X" indicates a Don't Care Level. 2. #WP should be biased to CMOS HIGH or LOW for standby. 13 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 8. COMMAND TABLE 1ST CYCLE 2ND CYCLE PAGE READ 00h 30h READ for COPY BACK 00h 35h READ ID 90h READ STATUS 70h Yes RESET FFh Yes PAGE PROGRAM 80h 10h PROGRAM for COPY BACK 85h 10h BLOCK ERASE 60h D0h RANDOM DATA INPUT*1 85h RANDOM DATA OUTPUT*1 05h READ PARAMETER PAGE ECh READ UNIQUE ID EDh GET FEATURES EEh SET FEATURES EFh READ STATUS ENHANCED 78h TWO PLANE READ PAGE 00h 00h 30h TWO PLANE READ FOR COPY BACK 00h 00h 35h TWO PLANE RANDOM DATA 06h E0h TWO PLANE PROGRAM(TRADITIONAL) 80h 11h 81h 10h TWO PLANE PROGRAM(ONFI) 80h 11h 80h 10h COMMAND READ 3rd CYCLE 4th CYCLE E0h Yes TWO PLANE PROGRAM BACK(TRADITIONAL) FOR COPY 85h 11h 81h 10h TWO PLANE BACK(ONFI) FOR COPY 85h 11h 85h 10h TWO PLANE BLOCK ERASE(TRADITIONAL) 60h 60h D0h TWO PLANE BLOCK ERASE(ONFI) 60h D1h 60h PROGRAM Acceptable during busy D0h Table 8-1 Command Table Notes: 1. RANDOM DATA INPUT and RANDOM DATA OUTPUT command is only to be used within a page. 2. Any commands that are not in the above table are considered as undefined and are prohibited as inputs. 3. Do not cross plane address boundaries when using Copy Back Read and Program for copy back. 14 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9. DEVICE OPERATIONS 9.1 READ operation 9.1.1 PAGE READ (00h-30h) When the device powers on, 00h command is latched to command register. Therefore, system only issues five address cycles and 30h command for initial read from the device. This operation can also be entered by writing 00h command to the command register, and then write five address cycles, followed by writing 30h command. After writing 30h command, the data is transferred from NAND array to Data Register during tR. Data transfer progress can be done by monitoring the status of the RY/#BY signal output. RY/#BY signal will be LOW during data transfer. Also, there is an alternate method by using the READ STATUS (70h) command. If the READ STATUS command is issued during read operation, the Read (00h) command must be re-issued to read out the data from Data Register. When the data transfer is complete, RY/#BY signal goes HIGH, and the data can be read from Data Register by toggling #RE. Read is sequential from initial column address to the end of the page. (See Figure 9-1) CLE #CE #WE ALE #RE l/Ox 00h Data Output ( Serial Access ) 30h Address (5cycles) tR RY/#BY Don't care Figure 9-1 Page Read Operations 9.1.2 TWO PLANE READ (00h-00h-30h) TWO PLANE READ (00h-00h-30h) transfers two pages data from the NAND array to the data registers. Each page address have to be indicated different plane address. To set the TWO PLANE READ mode, write the 00h command to the command register, and then write five address cycles for plane 0. Secondly, write the 00h command to the command register, and five address cycles for plane 1. Finally, the 30h command is issued. The first-plane and second-plane addresses must be identical for all of issued address except plane address. After the 30h command is written, page data is transferred from both planes to their respective data registers in tR. RY/#BY goes LOW While these are transfered,. When the transfers are complete, RY/#BY goes HIGH. To read out the data, at first, system writes TWO PLANE RAMDOM DATA READ (06h-E0h) command to select a plane, next, repeatedly pulse #RE to read out the data from selected plane. To change the plane address, issues TWO PLANE RANDOM DATA READ (06h-E0h) 15 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z command to select the another plane address, then repeatedly pulse #RE to read out the data from the selected plane data register. Alternatively, data transfers can be monitored by the READ STATUS (70h). When the transfers are complete, status register bit 6 is set to 1. To read data from the first of the two planes even when READ STATUS ENHANCED (78h) command is used, the system must issue the TWO PLANE RANDOM DATA READ (06h-E0h) command at first and pulse #RE repeatedly. Write a TWO PLANE RANDOM DATA READ (06h-E0h) command to select the other plane ,after the data cycle is complete. pulse #RE repeatedly to output the data beginning at the specified column address. During TWO PLANE READ operation,the READ STATUS ENHANCED (78h) command is prohibited . CLE #WE ALE #RE Plane address M Plane address M I/Ox 00h Col Add1 Col Add2 Column address J Row Add1 Row Add2 Row Add3 Col Add1 00h Plane 0 address Col Add2 Column address J Row Add1 Row Add2 Row Add3 30h Plane 1 address tR RY/#BY 1 CLE #WE ALE #RE I/Ox 06h Address (5cycles) Plane 0 or Plane 1 address E0h DOUT0 DOUT1 DOUTn Selected Plane data RY/#BY 1 Figure 9-2 Two Plane Read Page (00h-00h-30h) Operation 16 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.1.3 RANDOM DATA OUTPUT (05h-E0h) The RANDOM DATA OUTPUT allows the selection of random column addresses to read out data from a single or multiple of addresses. The use of the RANDOM DATA OUTPUT command is available after the PAGE READ (00h-30h) sequence by writing the 05h command following by the two cycle column address and then the E0h command. Toggling #RE will output data sequentially. The RANDOM DATA OUTPUT command can be issued multiple times, but limited to the current loaded page. tR RY/#BY #RE I/Ox 00h Address(5cycles) 30h Data out 05h Address(2cycles) E0h Data out Figure 9-3 Random Data Output 9.1.3.1. TWO PLANE RANDOM DATA OUTPUT (06h-E0h) TWO PLANE RANDOM DATA READ (06h-E0h) command can indicate to specified plane and column address on data register . This command is accepted by a device when it is ready. Issuing 06h to the command register, two column address cycles, three row address cycles, E0h are followed, this enables data output mode on the address device's data register at the specified column address. After the E0h command , the host have to wait at least tWHR before requesting data output. The selected device is in data output mode until another valid command is issued. The TWO PLANE RANDOM DATA READ (06h-E0h) command is used to select the data register to be enabled for data output. When the data output is complete on the selected plane, the command can be issued again to start data output on another plane. If there is a need to update the column address without selecting a new data register, the RANDOM DATA READ (05h-E0h) command can be used instead. CLE #CE #WE ALE #RE I/Ox Data Out 06h Address (5cycles) E0h Data Out Figure 9-4 Two Plane Random Data Read (06h-E0h) Operation 17 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.1.4 READ ID (90h) READ ID command is comprised of two modes determined by the input address, device (00h) or ONFI (20h) identification information. To enter the READ ID mode, write 90h to the Command Register followed by a 00h address cycle, then toggle #RE for 5 single byte cycles, W29N02GW/Z. The pre-programmed code includes the Manufacturer ID, Device ID, and Product-Specific Information (see Table 9.1). If the READ ID command is followed by 20h address, the output code includes 4 single byte cycles of ONFI identifying information (See Table 9.2). The device remains in the READ ID Mode until the next valid command is issued. CLE #CE #WE tAR ALE #RE tWHR I/Ox tREA Byte0 00h 90h Byte1 Byte2 Byte3 Byte4 (or 20h) Address 1 Cycle Figure 9-5 Read ID # of Byte/Cycles 1st Byte/Cycle 2nd Byte/Cycle 3rd Byte/Cycle 4th Byte/Cycle 5th Byte/Cycle W29N02GZ EFh AAh 90h 15h 04h W29N02GW EFh BAh 90h 55h 04h Device ID Cache Programming not Supported Page Size:2KB Spare Area Size:64b BLK Size w/o Spare:128KB Organized:x8 or x16 Serial Access:25ns Description MFR ID x16 device : the ID is outputted at word units, and defined lower-byte (IO0-7). ID table shows only lower-byte ID. Table 9-1 Device ID and configuration codes for Address 00h # of Byte/Cycles 1st Byte/Cycle 2nd Byte/Cycle 3rd Byte/Cycle 4th Byte/Cycle Code 4Fh 4Eh 46h 49h Table 9-2 ONFI identifying codes for Address 20h 18 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.1.5 READ PARAMETER PAGE (ECh) READ PARAMETER PAGE can read out the device's parameter data structure, such as, manufacturer information, device organization, timing parameters, key features, and other pertinent device parameters. The data structure is stored with at least three copies in the device's parameter page. Figure 9-9 shows the READ PARAMETER PAGE timing. The RANDOM DATA OUTPUT (05hE0h) command is supported during data output. CLE #WE ALE #RE I/Ox ECh 00h P00 P10 P01 P11 tR RY/#BY Figure 9-6 Read Parameter Page Byte Description Value 0-3 Parameter page signature 4Fh, 4Eh, 46h, 49h 4-5 Revision number 02h, 00h 6-7 Features supported W29N02GZ 18h,00h W29N02GW 19h,00h Optional commands supported 3Fh,00h 10-31 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 32-43 Device manufacturer 57h, 49h, 4Eh, 42h, 4Fh, 4Eh, 44h, 20h, 20h, 20h, 20h, 20h 8-9 44-63 64 W29N02GZ 57h,32h,39h,4Eh,30h,32h,47h,5Ah,20h,20h,20h,20h,20 h,20h,20h,20h,20h,20h,20h,20h,20h W29N02GW 57h,32h,39h,4Eh,30h,32h,47h,57h,20h,20h,20h,20h,20 h,20h,20h,20h,20h,20h,20h,20h,20h Device model Manufacturer ID EFh 65-66 Date code 00h, 00h 67-79 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 80-83 # of data bytes per page 00h, 08h, 00h, 00h 19 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z Byte Description Value 84-85 # of spare bytes per page 40h, 00h 86-89 # of data bytes per partial page 00h, 02h, 00h, 00h 90-91 # of spare bytes per partial page 10h, 00h 92-95 # of pages per block 40h, 00h, 00h, 00h 96-99 # of blocks per unit 00h, 08h, 00h, 00h 100 # of logical units 01h 101 # of address cycles 23h 102 # of bits per cell 01h 103-104 Bad blocks maximum per unit 28h, 00h 105-106 Block endurance 01h, 05h Guaranteed valid blocks at beginning of target 01h Block endurance for guaranteed valid blocks 00h, 00h 110 # of programs per page 04h 111 Partial programming attributes 00h 112 # of ECC bits 01h 113 # of interleaved address bits 01h 114 Interleaved operation attributes 0Ch Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h I/O pin capacitance 0Ah 129-130 Timing mode support 1Fh, 00h 131-132 Program cache timing 00h, 00h 133-134 Maximum page program time BCh, 02h 135-136 Maximum block erase time 10h, 27h 137-138 Maximum random read time 19h, 00h 139-140 tCCS minimum 46h, 00h 141-163 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 164-165 Vendor specific revision # 01h,00h 166-253 Vendor specific 00h 254-255 Integrity CRC Set at shipment 256-511 Value of bytes 0-255 107 108-109 115-127 128 20 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z Byte 512-767 >767 Description Value Value of bytes 0-255 Additional redundant parameter pages x16 device : the ID is outputted at word units, and defined lower-byte (IO0-7). ID table shows only lower-byte ID. Table 9-3 Parameter Page Output Value 9.1.6 READ STATUS (70h) The W29N02GW/Z has an 8-bit Status Register which can be read during device operation. Refer to Table 9.3 for specific Status Register definitions. After writing 70h command to the Command Register, read cycles will only read from the Status Register. The status can be read from I/O[7:0] outputs, as long as #CE and #RE are LOW. Note; #RE does not need to be toggled for Status Register read. The Command Register remains in status read mode until another command is issued. To change to normal read mode, issue the PAGE READ (00h) command. After the PAGE READ command is issued, data output starts from the initial column address. #CE tCLR CLE #WE tREA #RE I/Ox Status Output 70h Figure 9-7 Read Status Operation 21 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z SR bit I/O 0 Page Read Page Program Block Erase Definition 0=Successful Program/Erase Not Use Pass/Fail Pass/Fail 1=Error in Program/Erase I/O 2 Not Use Not Use Not Use 0 I/O 3 Not Use Not Use Not Use 0 I/O 4 Not Use Not Use Not Use 0 I/O 5 Ready/Busy Ready/Busy Ready/Busy I/O 6 Ready/Busy Ready/Busy Ready/Busy I/O 7 Write Protect Write Protect Write Protect Ready = 1 Busy = 0 Ready = 1 Busy = 0 Unprotected = 1 Protected = 0 Table 9-4 Status Register Bit Definition 9.1.7 READ STATUS ENHANCED (78h) The READ STATUS ENHANCED (78h) command returns the status of the addressed plane on a target even when it is busy (SR BIT 6 = 0). Writing 78h to the command register, followed by three row address cycles containing the page, plane and block addresses that is same as executed addresses, puts the device into read status mode. The device stays in this mode until another valid command is issued The device status is returned when the host requests data output. The SR BIT 6 and SR bit 5 bits of the status register are shared for all planes on the device. The SR BIT 1 and SR BIT 0 (SR bit0) bits are specific to the plane specified in the row address. The READ STATUS ENHANCED (78h) command also enables the device for data output. To begin data output following a READ operation after the device is ready (SR BIT 6 = 1), issue the READ MODE (00h) command, then begin data output. If the host needs to change the data register that will output data, use the TWO PLANE RANDOMDATA READ (06h-E0h) command after the device is ready. Use of the READ STATUS ENHANCED (78h) command is prohibited when OTP mode is enabled. It is also prohibited following some of the other reset, identification. 22 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z CLE #CE #WE ALE #RE I/Ox 78h Address (3cycles) Status Output Figure 9-8 Read Status Enhanced (78h) Operation 23 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.1.8 READ UNIQUE ID (EDh) The W29N02GW/Z NAND Flash device has a method to uniquely identify each NAND Flash device by using the READ UNIQUE ID command. The format of the ID is limitless, but the ID for every NAND Flash device manufactured, will be guaranteed to be unique. Numerous NAND controllers typically use proprietary error correction code (ECC) schemes. In these cases Winbond cannot protect unique ID data with factory programmed ECC. However, to ensure data reliability, Winbond will program the NAND Flash devices with 16 bytes of unique ID code, starting at byte 0 on the page, immediately followed by 16 bytes of the complement of that unique ID. The combination of these two actions is then repeated 16 times. This means the final copy of the unique ID will resides at location byte 511. At this point an XOR or exclusive operation can be performed on the first copy of the unique ID and its complement. If the unique ID is good, the results should yield all the bits as 1s. In the event that any of the bits are 0 after the XOR operation, the procedure can be repeated on a subsequent copy of the unique ID data. CLE #WE ALE #RE I/Ox EDh 00h Byte0 Byte1 Byte14 Byte15 Unique ID data tR RY/#BY Figure 9-9 Read Unique ID 24 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.2 PROGRAM operation 9.2.1 PAGE PROGRAM (80h-10h) The W29N02GW/Z Page Program command will program pages sequentially within a block, from the lower order page address to higher order page address. Programming pages out of sequence is prohibited. The W29N02GW/Z supports partial-page programming operations up to 4 times before an erase is required if partitioning a page. Note; programming a single bit more than once without first erasing it is not supported. 9.2.2 SERIAL DATA INPUT (80h) Page Program operation starts with the execution of the Serial Data Input command (80h) to the Command Register, following next by inputting five address cycles and then the data is loaded. Serial data is loaded to Data Register with each #WE cycle. The Program command (10h) is written to the Command Register after the serial data input is finished. At this time the internal write state controller automatically executes the algorithms for program and verifies operations. Once the programming starts, determining the completion of the program process can be done by monitoring the RY/#BY output or the Status Register Bit 6, which will follow the RY/#BY signal. RY/#BY will stay LOW during the internal array programming operation during the period of (tPROG). During page program operation, only two commands are available, READ STATUS (70h) and RESET (FFh). When the device status goes to the ready state, Status Register Bit 0 (I/O0) indicates whether the program operation passed (Bit0=0) or failed (Bit0=1), (see Figure 9-13). The Command Register remains in read status mode until the next command is issued. tPROG RY/#BY I/Ox 80h Address (5cycles) Din 10h 70h Status I/O0=0pass I/O0=1fail Figure 9-10 Page Program 25 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.2.3 RANDOM DATA INPUT (85h) After the Page Program (80h) execution of the initial data has been loaded into the Data Register, if the need for additional writing of data is required, using the RANDOM DATA INPUT (85h) command can perform this function to a new column address prior to the Program (10h) command. The RANDOM DATA INPUT command can be issued multiple times in the same page (See Figure 9-14). CLE #CE #WE ALE #RE tPROG RY/#BY I/Ox 80h Address (5cycles) Din 85h Address (2cycles) Din 10h 70h Status Don't care Figure 9-11 Random Data Input 9.2.4 TWO PLANE PAGE PROGRAM TWO PLANE PAGE PROGRAM command make it possible for host to input data to the addressed plane's data register and queue the data register to be moved to the NAND Flash array. This command can be issued several times. Each time a new plane address is specified that plane is also queued for data transfer. To input data for the final plane and to begin the program operation for all previously queued planes, the PAGE PROGRAM command has to be issued. All of the queued planes will move the data to the NAND Flash array. when it is ready (SR BIT 6 = 1),this command is accepted. At the block and page address is specified, input a page to the data register and queue it to be moved to the NAND Flash array ,the 80h is issued to the command register. Unless this command has been preceded by a TWO PLANE PAGE PROGRAM command, issuing the 80h to the command register clears all of the data registers' contents on the selected target. Write five address cycles containing the column address and row address; data input cycles follow. Serial data is input beginning at the column address specified. At any time, while the data input cycle, the RANDOM DATA INPUT (85h) command can be issued. When data input is complete, write 11h to the command register. The device will go busy (SR BIT 6 = 0, SR BIT 5 = 0) for tDBSY. To ascertain the progress of tDBSY, the host can monitor the target's RY/#BY signal or, the status operations (70h, 78h) can be used alternatively,. When the device status shows that it is ready (SR BIT 6 = 1), additional TWO PLANE PAGE PROGRAM commands can be issued to queue additional planes for data transfer, then, the PAGE PROGRAM commands can be issued. When the PAGE PROGRAM command is used as the final command of a two plane program operation, data is transferred from the data registers to the NAND Flash array for all of the addressed 26 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z planes during tPROG. When the device is ready (SR BIT 6 = 1, SR BIT 5 = 1), the host should check the status of the SR BIT 0 for each of the planes to verify that programming completed successfully. When system issues TWO PLANE PAGE PROGRAM and PAGE PROGRAM commands, READ STATUS (70h) command can confirm whether the operation(s) passed or failed. If the status after READ STATUS (70h) command indicates an error (SR BIT 0 = 1 and/or SR BIT 1 = 1), READ STATUS ENHANCED (78h) command can be determined which plane is failed. TWO PLANE PROGRAM commands require five-cycle addresses, one address indicates the operational plane. These addresses are subject to the following requirements: * The column address bits must be valid address for each plane * The plane select bit, A18, must be set to "L" for 1st address input, and set to "H" for 2nd address input. * The page address (A17-A12) and block address (A28-A19) of first input are don't care. It follows secondary inputted page address and block address. Two plane operations must be same type operation across the planes; for example, it is not possible to perform a PROGRAM operation on one plane with an ERASE operation on another. tPROG (Program busy time) tDBSY RY/#BY Busy l/Ox 80h Page program Setup code Address Inputs 81h 11h Data Input A0-A11=Valid A12-A17=set to Low A18=set to Low A19-A28=set to Low Confirm Code Busy Multiplane Page Program setup code Data Input Address Inputs A0-A11=Valid A12-A17=Valid A18=set to High A19-A28=Valid 10h Confirm Code 70h SR0 Read Status Register 1)The same row address, except for A18, is applied to the two blocks. 2)Any command between 11h and 81h is prohibited except 70h,78h,and FFh 81h:Traditional Protocol 80h:ONFI Protocol Data Input 80h 10h 81h 11h FirstPlane (1024 block) Second Plane (1024 block) Block 0 Block 1 Block 2 Block 3 : : Block 2044 Block 2045 Block 2046 Block 2047 Figure 9-12 Two Plane Page Program 27 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.3 COPY BACK operation Copy Back operations require two command sets. Issue a READ for COPY BACK (00h-35h) command first, then the PROGRAM for COPY BACK (85h-10h) command. Copy back operations are only supported within a same plane. 9.3.1 READ for COPY BACK (00h-35h) The READ for COPY BACK command is used together with the PROGRAM for COPY BACK (85h10h) command. To start execution, READ for COPY BACK (00h) command is written to the Command Register, followed by the five cycles of the source page address. To start the transfer of the selected page data from the memory array to the data register, write the 35h command to the Command Register. After execution of the READ for COPY BACK command sequence and RY/#BY returns to HIGH marking the completion of the operation, the transferred data from the source page into the Data Register may be read out by toggling #RE. Data is output sequentially from the column address that was originally specified with the READ for COPY BACK command. RANDOM DATA OUTPUT (05hE0h) commands can be issued multiple times without any limitation after READ for COPY BACK command has been executed (see Figures 9-19 and 9-20). At this point the device is in ready state to accept the PROGRAM for COPY BACK command. 9.3.2 PROGRAM for COPY BACK (85h-10h) After the READ for COPY BACK command operation has been completed and RY/#BY goes HIGH, the PROGRAM for COPY BACK command can be written to the Command Register. The command results in the transfer of data to the Data Register, then internal operations start programming of the new destination page. The sequence would be, write 85h to the Command Register, followed by the five cycle destination page address to the NAND array. Next write the 10h command to the Command Register; this will signal the internal controller to automatically start to program the data to new destination page. During this programming time, RY/#BY will LOW. The READ STATUS command can be used instead of the RY/#BY signal to determine when the program is complete. When Status Register Bit 6 (I/O6) equals to "1", Status Register Bit 0 (I/O0) will indicate if the operation was successful or not. The RANDOM DATA INPUT (85h) command can be used during the PROGRAM for COPY BACK command for modifying the original data. Once the data is copied into the Data Register using the READ for COPY BACK (00h-35h) command, follow by writing the RANDOM DATA INPUT (85h) command, along with the address of the data to be changed. The data to be changed is placed on the external data pins. This operation copies the data into the Data Register. Once the 10h command is written to the Command Register, the original data and the modified data are transferred to the Data Register, and programming of the new page commences. The RANDOM DATA INPUT command can be issued numerous times without limitation, as necessary before starting the programming sequence with 10h command. Since COPY BACK operations do not use external memory and the data of source page might include a bit errors, a competent ECC scheme should be developed to check the data before programming data to a new destination page. 28 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.3.3 TWO PLANE READ for COPY BACK To improve read through rate, TWO PLANE READ for COPY BACK operation is copied data concurrently from one or two plane to the specified data registers. TWO PLANE PROGRAM for COPY BACK command can move the data in two pages from the data registers to different pages. This operation improves system performance than PROGRAM for COPY BACK operation. 9.3.4 TWO PLANE PROGRAM for COPY BACK Function of TWO PLANE PROGRAM for COPY BACK command is equal to TWO-PLANE PAGE PROGRAM command, except that when 85h is written to the command register, then data register contents are not cleared. Refer to TWO-PLANE PAGE PROGRAM for more details features. 29 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z CLE #CE #WE ALE #RE I/ Ox 00h Address (5cycles) Data output 35h 05h Address (2cycles) E0h Data Output 85h Address(5cycles) 10h 70h Status Output No limitation Optional tPROG tR RY / # BY Don't care Figure 9-13 Program for copy back Operation CLE #CE #WE ALE #RE tPROG tR RY/#BY I/Ox 00h Address(5Cycles) 35h DataOutput 85h Address(5cycles) Data Input 85h Address (2cycles) Data Input 10h 70h Status Output No limitation Optional Don't care Figure 9-14 Copy Back Operation with Random Data Input 30 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z tR RY/#BY #RE 00h I/Ox Address(5cycles) 35h Address(5cycles) 00h Plane 0 source Address(5cycles) 06h E0h Plane 0 or Plane 1 source address Plane 1 source 1 RY/#BY #RE Data Output I/Ox Address(2cycles) 06h E0h Data Output Data from selected plane From new column address Selected Plane column address Data from selected Plane 1 2 Optional tDBSY RY/#BY tPROG #RE 85h I/Ox Address(5cycles) Address(5cycles) 85h 11h Plane 0 destination 10h 70h Status Plane 1 destination 2 Figure 9-15 Two Plane Copy Back tR RY/#BY I/Ox 00h Address(5cycles) Plane 0 source 00h Address(5cycles) 85h 35h data Address(5cycles) 85h Address(2cycles) Unlimited number of repetitions Plane 1 source Plane 0 destination optional Data 11h 1 tPROG tDBSY RY/#BY I/Ox 85h Address(5cycles) 10h 70h Status Plane 1 destination 1 Figure 9-16 Two Plane Copy Back with Random Data Input 31 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z Read code Read code l/O 00h Address (5 cycles) 35h 00h Copy back code Address (5 cycles) Col Add1,2 Row Add1, 2,3 Source address on Plane1 Col Add1,2 Row Add1,2,3 Source address on Plane0 35h Copy back code Address (5 cycles) 85h Col Add.1,2 Row Add.1,2,3 Destination address on Plane0 A0 - A11 = don't care A12-A17 = don't care A18 = set to Low' A19- A28 = don't care 35h 11h Read Status Register Address (5 cycles) 85h 10h 70h tR tR tDBSY tPROG Busy Busy Busy Busy RY/#BY SR0 Col Add.1,2 Row Add.1,2,3 Source address on Plane1 A0 - A11 = set to Low' A12-A17 = Valid A18 = set to High' A19-A28 = Valid Single plane copy back read can be used to two plane operation. First plane Second plane SourcePage 85h:ONFI Protocol 81h:Traditional Protocol TargetPage (1):Read for copy back on first plane (2):Read for copy back on second plane (3):Two-plane copy back program SourcePage TargetPage (1) (3) Main area (2) Spare area (3) Main area Spare area Figure 9-17 Two Plane Program for copy back 32 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.4 BLOCK ERASE operation 9.4.1 BLOCK ERASE (60h-D0h) Erase operations happen at the architectural block unit. This W29N02GW/Z has 2048 erase blocks. Each block is organized into 64 pages (x8:2112 bytes/page, x16:1056 words/page), 132K bytes (x8:128K + 4K bytes, x16:64 K+ 2Kwords)/block. The BLOCK ERASE command operates on a block by block basis. Erase Setup command (60h) is written to the Command Register. Next, the three cycle block address is written to the device. The page address bits are loaded during address block address cycle, but are ignored. The Erase Confirm command (D0h) is written to the Command Register at the rising edge of #WE, RY/#BY goes LOW and the internal controller automatically handles the block erase sequence of operation. RY/#BY goes LOW during Block Erase internal operations for a period of tBERS, The READ STATUS (70h) command can be used for confirm block erase status. When Status Register Bit6 (I/O6) becomes to "1", block erase operation is finished. Status Register Bit0 (I/O0) will indicate a pass/fail condition (see Figure 9-24). CLE #CE #WE ALE #RE I/Ox 60h Address Input (3cycles) 70h D0h tBERS Status Output I/ O 0 = 0 pass I/ O 0 = 1 fail RY/#BY Don't care Figure 9-18 Block Erase Operation 33 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.4.2 TWO PLANE BLOCK ERASE TWO PLANE BLOCK ERASE (60h-D1h) command indicates two blocks in the specified plane that is to be erased. To start ERASE operation for indicated blocks in the specified plane, write the BLOCK ERASE (60h-D0h) command. To indicate a block to be erased, writing 60h to the command register, then, write three address cycles containing the row address, the page address is ignored. By writing D1h command to command register, the device will go busy (SR BIT 6 = 0, SR BIT 5 = 0) for tDBSY. To confirm busy status during tDBSY, the host can monitor RY/#BY signal. Instead, system can use READ STATUS (70h) or READ STATUS ENHANCED (78h) commands. When the status shows ready (SR BIT 6 = 1, SR BIT 5 = 1), additional TWO PLANE BLOCK ERASE commands can be issued for erasing two blocks in a specified plane. When system issues TWO PLANE BLOCK ERASE (60h-D1h), and BLOCK ERASE (60h-D0h) commands, READ STATUS (70h) command can confirm whether the operation(s) passed or failed. If the status after READ STATUS (70h) command indicates an error (SR BIT 0 = 1), READ STATUS ENHANCED (78h) command can be determined which plane is failed. TWO PLANE BLOCK ERASE commands require three cycles of row addresses; one address indicates the operational plane. These addresses are subject to the following requirements: * The plane select bit, A18, must be different for each issued address. * Block address (A28-A19) of first input is don't care. It follows secondary inputted block address. Two plane operations must be same type operation across the planes; for example, it is not possible to perform a PROGRAM operation on one plane with an ERASE operation on another. CLE #CE #WE ALE #RE I/Ox 60h R1A R2A R3A D1h 60h R1B R2B R3B D0h tDBSY tBERS Busy Busy RY/#BY Don't care Figure 9-19 Two Plane Block Erase Operation 34 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.5 RESET operation 9.5.1 RESET (FFh) READ, PROGRAM, and ERASE commands can be aborted by the RESET (FFh) command during the time the W29N02GW/Z is in the busy state. The Reset operation puts the device into known status. The data that is processed in either the programming or erasing operations are no longer valid. This means the data can be partially programmed or erased and therefore data is invalid. The Command Register is cleared and is ready to accept next command. The Data Register contents are marked invalid. The Status Register indicates a value of E0h when #WP is HIGH; otherwise a value of 60h is written when #WP is LOW. After RESET command is written to the command register, RY/#BY goes LOW for a period of tRST (see Figure 9-26). CLE #CE tWB #WE tRST RY/#BY I/Ox FFh RESET command Figure 9-20 Reset Operation 35 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.6 FEATURE OPERATION The GET FEATURES (EEh) and SET FEATURES (EFh) commands are used to change the NAND Flash device behavior from the default power on settings. These commands use a one-byte feature address to determine which feature is to be read or modified. A range of 0 to 255 defines all features; each is described in the features table (see Table 9.5 thru 9.7). The GET FEATURES (EEh) command reads 4-Byte parameter in the features table (See GET FEATURES function). The SET FEATURES (EFh) command places the 4-Byte parameter in the features table (See SET FEATURES function). When a feature is set, meaning it remains active by default until the device is powered off. The set feature remains the set even if a RESET (FFh) command is issued. Feature address 00h 02h-7Fh Description N.A Reserved 80h Vendor specific parameter : Programmable I/O drive strength 81h Vendor specific parameter : Programmable RY/#BY pull-down strength 82h-FFh Reserved Table 9-5 Features 36 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z Feature Address 80h: Programmable I/O Drive Strength Sub feature Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes 1 parameter P1 I/O Full (default) Reserved (0) 0 0 00h drive strength Three-quarters Reserved (0) 0 1 01h One-half Reserved (0) 1 0 02h One-quarter Reserved (0) 1 1 03h P2 Reserved (0) 00h Reserved (0) 00h Reserved (0) 00h P3 P4 Table 9-6 Feature Address 80h Note: 1. The default drive strength setting is Full strength. The Programmable I/O Drive Strength mode is used to change from the default I/O drive strength. Drive strength should be selected based on expected loading of the memory bus. This table shows the four supported output drive-strength settings. The device returns to the default drive strength mode when a power cycle has occurred. AC timing parameters may need to be relaxed if I/O drive strength is not set to full. 37 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z Feature Address 81h: Programmable RY/#BY Pull-down Strength Sub feature Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes 1 parameter P1 RY/#BY Full (default) Reserved (0) 0 0 00h pull-down Three-quarters Reserved (0) 0 1 01h One-half Reserved (0) 1 0 02h One-quarter Reserved (0) 1 1 03h strength P2 Reserved (0) 00h Reserved (0) 00h Reserved (0) 00h P3 P4 Table 9-7 Feature Address 81h Note: 1. The default programmable RY/#BY pull-down strength is set to Full strength. The pull-down strength is used to change the RY/#BY pull-down strength. RY/#BY pull-down strength should be selected based on expected loading of RY/#BY. The four supported pull-down strength settings are shown. The device returns to the default pull-down strength when a power cycle has occurred. 38 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.6.1 GET FEATURES (EEh) The GET FEATURES command returns the device feature settings including those previously set by the SET FEATURES command. To use the Get Feature mode write the command (EEh) to the Command Register followed by the single cycle byte Feature Address. RY/#BY will goes LOW for the period of tFEAT. If Read Status (70h) command is issued for monitoring the process completion status, Read Command (00h) has to be executed to re-establish data output mode. Once, RY/#BY goes HIGH, the device feature settings can be read by toggling #RE. The device remains in Feature Mode until another valid command is issued to Command Register. See Figure 9-27. CLE #CE #WE ALE #RE I/Ox EEh RY/#BY P1 FA Feature address 1 cycle P2 P3 P4 tFEAT Figure 9-21 Get Feature Operation 39 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.6.2 SET FEATURES (EFh) The SET FEATURES command sets the behavior parameters by selecting a specified feature address. To change device behavioral parameters, execute Set Feature command by writing EFh to the Command Register, followed by the single cycle feature address. Each feature parameter (P1P4) is latched at the rising edge of each #WE. The RY/#BY signal will go LOW during the period of tFEAT while the four feature parameters are stored. The Read Status (70h) command can be issued for monitoring the progress status of this operation. The parameters are stored in device until the device goes through a power on cycle. The device remains in feature mode until another valid command is issued to Command Register. CLE #CE #WE ALE #RE tADL I/Ox EFh FA P1 P2 P3 P4 tWB RY/#BY tFEAT Figure 9-22 Set Feature Operation 40 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.7 ONE TIME PROGRAMMABLE (OTP) area The device has One-Time Programmable (OTP) memory area comprised of a number of pages (2112 bytes/page) (1056words/page). This entire range of pages is functionally guaranteed. Only the OTP commands can access the OTP area. When the device ships from Winbond, the OTP area is in an erase state (all bits equal "1"). The OTP area cannot be erased, therefore protecting the area only prevent further programming. Contact to Winbond for using this feature. 41 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.8 WRITE PROTECT #WP pin can enable or disable program and erase commands preventing or allowing program and erase operations. Figure 9-29 to 9-34 shows the enabling or disabling timing with #WP setup time (tWW) that is from rising or falling edge of #WP to latch the first commands. After first command is latched, #WP pin must not toggle until the command operation is complete and the device is in the ready state. (Status Register Bit5 (I/O5) equal 1) # WE tWW I /Ox 60h D0h #WP RY/#BY Figure 9-23 Erase Enable #WE tWW I/Ox 60h D0h #WP RY/#BY Figure 9-24 Erase Disable #WE tWW I/Ox 80 h 10h ( or 15h) #WP RY/#BY Figure 9-25 Program Enable 42 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z #WE tWW I/Ox 80 h 10h ( or 15h) #WP RY/#BY Figure 9-26 Program Disable #WE tWW I /Ox 85h 10h # WP RY/#BY Figure 9-27 Program for Copy Back Enable #WE tWW I/Ox 10 h 85h # WP RY/#BY Figure 9-28 Program for Copy Back Disable 43 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 9.9 BLOCK LOCK The device has block lock feature that can protect the entire device or user can indicate a ranges of blocks from program and erase operations. Using this feature offers increased functionality and flexibility data protection to prevent unexpected program and erase operations. Contact to Winbond for using this feature. 44 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 10. ELECTRICAL CHARACTERISTICS 10.1 Absolute Maximum Ratings (1.8V) PARAMETERS SYMBOL Supply Voltage CONDITIONS VCC Voltage Applied to Any Pin VIN Storage Temperature Relative to Ground TSTG RANGE UNIT -0.6 to +2.4 V -0.6 to +2.4 V -65 to +150 C 5 mA Short circuit output current, I/Os Table 10-1 Absolute Maximum Ratings Notes: 1. 2. Specification for W29N02GW/Z is preliminary. See preliminary designation at the end of this document. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damage. 10.2 Operating Ranges (1.8V) PARAMETER Supply Voltage Ambient Temperature, Operating SYMBOL CONDITIONS VCC TA Industrial SPEC UNIT MIN MAX 1.7 1.95 V -40 +85 C Table 10-2 Operating Ranges 45 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 10.3 Device power-up timing The device is designed to avoid unexpected program/erase operations during power transitions. When the device is powered on, an internal voltage detector disables all functions whenever Vcc is below about 1.1V at 1.8V device. Write Protect (#WP) pin provides hardware protection and is recommended to be kept at VIL during power up and power down. A recovery time of minimum 1ms is required before internal circuit gets ready for any command sequences (See Figure 10-1). Vcc #WP #WE 1ms (Min) RY/#BY 5 ms (Max) Undefined Figure 10-1 Power ON/OFF sequence 46 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 10.4 DC Electrical Characteristics (1.8V) SPEC PARAMETER SYMBOL CONDITIONS UNIT MIN TYP MAX - 13 20 mA tRC= tRC MIN Sequential Read current Icc1 #CE=VIL IOUT=0mA Program current Icc2 - - 10 20 mA Erase current Icc3 - - 10 20 mA Standby current (TTL) ISB1 - - 1 mA Standby current (CMOS) ISB2 - 10 50 A #CE=VIH #WP=0V/Vcc #CE=Vcc - 0.2V #WP=0V/Vcc Input leakage current ILI VIN= 0 V to Vcc - - 10 A Output leakage current ILO VOUT=0V to Vcc - - 10 A Input high voltage VIH I/O15~0, #CE,#WE,#RE, #WP,CLE,ALE 0.8 x Vcc - Vcc + 0.3 V Input low voltage VIL - -0.3 - 0.2 x Vcc V Output high voltage(1) VOH IOH=-100A Vcc -0.1 - - V Output low voltage(1) VOL IOL=+100A - - 0.1 V IOL(RY/#BY) VOL=0.2V 3 4 Output low current mA Table 10-3 DC Electrical Characteristics Note: 1. VOH and VOL may need to be relaxed if I/O drive strength is not set to full. 47 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 10.5 AC Measurement Conditions (1.8V) PARAMETER SYMBOL Input Capacitance(1), (2) SPEC UNIT MIN MAX CIN - 10 pF Input/Output Capacitance(1), (2) CIO - 10 pF Input Rise and Fall Times TR/TF - 2.5 ns Input Pulse Voltages - 0 to VCC V Input/Output timing Voltage - Vcc/2 V Output load (1) CL 1TTL GATE and CL=30pF - Table 10-4 AC Measurement Conditions Notes: 1. Verified on device characterization , not 100% tested 2. Test conditions TA=25'C, f=1MHz, VIN=0V 48 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 10.6 AC timing characteristics for Command, Address and Data Input (1.8V) SPEC PARAMETER SYMBOL UNIT MIN MAX ALE to Data Loading Time tADL 70 - ns ALE Hold Time tALH 5 - ns ALE setup Time tALS 10 - ns #CE Hold Time tCH 5 - ns CLE Hold Time tCLH 5 - ns CLE setup Time tCLS 10 - ns #CE setup Time tCS 20 - ns Data Hold Time tDH 5 - ns Data setup Time tDS 10 - ns Write Cycle Time tWC 25 - ns #WE High Hold Time tWH 10 - ns #WE Pulse Width tWP 12 - ns #WP setup Time tWW 100 - ns Table 10-5 AC timing characteristics for Command, Address and Data Input Note: 1. tADL is the time from the #WE rising edge of final address cycle to the #WE rising edge of first data cycle. 49 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 10.7 AC timing characteristics for Operation (1.8V) SPEC PARAMETER SYMBOL UNIT MIN MAX tAR 10 - ns tCEA - 25 ns #CE HIGH to Output High-Z tCHZ - 50 ns CLE to #RE Delay tCLR 10 - ns #CE HIGH to Output Hold tCOH 15 - ns Output High-Z to #RE LOW tIR 0 - ns Data Transfer from Cell to Data Register tR - 25 s READ Cycle Time tRC 25 - ns #RE Access Time tREA - 22 ns #RE HIGH Hold Time tREH 10 - ns #RE HIGH to Output Hold tRHOH 15 - ns #RE HIGH to #WE LOW tRHW 100 - ns #RE HIGH to Output High-Z(1) tRHZ - 100 ns tRLOH 3 - ns #RE Pulse Width tRP 12 - ns Ready to #RE LOW tRR 20 - ns Reset Time (READ/PROGRAM/ERASE)(2) tRST - 5/10/500 s #WE HIGH to Busy(3) tWB - 100 ns tWHR 80 - ns ALE to #RE Delay #CE Access Time (1) #RE LOW to output hold #WE HIGH to #RE LOW Table 10-6 AC timing characteristics for Operation Notes: AC characteristics may need to be relaxed if I/O drive strength is not set to "full." 1. Transition is measured 200mV from steady-state voltage with load. This parameter is sampled and not 100 % tested 2. Do not issue new command during tWB, even if RY/#BY is ready. 50 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 10.8 Program and Erase Characteristics SPEC PARAMETER SYMBOL UNIT TYP MAX NoP - 4 cycles Page Program time tPROG 250 700 s Busy Time for SET FEATURES /GET FEATURES tFEAT - 1 s Busy Time for program/erase at locked block tLBSY - 3 s Busy Time for OTP program when OTP is protected tOBSY - 30 s Block Erase Time tBERS 2 10 ms tLPROG - - - tDBSY 0.5 1 s Number of partial page programs Last Page Program time (1) Busy Time for Two Plane page program and Two Plane Block Erase Table 10-7 Program and Erase Characteristics Note: 1. tLPROG = Last Page program time (tPROG) + Last -1 Page program time (tPROG) - Last page Address, Command and Data load time. 51 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 11. TIMING DIAGRAMS CLE tCLS tCLH tCH tCS #CE tWP #WE tALS tALH ALE tDS tDH I/Ox Command Don't care Figure 11-1 Command Latch Cycle CLE tCS tCLS tWC #CE tWH tWP #WE tALH tALS ALE tDS I/Ox tDH Address Don't care Undefined Figure 11-2 Address Latch Cycle 52 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z CLE tCLH #CE tCH tALS ALE tWP tWC #WE tWH tDH tDS I/Ox tWP tWP tDS Din 0 tDH tDS Din 1 tDH Din Final1 Don't care Figure 11-3 Data Latch Cycle Note: 1. Din Final = 2,111(x8) #CE tCEA tREA tREA tRP tREA tCHZ tREH tCOH #RE tRHZ tRHOH tRHZ I/Ox Dout tRR Dout Dout tRC RY/#BY Don't care Figure 11-4 Serial Access Cycle after Read 53 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z #CE tCHZ tRC tRP tREH tCOH #RE tRHZ tREA tRLOH tREA tCEA I/Ox Dout tRHOH Dout Dout tRR RY/#BY Don't care Figure 11-5 Serial Access Cycle after Read (EDO) tCLR CLE tCLS tCLH tCS #CE tWP tCH #WE tCEA tRP tWHR #RE tDS tDH I/Ox tIR tREA tCHZ tCOH tRHZ tRHOH Status output 70h Don't care Figure 11-6 Read Status Operation 54 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z CLE tCLR #CE tWC #WE tWB tAR ALE tR tRHZ tRC #RE tRP tRR I/Ox 00h Address(5Cycles) Dout n 30h Dout n+1 Dout m Busy RY/#BY Don't care Figure 11-7 Page Read Operation CLE #CE #RE ALE tR RY/#BY #WE I/Ox 00h Address (4 cycles) 30h Data output Don't care tCEA #CE tREA #RE I/Ox tCHZ tCOH Out Figure 11-8 #CE Don't Care Read Operation 55 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z CLE tCLR #CE tWC #WE tWB tAR tWHR ALE tREA tRC #RE I/Ox tRR 00h 30h Colu mn address n RY/#BY 05h tR E0h Colu mn address m Bu sy Don't care Figure 11-9 Random Data Output Operation 56 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z CLE #CE #WE tAR ALE #RE tWHR I/Ox tREA Byte 0 00h 90h Byte 1 Byte 2 Byte 4 Byte 3 (or 20h) Address, 1 cycle Figure 11-10 Read ID CLE #CE tWC tADL #WE tWB tWHR tPROG ALE #RE I/Ox 80h SERIAL DATA INPUT comman d Col add 1 Col add 2 Row add 1 Row add 2 10h 1 up to m Byte serial inpu t PROGRAM command 70h Status READ STATUS command RY/#BY x8 device:m = 2112 bytes Don't care Figure 11-11 Page Program 57 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z CLE #CE #WE ALE I/Ox 80h Data inpu t Address(4 cycles) tCS Data inpu t 10h tCH #CE tWP #WE Don't care Figure 11-12 #CE Don't Care Page Program Operation 58 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z CLE #CE tADL WC tADL #WE tWB ALE #RE I/Ox 80h Col add 1 Col add 2 Row add1 Row add2 Din N+1 Din Serial Data Inpu t Command Serial INPUT Command RY/#BY 85h Col add1 Col add2 Din N+1 Din Rand om Data Inpu t Colu mn address Command Serial INPUT 10h Program 70h Status tPROG Command Don't care Figure 11-13 Page Program with Random Data Input CLE #CE tADL WC #WE tWB tWB ALE #RE I/Ox Col 00h add 1 Serial data INPUT Command Col add 2 Row add1 Row add2 35h 85h Col add 1 Col add 2 Row add1 Row add2 Din 1 Din n 70h 10h Program tR Command Status tPROG RY/#BY Busy Don't care Figure 11-14 Copy Back 59 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z CLE #CE tWC #WE tWB tBERS ALE #RE I/Ox 60h Address(3cycles) D0h 70h ERASE command RY/#BY Status READ STATUS command Busy BLOCK ERASE SETUP command Don't care Figure 11-15 Block Erase CLE #CE #WE tWB tRST RY/#BY I/Ox FFh RESET command Figure 11-16 Reset 60 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 12. INVALID BLOCK MANAGEMENT 12.1 Invalid blocks The W29N02GW/Z may have initial invalid blocks when it ships from factory. Also, additional invalid blocks may develop during the use of the device. Nvb represents the minimum number of valid blocks in the total number of available blocks (See Table 12.1). An invalid block is defined as blocks that contain one or more bad bits. Block 0, block address 00h is guaranteed to be a valid block at the time of shipment. Parameter Valid block number Symbol Min Max Unit Nvb 2008 2048 blocks Table 12-1 Valid Block Number 12.2 Initial invalid blocks Initial invalid blocks are defined as blocks that contain one or more invalid bits when shipped from factory. Although the device contains initial invalid blocks, a valid block of the device is of the same quality and reliability as all valid blocks in the device with reference to AC and DC specifications. The W29N02GW/Z has internal circuits to isolate each block from other blocks and therefore, the invalid blocks will not affect the performance of the entire device. Before the device is shipped from the factory, it will be erased and invalid blocks are marked. All initial invalid blocks are marked with non-FFh at the first byte of spare area on the 1st or 2nd page. The initial invalid block information cannot be recovered if inadvertently erased. Therefore, software should be created to initially check for invalid blocks by reading the marked locations before performing any program or erase operation, and create a table of initial invalid blocks as following flow chart 61 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z Figure 12-1 Flow chart of create initial invalid block table 12.3 Error in operation Additional invalid blocks may develop in the device during its life cycle. Following the procedures herein is required to guarantee reliable data in the device. After each program and erase operation, check the status read to determine if the operation failed. In case of failure, a block replacement should be done with a bad-block management algorithm. The system has to use a minimum 1-bit ECC per 528 bytes of data to ensure data recovery. Operation Detection and recommended procedure Erase Status read after erase Block Replacement Program Status read after program Block Replacement Read Verify ECC ECC correction Table 12-2 Block failure 62 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z Figure 12-2 Bad block Replacement Note: 1. An error happens in the nth page of block A during program or erase operation. 2. Copy the data in block A to the same location of block B which is valid block. 3. Copy the nth page data of block A in the buffer memory to the nth page of block B 4. Creating or updating bad block table for preventing further program or erase to block A . 12.4 Addressing in program operation The pages within the block have to be programmed sequentially from LSB (least significant bit) page to the MSB (most significant bit) within the block. The LSB is defined as the start page to program, does not need to be page 0 in the block. Random page programming is prohibited. 63 Release Date: May 19, 2015 Preliminary - Revision 0.3 W29N02GW/Z 13. REVISION HISTORY VERSION DATE 0.1 8/22/14 0.2 10/23/14 0.3 05/19/15 06/08/2015 PAGE DESCRIPTION New Create as preliminary 77 79 Update POD Correct Valid Part Numbers Remove Cache operation mode Modified for MCP Datasheet. Table 16-1 History Table Preliminary Designation The "Preliminary" designation on a Winbond datasheet indicates that the product is not fully characterized. The specifications are subject to change and are not guaranteed. Winbond or an authorized sales representative should be consulted for current information before using this product. Trademarks Winbond is trademark of Winbond Electronics Corporation. All other marks are the property of their respective owner. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation where in personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. 64 Release Date: May 19, 2015 Preliminary - Revision 0.3 PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 1. GENERAL DESCRIPTION LPDDR2 is a high-speed SDRAM device internally configured as a 8-Bank memory.These devices contain 1 Gb has 1,073,741,824 bits. All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock. For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access. 2. FEATURES * VDD1 = 1.7~1.95V * Double data rate for data output * VDD2/VDDCA/VDDQ = 1.14V ~ 1.30V * Differential clock inputs * Data width: x32 * Bidirectional differential data strobe * Clock rate: up to 533MHz * Interface: HSUL_12 * Four-bit prefetch DDR architecture * JEDEC LPDDR2-S4B compliance * Eight internal banks for concurrent operation * Support KGD (Known Good Die) form * Programmable READ and WRITE latencies (RL/WL) * Operating Temperature Range * Programmable burst lengths: 4, 8, or 16 Tj : * Per Bank Refresh -25 ~ 85 C * Partial Array Self-Refresh(PASR) -40 ~ 85 C * Deep Power Down Mode (DPD Mode) * Programmable output buffer driver strength * Data mask (DM) for write data * Clock Stop capability during idle periods - 1 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb TABLE OF CONTENTS 1. GENERAL DESCRIPTION ....................................................................................................... 1 2. FEATURES .............................................................................................................................. 1 4. PIN DESCRIPTION .................................................................................................................. 7 4.1 Signal Description .............................................................................................................................7 5. BLOCK DIAGRAM ................................................................................................................... 9 6. FUNCTIONAL DESCRIPTION ............................................................................................... 10 6.1 Simplified LPDDR2 State Diagram .................................................................................................10 6.1.1 Figure of Simplified LPDDR2 Bus Interface State Diagram................................................................. 11 6.2 Power-up, Initialization, and Power-Off ...........................................................................................12 6.2.1 Power Ramp and Device Initialization ................................................................................................. 12 6.2.2 Timing Parameters for initialization ...................................................................................................... 14 6.2.3 Figure of Power Ramp and Initialization Sequence ............................................................................. 14 6.2.4 Initialization after Reset (without Power ramp) .................................................................................... 15 6.2.5 Power-off Sequence............................................................................................................................. 15 6.2.6 Timing Parameters Power-Off ............................................................................................................. 15 6.2.7 Uncontrolled Power-Off Sequence ...................................................................................................... 15 6.3 Mode Register Definition .................................................................................................................16 6.3.1 Mode Register Assignment and Definition ........................................................................................... 16 6.3.1.1 Table of Mode Register Assignment...........................................................................................................16 6.3.2 MR0_Device Information (MA[7:0] = 00H) ........................................................................................... 17 6.3.3 MR1_Device Feature 1 (MA[7:0] = 01H) ............................................................................................. 17 6.3.3.1 1 Table of Burst Sequence by Burst Length (BL), Burst Type (BT), and Warp Control (WC) .....................18 6.3.3.2 Table of Non Wrap Restrictions ..................................................................................................................18 6.3.4 MR2_Device Feature 2 (MA[7:0] = 02H) ............................................................................................. 19 6.3.5 MR3_I/O Configuration 1 (MA[7:0] = 03H) ........................................................................................... 19 6.3.6 MR4_Device Temperature (MA[7:0] = 04H ) ....................................................................................... 19 6.3.7 MR5_Basic Configuration 1 (MA[7:0] = 05H) ....................................................................................... 20 6.3.8 MR6_Basic Configuration 2 (MA[7:0] = 06H) ....................................................................................... 20 6.3.9 MR7_Basic Configuration 3 (MA[7:0] = 07H) ....................................................................................... 20 6.3.10 MR8_Basic Configuration 4 (MA[7:0] = 08H)..................................................................................... 20 6.3.11 MR9_Test Mode (MA[7:0] = 09H) ...................................................................................................... 20 6.3.12 MR10_Calibration (MA[7:0] = 0AH) ................................................................................................. 20 6.3.13 MR16_PASR_Bank Mask (MA[7:0] = 10H) ....................................................................................... 21 6.3.14 MR17_PASR_Segment Mask (MA[7:0] = 11H) ................................................................................. 21 6.3.15 MR32_DQ Calibration Pattern A (MA[7:0] = 20H) ............................................................................. 22 6.3.16 MR40_DQ Calibration Pattern B (MA[7:0] = 28H) ............................................................................. 22 6.3.17 MR63_Reset (MA[7:0] = 3FH): MRW only ......................................................................................... 22 6.4 Command Definitions and Timing Diagram ....................................................................................23 6.4.1 LPDDR2-S4: Activate Command . ............................................................................................... 23 6.4.1.1 Figure of LPDDR2-S4 : Activate command cycle : tRCD=3,tRP=3,tRRD=2 ..............................................23 6.4.1.2 Figure of LPDDR2-S4: tFAW timing ...........................................................................................................24 6.4.1.3 Figure of LPDDR2 Command Input Setup and Hold Timing ......................................................................24 6.4.1.4 Figure of LPDDR2 CKE Input Setup and Hold Timing................................................................................25 6.4.2 LPDDR2-S4: Read and Write access modes ...................................................................................... 25 6.4.3 Burst Read command .......................................................................................................................... 25 6.4.3.1 Figure of Data output(read)timing(tDQSCKmax) ........................................................................................26 6.4.3.2 Figure of Data output(read)timing(tDQSCKmin) .........................................................................................27 6.4.3.3 Figure of LPDDR2-S4 : Burst read : RL = 5. BL = 4. tDQSCK > tCK .........................................................27 6.4.3.4 Figure of LPDDR2-S4 : Burst read : RL = 3. BL = 8. tDQSCK < tCK .......................................................28 6.4.3.5 Figure of LPDDR2: tDQSCKDL timing .......................................................................................................28 6.4.3.6 Figure of LPDDR2: tDQSCKDM timing ......................................................................................................29 6.4.3.7 Figure of LPDDR2: tDQSCKDS timing .......................................................................................................29 6.4.3.8 LPDDR2-S4 : Burst read followed by burst write: RL = 3, WL = 1, BL = 4 .................................................30 - 2 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.3.9 Figure of LPDDR2-S4 : Seamless burst read : RL = 3, BL= 4, tCCD=2 .....................................................30 6.4.4 Reads interrupted by a read ................................................................................................................ 31 6.4.4.1 Figure of LPDDR2-S4 : Read burst interrupt example : RL = 3, BL= 8, tCCD=2 ........................................31 6.4.5 Burst Write operation ........................................................................................................................... 31 6.4.5.1 Data input (write) timing..............................................................................................................................32 6.4.5.2 LPDDR2-S4 : Burst write : WL = 1, BL= 4 ..................................................................................................32 6.4.5.3 LPDDR2-S4 : Burst wirte followed by burst read : RL = 3, WL= 1, BL=4 ...................................................33 6.4.5.4 LPDDR2-S4 : Seamless burst write : WL= 1, BL=4, tCCD=2 .....................................................................33 6.4.6 Writes interrupted by a write ................................................................................................................ 34 6.4.6.1 LPDDR2-S4 : Write burst interrupt timing : WL= 1, BL=8, tCCD=2 ............................................................34 6.4.7 Burst Terminate .................................................................................................................................... 34 6.4.7.1 LPDDR2-S4 : Write burst truncated by BST : WL= 1, BL=16 .....................................................................35 6.4.7.2 LPDDR2-S4 : Burst Read truncated by BST : RL= 3, BL=16 .....................................................................35 6.4.8 Write data mask ................................................................................................................................... 36 6.4.8.1 LPDDR2-S4 : Write data mask ...................................................................................................................36 6.4.9 LPDDR2-S4: Precharge operation....................................................................................................... 37 6.4.9.1 Table of Bank selection for Precharge by address bits...............................................................................37 6.4.10 LPDDR2-S4: Burst Read operation followed by Precharge .............................................................. 37 6.4.10.1 Figure of LPDDR2-S4 Burst read followed by Precharge : RL= 3, BL=8, RU(tRTP(min)/tCK) = 2 ...........38 6.4.10.2 Figure of LPDDR2-S4 : Burst read followed by Precharge : RL= 3, BL=4, RU(tRTP(min)/tCK)=3 ...........38 6.4.11 LPDDR2-S4: Burst Write followed by Precharge ............................................................................... 39 6.4.11.1 Figure of LPDDR2-S4 : Burst write follwed by precharge : WL = 1, BL= 4 ...............................................39 6.4.12 LPDDR2-S4: Auto Precharge operation ............................................................................................ 40 6.4.13 LPDDR2-S4: Burst Read with Auto-Precharge.................................................................................. 40 6.4.13.1 Figure of LPDDR2-S4 : Burst read with Auto-Precharge : RL= 3, BL=4, RU(tRTP(min)/tCK)=2 ..............40 6.4.14 LPDDR2-S4: Burst write with Auto-Precharge................................................................................... 41 6.4.14.1 Figure of LPDDR2-S4 : Burst write w/Auto precharge : WL = 1, BL= 4 ....................................................41 6.4.14.2 Table of LPDDR2-S4 Precharge & Auto Precharge Clarification .............................................................42 6.4.15 LPDDR2-S4: Refresh command ........................................................................................................ 43 6.4.15.1 Table of Command Scheduling Separations related to Refresh ...............................................................44 6.4.16 LPDDR2 SDRAM Refresh Requirements .......................................................................................... 44 6.4.16.1 Figure of LPDDR2-S4 : Definition of tSRF................................................................................................45 6.4.16.2 Figure of LPDDR2-S4 Regular, Distributed Refresh Pattern vs. Repetitive Burst Refresh with Subsequent Refresh Pause........................................................................................................................................................46 6.4.16.3 Figure of LPDDR2-S4: Allowable Transition from Repetitive Burst Refresh with Subsequent Refresh Pause to Regular, Distributed Refresh Pattern.......................................................................................................47 6.4.16.4 Figure of LPDDR2-S4: NOT-Allowable Transition from Repetitive Burst Refresh with Subsequent Refresh Pause to Regular, Distributed Refresh Pattern .........................................................................................47 6.4.16.5 Figure of LPDDR2-S4: Recommended Self-refresh entry and exit in conjunction with a Burst/Pause Refresh patterns. ....................................................................................................................................................48 6.4.16.6 Figure of LPDDR2-S4 All Bank Refresh Operation ..................................................................................48 6.4.16.7 Figure of LPDDR2-S4 Per Bank Refresh Operation .................................................................................49 6.4.17 LPDDR2-S4: Self Refresh operation ................................................................................................. 50 6.4.17.1 Figure of LPDDR2-S4 : Self Refresh Operation .......................................................................................51 6.4.18 LPDDR2-S4: Partial Array Self-Refresh: Bank Masking.................................................................... 51 6.4.19 LPDDR2-S4: Partial Array Self-Refresh: Segment Masking ............................................................. 51 6.4.20 Mode Register Read Command ........................................................................................................ 52 6.4.20.1 Figure of Mode Register Read timing example : RL = 3, tMRR = 2 ..........................................................53 6.4.20.2 Figure of LPDDR2 Read to MRR timing example : RL = 3, tMRR = 2 ......................................................54 6.4.20.3 Figure of LPDDR2 : Burst Write Followed by MRR : RL = 3, WL = 1, BL = 4 ...........................................54 6.4.21 Temperature Sensor .......................................................................................................................... 55 6.4.21.1 Figure of Temp Sensor Timing .................................................................................................................56 6.4.21.2 DQ Calibration ..........................................................................................................................................56 6.4.21.3 Figure of MR32 and MR40 DQ Calibration timing example: RL = 3, tMRR = 2 ........................................57 6.4.22 Mode Register Write Command ......................................................................................................... 58 Publication Release : July 15, 2014 - 3 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.22.1 Figure of Mode Register Write timing example : RL = 3, tMRW = 5 .........................................................58 6.4.22.2 Truth Table for Mode Register Read (MRR) and Mode Register Write (MRW) ........................................58 6.4.23 Mode Register Write Reset (MRW Reset) ......................................................................................... 59 6.4.24 Mode Register Write ZQ Calibration Command ................................................................................ 59 6.4.24.1 Figure of ZQ Calibration Initialization timing example...............................................................................60 6.4.24.2 Figure of ZQ Calibration Short timing example .........................................................................................60 6.4.24.3 Figure of ZQ Calibration Long timing example .........................................................................................61 6.4.24.4 Figure of ZQ Calibration Reset timing example ........................................................................................61 6.4.25 ZQ External Resistor Value, Tolerance, and Capacitive Loading...................................................... 62 6.4.26 Power-down ....................................................................................................................................... 62 6.4.26.1 Figure of LPDDR2-S4 : Basic power down entry and exit timing diagram ................................................62 6.4.26.2 Figure of Example of CKE intensive environment ....................................................................................63 6.4.26.3 Figure of Refresh to Refresh timing with CKE intensive environment for LPDR2 SDRAM .......................63 6.4.26.4 Figure of Read to power - down entry......................................................................................................64 6.4.26.5 Figure of LPDDR2 SDRAM Read with auto precharge to power-down entry ...........................................64 6.4.26.6 Figure of Write to power-down entry.........................................................................................................65 6.4.26.7 Figure of LPDDR2-S4: Write with autoprecharge to power-down entry....................................................65 6.4.26.8 Figure of LPDDR2-S4 Refresh command to power-down entry ...............................................................66 6.4.26.9 Figure of Activate command to power-down entry ...................................................................................66 6.4.26.10 Figure of Precharge/Precharge-all command to power-down entry .....................................................66 6.4.26.11 Figure of Mode Register Read to power-down entry ..............................................................................67 6.4.26.12 Figure of MRW command to power-down entry .....................................................................................67 6.4.27 LPDDR2-S4: Deep Power-Down ....................................................................................................... 67 6.4.27.1 Figure of LPDDR2-S4 Deep power down entry and exit timing diagram ..................................................68 6.4.28 Input clock stop and frequency change ............................................................................................. 68 6.4.29 No Operation command ..................................................................................................................... 69 6.4.30 Truth tables ........................................................................................................................................ 69 6.4.31 Command truth table.......................................................................................................................... 70 6.4.32 LPDDR2-SDRAM Truth Tables ......................................................................................................... 71 6.4.32.1 Table of LPDDR2-S4 : CKE Table............................................................................................................71 6.4.32.2 Table of Current State Bank n - Command to Bank n ..............................................................................72 6.4.32.3 Tableof Current State Bank n - Command to Bank m ..............................................................................74 6.4.33 Data mask truth table ......................................................................................................................... 75 7. ELECTRICAL CHARACTERISTIC ........................................................................................ 76 7.1 Absolute Maximum DC Ratings ......................................................................................................76 7.2 AC & DC operating conditions ........................................................................................................76 7.2.1 Recommended DC Operating Conditions............................................................................................ 76 7.2.1.1 Recommended DC Operating Conditions ..................................................................................................76 7.2.2 Input Leakage Current ......................................................................................................................... 77 7.2.3 Operating Temperature Conditions...................................................................................................... 77 7.2.4 AC and DC Input Measurement Levels ............................................................................................... 77 7.2.4.1 AC and DC Logic Input Levels for Single-Ended Signals ...........................................................................77 7.2.4.1.1 Table of Single-Ended AC and DC Input Levels for CA and CS_n Inputs............................................................. 77 7.2.4.1.2 Table of Single-Ended AC and DC Input Levels for CKE ...................................................................................... 78 7.2.4.1.3 Table of Single-Ended AC and DC Input Levels for DQ and DM .......................................................................... 78 7.2.4.2 Vref Tolerances ..........................................................................................................................................78 7.2.4.2.1 Figure of Illustration of VRef(DC) tolerance and VRef ac-noise limits ................................................................... 79 7.2.4.3 Input Signal ................................................................................................................................................80 7.2.4.3.1 LPDDR2-466 to LPDDR2-1066 Input Signal ......................................................................................................... 80 7.2.4.3.2 LPDDR2-200 to LPDDR2-400 Input Signal ........................................................................................................... 81 7.2.4.4 AC and DC Logic Input Levels for Differential Signals................................................................................82 7.2.4.4.1 Differential signal definition .................................................................................................................................... 82 7.2.4.4.2 Differential swing requirements for clock and strobe ............................................................................................. 82 7.2.4.5 Single-ended requirements for differential signals ......................................................................................83 7.2.4.6 Differential Input Cross Point Voltage .........................................................................................................84 - 4 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.2.4.7 Slew Rate Definitions for Single-Ended Input Signals ................................................................................85 7.2.4.8 Slew Rate Definitions for Differential Input Signals ....................................................................................85 7.2.5 AC and DC Output Measurement Levels............................................................................................. 86 7.2.5.1 Single Ended AC and DC Output Levels ....................................................................................................86 7.2.5.2 Differential AC and DC Output Levels ........................................................................................................86 7.2.5.3 Single Ended Output Slew Rate .................................................................................................................86 7.2.5.4 Differential Output Slew Rate .....................................................................................................................88 7.2.5.5 Overshoot and Undershoot Specifications .................................................................................................89 7.2.6 Output buffer characteristics ................................................................................................................ 90 7.2.6.1 HSUL_12 Driver Output Timing Reference Load .......................................................................................90 7.2.6.2 RONPU and RONPD Resistor Definition....................................................................................................90 7.2.6.3 RONPU and RONPD Characteristics with ZQ Calibration..........................................................................91 7.2.6.3.1 Output Driver Temperature and Voltage Sensitivity .............................................................................................. 91 7.2.6.4 RONPU and RONPD Characteristics without ZQ Calibration.....................................................................92 7.2.6.5 RZQ I-V Curve ............................................................................................................................................93 7.2.7 Input/Ouput Capacitance ..................................................................................................................... 95 7.3 IDD Specification Parameters and Test Conditions ........................................................................96 7.3.1 IDD Measurement Conditions .............................................................................................................. 96 7.3.1.1 Table of Definition of Switching for CA Input Signals .................................................................................96 7.3.1.2 Table of Definition of Switching for IDD4R .................................................................................................97 7.3.1.3 Table of Definition of Switching for IDD4W .................................................................................................97 7.3.2 IDD Specifications ................................................................................................................................ 98 7.3.2.1 Table of LPDDR2 IDD Specification Parameters and Operating Conditions (x32) ................................98 7.3.2.2 Table of IDD6 Partial Array Self-Refresh Current .....................................................................................100 7.4 Clock Specification ........................................................................................................................100 7.4.1 Definition for tCK(avg) and nCK ......................................................................................................... 100 7.4.2 Definition for tCK(abs) ........................................................................................................................ 100 7.4.3 Definition for tCH(avg) and tCL(avg) .................................................................................................. 101 7.4.4 Definition for tJIT(per) ........................................................................................................................ 101 7.4.5 Definition for tJIT(cc) .......................................................................................................................... 101 7.4.6 Definition for tERR(nper) .................................................................................................................... 101 7.4.7 Definition for duty cycle jitter tJIT(duty) .............................................................................................. 102 7.4.8 Definition for tCK(abs), tCH(abs) and tCL(abs) ................................................................................. 102 7.4.9 Period Clock Jitter .............................................................................................................................. 102 7.4.9.1 Clock period jitter effects on core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW ) .......................................................................................................................................................102 7.4.9.2 Cycle time de-rating for core timing parameters .......................................................................................102 7.4.9.3 Clock Cycle de-rating for core timing parameters .....................................................................................103 7.4.9.4 Clock jitter effects on C/A timing (tIS,tIH,tISCKE,tIHCKE,tISb, tIHb, tISCKEb, tIHCKEb) ........................103 7.4.9.5 Clock jitter effects on Read timing tRPRE ................................................................................................103 7.4.9.6 Clock jitter effects on Read timing tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) ............................103 7.4.9.7 Clock jitter effects on Read timing parameters tQSH, tQSL .....................................................................103 7.4.9.8 Clock jitter effects on Read timing parameters tRPST..............................................................................104 7.4.9.9 Clock jitter effects on Write timing parameters tDS, tDH ..........................................................................104 7.4.9.10 Clock jitter effects on Write timing parameters tDSS, tDSH ...................................................................104 7.4.9.11 Clock jitter effects on Write timing parameters tDQSS ...........................................................................104 7.5 Refresh Requirements ..................................................................................................................105 7.5.1 LPDDR2-S4 Refresh Requirement Parameters ................................................................................ 105 7.6 AC Timings ...................................................................................................................................106 7.6.1 Table of LPDDR2 AC Timing ............................................................................................................. 106 7.6.2 CA and CS_n Setup, Hold and Derating............................................................................................ 114 7.6.2.1 Table of CA and CS_n Setup and Hold Base-Values for 1V/ns ...............................................................115 7.6.2.2 Table of Derating values LPDDR2 tIS/tIH - ac/dc based AC220 ............................................................115 7.6.2.3 Table of Derating values LPDDR2 tIS/tIH - ac/dc based AC300 ..............................................................116 7.6.2.4 Table of Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition ......................................116 - 5 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6.2.5 Figure of nominal slew rate and tVAC for tIS for CA and CS_n with respect to clock. .............................117 7.6.2.6 Figure of nominal slew rate for hold time tIH for CA and CS_n with respect to clock ...............................118 7.6.2.7 Figure of tangent line for setup time tIS for CA and CS_n with respect to clock .......................................119 7.6.2.8 Figure of tangent line for for hold time tIH for CA and CS_n with respect to clock ...................................120 7.6.3 Data Setup, Hold and Slew Rate Derating......................................................................................... 121 7.6.3.1 Table of Data Setup and Hold Base-Values .............................................................................................121 7.6.3.2 Table of Derating values LPDDR2 tDS/tDH - ac/dc based AC220 ...........................................................122 7.6.3.3 Table of Derating values LPDDR2 tDS/tDH - ac/dc based AC300 ...........................................................122 7.6.3.4 Table of Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition ......................................123 7.6.3.5 Figure of nominal slew rate and tVAC for setup time tDS for DQ with respect to strobe ..........................124 7.6.3.6 Figure of nominal slew rate for hold time tDH for DQ with respect to strobe ............................................125 7.6.3.7 Figure of tangent line for setup time tDS for DQ with respect to strobe ....................................................126 7.6.3.8 Figure of tangent line for for hold time tDH for DQ with respect to strobe ................................................127 8. REVISION HISTORY ............................................................................................................ 128 - 6 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 4. PIN DESCRIPTION 4.1 Signal Description Name Type Description Clock: CK_t and CK_c are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on both positive and negative edge of CK_t. Single Data Rate (SDR) inputs, CS_n and CKE, are sampled CK_t, CK_c Input at the positive Clock edge. Clock is defined as the differential pair, CK_t and CK_c. The positive Clock edge is defined by the crosspoint of a rising CK_t and a falling CK_c. The negative Clock edge is defined by the crosspoint of a falling CK_t and a rising CK_c. Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device CKE Input input buffers and output drivers. Power savings modes are entered and exited through CKE transitions.CKE is considered part of the command code. CKE is sampled at the positive Clock edge. CS_n Input CA[n:0] Input DQ[n:0] I/O Chip Select: CS_n is considered part of the command code and CS_n is sampled at the positive Clock edge. DDR Command/Address Inputs: Uni-directional command/address bus inputs. CA is considered part of the command code. Data Inputs/Output: Bi-directional data bus. n=15 for 16 bits DQ; n=31 for 32 bits DQ. Data Strobe (Bi-directional, Differential): DQSn_t, DQSn_c I/O The data strobe is bi-directional (used for read and write data) and differential (DQS_t and DQS_c). It is output with read data and input with write data. DQS_t is edge-aligned to read data and centered with write data. For x32 DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7, DQS1_t and DQS1_c to the data on DQ8 - DQ15, DQS2_t and DQS2_c to the data on DQ16 - DQ23, DQS3_t and DQS3_c to the data on DQ24 - DQ31. Input Data Mask: DM is the input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS_t. Although DM is for input only, the DM loading shall match the DQ and DQS (or DQS_c). DM0 is the input data mask signal for the data on DQ0-7. For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is the input data mask signal for the data on DQ24-31. DMn Input VDD1 VDD2 VDDCA VDDQ Supply Core Power Supply 1: Power supply for core. VREF(CA) Supply VREF(DQ) Supply VSS VSSCA VSSQ ZQ Supply Ground Supply Ground for CA Input Receivers Supply I/O Ground I/O Reference Pin for Output Drive Strength Calibration TQ (option) Output GOHIZ (option) Supply Core Power Supply 2: Power supply for core. Supply Input Receiver Power Supply: Power supply for CA[n:0], CKE, CS_n, CK_t, and CK_c Supply I/O Power Supply: Power supply for Data input/output buffers. Input input buffers. Reference Voltage for CA Command and Control Input Receiver: Reference voltage for all CA[n:0], CKE, CS_n, CK_t, and CK_c input buffers. Reference Voltage for DQ Input Receiver: Reference voltage for all DQ input buffers: Reference voltage for all Data input buffers. Temperature sensor output: Asynchronous, HSUL_12 level output. It is logic-HIGH when device temperature equals or exceeds 85C. It is logic-LOW when device temperature is less than 85C.The drive strength is same as DQ (40 ohm). Asynchronous, HSUL_12 level input. When logic High, all outputs of device are in Hi-Z state, when Low, device is in normal operation. When GOHIZ pad transitions from Low to High, all outputs will enter Hi-z within tgo-hiz. When GOHIZ pad transitions from High to Low, all outputs will return to normal function within texit-hiz. The tgo-hiz and texit-hiz are to be defined. Internal pulldown is implemented. E-fuse option is provided to change GOHIZ's polarity(from active HIGH to active Low). Note : Data includes DQ and DM. - 7 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 4.2 Addressing Table Density 1Gb Number of Banks 8 Bank Addresses BA0-BA2 tREFI(us) (*2) 7.8 Row Addresses R0-R12 Column Addresses*1 C0-C8 X32 Note 1.The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero. 2. tREFI values for all bank refresh is Tj = -40~85C. 3. Row and Column Address values on the CA bus that are not used are "don't care." - 8 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 5. BLOCK DIAGRAM CK_c CK_t CLOCK BUFFER CKE CONTROL SIGNAL COMMAND COLUMN DECODER GENERATOR R O W DECODER CA0 MODE REGISTER CA9 ADDRESS D E C O R D E R CELL ARRAY BANK #7 BANK #0 BUFFER SENSE AMPLIFIER Power GND ZQ REFRESH COUNTER COLUMN COUNTER DATA CONTROL CIRCUIT - 9 - DQ BUFFER DQ , DQS_t , DQS_c DM Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6. FUNCTIONAL DESCRIPTION LPDDR2-S4 devices use a double data rate architecture on the DQ pins to achieve highspeed operation. The double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR2-S4 effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal SDRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Prior to normal operation, the LPDDR2 device must be initialized. The following section provides detailed information covering device initialization, register definition, command description and device operation. 6.1 Simplified LPDDR2 State Diagram LPDDR2-SDRAM state diagram provides a simplified illustration of allowed state transitions and the related commands to control them. For a complete definition of the device behavior, the information provided by the state diagram should be integrated with the truth tables and timing specification. The truth tables provide complementary information to the state diagram, they clarify the device behavior and the applied restrictions when considering the actual state of all the banks. - 10 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.1.1 Figure of Simplified LPDDR2 Bus Interface State Diagram Power Applied Resetting MR Reading Deep Power Down DPDX Power On Reset Automatic Sequence Command Sequence MRR Resetting DPD PD PDX Resetting Power Down Self Refreshing SREF SREFX Reset Idle MR Reading MRR REF Idle MRW PDX MR Writing Active Power Down ACT PD Idle Power Down MRR PDX Refreshing Active MR Reading PR,PRA PD Active*1 BST RD WR WR Writing RD Reading WRA RDA WRA RDA PR,PRA Writing With Autoprecharge PR(A)=Precharge (All) ACT=Activate WR(A)=Write(with Autoprecharge) RD(A)=Read (with Autoprecharge) BST=Burst Terminate Reset=Reset is achieved through MRW command MRW=Mode Register Write MRR=Mode Register Read PD=Enter Power Down PDX=Exit Power Down SREF=Enter Self Refresh SREFX=Exit Self Refresh DPD=Enter Deep Power Down DPDX=Exit Deep Power Down REF=Refresh BST Reading With Autoprecharge Precharging Note : For LPDDR2-SDRAM in the Idle state, all banks are precharged - 11 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.2 Power-up, Initialization, and Power-Off The LPDDR2 Devices must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. 6.2.1 Power Ramp and Device Initialization The following sequence shall be used to power up an LPDDR2 device. Unless specified otherwise, these steps are mandatory. 1. Power Ramp While applying power (after Ta), CKE shall be held at a logic low level (=<0.2xVDDCA), all other inputs shall be between VILmin and VIHmax. The LPDDR2 device will only guarantee that outputs are in a high impedance state while CKE is held low. On or before the completion of the power ramp (Tb) CKE must be held low. DQ, DM, DQS_t and DQS_c voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid latchup. CK_t, CK_c, CS_n, and CA input levels must be between VSSCA and VDDCA during voltage ramp to avoid latch-up. The following conditions apply: Ta is the point where any power supply first reaches 300mV. After Ta is reached, VDD1 must be greater than VDD2 - 200mV. After Ta is reached, VDD1 and VDD2 must be greater than VDDCA - 200mV. After Ta is reached, VDD1 and VDD2 must be greater than VDDQ - 200mV. After Ta is reached, VREF must always be less than all other supply voltages. The voltage difference between any of VSS, VSSQ, and VSSCA pins may not exceed 100mV. The above conditions apply between Ta and power-off (controlled or uncontrolled). Tb is the point when all supply voltages are within their respective min/max operating conditions. Reference voltages shall be within their respective min/max operating conditions a minimum of 5 clocks before CKE goes high. Power ramp duration tINIT0 (Tb - Ta) must be no greater than 20 ms. 2. CKE and clock Beginning at Tb, CKE must remain low for at least tINIT1 = 100 ns, after which it may be asserted high. Clock must be stable at least tINIT2 = 5 x tCK prior to the first low to high transition of CKE (Tc). CKE, CS_n and CA inputs must observe setup and hold time (tIS, tIH) requirements with respect to the first rising clock edge (as well as to the subsequent falling and rising edges). The clock period shall be within the range defined for tCKb (18 ns to 100 ns), if any Mode Register Reads are performed. Mode Register Writes can be sent at normal clock operating frequencies so long as all AC Timings are met. Furthermore, some AC parameters (e.g. tDQSCK) may have relaxed timings (e.g. tDQSCKb) before the system is appropriately configured. While keeping CKE high, issue NOP commands for at least tINIT3 = 200 us. (Td). - 12 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 3. Reset command After tINIT3 is satisfied, a MRW(Reset) command shall be issued (Td). The memory controller may optionally issue a Precharge-All command prior to the MRW Reset command. Wait for at least tINIT4 = 1 s while keeping CKE asserted and issuing NOP commands. 4. Mode Registers Reads and Device Auto-Initialization (DAI) polling: After tINIT4 is satisfied (Te) only MRR commands and power-down entry/exit commands are allowed. Therefore, after Te, CKE may go low in accordance to Power-Down entry and exit specification. The MRR command may be used to poll the DAI-bit to acknowledge when Device Auto-Initialization is complete or the memory controller shall wait a minimum of tINIT5 before proceeding. As the memory output buffers are not properly configured yet, some AC parameters may have relaxed timings before the system is appropriately configured. After the DAI-bit (MR#0, "DAI") is set to zero "DAI complete" by the memory device, the device is in idle state (Tf). The state of the DAI status bit can be determined by an MRR command to MR#0. The LPDDR2 SDRAM device will set the DAI-bit no later than tINIT5 (10 us) after the Reset command. The memory controller shall wait a minimum of tINIT5 or until the DAI-bit is set before proceeding. After the DAI-Bit is set, it is recommended to determine the device type and other device characteristics by issuing MRR commands (MR0 "Device Information" etc.). 5. ZQ Calibration: After tINIT5 (Tf), an MRW ZQ Initialization Calibration command may be issued to the memory. This command is used to calibrate the LPDDR2 output drivers (RON) over process, voltage, and temperature variations. Optionally, the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connection. In systems in which more than one LPDDR2 device exists on the same bus, the controller must not overlap ZQ Calibration commands. The device is ready for normal operation after tZQINIT. 6. Normal Operation: After tZQINIT (Tg), MRW commands may be used to properly configure the memory, for example the output buffer driver strength, latencies etc. Specifically, MR1, MR2, and MR3 shall be set to configure the memory for the target frequency and memory configuration. The LPDDR2 device will now be in IDLE state and ready for any valid command. After Tg, the clock frequency may be changed according to the clock frequency change procedure. - 13 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.2.2 Timing Parameters for initialization Symbol tINIT0 tINIT1 tINIT2 tINIT3 tINIT4 tINIT5 tZQINIT tCKb Value min max 20 100 5 200 1 10 1 18 100 Unit ms ns tCK s s s s ns Comment Maximum Power Ramp Time Minimum CKE low time after completion of power ramp Minimum stable clock before first CKE high Minimum Idle time after first CKE assertion Minimum Idle time after Reset command Maximum duration of Device Auto-Initialization ZQ Initial Calibration for LPDDR2-S4 Clock cycle time during boot 6.2.3 Figure of Power Ramp and Initialization Sequence Ta Tb Td Tc Te Tf Tg tINIT2 CK_t / CK_c tINIT0 Supplies tINIT3 tINIT1 CKE PD tISCKE tINIT5 tZQINIT tINIT4 CA* RESET MRR ZQC Valid DQ *Midlevel on CA bus means : valid NOP - 14 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.2.4 Initialization after Reset (without Power ramp) If the RESET command is issued outside the power up initialization sequence, the reinitialization procedure shall begin with step 3 (Td). 6.2.5 Power-off Sequence The following sequence shall be used to power off the LPDDR2 device. While removing power, CKE shall be held at a logic low level (=< 0.2 x VDDCA), all other inputs shall be between VILmin and VIHmax. The LPDDR2 device will only guarantee that outputs are in a high impedance state while CKE is held low. DQ, DM, DQS_t and DQS_c voltage levels must be between VSSQ and VDDQ during power off sequence to avoid latch-up. CK_t, CK_c, CS_n and CA input levels must be between VSSCA and VDDCA during power off sequence to avoid latch-up. Tx is the point where any power supply decreases under its minimum value specified in the DC operating condition table. Tz is the point where all power supplies are below 300 mV. After Tz, the device is powered off. The time between Tx and Tz (tPOFF) shall be less than 2s. The following conditions apply: Between Tx and Tz, VDD1 must be greater than VDD2 - 200 mV. Between Tx and Tz, VDD1 and VDD2 must be greater than VDDCA - 200 mV. Between Tx and Tz, VDD1 and VDD2 must be greater than VDDQ - 200 mV. Between Tx and Tz, VREF must always be less than all other supply voltages. The voltage difference between any of VSS, VSSQ, and VSSCA pins may not exceed 100 mV. 6.2.6 Timing Parameters Power-Off Symbol tPOFF Value min max 2 Unit s Comment Maximum Power-Off Ramp Time 6.2.7 Uncontrolled Power-Off Sequence The following sequence shall be used to power off the LPDDR2 device under uncontrolled condition. Tx is the point where any power supply decreases under its minimum value specified in the DC operating condition table. After turning off all power supplies, any power supply current capacity must be zero, except for any static charge remaining in the system. Tz is the point where all power supply first reaches 300 mV. After Tz, the device is powered off. The time between Tx and Tz shall be less than 2s. The relative level between supply voltages are uncontrolled during this period. VDD1 and VDD2 shall decrease with a slope lower than 0.5 V/us between Tx and Tz. Uncontrolled power off sequence can be applied only up to 400 times in the life of the device. - 15 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.3 Mode Register Definition 6.3.1 Mode Register Assignment and Definition Each register is denoted as "R" if it can be read but not written, "W" if it can be written but not read, and "R/W" if it can be read and written. Mode Register Read command shall be used to read a register. Mode Register Write command shall be used to write a register. 6.3.1.1 Table of Mode Register Assignment MR# MA[7:0] Function 0 00H 01H Device Info. R (RFU) Device Feature 1 W nWR (for AP) Device Feature 2 W (RFU) RL & WL go to MR2 I/O Config-1 W (RFU) DS go to MR3 1 2 3 4 5 6 7 8 9 10 11-15 16 17 18-19 20-31 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH~0FH 10H 11H 12H~13H 14h-1Fh 32 20H 33-39 21H~27H 40 28H 41-47 48-62 63 64-126 127 29H~2FH 30H~3EH 3FH 40H~7EH 7FH 128-190 80H~BEH 191 BFH 192-254 C0H~FEH 255 FFH Access OP7 OP6 TUF OP5 OP4 OP3 RZQI WC OP2 OP1 OP0 Link DI DAI go to MR0 DNVI BT BL (RFU) go to MR1 Refresh Rate R Basic Config-1 R LPDDR2 Manufacturer ID go to MR5 Basic Config-2 R Revision ID1 go to MR6 Basic Config-3 R Revision ID2 go to MR7 Density Type go to MR4 Basic Config-4 R Test Mode W Vendor-Specific Test Mode go to MR9 I/O Calibration W Calibration Code go to MR10 (reserved) W W (RFU) PASR_Bank PASR_Seg (Reserved) I/O width Refresh Rate go to MR8 Bank Mask Segment Mask (RFU) go to MR16 go to MR17 See "DQ Calibration" go to MR32 R See "DQ Calibration" go to MR40 W - (RFU) X (RFU) go to MR63 - (RFU) Reserved for NVM DQ Calibration Pattern A (Do Not Use) DQ Calibration Pattern B (Do Not Use) (Reserved) Reset (Reserved) (Do Not Use) (Reserved for Vendor Use) (Do Not Use) (Reserved for Vendor Use) (Do Not Use) R - - (RFU) - Note 1. RFU bits shall be set to `0' during Mode Register writes. 2. RFU bits shall be read as `0' during Mode Register reads. 3. All Mode Registers that are specified as RFU or write-only shall return undefined data when read and DQS shall be toggled. 4. All Mode Registers that are specified as RFU shall not be written. 5. Writes to read-only registers shall have no impact on the functionality of the device. - 16 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.3.2 MR0_Device Information (MA[7:0] = 00H) OP7 OP6 OP5 OP4 (RFU) OP3 OP2 RZQI DNVI DAI (Device Auto-Initialization Status) Read-only OP0 DI (Device Information) Read-only OP1 DNVI (Data Not Valid Information) Read-only OP2 OP1 OP0 DI DAI 0b: DAI complete 1b: DAI still in progress 0b: SDRAM 1b: NVM LPDDR2 SDRAM will not implement DNV functionalit 00b: RZQ self test not executed. RZQI (Built in Self Test for RZQ Information) 01b: ZQ-pin may connect to VDDCA or float Read-only OP[4:3] 10b: ZQ-pin may short to GND 11b: ZQ-pin self test completed, no error condition detected (ZQ-pin may not connect to VDDCA or float nor short to GND) Note 1. RZQI will be set upon completion of the MRW ZQ Initialization Calibration command. 2.If ZQ is connected to VDDCA to set default calibration, OP[4:3] shall be set to 01. If ZQ is not connected to VDDCA, either OP[4:3]=01 or OP[4:3]=10 might indicate a ZQ-pin assembly error. It is recommended that the assembly error is corrected. 3. In the case of possible assembly error (either OP[4:3]=01 or OP[4:3]=10 per Note 4), the LPDDR2 device will default to factory trim settings for RON, and will ignore ZQ calibration commands. In either case, the system may not function as intended. 4. In the case of the ZQ self-test returning a value of 11b, this result indicates that the device has detected a resistor connection to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or that the ZQ resistor tolerance meets the specified limits (i.e. 240-ohm +/-1%). . 6.3.3 MR1_Device Feature 1 (MA[7:0] = 01H) OP7 OP6 OP5 nWR (for AP) BL Write-only OP[2:0] OP4 OP3 WC BT OP2 OP1 OP0 BL 010b: BL4 (default) 011b: BL8 100b: BL16 All others: reserved BT Write-only OP3 WC Write-only OP4 0b: Sequential (default) 1b: Interleaved 0b: Wrap (default) 1 b: No wrap (allowed for SDRAM BL4 only) 001b nWR=3 (default) 010b: nWR=4 011b: nWR=5 nWR Write-only OP[7:5] 100b: nWR=6 101b: nWR=7 1 110b: nWR=8 All others: reserved Note 1. Programmed value in nWR register is the number of clock cycles which determines when to start internal precharge operation for a write burst with AP enabled. It is determined by RU(tWR/tCK). - 17 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.3.3.1 1 Table of Burst Sequence by Burst Length (BL), Burst Type (BT), and Warp Control (WC) Burst Cycle Number and Burst Address Sequence C3 X C2 X C1 0b C0 WC BT BL 0b wrap X X 1b 0b X X X 0b X 0b 0b 0b X 0b 1b 0b 2 3 4 5 6 7 8 0 1 2 3 2 3 0 1 y y+1 y+2 y+3 0 1 2 3 4 5 6 7 2 3 4 5 6 7 0 1 4 5 6 7 0 1 2 3 6 7 0 1 2 3 4 5 0 1 2 3 4 5 6 7 2 3 0 1 6 7 4 5 9 10 11 12 13 14 15 16 any 4 nw 1 any seq X 1b 0b 0b X 1b 1b 0b wrap X 0b 0b 0b X 0b 1b 0b 8 int X 1b 0b 0b 4 5 6 7 0 1 2 3 X 1b 1b 0b 6 7 4 5 2 3 0 1 X X X 0b 0b 0b 0b 0b 0 1 2 3 4 5 6 7 8 9 A B C D E F 0b 0b 1b 0b 2 3 4 5 6 7 8 9 A B C D E F 0 1 0b 1b 0b 0b 4 5 6 7 8 9 A B C D E F 0 1 2 3 0b 1b 1b 0b 6 7 8 9 A B C D E F 0 1 2 3 4 5 8 9 A B C D E F 0 1 2 3 4 5 6 7 nw any illegal (not allowed) seq 1b 0b 0b 0b wrap 16 1b 0b 1b 0b A B C D E F 0 1 2 3 4 5 6 7 8 9 1b 1b 0b 0b C D E F 0 1 2 3 4 5 6 7 8 9 A B 1b 1b 1b 0b E F 0 1 2 3 4 5 6 7 8 9 A B C D X X X 0b X X X 0b nw int illegal (not allowed) any illegal (not allowed) Note:1. C0 input is not present on CA bus. It is implied zero. 2. For BL=4, the burst address represents C[1: 0]. 3. For BL=8, the burst address represents C[2:0]. 4. For BL=16, the burst address represents C[3:0]. 5. For no-wrap (nw), BL4, the burst shall not cross the page boundary and shall not cross sub-page boundary. The variable y may start at any address with C0 equal to 0 and may not start at any address in table below for the respective density and bus width combinations. 6.3.3.2 Table of Non Wrap Restrictions Bus Width x32 X32 1Gb Not across full page boundary 1FE, 1FF, 000, 001 Not across sub page boundary None Note : Non-wrap BL=4 data-orders shown above are prohibited. - 18 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.3.4 MR2_Device Feature 2 (MA[7:0] = 02H) OP7 OP6 OP5 OP4 OP3 OP2 (RFU) RL & WL OP1 OP0 RL & WL Write-only 0001b: RL = 3 / WL = 1 (default) 0010b: RL = 4 / WL = 2 0011b: RL = 5 / WL = 2 0100b: RL = 6 / WL = 3 0101b: RL = 7 / WL = 4 0110b: RL = 8 / WL = 4 All others: reserved OP[3:0] . 6.3.5 MR3_I/O Configuration 1 (MA[7:0] = 03H) OP7 OP6 OP5 OP4 OP3 OP2 (RFU) DS OP1 OP0 DS Write-only 0000b: reserved 0001b: 34.3-ohm typical 0010b: 40-ohm typical (default) 0011b: 48-ohm typical 0100b: 60-ohm typical 0101b: reserved for 68.6-ohm typical 0110b: 80-ohm typical 0111b: 120-ohm typical All others: reserved OP[3:0] 6.3.6 MR4_Device Temperature (MA[7:0] = 04H ) OP7 OP6 OP5 TUF OP4 OP3 (RFU) SDRAM Refresh Rate Read-only OP[2:0] Temperature Update Flag (TUF) Read-only OP7 OP2 OP1 OP0 SDRAM Refresh Rate 000b: SDRAM Low temperature operating limit exceeded 001b: 4x tREFI, 4x tREFIpb, 4x tREFW 010b: 2x tREFI, 2x tREFIpb, 2x tREFW 011b: 1x tREFI, 1x tREFIpb, 1x tREFW (<=85C) 100b: Reserved 101b: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW, do not de-rate SDRAM AC timing 110b: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW, de-rate SDRAM AC timing 111b: SDRAM High temperature operating limit exceeded 0b: OP[2:0] value has not changed since last read of MR4 . 1b: OP[2:0] value has changed since last read of MR4. Note 1. A Mode Register Read from MR4 will reset OP7 to `0'. 2. OP7 is reset to `0' at power-up 3. If OP2 equals `1', the device temperature is greater than 85'C 4. OP7 is set to `1' if OP2:OP0 has changed at any time since the last read of MR4. 5. LPDDR2 might not operate properly when OP[2:0] = 000b or 111b. 6. LPDDR2 devices must be derated by adding 1.875ns to the following core timing parameters: tRCD, tRC, tRAS, tRP, and tRRD. tDQSCK shall be de-rated according to the tDQSCK de-rating value in AC timing table. Prevailing clock frequency spec and related setup and hold timings shall remain unchanged. 7. The recommended frequency for reading MR4 is provided in Temperature Sensor - 19 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.3.7 MR5_Basic Configuration 1 (MA[7:0] = 05H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 LPDDR2 Manufacturer ID LPDDR2 Manufacturer ID Read-only OP[7:0] 0000 1000b : Winbond 6.3.8 MR6_Basic Configuration 2 (MA[7:0] = 06H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Revision ID1 Revision ID1 Read-only OP[7:0] 00000000b: A-version 6.3.9 MR7_Basic Configuration 3 (MA[7:0] = 07H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Revision ID2 Revision ID2 Read-only OP[7:0] 00000000b: A-version 6.3.10 MR8_Basic Configuration 4 (MA[7:0] = 08H) OP7 OP6 OP5 OP4 I/O width OP3 OP2 OP1 Density OP0 Type Type Read-only OP[1:0] 00b: S4 SDRAM Density Read-only OP[5:2] 0100b: 1Gb I/O width Read-only OP[7:6] 00b: x32 6.3.11 MR9_Test Mode (MA[7:0] = 09H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Vendor-specific Test Mode 6.3.12 MR10_Calibration (MA[7:0] = 0AH) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Calibration Code - 20 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb Write-only Calibration Code OP[7:0] 0xFF: Calibration command after initialization 0xAB: Long calibration 0x56: Short calibration 0xC3: ZQ Reset others: Reserved Note: 1. Host processor shall not write MR10 with "Reserved" values 2. LPDDR2 devices shall ignore calibration command when a "Reserved" value is written into MR10. 3. See AC timing table for the calibration latency. 4. If ZQ is connected to VSSCA through RZQ, either the ZQ calibration function or default calibration (through the ZQreset command) is supported. If ZQ is connected to VDDCA, the device operates with default calibration, and ZQ calibration commands are ignored. In both cases, the ZQ connection shall not change after power is applied to the device. 5. Optionally, the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connec-tion. 6.3.13 MR16_PASR_Bank Mask (MA[7:0] = 10H) OP7 OP6 OP5 OP4 S4 SDRAM Bank [7:0] Mask OP3 OP2 OP1 OP0 Bank Mask (8-bank) Write-only 0b: refresh enable to the bank (=unmasked, default) 1b: refresh blocked (=masked) OP[7:0] OP Bank Mask 8-Bank S4 SDRAM 0 XXXXXXX1 Bank 0 1 XXXXXX1X Bank 1 2 XXXXX1XX Bank 2 3 XXXX1XXX Bank 3 4 XXX1XXXX Bank 4 5 XX1XXXXX Bank 5 6 X1XXXXXX Bank 6 7 1XXXXXXX Bank 7 6.3.14 MR17_PASR_Segment Mask (MA[7:0] = 11H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Segment Mask Segment [7:0] Mask Write-only OP[7:0] 0b: refresh enable to the segment (=unmasked, default) 1b: refresh blocked (=masked) - 21 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb Segment OP Segment Mask R[12:10] 0 0 XXXXXXX1 000b 1 1 XXXXXX1X 001b 2 2 XXXXX1XX 010b 3 3 XXXX1XXX 011b 4 4 XXX1XXXX 100b 5 5 XX1XXXXX 101b 6 6 X1XXXXXX 110b 7 7 1XXXXXXX 111b 6.3.15 MR32_DQ Calibration Pattern A (MA[7:0] = 20H) Reads to MR32 return DQ Calibration Pattern "A". See "DQ Calibration". 6.3.16 MR40_DQ Calibration Pattern B (MA[7:0] = 28H) Reads to MR40 return DQ Calibration Pattern "B". See "DQ Calibration". 6.3.17 MR63_Reset (MA[7:0] = 3FH): MRW only OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 X For additonal information on MRW RESET see "Mode Register Write Command". - 22 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4 Command Definitions and Timing Diagram 6.4.1 LPDDR2-S4: Activate Command . The SDRAM Activate command is issued by holding CS_n LOW, CA0 LOW, and CA1 HIGH at the rising edge of the clock. The bank addresses are used to select the desired bank. The row addresses are used to determine which row to activate in the selected bank. The Activate command must be applied before any Read or Write operation can be executed. The LPDDR2 SDRAM can accept a read or write command at time tRCD after the activate command is sent. Once a bank has been activated it must be precharged before another Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between Activate commands to different banks is tRRD. Certain restrictions on operation of the 8-bank devices must be observed. There are two rules. One for restricting the number of sequential Activate commands that can be issued and another for allowing more time for RAS precharge for a Precharge All command. The rules are as follows: 8-bank device Sequential Bank Activation Restriction : No more than 4 banks may be activated (or refreshed, in the case of REFpb) in a rolling tFAW window. Converting to clocks is done by dividing tFAW[ns] by tCK[ns], and rounding up to next integer value. As an example of the rolling window, if RU{ (tFAW / tCK) } is 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued at or between clock N+1 and N+9. REFpb also counts as bank-activation for the purposes of tFAW. 8-bank device Precharge All Allowance : tRP for a Precharge All command for an 8-bank device shall equal tRPab, which is greater than tRPpb. 6.4.1.1 Figure of LPDDR2-S4 : Activate command cycle : tRCD=3,tRP=3,tRRD=2 T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 CK_t / CK_c CA0-9 Bank A Row Addr Row Addr Bank B Bank A Row Addr Row Addr Col Addr Col Addr RAS-CAS delay=tRCD Bank A Read Begins RAS-RAS delay time=tRRD [Cmd] Activate Nop Activate Bank A Row Addr Row Addr Bank Precharge time=tRP Precharge Read Nop Nop Activate Bank Active=tRAS Row Cycle time=tRC Note: A Precharge-All command uses tRPab timing, while a Single Bank Precharge command uses tRPpb timing. In this figure, tRP is used to denote either an All-bank Precharge or a Single Bank Precharge - 23 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.1.2 Figure of LPDDR2-S4: tFAW timing Tn+ Tn Tx Tm+ Tm Ty+2 Ty+1 Ty Tx+ Tz Tz+1 Tz+2 CK_t / CK_c CA0-9 Bank A Bank A [Cmd] Bank B Bank B Bank C Bank C Bank D Bank D ACT ACT ACT ACT tRRD Bank E Bank E Nop Nop Nop ACT Nop tRRD tRRD tFAW Note : tFAW is for 8-bank devices only. 6.4.1.3 Figure of LPDDR2 Command Input Setup and Hold Timing T0 T1 T2 T3 CK_t / CK_c tIS CS_n [Cmd] tIH VIH(AC) VIL(DC) VIL(AC) tIS CA0-9 tIS tIH VIH(DC) tIH tIS tIH CA CA CA CA CA CA CA CA Rise Fall Rise Fall Rise Fall Rise Fall Nop Command Nop Command HIGH or LOW (but a defined logic level) Note: Setup and hold conditions also apply to the CKE pin. See section related to power down for timing diagrams related to the CKE pin. - 24 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.1.4 Figure of LPDDR2 CKE Input Setup and Hold Timing T0 T1 Tx Tx+1 CK_t / CK_c tIHCKE tIHCKE CKE VIHCKE VILCKE VIHCKE VILCKE tISCKE tISCKE HIGH or LOW (but a defined logic level) Note: 1.After CKE is registered LOW, CKE signal level shall be maintained below VILCKE for tCKE specification (LOW pulse width). 2.After CKE is registered HIGH, CKE signal level shall be maintained above VIHCKE for tCKE specification (HIGH pulse width) 6.4.2 LPDDR2-S4: Read and Write access modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting CS_n LOW, CA0 HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this time to determine whether the access cycle is a READ operation (CA2 HIGH) or a WRITE operation (CA2 LOW). The LPDDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a burst read or write operation on successive clock cycles. For LPDDR2-S4 devices, a new burst access must not interrupt the previous 4-bit burst operation in case of BL = 4 setting. In case of BL = 8 and BL = 16 settings, Reads may be interrupted by Reads and Writes may be interrupted by Writes provided that this occurs on even clock cycles after the Read or Write command and tCCD is met. 6.4.3 Burst Read command The Burst Read command is initiated by having CS_n LOW, CA0 HIGH, CA1 LOW and CA2 HIGH at the rising edge of the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address for the burst. The Read Latency (RL) is defined from the rising edge of the clock on which the Read Command is issued to the rising edge of the clock from which the tDQSCK delay is measured. The first valid datum is available RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Read Command is issued. The data strobe output is driven LOW tRPRE before the first rising valid strobe edge. The first bit of the burst is synchronized with the first rising edge of the data strobe. Each subsequent data-out appears on each DQ pin edge aligned with the data strobe. The RL is programmed in the mode registers. Timings for the data strobe are measured relative to the crosspoint of DQS_t and its complement, DQS_c. - 25 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.3.1 Figure of Data output(read)timing(tDQSCKmax) RL-1 RL tCH RL+BL/2 tCL CK_c CK_t tLZ(DQS) tDQSCKmax tQSH DQS_c DQS_c DQS_t tQSL tHZ(DQs) DQS_t tRPRE DQ tRPST Q tDQSQmax Q Q Q tDQSQmax tQH tLZ(DQ) tQH tHZ(DQ) Note : 1. tDQSCK may span multiple clock periods. 2. An effective Burst Length of 4 is shown - 26 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.3.2 Figure of Data output(read)timing(tDQSCKmin) RL-1 RL tCH RL+BL/2 tCL CK_c CK_t tHZ(DQs) tLZ(DQS) tDQSCKmin tQSH DQS_c DQS_c DQS_t tQSL DQS_t tRPST tRPRE DQ Q tDQSQmax tLZ(DQ) Q Q Q tDQSQmax tQH tQH tHZ(DQ) Note: An effective Burst Length of 4 is shown 6.4.3.3 Figure of LPDDR2-S4 : Burst read : RL = 5. BL = 4. tDQSCK > tCK T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank A Col Addr Col Addr [Cmd] Read Nop Nop Nop Nop Nop Nop Nop Nop tDQSCK DQS_c DQS_t RL = 5 DQS DOUT A0 - 27 - DOUT A1 DOUT A2 DOUT A3 Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.3.4 Figure of LPDDR2-S4 : Burst T0 read : RL = 3. BL = 8. tDQSCK < tCK T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank A Col Addr Col Addr Read Nop Nop Nop Nop Nop Nop Nop Nop tDQSCK DQS_c DQS_t RL = 3 DQS DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7 6.4.3.5 Figure of LPDDR2: tDQSCKDL timing Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 Tn+6 Tn+7 Tn+8 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 Col Col Addr Addr Col Col Addr Addr CK_t / CK_c CA0-9 [Cmd] DQS_c DQS_t DQS Read Nop Nop Nop Nop Nop Nop Nop Nop Read Nop Nop Nop Nop Nop Nop Nop Nop tDQSCKn tDQSCKm RL = 5 RL = 5 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 32ms maximum tDQSCKDL = l tDQSCKn - tDQSCKm l Note : tDQSCKDLmax is defined as the maximum of ABS(tDQSCKn - tDQSCKm) for any {tDQSCKn ,tDQSCKm} pair within any 32ms rolling window. - 28 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.3.6 Figure of LPDDR2: tDQSCKDM timing Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 Tn+6 Tn+7 Tn+8 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 Col Col Addr Addr Col Col Addr Addr CK_t / CK_c CA0-9 [Cmd] Read Nop Nop Nop Nop Nop Nop Nop Nop Read Nop Nop Nop Nop Nop Nop Nop Nop tDQSCKn DQS_c DQS_t DQS tDQSCKm RL = 5 RL = 5 DOUTA0 DOUTA1 DOUTA2 DOUTA3 DOUTA0 DOUTA1 DOUTA2 DOUTA3 1.6us maximum tDQSCKDM = l tDQSCKn - tDQSCKm l Note : tDQSCKDMmax is defined as the maximum of ABS(tDQSCKn - tDQSCKm) for any {tDQSCKn,tDQSCKm} pair within any 1.6us rolling window. 6.4.3.7 Figure of LPDDR2: tDQSCKDS timing Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 Tn+6 Tn+7 Tn+8 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 CK_t / CK_c CA0-9 [Cmd] Col Col Addr Addr Col Col Addr Addr Read Nop Nop Nop Nop Nop Nop Nop Nop Read Nop Nop tDQSCKn DQS_c DQS_t DQS Nop Nop Nop Nop Nop Nop tDQSCKm RL = 5 RL = 5 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 160ns maximum tDQSCKDS = l tDQSCKn - tDQSCKm l Note : tDQSCKDSmax is defined as the maximum of ABS(tDQSCKn - tDQSCKm) for any {tDQSCKn ,tDQSCKm} pair for reads within a consecutive burst within any 160ns rolling window. - 29 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.3.8 LPDDR2-S4 : Burst read followed by burst write: RL = 3, WL = 1, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank A Col Addr [Cmd] Bank A Col Addr Col Addr Read Nop Nop Nop Nop Nop tDQSCK Col Addr Write Nop Nop tDQSSmin BL / 2 DQS_c DQS_t RL = 3 DQS WL=1 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DIN A0 DIN A1 DIN A2 The minimum time from the burst read command to the burst write command is defined by the Read Latency (RL) and the Burst Length (BL). Minimum read to write latency is RL + RU(tDQSCKmax/tCK) + BL/2 + 1 - WL clock cycles. Note that if a read burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated read burst should be used as "BL" to calculate the minimum read to write delay. 6.4.3.9 Figure of LPDDR2-S4 : Seamless burst read : RL = 3, BL= 4, tCCD=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank N Col Addr A Col Addr A Read Bank N Col Addr B Col Addr B Nop Read Nop Nop Nop Nop Nop Nop tCCD = 2 DQS_c DQS_t RL = 3 DQS DOUTA0 DOUTA1 DOUTA2 DOUTA3 DOUTB0 DOUTB1 DOUTB2 DOUTB3 The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation, every 4 clocks for BL = 8 operation, and every 8 clocks for BL=16 operation. For LPDDR2-SDRAM, this operation is allowed regardless of whether the accesses read the same or different banks as long as the banks are activated. - 30 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.4 Reads interrupted by a read For LPDDR2-S4 device, burst read can be interrupted by another read on even clock cycles after the Read command, provided that tCCD is met. 6.4.4.1 Figure of LPDDR2-S4 : Read burst interrupt example : RL = 3, BL= 8, tCCD=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank N Col Addr A Col Addr A [Cmd] Read Bank N Col Addr B Col Addr B Nop Read Nop Nop Nop Nop Nop Nop tCCD=2 DQS_c DQS_t RL = 3 DQS DOUTA0 DOUTA1 DOUTA2 DOUTA3 DOUTB0 DOUTB1 DOUTB2 DOUTB3 DOUTB4 DOUTB5 Note : 1. For LPDDR2-S4 devices, read burst interrupt function is only allowed on burst of 8 and burst of 16. 2. For LPDDR2-S4 devices, read burst interrupt may only occur on even clock cycles after the previous commands, provided that tCCD is met. 3. Reads can only be interrupted by other reads or the BST command. 4. Read burst interruption is allowed to any bank inside DRAM. 5. Read burst with Auto-Precharge is not allowed to be interrupted. 6.The effective burst length of the first read equals two times the number of clock cycles between the first read and the interrupting read. 6.4.5 Burst Write operation The Burst Write command is initiated by having CS_n LOW, CA0 HIGH, CA1 LOW and CA2 LOW at the rising edge of the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address for the burst. The Write Latency (WL) is defined from the rising edge of the clock on which the Write Command is issued to the rising edge of the clock from which the tDQSS delay is measured. The first valid data must be driven WL * tCK + tDQSS from the rising edge of the clock from which the Write command is issued. The data strobe signal (DQS) should be driven LOW tWPRE prior to the data input. The data bits of the burst cycle must be applied to the DQ pins tDS prior to the respective edge of the DQS and held valid until tDH after that edge. The burst data are sampled on successive edges of the DQS until the burst length is completed, which is 4, 8, or 16 bit burst. For LPDDR2-SDRAM devices, tWR must be satisfied before a precharge command to the same bank may be issued after a burst write operation. Input timings are measured relative to the crosspoint of DQS_t and its complement, DQS_c. - 31 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.5.1 Data input (write) timing tDQSH tDQSL DQS_c DQS_c DQS_t DQS_t tWPST tWPRE VIH(dc) VIH(ac) DQ D D D D VIL(dc) VIL(ac) tDS VIH(ac) DM VIH(dc) DMin DMin tDH tDH tDS DMin DMin VIL(dc) VIL(ac) 6.4.5.2 LPDDR2-S4 : Burst write : WL = 1, BL= 4 T0 T1 T3 T2 T4 Tx Tx+1 Ty Ty+1 CK_t / CK_c CA0-9 [Cmd] Bank A Col Addr Write Case 1:with tDQSS(max) DQS_c DQS_t Bank A Row Addr Row Addr Bank A Col Addr Nop Nop Nop tDSS tDSS tDQSSmax Precharge Nop Nop Activate Nop Completion of Burst Write WL = 1 tWR DQS DIN A0 DIN A1 DIN A2 DIN A3 tRP Case 2:with tDQSS(min) tDQSSmin DQS_c DQS_t DQS tDSH tDSH WL = 1 tWR DIN A0 DIN A1 DIN A2 DIN A3 - 32 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.5.3 LPDDR2-S4 : Burst wirte followed by burst read : RL = 3, WL= 1, BL=4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank M Col Addr A Col Addr A [Cmd] Write Bank N Col Addr B Col Addr B Nop Nop Nop Nop Nop Read Nop Nop RL = 3 WL = 1 DQS_c DQS_t tWTR DQS DIN A0 DIN A1 DIN A2 DIN A3 Note :1.The minimum number of clock cycles from the burst write command to the burst read command for any bank is [WL + 1 + BL/2 + RU( tWTR/tCK)]. 2. tWTR starts at the rising edge of the clock after the last valid input datum. 3. If a write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated write burst should be used as "BL" to calculate the minimum write to read delay. 6.4.5.4 LPDDR2-S4 : Seamless burst write : WL= 1, BL=4, tCCD=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank M Col Addr A Col Addr A [Cmd] Write Bank N Col Addr B Col Addr B Nop Nop Nop Write Nop Nop Nop Nop tCCD = 2 DQS_c DQS_t WL=1 DQS DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 Note: The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation, every four clocks for BL = 8 operation, or every eight clocks for BL=16 operation. This operation is allowed regardless of same or different banks as long as the banks are activated. - 33 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.6 Writes interrupted by a write For LPDDR2-S4 devices, burst writes can only be interrupted by another write on even clock cycles after the write command, provided that tCCD(min) is met. 6.4.6.1 LPDDR2-S4 : Write burst interrupt timing : WL= 1, BL=8, tCCD=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank M Col Addr A Col Addr A [Cmd] Write Bank N Col Addr B Col Addr B Nop Nop Nop Write Nop Nop Nop Nop tCCD = 2 DQS_c DQS_t WL=1 DQS DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 DIN B4 DIN B5 DIN B6 DIN B7 Note : 1. For LPDDR2-S4 devices, write burst interrupt function is only allowed on burst of 8 and burst of 16. 2. For LPDDR2-S4 devices, write burst interrupt may only occur on even clock cycles after the previous write commands, provided that tCCD(min) is met. 3. Writes can only be interrupted by other writes or the BST command. 4. Write burst interruption is allowed to any bank inside DRAM. 5. Write burst with Auto-Precharge is not allowed to be interrupted. 6. The effective burst length of the first write equals two times the number of clock cycles between the first write and the interrupting write. 6.4.7 Burst Terminate The Burst Terminate (BST) command is initiated by having CS_n LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 LOW at the rising edge of clock. A Burst Teminate command may only be issued to terminate an active Read or Write burst. Therefore, a Burst Terminate command may only be issued up to and including BL/2 - 1 clock cycles after a Read or Write command. The effective burst length of a Read or Write command truncated by a BST command is as follows: Effective burst length = 2 x {Number of clock cycles from the Read or Write Command to the BST command} Note that if a read or write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated burst should be used as "BL" to calculate the minimum read to write or write to read delay. The BST command only affects the most recent read or write command. The BST command truncates an ongoing read burst RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Burst Terminate command is issued. The BST command truncates an on going write burst WL * tCK + tDQSS after the rising edge of the clock where the Burst Terminate command is issued. For LPDDR2-S4 devices, the 4-bit prefetch architecture allows the BST command to be issued on an even number of clock cycles after a Write or Read command. Therefore, the effective burst length of a Read or Write command truncated by a BST command is an integer multiple of 4. - 34 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.7.1 LPDDR2-S4 : Write burst truncated by BST : WL= 1, BL=16 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank M Col Addr A Col Addr A [Cmd] Write Nop Nop Nop Nop BST Nop Nop WL*tCK+tDQSS Nop BST not allowed WL=1 DQS_c DQS_t DQS DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 DIN A5 DIN A6 DIN A7 Note :1. The BST command truncates an ongoing write burst WL * tCK + tDQSS after the rising edge of the clock where the Burst Terminate command is issued. 2. Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write command. 6.4.7.2 LPDDR2-S4 : Burst Read truncated by BST : RL= 3, BL=16 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank N Col Addr A Col Addr A [Cmd] Read Nop Nop Nop BST Nop Nop Nop Nop RL*tCK+tDQSCK+tDQSQ BST not allowed DQS_c DQS_t RL = 3 DQS DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7 Note :1. The BST command truncates an ongoing read burst RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Burst Terminate command is issued. 2. For LPDDR2-S4 devices, BST can only be issued at even number of clock cycles after the Write command. 3. Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write command. - 35 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.8 Write data mask One write data mask (DM) pin for each data byte (DQ) will be supported on LPDDR2 devices, consistent with the implementation on LPDDR SDRAMs. Each data mask (DM) may mask its respective data byte (DQ) for any given cycle of the burst. Data mask has identical timings on write operations as the data bits, though used as input only, is internally loaded identically to data bits to insure matched system timing. 6.4.8.1 LPDDR2-S4 : Write data mask Data Mask Timing DQS_c DQS_t DQ VIH(ac) VIH(dc) VIL(ac) VIL(dc) VIH(ac) VIH(dc) VIL(ac) VIL(dc) DM tDS tDH tDS tDH Data Mask Function,WL= 2, BL=4 shown,second DQ masked CK_c CK_t [Cmd] Case 1: min tDQSS DQS_c DQS_t DQ Wirte WL = 2 tWR tWTR tDQSSmin 0 1 2 3 0 1 2 DM Case 2: max tDQSS tDQSSmax DQS_c DQS_t DQ 3 DM - 36 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.9 LPDDR2-S4: Precharge operation The Precharge command is used to precharge or close a bank that has been activated. The Precharge command is initiated by having CS_n LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. For 8bank devices, the AB flag, and the bank address bits, BA0, BA1, and BA2, are used to determine which bank(s) to precharge. The bank(s) will be available for a subsequent row access tRPab after an All-Bank Precharge command is issued and tRPpb after a Single-Bank Precharge command is issued. In order to ensure that 8-bank devices do not exceed the instantaneous current supplying capability of 4-bank devices, the Row Precharge time (tRP) for an All-Bank Precharge for 8-bank devices (tRPab) will be longer than the Row Precharge time for a Single-Bank Precharge (tRPpb). 6.4.9.1 Table of Bank selection for Precharge by address bits AB (CA4r) BA2 (CA9r) BA1 (CA8r) BA0 (CA7r) 0 0 0 0 Precharged Bank(s) 8-bank device Bank 0 only 0 0 0 1 Bank 1 only 0 0 1 0 Bank 2 only 0 0 1 1 Bank 3 only 0 1 0 0 Bank 4 only 0 1 0 1 Bank 5 only 0 1 1 0 Bank 6 only 0 1 1 1 Bank 7 only 1 DON'T CARE DON'T CARE DON'T CARE All Banks 6.4.10 LPDDR2-S4: Burst Read operation followed by Precharge For the earliest possible precharge, the precharge command may be issued BL/2 clock cycles after a Read command. For an untruncated burst, BL is the value from the Mode Register. For a truncated burst, BL is the effective burst length. A new bank active (command) may be issued to the same bank after the Row Precharge time (tRP). A precharge command cannot be issued until after tRAS is satisfied. For LPDDR2-S4 devices, the minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a Read command.This time is called tRTP (Read to Precharge). For LPDDR2-S4 devices, tRTP begins BL/2 - 2 clock cycles after the Read command. If the burst is truncated by a BST command or a Read command to a different bank, , the effective "BL" shall be used to calculate when tRTP begins. - 37 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.10.1 Figure of LPDDR2-S4 Burst read followed by Precharge : RL= 3, BL=8, RU(tRTP(min)/tCK) = 2 T0 T2 T1 T3 T4 T5 T7 T6 T8 CK_t / CK_c CA0-9 Bank M Col Addr A Col Addr A [Cmd] Read Bank M Nop Nop Nop Bank M Row Addr Row Addr Nop Precharge Activate Nop Nop BL / 2 tRTP DQS_c DQS_t RL = 3 DQS DOUT A0 DOUT A1 DOUT A3 DOUT A2 DOUT A4 DOUT A5 DOUT A6 DOUT A7 tRP 6.4.10.2 Figure of LPDDR2-S4 : Burst read followed by Precharge : RL= 3, BL=4, RU(tRTP(min)/tCK)=3 T0 T2 T1 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Bank M Col Addr A Col Addr A [Cmd] Read Bank M Nop Nop Bank M Row Addr Row Addr Precharge Nop Nop Activate Nop Nop BL / 2 DQS_c DQS_t DQS RL = 3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 tRTP=3 tRP - 38 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.11 LPDDR2-S4: Burst Write followed by Precharge For write cycles, a delay must be satisfied from the time of the last valid burst input data until the Precharge command may be issued. This delay is known as the write recovery time (tWR) referenced from the completion of the burst write to the precharge command. No Precharge command should be issued prior to the tWR delay. These devices write data to the array in prefetch quadruples (prefetch = 4). The beginning of an internal write operation may only begin after a prefetch group has been latched completely. The minimum Write to Precharge command spacing to the same bank is WL + BL/2 + 1 + RU(tWR/tCK) clock cycles. For an untruncated burst, BL is the value from the Mode Register. For an truncated burst, BL is the effective burst length. 6.4.11.1 Figure of LPDDR2-S4 : Burst write follwed by precharge : WL = 1, BL= 4 T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1 CK_t / CK_c CA0-9 [Cmd] Bank A Col Addr Bank A Write Case 1:with tDQSS(max) DQS_c DQS_t Nop Nop Nop Nop tDQSSmax Nop Activate Nop tWR DIN A0 DIN A1 DIN A2 DIN A3 Case 2:with tDQSS(min) WL = 1 Precharge Completion of Burst Write WL = 1 DQS >=tRP tDQSSmin DQS_c DQS_t DQS Bank A Row Addr Row Addr Col Addr tWR DIN A0 DIN A1 DIN A2 DIN A3 - 39 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.12 LPDDR2-S4: Auto Precharge operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge command or the auto-precharge function. When a Read or a Write command is given to the LPDDR2 SDRAM, the AP bit (CA0f) may be set to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If AP is LOW when the Read or Write command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst. If AP is HIGH when the Read or Write command is issued, then the auto-precharge function is engaged. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon Read or Write latency) thus improving system performance for random data access. 6.4.13 LPDDR2-S4: Burst Read with Auto-Precharge If AP (CA0f) is HIGH when a Read Command is issued, the Read with Auto-Precharge function is engaged. LPDDR2-S4 devices start an Auto-Precharge operation on the rising edge of the clock BL/2 or BL/2 - 2 + RU(tRTP/tCK) clock cycles later than the Read with AP command. A new bank Activate command may be issued to the same bank if both of the following two conditions are satisfied simultaneously. The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. The RAS cycle time (tRC) from the previous bank activation has been satisfied 6.4.13.1 Figure of LPDDR2-S4 : Burst read with Auto-Precharge : RL= 3, BL=4, RU(tRTP(min)/tCK)=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank M Row Addr Row Addr Bank M Col Addr A Col Addr A Read Nop Nop Nop Nop Activate Nop Nop Nop BL / 2 DQS_c DQS_t RL = 3 DQS DOUT A0 tRTP DOUT A1 DOUT A2 DOUT A3 >=tRPpb - 40 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.14 LPDDR2-S4: Burst write with Auto-Precharge If AP (CA0f) is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged. The LPDDR2 SDRAM starts an Auto Precharge operation on the rising edge which is tWR cycles after the completion of the burst write. A new bank activate (command) may be issued to the same bank if both of the following two conditions are satisfied. The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. RAS cycle time (tRC) from the previous bank activation has been satisfied. 6.4.14.1 Figure of LPDDR2-S4 : Burst write w/Auto precharge : WL = 1, BL= 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] Bank A Col Addr Col Addr Write Bank A Row Addr Row Addr Nop Nop Nop Nop Activate Nop tWR WL = 1 DQS_c DQS_t DQS Nop Nop tRPpb DIN A0 DIN A1 DIN A2 DIN A3 - 41 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.14.2 Table of LPDDR2-S4 Precharge & Auto Precharge Clarification From Command Minimum Delay between To Command Unit Note "From Command" to "To Command" Precharge (to same Bank as Read) BL/2 + max(2, RU(tRTP/tCK)) - 2 CLK 1 Precharge ALL BL/2 + max(2, RU(tRTP/tCK)) - 2 CLK 1 BST Precharge (to same Bank as Read) 1 CLK 1 (for Reads) Precharge ALL 1 CLK 1 Precharge (to same Bank as Read w/AP) BL/2 + max(2, RU(tRTP/tCK)) - 2 CLK 1,2 Precharge ALL BL/2 + max(2, RU(tRTP/tCK)) - 2 CLK 1 Activate (to same Bank as Read w/AP) BL/2 + max(2, RU(tRTP/tCK)) - 2 + RU(tRPpb/tCK) CLK 1 Write or Write w/AP (same bank) lllegal CLK 3 Write or Write w/AP (different bank) RL + BL/2 + RU(tDQSCKmax/tCK) - WL + 1 CLK 3 Read or Read w/AP (same bank) lllegal CLK 3 Read or Read w/AP (different bank) BL/2 CLK 3 Precharge (to same Bank as Write) WL + BL/2 + RU(tWR/tCK) + 1 CLK 1 Precharge ALL WL + BL/2 + RU(tWR/tCK) + 1 CLK 1 BST Precharge (to same Bank as Write) WL + RU(tWR/tCK) + 1 CLK 1 (for Writes) Precharge ALL WL + RU(tWR/tCK) + 1 CLK 1 Precharge (to same Bank as Write w/AP) WL + BL/2+ RU(tWR/tCK) + 1 CLK 1 Precharge ALL WL + BL/2 + RU(tWR/tCK) + 1 CLK 1 Activate (to same Bank as Write w/AP) WL + BL/2 + RU(tWR/tCK) + 1 + RU(tRPpb/tCK) CLK 1 Write or Write w/AP (same bank) lllegal CLK 3 Write or Write w/AP (different bank) BL/2 CLK 3 Read or Read w/AP (same bank) lllegal CLK 3 Read or Read w/AP (different bank) WL + BL/2 + RU(tWTR/tCK) + 1 CLK 3 Precharge (to same Bank as Precharge) 1 CLK 1 Precharge ALL 1 CLK 1 Precharge 1 CLK 1 Read Read w/AP Write Write w/AP Precharge Precharge All 1 CLK 1 Precharge ALL Note :1. For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge all, issued to that bank. The precharge period is satisfied after tRP depending on the latest precharge command issued to that bank. 2. Any command issued during the minimum delay time is illegal. 3. After Read with AP, seamless read operations to different banks are supported. After Write with AP, seamless write operations to different banks are supported. Read w/AP and Write w/AP may not be interrupted or truncated. - 42 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.15 LPDDR2-S4: Refresh command The Refresh command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of clock. Per Bank Refresh is initiated by having CA3 LOW at the rising edge of clock and All Bank Refresh is initiated by having CA3 HIGH at the rising edge of clock. Per Bank Refresh is only allowed in devices with 8 banks. A Per Bank Refresh command, REFpb performs a refresh operation to the bank which is scheduled by the bank counter in the memory device. The bank sequence of Per Bank Refresh is fixed to be a sequential round-robin: "01-2-3-4-5-6-7-0-1-...". The bank count is synchronized between the controller and the SDRAM upon issuing a RESET command or at every exit from self refresh, by resetting bank count to zero. The bank addressing for the Per Bank Refresh count is the same as established in the single-bank Precharge command. A bank must be idle before it can be refreshed. It is the responsibility of the controller to track the bank being refreshed by the Per Bank Refresh command. The REFpb command may not be issued to the memory until the following conditions are met: a) tRFCab has been satisified after the prior REFab command b) tRFCpb has been satisfied after the prior REFpb command c) tRP has been satisified after the prior Precharge command to that given bank tRRD has been satisfied after the prior ACTIVATE command (if applicable, for example after activating a row in a different bank than affected by the REFpb command). The target bank is inaccessable during the Per Bank Refresh cycle time (tRFCpb), however other banks within the device are accessable and may be addressed during the Per Bank Refresh cycle. During the REFpb operation, any of the banks other than the one being refreshed can be maintained in active state or accessed by a read or a write command. When the Per Bank refresh cycle has completed, the affected bank will be in the Idle state.after issuing REFpb: a) tRFCpb must be satisified before issuing a REFab command b) tRFCpb must be satisfied before issuing an ACTIVATE command to the same bank c) tRRD must be satisified before issuing an ACTIVATE command to a different bank d) tRFCpb must be satisified before issuing another REFpb command An All Bank Refresh command, REFab performs a refresh operation to all banks. All banks have to be in Idle state when REFab is issued (for instance, by Precharge all-bank command). REFab also synchronizes the bank count between the controller and the SDRAM to zero. the REFab command may not be issued to the memory until the following conditions have been met: a) tRFCab has been satisified after the prior REFab command b) tRFCpb has been satisified after the prior REFpb command c) tRP has been satisified after prior PRECHARGE commands When the All Bank refresh cycle has completed, all banks will be in the Idle state. after issuing REFab: a) the tRFCab latency must be satisfied before issuing an ACTIVATE command b) the tRFCab latency must be satisfied before issuing a REFab or REFpb command - 43 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.15.1 Table of Command Scheduling Separations related to Refresh Symbol minimum delay from to Note REFab tRFCab REFab Activate cmd to any bank REFpb REFab tRFCpb REFpb Activate cmd to same bank as REFpb REFpb REFpb tRRD Activate Activate cmd to different bank than REFpb REFpb affecting an idle bank (different bank than Activate) 1 Activate cmd to different bank than prior Activate Note : A bank must be in the Idle state before it is refreshed. Therefore, after Activate,REFab is not allowed and REFpb is allowed only if it affects a bank which is in the Idle state.. 6.4.16 LPDDR2 SDRAM Refresh Requirements (1) Minimum number of Refresh commands: The LPDDR2 SDRAM requires a minimum number of R Refresh (REFab) commands within any rolling Refresh Window (tREFW = 32 ms @ MR4[2:0] = "011" or Tj 85 C). The minimum number R depends on density. The resulting average refresh interval (tREFI) also depends on density. See Mode Register 4 for tREFW and tREFI refresh multipliers at different MR4 settings. (2) Burst Refresh limitation: To limit maximum current consumption, a maximum of 8 REFab commands may be issued in any rolling tREFBW (tREFBW = 4 x 8 x tRFCab). (3) Refresh Requirements and Self-Refresh: If any time within a refresh window is spent in Self-Refresh Mode, the number of required Refresh commands in this particular window is reduced to: R* = R - RU{tSRF / tREFI} = R - RU{R * tSRF / tREFW}; where RU stands for the round-up function - 44 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.16.1 Figure of LPDDR2-S4 : Definition of tSRF A) tREFW tSRF CKE Enter Self-Refresh Exit Self-Refresh tREFW B) tSRF CKE C) CKE tREFW tSRF Exit Self-Refresh D) Enter Self-Refresh tREFW tSRF1 tSRF2 CKE Exit Self-Refresh Enter Self-Refresh tSRF=tSRF1+tSRF2 Exit Self-Refresh Several examples on how tSRF is caclulated: A: with the time spent in Self-Refresh Mode fully enclosed in the Refresh Window (tREFW), B: at Self-Refresh entry C: at Self-Refresh exit D: with several different invervals spent in Self Refresh during one tREFW interval - 45 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb In contrast to JESD79 and JESD79-2 and JESD79-3 compliant SDRAM devices, LPDDR2-S4 devices allow significant flexibiliy in scheduling REFRESH commands, as long as the boundary conditions above are met. In the most straight forward case a REFRESH command should be scheduled every tREFI. In this case SelfRefresh may be entered at any time. The users may choose to deviate from this regular refresh pattern e.g., to enable a period where no refreshes are required. In the extreme the user may choose to issue a refresh burst of 4096 REFRESH commands with the maximum allowable rate (limited by tREFBW) followed by a long time without any REFRESH commands, until the refresh window is complete, then repeating this sequence. The achieveable time without REFRESH commands is given by tREFW - (R / 8) * tREFBW = tREFW - R * 4 * tRFCab.@ Tj <= 85 this can be up to 32 ms - 4096 * 4 * 130 ns ~ 30 ms. While both - the regular and the burst/pause - patterns can satisfy the refresh requirements per rolling refresh interval, if they are repeated in every subsequent 32 ms window, extreme care must be taken when transitioning from one pattern to another to satisfy the refresh requirement in every rolling refresh window during the transition. If this transition happens directly after the burst refresh phase, all rolling tREFW intervalls will have at least the required number of refreshes. As an example of a non-allowable transition, the regular refresh pattern starts after the completion of the pausephase of the burst/pause refresh pattern. For several rolling tREFW intervals the minimmun number of REFRESH commands is not satisfied. The understanding of the pattern transition is extremly relevant (even if in normal operation only one pattern is employed), as in Self-Refresh-Mode a regular, distributed refresh pattern has to be assumed, which is reflected in the equation for R* above. Therefore it is recommended to enter Self-Refresh-Mode ONLY directly after the burstphase of a burst/pause refresh pattern and begin with the burst phase upon exit from Self-Refresh. 6.4.16.2 Figure of LPDDR2-S4 Regular, Distributed Refresh Pattern vs. Repetitive Burst Refresh with Subsequent Refresh Pause tREFI 64 ms 96 ms 6 1 4 8 ,3 6 4 9 ,0 2 8 9 ,1 2 1 9 8 , 2 2 1 8 ,8 2 32 ms 3 8 9 , 1 2 8 ,9 1 7 4 ,9 0 6 4 ,9 0 tREFBW 2 1 8 8 , 2 0 ms tREFI tREFBW Note : For a device @ Tj less than or equal to 85 C the distributed refresh pattern would have one REFRESH command per 7.8 us; the burst refresh pattern would have one refresh command per 0.52 us followed by ~30 ms without any REFRESH command. - 46 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.16.3 Figure of LPDDR2-S4: Allowable Transition from Repetitive Burst Refresh with Subsequent Refresh Pause to Regular, Distributed Refresh Pattern tREFI 32 ms 0 1 0 ,4 2 2 1 8 8 ,2 2 8 9 ,1 7 4 9 ,0 6 4 9 ,0 tREFBW 96 ms 64 ms 6 1 4 8 ,3 0 ms tREFI tREFBW Note : in a 1Gb LPDDR2 device @ Tj less than or equal to 85 C the distributed refresh pattern would have one REFRESH command per 7.8 us; the burst refresh pattern would have one refresh command per 0.52us followed by ~30 ms without any REFRESH command. 1 6.4.16.4 Figure of LPDDR2-S4: NOT-Allowable Transition from Repetitive Burst Refresh with Subsequent Refresh Pause to Regular, Distributed Refresh Pattern tREFI tREFI 96 ms 64 ms 2 1 8 8 , 2 32 ms 0 1 0 4 ,2 2 8 9 , 1 3 8 9 , 1 0 ms 7 4 9 , 0 6 4 ,9 0 tREFW=32ms tREFBW tREFBW Not enough Refresh commands In this refresh window!! Note : Only ~2048 REFRESH commands (<R which is 4096) in the indicated tREFW window. - 47 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.16.5 Figure of LPDDR2-S4: Recommended Self-refresh entry and exit in conjunction with a Burst/Pause Refresh patterns. 0 ms 32 ms 6 94 0, 2 98 1, 7 94 0, Self-Refresh tREFBW tREFBW 6.4.16.6 Figure of LPDDR2-S4 All Bank Refresh Operation T0 T2 T1 T3 T4 Tx Tx+1 Ty Ty+1 CK_t / CK_c CA0-9 [Cmd] AB Precharge Nop >=tRPab Nop REFab >=tRFCab - 48 - Nop REFab Nop ANY >=tRFCab Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.16.7 Figure of LPDDR2-S4 Per Bank Refresh Operation T0 Tx T1 Tx+1 Tx+2 Ty Ty+1 Tz Tz+1 CK_t / CK_c CA0-9 [Cmd] AB Precharge Bank 1 Row A NOP NOP >=tRPab ACT REFpb REFpb >=tRFCpb Refresh to Bank 0 Row A >=tRFCpb Refresh to Bank 1 Activate command to Bank 1 Note : 1.In the beginning of this example, the REFpb bank is pointing to Bank 0. 2.Operations to other banks than the bank being refreshed are allowed during the tRFCpb period. - 49 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.17 LPDDR2-S4: Self Refresh operation The Self Refresh command can be used to retain data in the LPDDR2 SDRAM, even if the rest of the system is powered down. When in the Self Refresh mode, the LPDDR2 SDRAM retains data without external clocking. The LPDDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CKE LOW, CS_n LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock. CKE must be HIGH during the previous clock cycle. A NOP command must be driven in the clock cycle following the power-down command. Once the command is registered, CKE must be held LOW to keep the device in Self Refresh mode. LPDDR2-S4 devices can operate in Self Refresh in both the Standard or Extended Temperature Ranges. LPDDR2S4 devices will also manage Self Refresh power consumption when the operating temperature changes, lower at low temperatures and higher temperatures. Once the LPDDR2 SDRAM has entered Self Refresh mode, all of the external signals except CKE, are "don't care". For proper self refresh operation, power supply pins (VDD1, VDD2, and VDDCA) must be at valid levels. VDDQ may be turned off during Self-Refresh. Prior to exiting Self-Refresh, VDDQ must be within specified limits. VrefDQ and VrefCA may be at any level within minimum and maximum levels. However prior to exit Self-Refresh, VrefDQ and VrefCA must be within specified limits. The SDRAM initiates a minimum of one all-bank refresh command internally within tCKESR period once it enters Self Refresh mode. The clock is internally disabled during Self Refresh Operation to save power. The minimum time that the LPDDR2 SDRAM must remain in Self Refresh mode is tCKESR. The user may change the external clock frequency or halt the external clock one clock after Self Refresh entry is registered; however, the clock must be restarted and stable before the device can exit Self Refresh operation. The procedure for exiting Self Refresh requires a sequence of commands.First, the clock shall be stable and within specified limits for a minmum of 2 clock cycles prior to CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least tXSR must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. CKE must remain HIGH for the entire Self Refresh exit period tXSR for proper operation except for self refresh re-entry. NOP commands must be registered on each positive clock edge during the Self Refresh exit interval tXSR. The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, it is required that at least one Refresh command (8 per-bank or 1 all-bank) is issued before entry into a subsequent Self Refresh. For LPDDR2 SDRAM, the maximum duration in power-down mode is only limited by the refresh requirements outlined in section "LPDDR2 SDRAM Refresh Requirements", since no refresh operations are performed in powerdown mode. - 50 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.17.1 Figure of LPDDR2-S4 : Self Refresh Operation 2 tCK(min) CK_c CK_t tIHCKE Input clock frequency may be changed or stopped during Self-Refresh tIHCKE CKE tISCKE tISCKE CS_n [Cmd] Valid Enter SR NOP Exit SR NOP Valid tXSR(min) tCKESR(min) Enter Self-Refresh NOP Exit Self-Refresh Note :1. Input clock frequency may be changed or stopped during self-refresh, provided that upon exiting self-refresh, a minimum of 5 clocks (tINIT2) of stable clock are provided and the clock frequency is between the minimum and maximum frequency for the particular speed grade. 2. Device must be in the "All banks idle" state prior to entering Self Refresh mode. 3. tXSR begins at the rising edge of the clock after CKE is driven HIGH. 4. A valid command may be issued only after tXSR is satisfied. NOPs shall be issued during tXSR. 6.4.18 LPDDR2-S4: Partial Array Self-Refresh: Bank Masking Each bank of LPDDR2 SDRAM can be independently configured whether a self refresh operation is taking place. One mode register unit of 8 bits accessible via MRW command is assigned to program the bank masking status of each bank up to 8 banks. For bank masking bit assignments, see Mode Register 16 The mask bit to the bank controls a refresh operation of entire memory within the bank. If a bank is masked via MRW, a refresh operation to the entire bank is blocked and data retention by a bank is not guaranteed in self refresh mode. To enable a refresh operation to a bank, a coupled mask bit has to be programmed, "unmasked". When a bank mask bit is unmasked, a refresh to a bank is determined by the programmed status of segment mask bits, which is decribed in the following chapter. 6.4.19 LPDDR2-S4: Partial Array Self-Refresh: Segment Masking Segment masking scheme may be used in place of or in combination with bank masking scheme in LPDDR2-S4 SDRAM. The number of segments differ by the density and the setting of each segment mask bit is applied across all the banks. For segment masking bit assignments, see Mode Register 17. For those refresh-enabled banks, a refresh operation to the address range which is represented by a segment is blocked when the mask bit to this segment is programmed, "masked". Programming of segment mask bits is similar to the one of bank mask bits. - 51 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb Example of Bank and Segment Masking use in LPDDR2-S4 devices Segment Mask (MR17) Segment Mask (MR16) Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 0 1 0 0 0 0 0 1 Segment 0 0 - M - - - - - M Segment 1 0 - M - - - - - M Segment 2 1 M M M M M M M M Segment 3 0 - M - - - - - M Segment 4 0 - M - - - - - M Segment 5 0 - M - - - - - M Segment 6 0 - M - - - - - M Segment 7 1 M M M M M M M M Note : This table illustrates an example of an 8-bank LPDDR2-S4 device, when a refresh operation to bank 1 and bank 7, as well as segment 2 and segment 7 are masked. 6.4.20 Mode Register Read Command The Mode Register Read command is used to read configuration and status data from mode registers. The Mode Register Read (MRR) command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r- CA4r}. The mode register contents are available on the first data beat of DQ[0:7], RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Mode Register Read Command is issued. Subsequent data beats contain valid, but undefined content. The MRR command has a burst length of four. The Mode Register Read operation (consisting of the MRR command and the corresponding data traffic) shall not be interrupted. The MRR command period (tMRR) is 2 clock cycles. Mode Register Reads to reserved and write-only registers shall return valid, but undefined content on all data beats and DQS shall be toggled. - 52 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.20.1 Figure of Mode Register Read timing example : RL = 3, tMRR = 2 T0 T2 T1 T3 T4 T5 T7 T6 T8 CK_t / CK_c CA0-9 [Cmd] DQS_t DQS_c Reg A Reg A Reg B MRR Reg B MRR tMRR = 2 tMRR = 2 RL = 3 DQ[0-7] DQ[8-max] DOUT A UNDEF UNDEF UNDEF DOUT B UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF UNDEF CMD not allowed Note:1. Mode Register Read has a burst length of four. 2. Mode Register Read operation shall not be interrupted. 3. Mode Register data is valid only on DQ[0-7] on the first beat. Subsequent beats contain valid, but undefined data. DQ[8-max] contain valid, but undefined data for the duration of the MRR burst. 4. The Mode Register Command period is tMRR. No command (other than Nop) is allowed during this period. 5. Mode Register Reads to DQ Calibration registers MR32 and MR40 are described in the section on DQ Calibration. 6. Minimum Mode Register Read to write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 - WL clock cycles. 7. Minimum Mode Register Read to Mode Register Write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 clock cycles. The MRR command shall not be issued earlier than BL/2 clock cycles after a prior Read command and WL + 1 + BL/2 + RU( tWTR/tCK) clock cycles after a prior Write command, because read-bursts and write-bursts shall not be truncated by MRR. Note that if a read or write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated burst should be used as "BL." - 53 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.20.2 Figure of LPDDR2 Read to MRR timing example : RL = 3, tMRR = 2 T0 T2 T1 T3 T4 T5 T7 T6 T8 CK_t / CK_c CA0-9 BA M Col Addr A [Cmd] Col Addr A Reg B Read Reg B MRR tMRR = 2 BL / 2 DQS_c DQS_t RL = 3 DQ[0-7] DQ[8-max] DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT B UNDEF UNDEF UNDEF DOUT A0 DOUT A1 DOUT A2 DOUT A3 UNDEF UNDEF UNDEF UNDEF CMD not allowed Note :1.The minimum number of clocks from the burst read command to the Mode Register Read command is BL/2. 2.The Mode Register Read Command period is tMRR. No command (other than Nop) is allowed during this period 6.4.20.3 Figure of LPDDR2 : Burst Write Followed by MRR : RL = 3, WL = 1, BL = 4 T1 T0 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 [Cmd] BA N Col Addr A Reg B Col Addr A Write Reg B MRR RL = 3 DQS_c DQS_t tWTR WL = 1 DIN A0 DIN A1 DIN A2 tMRR = 2 DIN A3 CMD not allowed Note :1.The minimum number of clock cycles from the burst write command to the Mode Register Read command is [WL + 1 + BL/2 + RU( tWTR/tCK)]. 2.The Mode Register Read Command period is tMRR. No command (other than No) is allowed during this period - 54 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.21 Temperature Sensor LPDDR2 SDRAM features a temperature sensor whose status can be read from MR4. This sensor can be used to determine an appropriate refresh rate (SDRAM), determine whether AC timing derating is required in the Extended Temperature Range and/or monitor the operating temperature. Either the temperature sensor or the device TOPER (See "Operating Temperature Conditions") may be used to determine whether operating temperature requirements are being met. LPDDR2 devices shall monitor device temperature and update MR4 according to tTSI. Upon exiting self-refresh or power-down, the device temperature status bits shall be no older than tTSI. When using the temperature sensor, the actual device temperature may be higher than the TOPER specification (See "Operating Temperature Conditions" that applies for the Standard or Extended Temperature Ranges. For example, Tj may be above 85 C when MR4[2:0] equals 011b. To assure proper operation using the temperature sensor, applications should consider the following factors: TempGradient is the maximum temperature gradient experienced by the memory device at the temperature of interest over a range of 2C. ReadInterval is the time period between MR4 reads from the system. TempSensorInterval (tTSI) is maximum delay between internal updates of MR4. SysRespDelay is the maximum time between a read of MR4 and the response by the system. TempMargin: LPDDR2 devices shall allow for a 2C temperature margin between the point at which the device temperature enters the Extended Temperature Range and point at which the controller re-configures the system accordingly. Symbol Parameter Max/Min Value Unit TempGradient System Temperature Gradient Max System Dependent C/s ReadInterval MR4 Read Interval Max System Dependent ms tTSI Temperature Sensor Interval Max 32 ms SysRespDelay System Response Delay Max System Dependent ms TempMargin Device Temperature Margin Max 2 C In order to determine the required frequency of polling MR4, the system shall use the maximum TempGradient and the maximum response time of the system using the following equation: TempGradient x (ReadInterval + tTSI + SysRespDelay) 2C For example, if TempGradient is 10C/s and the SysRespDelay is 1 ms: 10C/s * (ReadInterval+32ms+1ms) 2C In this case, ReadInterval shall be no greater than 167ms. - 55 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.21.1 Figure of Temp Sensor Timing Temp < (tTSI + Readlnterval + SysRespDelay) Device Temp Margin ient Grad p Tem 2C MR4 Trip Level tTSI MR4=0x03 MR4=0x86 MR4=0x86 MR4=0x86 Temperature Sensor Update Readlnterval Host MR4 Read MRR MR4=0x03 MR4=0x06 MR4=0x86 Time SysRespDelay MRR MR4=0x86 6.4.21.2 DQ Calibration LPDDR2-S4 device features a DQ Calibration function that outputs one of two predefined system timing calibration patterns. A Mode Register Read to MR32 (Pattern "A") or MR40 (Pattern "B") will return the specified pattern on DQ[0], DQ[8], DQ[16], and DQ[24] for x32 devices. For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] may optionally drive the same information as DQ[0] or may drive 0b during the MRR burst. For LPDDR2-S4 devices, MRR DQ Calibration commands may only occur in the Idle state. Pattern MR# Bit Time 0 Bit Time 1 Bit Time 2 Bit Time 3 Description Pattern A MR32 1 0 1 0 Read to MR32 return DQ calibration pattern A Pattern B MR40 0 0 1 1 Read to MR32 return DQ calibration pattern B - 56 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.21.3 Figure of MR32 and MR40 DQ Calibration timing example: RL = 3, tMRR = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t / CK_c CA0-9 Reg 32 Reg 32 [Cmd] MRR32 Reg 40 MRR40 tMRR=2 DQS_t DQS_c Reg 40 tMRR=2 RL=3 DQ[0] 1 0 1 0 0 0 1 1 x8 DQ[7:1] 1 0 1 0 0 Pattern "A" 0 1 1 Pattern "B" x16 DQ[8] 1 0 1 0 0 0 1 1 DQ[15:9] 1 0 1 0 0 0 1 1 x32 DQ[16] 1 0 1 0 0 0 1 1 DQ[23:17] 1 0 1 0 0 0 1 1 DQ[24] 1 0 1 0 0 0 1 1 DQ[31:25] 1 0 1 0 0 0 1 1 CMD not allowed Optionally driven the same as DQ0 or to 0b NOTE : 1. Mode Register Read has a burst length of four. 2. Mode Register Read operation shall not be interrupted. 3. Mode Register Reads to MR32 and MR40 drive valid data on DQ[0] during the entire burst. For x32 devices, DQ[8], DQ[16], and DQ[24] shall drive the same information as DQ[0] during the burst. 4.For x8 devices, DQ[7:1] may optionally drive the same information as DQ[0] or they may drive 0b during the burst. For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] may optionally drive the same information as DQ[0] or they may drive 0b during the burst. 5. The Mode Register Command period is tMRR. No command (other than Nop) is allowed during this period. - 57 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.22 Mode Register Write Command The Mode Register Write command is used to write configuration data to mode registers. The Mode Register Write (MRW) command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 LOW at the rising edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r-CA4r}. The data to be written to the mode register is contained in CA9f-CA2f. The MRW command period is defined by tMRW. Mode Register Writes to readonly registers shall have no impact on the functionality of the device. For LPDDR2-S4 devices, the MRW may only be issued when all banks are in the idle precharge state. One method of ensuring that the banks are in the idle precharge state is to issue a Precharge-All command 6.4.22.1 Figure of Mode Register Write timing example : RL = 3, tMRW = 5 T1 T0 T2 Tx + 1 Tx Tx + 2 Ty Ty + 1 Ty + 2 CK_t / CK_c CA0-9 MR Addr MR Data MR Addr MR Data [Cmd] MRW MRW ANY tMRW tMRW CMD not allowed Note :1. The Mode Register Write Command period is tMRW. No command (other than Nop )is allowed during this period 2. At time Ty, the device is in the idle state 6.4.22.2 Truth Table for Mode Register Read (MRR) and Mode Register Write (MRW) Current State All Banks Idle Bank(s) Active Command Intermediate State Next State MRR Mode Register Reading (All Banks Idle) All Banks Idle MRW Mode Register Writing (All Banks Idle) All Banks Idle MRW (RESET) Resetting (Device Auto-Init) All Banks Idle MRR Mode Register Reading (Bank(s) Active) Bank(s) Active MRW Not Allowed Not Allowed MRW (RESET) Not Allowed Not Allowed - 58 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.23 Mode Register Write Reset (MRW Reset) Any MRW command issued to MRW63 initiates an MRW Reset. The MRW Reset command brings the device to the Device Auto-Initialization (Resetting) State in the Power-On Initialization sequence. The MRW Reset command may be issued from the Idle state for LPDDR2-S4 devices. This command resets all Mode Registers to their default values. No commands other than NOP may be issued to the LPDDR2 device during the MRW Reset period (tINIT4). After MRW Reset, boot timings must be observed until the device initialization sequence is complete and the device is in the Idle state. Array data for LPDDR2-S4 devices are undefined after the MRW Reset command. 6.4.24 Mode Register Write ZQ Calibration Command The MRW command is also used to initiate the ZQ Calibration command. The ZQ Calibration command is used to calibrate the LPDDR2 ouput drivers (RON) over process, temperature, and voltage. LPDDR2-S4 devices support ZQ Calibration. There are four ZQ Calibration commands and related timings times, tZQINIT, tZQRESET, tZQCL, and tZQCS. tZQINIT corresponds to the initialization calibration, tZQRESET for resetting ZQ setting to default, tZQCL is for long calibration, and tZQCS is for short calibration. The Initialization ZQ Calibration (ZQINIT) shall be performed for LPDDR2-S4 devices. This Initialization Calibration achieves a RON accuracy of +/-15%. After initialization, the ZQ Long Calibration may be used to re-calibrate the system to a RON accuracy of +/-15%. A ZQ Short Calibration may be used periodically to compensate for temperature and voltage drift in the system. The ZQReset Command resets the RON calibration to a default accuracy of +/-30% across process, voltage, and temperature. This command is used to ensure RON accuracy to +/-30% when ZQCS and ZQCL are not used. One ZQCS command can effectively correct a minimum of 1.5% (ZQCorrection) of RON impedance error within tZQCS for all speed bins assuming the maximum sensitivities specified in the `Output Driver Voltage and Temperature Sensitivity'. The appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the LPDDR2 is subject to in the application, is illustrated. The interval could be defined by the following formula: where TSens = max(dRONdT) and VSens = max(dRONdV) define the LPDDR2 temperature and voltage sensitivities. For example, if TSens = 0.75% / oC, VSens = 0.20% / mV, Tdriftrate = 1 oC / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calculated as: For LPDDR2-S4 devices, a ZQ Calibration command may only be issued when the device is in Idle state with all banks precharged. No other activities can be performed on the LPDDR2 data bus during the calibration period (tZQINIT, tZQCL, tZQCS). The quiet time on the LPDDR2 data bus helps to accurately calibrate RON. There is no required quiet time after the ZQ Reset command. If multiple devices share a single ZQ Resistor, only one device may be calibrating at any given time. After calibration is achieved, the LPDDR2 device shall disable the ZQ ball's current consumption path to reduce power. In systems that share the ZQ resistor between devices, the controller must not allow overlap of tZQINIT, tZQCS, or tZQCL between the devices. ZQ Reset overlap is allowed. If the ZQ resistor is absent from the system, ZQ shall be connected to VDDCA. In this case, the LPDDR2 device shall ignore ZQ calibration commands and the device will use the default calibration settings. - 59 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.24.1 Figure of ZQ Calibration Initialization timing example T0 T1 T2 T3 T4 T5 Tx Tx+1 Tx+2 Tx+1 Tx+2 CK_t / CK_c CA0-9 MR Addr MR Data [Cmd] MRW ANY tZQINIT CMD not allowed Note 1. The ZQ Calibration Initialization period is tZQINIT. No command (other than Nop) is allowed during this period. 2. CKE must be continuously registered HIGH during the calibration period. 3. All devices connected to the DQ bus should be high impedance during the calibration process. 6.4.24.2 Figure of ZQ Calibration Short timing example T0 T1 T2 T3 T4 T5 Tx CK_t / CK_c CA0-9 [Cmd] MR Addr MR Data MRW ANY tZQCS CMD not allowed Note 1. The ZQ Calibration Short period is tZQCS. No command (other than Nop) is allowed during this period. 2. CKE must be continuously registered HIGH during the calibration period. 3. All devices connected to the DQ bus should be high impedance during the calibration process. - 60 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.24.3 Figure of ZQ Calibration Long timing example T0 T1 T2 T3 T4 T5 Tx Tx+1 Tx+2 CK_t / CK_c CA0-9 MR Addr MR Data [Cmd] MRW ANY tZQCL CMD not allowed Note 1. The ZQ Calibration Long period is tZQCL. No command (other than Nop) is allowed during this period. 2. CKE must be continuously registered HIGH during the calibration period. 3. All devices connected to the DQ bus should be high impedance during the calibration process. 6.4.24.4 Figure of ZQ Calibration Reset timing example T0 T1 T2 T3 T4 T5 Tx Tx+1 Tx+2 CK_t / CK_c CA0-9 [Cmd] MR Addr MR Data MRW ANY tZQRESET CMD not allowed Note 1. The ZQ Calibration Reset period is tZQRESET. No command (other than Nop) is allowed during this period 2. CKE must be continuously registered HIGH during the calibration period. 3. All devices connected to the DQ bus should be high impedance during the calibration process. - 61 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.25 ZQ External Resistor Value, Tolerance, and Capacitive Loading To use the ZQ Calibration function, a 240 Ohm +/- 1% tolerance external resistor must be connected between the ZQ pin and ground. A single resistor can be used for each LPDDR2 device or one resistor can be shared between multiple LPDDR2 devices if the ZQ calibration timings for each LPDDR2 device do not overlap. The total capacitive loading on the ZQ pin must be limited. 6.4.26 Power-down For LPDDR2 SDRAM, power-down is synchronously entered when CKE is registered LOW and CS_n HIGH at the rising edge of clock. CKE must be registered HIGH in the previous clock cycle. A NOP command must be driven in the clock cycle following the power-down command. CKE is not allowed to go LOW while mode register, read, or write operations are in progress. CKE is allowed to go LOW while any of other operations such as row activation, precharge, autoprecharge, or refresh is in progress, but power-down IDD spec will not be applied until finishing those operations. For LPDDR2 SDRAM, if power-down occurs when all banks are idle, this mode is referred to as idle power- down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK_t, CK_c, and CKE. In power-down mode, CKE must be maintained LOW while all other input signals are "Don't Care". CKE LOW must be maintained until tCKE has been satisfied. VREF must be maintained at a valid level during power down., VDDQ may be turned off during power down. If VDDQ is turned off, then VREFDQ must also be turned off. Prior to exiting power down, both VDDQ and VREFDQ must be within their respective min/max operating ranges. For LPDDR2 SDRAM, the maximum duration in power-down mode is only limited by the refresh requirements, as no refresh operations are performed in power-down mode. The power-down state is exited when CKE is registered HIGH. The controller shall drive CS_n HIGH in conjunction with CKE HIGH when exiting the power-down state. CKE HIGH must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down exit latency, tXP after CKE goes HIGH. 6.4.26.1 Figure of LPDDR2-S4 : Basic power down entry and exit timing diagram 2 tCK(min) CK_c CK_t tIHCKE Input clock frequency may be changed or the input clock stopped during Power-Down CKE tIHCKE tISCKE tISCKE CS_n [CMD] Valid Enter PD Exit PD NOP Valid Valid tXP(min) tCKE(min) Enter Power-Down mode NOP Exit Power-Down mode tcKE(min) Note :1. Input clock frequency may be changed or the input clock stopped during power-down, provided that upon exiting power-down, the clock is stable and within specified limits for a minmum of 2 clock cycles prior to power-down exit and the clock frequency is between the minimum and maximum frequency for the particular speed grade - 62 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.26.2 Figure of Example of CKE intensive environment CK_c CK_t tCKE tCKE CKE tCKE tCKE 6.4.26.3 Figure of Refresh to Refresh timing with CKE intensive environment for LPDR2 SDRAM CK_c CK_t CKE tCKE tCKE tXP [Cmd] tCKE REF tCKE tXP REF tREFI Note : The pattern shown above can repeat over a long period of time. With this pattern, LPDDR2 SDRAM guarantees all AC and DC timing & voltage specifications with temperature and voltage drift - 63 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.26.4 Figure of Read to power - down entry T0 CK_c CK_t [Cmd] T1 T2 Tx+1 Tx Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 Read operation starts with a read command and CKE should be kept HIGH until the end of burst operation. RD CKE RL DQ Q Q Q tISCKE Q DQS_t DQS_c T0 [Cmd] T1 T2 Tx+1 Tx Tx+2 Tx+3 RD Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 CKE should be kept HIGH until the end of burst operation. CKE RL DQ DQS_t DQS_c Q Q Q Q Q tISCKE Q Q Q Note : CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1 clock cycles after the clock on which the Read command is registered 6.4.26.5 Figure of LPDDR2 SDRAM Read with auto precharge to power-down entry T0 T1 T2 Tx+1 Tx CK_c CK_t Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 Start internal precharge [Cmd] RDA PRE BL = 4 CKE should be kept HIGH until the end of burst operation. BL/2 With tRTP = 7.5ns & tRAS min satisfied CKE RL tISCKE DQ Q Q Q Q DQS_t DQS_c T0 T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 Start internal precharge [Cmd] RDA BL = 8 CKE DQ PRE CKE should be kept HIGH until the end of burst operation. BL/2 With tRTP = 7.5ns & tRAS min satisfied RL tISCKE Q Q Q Q Q Q Q Q DQS_t DQS_c Note : CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK)+ BL/2 + 1 clock cycles after the clock on which the Read command is registered - 64 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.26.6 Figure of Write to power-down entry T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx+1 Tx Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+2 Tx+3 Tx+4 CK_c CK_t [Cmd] WR BL = 4 CKE WL DQ D D D tISCKE D tWR DQS_t DQS_c T0 T1 [Cmd] Tm Tm+1 Tm+2 Tm+3 Tm+4 D D Tm+5 Tx Tx+1 WR BL = 8 CKE WL DQ D D D D D tISCKE D tWR DQS_t DQS_c Note : CKE may be registered LOW WL + 1 + BL/2 + RU(tWR/tCK)clock cycles after the clock on which the Write command is registered 6.4.26.7 Figure of LPDDR2-S4: Write with autoprecharge to power-down entry T0 CK_c CK_t [Cmd] T1 Tm Tm+1 Tm+2 Tm+3 Tx+1 Tx WRA Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Start Internal Precharge PRE BL = 4 CKE WL tISCKE DQ D D D D tWR DQS_t DQS_c T0 T1 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx Tx+1 Tx+2 Tx+3 Tx+4 CK_c CK_t [Cmd] PRE WRA Start Internal Precharge CKE DQ DQS_t DQS_c BL = 8 WL D D D D D D D tISCKE D tWR Note : CKE may be registered LOW WL + 1 + BL/2 + RU(tWR/tCK) + 1 clock cycles after the Write command is registered - 65 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.26.8 Figure of LPDDR2-S4 Refresh command to power-down entry T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T8 T9 T10 T11 T8 T9 T10 T11 CK_c CK_t [Cmd] REF CKE tIHCKE tISCKE Note : CKE may go LOW tIHCKE after the clock on which the Refresh command is registered 6.4.26.9 Figure of Activate command to power-down entry T0 T1 T2 T3 T4 T5 T6 T7 CK_c CK_t [Cmd] ACT CKE tIHCKE tISCKE Note : CKE may go LOW tIHCKE after the clock on which the Activate command is registered 6.4.26.10 Figure of T0 Precharge/Precharge-all command to power-down entry T1 T2 T3 T4 T5 T6 T7 CK_c CK_t [Cmd] PRE CKE tIHCKE tISCKE Note : CKE may go LOW tIHCKE after the clock on which the Preactive/Precharge/Precharge-All command is registered - 66 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.26.11 Figure of Mode Register Read to power-down entry T0 T1 T2 Tx+1 Tx Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 CK_c CK_t Mode Register Read operation starts with a MRR command and [Cmd] MRR CKE CKE should be kept HIGH until the end of burst operation. RL tISCKE DQ Q Q Q Q DQS_t DQS_c Note : CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK)+ BL/2 + 1 clock cycles after the clock on which the Mode Register Read command is registered 6.4.26.12 Figure of MRW command to power-down entry T0 T1 T3 T2 T4 T5 T6 T7 T8 T9 T10 T11 CK_c CK_t [Cmd] MRW CKE can go to LOW tMRW after a Mode Register Write command CKE tISCKE tMRW Note : CKE may be registered LOW tMRW after the clock on which the Mode Register Write command is registered 6.4.27 LPDDR2-S4: Deep Power-Down Deep Power-Down is entered when CKE is registered LOW with CS_n LOW, CA0 HIGH, CA1 HIGH, and CA2 LOW at the rising edge of clock. A NOP command must be driven in the clock cycle following the power-down command. CKE is not allowed to go LOW while mode register, read, or write operations are in progress.All banks must be in idle state with no activity on the data bus prior to entering the Deep Power Down mode. During Deep Power-Down, CKE must be held LOW. In Deep Power-Down mode, all input buffers except CKE, all output buffers, and the power supply to internal circuitry may be disabled within the SDRAM. All power supplies must be within specified limits prior to exiting Deep Power-Down. VrefDQ and VrefCA may be at any level within minimum and maximum levels (See "Absolute Maximum DC Ratings"). However prior to exiting Deep Power-Down, Vref must be within specified limits (See "Recommended DC Operating Conditions"). - 67 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb The contents of the SDRAM may be lost upon entry into Deep Power-Down mode. The Deep Power-Down state is exited when CKE is registered HIGH, while meeting tISCKE with a stable clock input. The SDRAM must be fully re-initialized by controller as described in the Power up initialization Sequence. The SDRAM is ready for normal operation after the initialization sequence. 6.4.27.1 Figure of LPDDR2-S4 Deep power down entry and exit timing diagram Tc 2 tCK(min) CK_c CK_t tIHCKE Input clock frequency may be changed or the input clock stopped during Deep Power-Down tINIT3=200us(min) CKE tISCKE tISCKE CS_n [Cmd] NOP Enter DPD Exit NOP NOP PD NOP tRP Reset tDPD Exit Deep Power-Down mode Enter Deep Power-Down mode Note :1. Initialization sequence may start at any time after Tc. 2. tINIT2, tINIT3, and Tc refer to timings in the LPDDR2 initialization sequence. For more detail, see "Power- up, Initialization, and Power-down". 3. Input clock frequency may be changed or the input clock stopped during deep power-down, provided that upon exiting deep powerdown, the clock is stable and within specified limits for a minmum of 2 clock cycles prior to deep power-down exit and the clock frequency is between the minimum and maximum frequency for the particular speed grade 6.4.28 Input clock stop and frequency change LPDDR2 devices support input clock frequency change during CKE LOW under the following conditions: * tCK(MIN) and tCK(MAX) are met for each clock cycle; * Refresh Requirements apply during clock frequency change; * During clock frequency change, only REFab or REFpb commands may be executing; * Any Activate, or Precharge commands have executed to completion prior to changing the frequency; * The related timing conditions (tRCD, tRP) have been met prior to changing the frequency; * The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW; * The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH. After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may be required to set the WR, RL etc. These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency. - 68 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb LPDDR2 devices support clock stop during CKE LOW under the following conditions: * CK_t is held LOW and CK_c is held HIGH during clock stop; * Refresh Requirements apply during clock stop; * During clock stop, only REFab or REFpb commands may be executing; * Any Activate, or Precharge commands have executed to completion prior to stopping the clock; * The related timing conditions (tRCD, tRP) have been met prior to stopping the clock; * The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW; * The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH. LPDDR2 devices support input clock frequency change during CKE HIGH under the following conditions: * tCK(MIN) and tCK(MAX) are met for each clock cycle; * Refresh Requirements apply during clock frequency change; * Any Activate, Read, Write, Precharge, Mode Register Write, or Mode Register Read commands must have executed to completion, including any associated data bursts prior to changing the frequency; * The related timing conditions (tRCD, tWR, tWRA, tRP, tMRW, tMRR, etc.) have been met prior to changing the frequency; * CS_n shall be held HIGH during clock frequency change; * During clock frequency change, only REFab or REFpb commands may be executing; * The LPDDR2 device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs) for a minimum of 2tCK + tXP. After the input clock frequency is changed, additional MRW commands may be required to set the WR, RL etc. These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency. LPDDR2 devices support clock stop during CKE HIGH under the following conditions: * CK_t is held LOW and CK_c is held HIGH during clock stop; * CS_n shall be held HIGH during clock clock stop; * Refresh Requirements apply during clock stop; * During clock stop, only REFab or REFpb commands may be executing; * Any Activate, Read, Write, Precharge, Mode Register Write, or Mode Register Read commands must have executed to completion, including any associated data bursts prior to stopping the clock; * The related timing conditions (tRCD, tWR, tWRA, tRP, tMRW, tMRR, etc.) have been met prior to stopping the clock; * The LPDDR2 device is ready for normal operation after the clock is restarted and satisfies tCH(abs) and tCL(abs) for a minimum of 2tCK + tXP. 6.4.29 No Operation command The purpose of the No Operation command (NOP) is to prevent the LPDDR2 device from registering any unwanted command between operations. Only when the CKE level is constant for clock cycle N-1 and clock cycle N, a NOP command may be issued at clock cycle N. A NOP command has two possible encodings: 1. CS_n HIGH at the clock rising edge N. 2. CS_n LOW and CA0, CA1, CA2 HIGH at the clock rising edge N. The No Operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 6.4.30 Truth tables Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the LPDDR2 device must be powered down and then restarted through the specified initialization sequence before normal operation can continue. - 69 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.31 Command truth table Command Pins Command MRW MRR Refresh (per bank)11 Refresh (all bank) CKE CK_t(n-1) CK_t(n) H H H H H H H Enter H Self Refresh X Activate (bank) Write (bank) Read H H H L H H H H H H BST H H (bank) Precharge (per bank, all bank) Enter Deep H Power Down X NOP H Maintain PD, SREF,DPD(NOP) NOP Maintain PD, SREF,DPD(NOP) L H L L H H L Enter H Power Down X Exit PD, L SREF,DPD X L L H DDR CA pins (10) CS_N CA0 CA1 CA2 CK CA3 CA4 CA5 CA6 CA7 CA8 CA9 MA5 L L L L L MA0 MA1 MA2 MA3 MA4 X MA6 MA7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 L L L L H MA0 MA1 MA2 MA3 MA4 MA5 X MA6 MA7 L L L H L BA2 X X X L X L L H L L H H X X L X X X X L L H R8 R9 R10 R11 R12 BA0 BA1 X R0 R1 R2 R3 R4 R5 R6 R7 R13 R14 L H L L RFU RFU C1 C2 BA0 BA1 BA2 X AP3,4 C3 C4 C5 C6 C7 C8 C9 C10 C11 L H L H RFU RFU C1 C2 BA0 BA1 BA2 X AP3,4 C3 C4 C5 C6 C7 C8 C9 C10 C11 L H H L H AB X X BA0 BA1 BA2 X L X H H L X L H H X L X X H H H H H H X L L X X L EDGE X X X X X H X X X H X X X H X X X H X X X Note :1. All LPDDR2 commands are defined by states of CS_n, CA0, CA1, CA2, CA3, and CKE at the rising edge of the clock. 2. For LPDDR2 SDRAM, Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. 3. AP is significant only to SDRAM. 4. AP "high" during a READ or WRITE command indicates that an auto-precharge will occur to the bank associated with the READ or WRITE command. 5. "X" means "H or L (but a defined logic level)" 6. Self refresh exit and Deep Power Down exit are asynchronous. 7. VREF must be between 0 and VDDQ during Self Refresh and Deep Power Down operation. 8. CAxr refers to command/address bit "x" on the rising edge of clock. 9. CAxf refers to command/address bit "x" on the falling edge of clock. 10. CS_n and CKE are sampled at the rising edge of clock. 11. Per Bank Refresh is only allowed in devices with 8 banks. 12. The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero. 13. AB "high"during Precharge command indicates that all bank Precharge will occur. In this case, Bank Address is do-not-care. - 70 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.32 LPDDR2-SDRAM Truth Tables The truth tables provide complementary information to the state diagram, they clarify the device behavior and the applied restrictions when considering the actual state of all the Banks. 6.4.32.1 Table of LPDDR2-S4 : CKE Table Device Current State CKEn-1 CKEn CS_n Command n *3 Active Power Down Idle Power Down Resetting Power Down Deep Power Down (DPD) Self Refresh Bank(s) Active All Banks Idle Resetting Others states *1 *1 *2 L L L L L L L L L L H H H H H H L H L H L H L H L H L L L L L H X H X H X H X H X H H H L L H *4 Operation n *4 Device Next State Note X Maintain Active Power Down Active Power Down NOP Exit Active Power Down Active 6, 9 X Maintain Idle Power Down Idle Power Down NOP Exit Idle Power Down Idle 6, 9 X Maintain Resetting Power Down Resetting Power Down NOP Exit Resetting Power Down Idle or Resetting 6, 9, 12 X Maintain Deep Power Down Deep Power Down NOP Exit Deep Power Down Power On 8 X Maintain Self Refresh Self Refresh NOP Exit Self Refresh Idle 7, 10 NOP Enter Active Power Down Active Power Down NOP Enter Idle Power Down Idle Power Dow Self-Refresh Enter Self Refresh Self Refresh DPD Enter Deep Power Down Deep Power Down NOP Enter Resetting Power Down Resetting Power Down Refer to the Command Truth Table Note :1. "CKEn" is the logic state of CKE at clock rising edge n; "CKEn-1" was the state of CKE at the previous clock edge. 2. "CS_n" is the logic state of CS_n at the clock rising edge n; 3. "Current state" is the state of the LPDDR2 device immediately prior to clock edge n. 4. "Command n" is the command registered at clock edge N, and "Operation n" is a result of "Command n". 5. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 6. Power Down exit time (tXP) should elapse before a command other than NOP is issued. 7. Self-Refresh exit time (tXSR) should elapse before a command other than NOP is issued. 8.The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Func tional Description. 9. The clock must toggle at least once during the tXP period. 10. The clock must toggle at least once during the tXSR time. 11. X' means `Don't care'. 12. Upon exiting Resetting Power Down, the device will return to the Idle state if tINIT5 has expired. - 71 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.32.2 Table of Current State Bank n - Command to Bank n Current State Any Command NOP ACTIVATE Idle Operation Next State Continue previous operation Current State Select and activate row Note Active Refresh (Per Bank) Begin to refresh Refreshing (Per Bank) 6 Refresh (All Bank) Begin to refresh Refreshing(All Bank) 7 MR Writing 7 MRW Load value to Mode Register MRR Read value from Mode Register Idle MR Reading Reset Begin Device Auto-Initialization Resetting 7, 8 Precharging 9, 15 Precharge Deactivate row in bank or banks Read Select column, and start read burst Reading Row Write Select column, and start write burst Writing Active MRR Read value from Mode Register Active MR Reading Precharge Deactivate row in bank or banks Precharging 9 Reading 10, 11 Reading Writing Read Select column, and start new read burst Write Select column, and start write burst Writing 10, 11, 12 BST Read burst terminate Active 13 Write Select column, and start new write burst Writing 10, 11 Read Select column, and start read burst Reading 10, 11, 14 BST Write burst terminate Active 13 7, 9 Power On Reset Begin Device Auto-Initialization Resetting Resetting MRR Read value from Mode Register Resetting MR Reading Note : 1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Power Down. 2. All states and sequences not shown are illegal or reserved. 3. Current State Definitions: Idle: The bank or banks have been precharged, and tRP has been met. Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accessesare in progress. Reading: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Writing: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4.The following states must not be interrupted by a command issued to the same bank. NOP commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other banks are determined by its current state, and according to Table of Current State Bank n - Command to Bank m. Precharging: starts with the registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: starts with registration of an Activate command and ends when tRCD is met. Once tRCD is met, the bank will be in the `Active' state. Read with AP Enabled: starts with the registration of the Read command with Auto Precharge enabled and ends when tRP has been met. Once tRP has been met, the bank will be in the idle state. Write with AP Enabled: starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. - 72 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 5. The following states must not be interrupted by any executable command; NOP commands must be applied to each positive clock edge during these states. Refreshing (Per Bank): starts with registration of an Refresh (Per Bank) command and ends when tRFCpb is met. Once tRFCpb is met, the bank will be in an `idle' state. Refreshing (All Bank): starts with registration of an Refresh (All Bank) command and ends when tRFCab is met. Once tRFCab is met, the device will be in an `all banks idle' state. Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Idle state. Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Resetting state. Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Active state. MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met, the bank will be in the Idle state. Precharging All: starts with the registration of a Precharge-All command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. 6. Bank-specific; requires that the bank is idle and no bursts are in progress. 7. Not bank-specific; requires that all banks are idle and no bursts are in progress. 8. Not bank-specific reset command is achieved through Mode Register Write command. 9. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for pre- charging. 10. A command other than NOP should not be issued to the same bank while a Read or Write burst with Auto Precharge is enabled. 11. The new Read or Write command could be Auto Precharge enabled or Auto Precharge disabled. 12. A Write command may be applied after the completion of the Read burst; otherwise, a BST must be used to end the Read prior to asserting a Write command. 13. Not bank-specific. Burst Terminate (BST) command affects the most recent read/write burst started by the most recent Read/Write command, regardless of bank. A Read command may be applied after the completion of the Write burst; other- wise, a BST must be used to end the Write prior to asserting a Read command. 14. A Read command may be applied after the completion of the Write burst; otherwise, a BST must be used to end the Write prior to asserting a Read command. 15. If a Precharge command is issued to a bank in the Idle state, tRP shall still apply. - 73 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 6.4.32.3 Tableof Current State Bank n - Command to Bank m Next State for NOTES Bank m Current State of Bank n Command for Bank m Any NOP Continue previous operation Idle Any Any command allowed to Bank m - 18 Activate Select and activate row in Bank m Active 7 Reading 8 Writing 8 Precharging 9 Idle MR Reading or Active MR Readin 10, 11, 13 Active 18 Reading 8 8, 14 Row Activating, Active, or Precharging Select column, and start read burst from Bank m Write Select column, and start write burst to Bank m Precharge Deactivate row in bank or banks MRR Read value from Mode Register Note Current State of Bank m Read BST Reading Operation Read or Write burst terminate an ongoing Read/Write from/to Bank m Read Select column, and start read burst from Bank m Write Select column, and start write burst to Bank m Writing Select and activate row in Bank m Active (Autoprecharge disabled) Activate Precharge Writing Deactivate row in bank or banks Precharging 9 Reading 8, 16 8 Read Select column, and start read burst from Bank m Write Select column, and start write burst to Bank m Writing Select and activate row in Bank m Active (Autoprecharge disabled) Activate Precharge Deactivate row in bank or banks Precharging 9 Reading 8, 15 8, 14, 15 Read Select column, and start read burst from Bank m Reading with Write Select column, and start write burst to Bank m Writing Autoprecharge Activate Select and activate row in Bank m Active Precharge Deactivate row in bank or banks Precharging 9 Reading 8, 15, 16 8, 15 Read Select column, and start read burst from Bank m Writing with Write Select column, and start write burst to Bank m Writing Autoprecharge Activate Select and activate row in Bank m Active Precharge Deactivate row in bank or banks Precharging 9 Power On Reset Begin Device Auto-Initialization Resetting 12, 17 Resetting MRR Read value from Mode Register Resetting MR Reading Note : 1.The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or Power Down. 2. All states and sequences not shown are illegal or reserved. 3. Current State Definitions: Idle: the bank has been precharged, and tRP has been met. Active: a row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Reading: a Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Writing: a Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. - 74 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 4. Refresh, Self-Refresh, and Mode Register Write commands may only be issued when all bank are idle. 5. A Burst Terminate (BST) command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. The following states must not be interrupted by any executable command; NOP commands must be applied during each clock cycle while in these states: Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Idle state. Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Resetting state. Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Active state. MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met, the bank will be in the Idle state. 7. tRRD must be met between Activate command to Bank n and a subsequent Activate command to Bank m. 8. Reads or Writes listed in the Command column include Reads and Writes with Auto Precharge enabled and Reads and Writes with Auto Precharge disabled. 9. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for pre- charging. 10. MRR is allowed during the Row Activating state (Row Activating starts with registration of an Activate command and ends when tRCD is met.) 11. MRR is allowed during the Precharging state. (Precharging starts with registration of a Precharge command and ends when tRP is met. 12. Not bank-specific; requires that all banks are idle and no bursts are in progress. 13. The next state for Bank m depends on the current state of Bank m (Idle, Row Activating, Precharging, or Active). The reader shall note that the state may be in transition when a MRR is issued. Therefore, if Bank m is in the Row Activating state and Precharging, the next state may be Active and Precharge dependent upon tRCD and tRP respectively. 14. A Write command may be applied after the completion of the Read burst, otherwise a BST must be issued to end the Read prior to asserting a Write command. 15. Read with auto precharge enabled or a Write with auto precharge enabled may be followed by any valid command to other banks provided that the timing restrictions of auto precharge are followed. 16. A Read command may be applied after the completion of the Write burst; otherwise, a BST must be issued to end the Write prior to asserting a Read command. 17. Reset command is achieved through Mode Register Write command. 18. BST is allowed only if a Read or Write burst is ongoing. 6.4.33 Data mask truth table Table below provides the data mask truth table. Name (Functional) DM DQs Note Write enable L Valid 1 Write inhibit H X 1 Note : Used to mask write data, provided coincident with the corresponding data - 75 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7. ELECTRICAL CHARACTERISTIC 7.1 Absolute Maximum DC Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Symbol Min Max Units Notes VDD1 supply voltage relative to VSS VDD1 -0.4 +2.3 V 2 VDD2 supply voltage relative to VSS VDD2 -0.4 +1.6 V 2 VDDCA supply voltage relative to VSSCA VDDCA -0.4 +1.6 V 2,4 VDDQ supply voltage relative to VSSQ VDDQ -0.4 +1.6 V 2,3 VIN, VOUT -0.4 +1.6 V TSTG -55 +125 C Voltage on any ball relative to VSS Storage Temperature 5 Note :1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. See "Power-Ramp" section in "Power-up, Initialization, and Power-Off" for relationships between power supplies. 3. VREFDQ 0.6 x VDDQ; however, VREFDQ may be VDDQ provided that VREFDQ 300mV. 4. VREFCA 0.6 x VDDCA; however, VREFCA may be VDDCA provided that VREFCA 300mV. 5.Storage Temperature is the case surface temperature on the center/top side of the LPDDR2 device. For the measurement conditions, please refer to JESD51-2 standard. 7.2 AC & DC operating conditions Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the LPDDR2 Device must be powered down and then restarted through the specialized initialization sequence before normal operation can continue. 7.2.1 Recommended DC Operating Conditions 7.2.1.1 Recommended DC Operating Conditions Symbol LPDDR2-S4B DRAM Unit 1.95 Core Power1 V 1.20 1.30 Core Power2 V 1.14 1.20 1.30 Input Buffer Power V 1.14 1.20 1.30 I/O Buffer Power V Min Typ Max VDD1 1.70 1.80 VDD2 1.14 VDDCA VDDQ Note :1. When VDD2 is used, VDD1 uses significantly less current than VDD2; - 76 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.2.2 Input Leakage Current Parameter/Condition Symbol Min Max Unit Note IL -2 2 uA 2 IVREF -1 1 uA 1 Input Leakage current For CA, CKE, CS_n, CK_t, CK_c Any input 0V VIN VDDCA (All other pins not under test = 0V) VREF supply leakage current VREFDQ = VDDQ/2 or VREFCA = VDDCA/2 (All other pins not under test = 0V) Note :1. The minimum limit requirement is for testing purposes. The leakage current on VREFCA and VREFDQ pins should be minimal. 2. Although DM is for input only, the DM leakage shall match the DQ and DQS_t/DQS_c output leakage specification. 7.2.3 Operating Temperature Conditions Parameter/Condition Symbol Standard TOPER Extended Min Max Unit -40 85 85 105 Note :1. Operating Temperature is the case surface temperature on the center/top side of the LPDDR2 device. For the measurement conditions, please refer to JESD51-2 standard. 2. Some applications require operation of LPDDR2 in the maximum temperature conditons in the Extended Temperature Range between 85 and 105 temperature. For LPDDR2 devices, some derating is neccessary to operate in this range. (see the MR4 Device Temperature (MA[7:0] = 04h) table). 3. Either the device temperature rating or the temperature sensor (See "Temperature Sensor" ) may be used to set an appropriate refresh rate (SDRAM), determine the need for AC timing derating (SDRAM ) and/or monitor the operating temperature (SDRAM). When using the temperature sensor, the actual device temperature may be higher than the TOPER rating that applies for the Standard or Extended Temperature Ranges. For example, Tj may be above 85C when the temperature sensor indicates a temperature of less than 85C. 7.2.4 AC and DC Input Measurement Levels 7.2.4.1 AC and DC Logic Input Levels for Single-Ended Signals 7.2.4.1.1 Table of Single-Ended AC and DC Input Levels for CA and CS_n Inputs LPDDR2-1066 to LPDDR2-466 Symbol LPDDR2-400 to LPDDR2-200 Parameter Min Max Min Max Unit Note VIHCA(AC) AC input logic high Vref + 0.220 Note 2 Vref + 0.300 Note 2 V 1, 2 VILCA(AC) AC input logic low Note 2 Vref - 0.220 Note 2 Vref - 0.300 V 1, 2 VIHCA(DC) DC input logic high Vref + 0.130 VDDCA Vref + 0.200 VDDCA V 1 VILCA(DC) DC input logic low VSSCA Vref - 0.130 VSSCA Vref - 0.200 V 1 0.49 * VDDCA 0.51 * VDDCA 0.49 * VDDCA 0.51 * VDDCA V 3, 4 VRefCA(DC) Reference Voltage for CA and CS_n inputs Note 1. For CA and CS_n input only pins. Vref = VrefCA(DC). 2. See "Overshoot and Undershoot Specifications" 3. The ac peak noise on VRefCA may not allow VRefCA to deviate from VRefCA(DC) by more than +/-1% VDDCA (for reference: approx. +/12 mV) 4. For reference: approx. VDDCA/2 +/- 12 mV - 77 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.2.4.1.2 Table of Single-Ended AC and DC Input Levels for CKE Symbol Parameter Min Max Unit Note VIHCKE CKE Input High Level 0.8 * VDDCA Note 1 V 1 VILCKE CKE Input Low Level Note 1 0.2 * VDDCA V 1 Note : See "Overshoot and Undershoot Specifications" 7.2.4.1.3 Table of Single-Ended AC and DC Input Levels for DQ and DM LPDDR2-1066 to LPDDR2-466 Symbol LPDDR2-400 to LPDDR2-200 Parameter Min Max Min Max Unit Note VIHDQ(AC) AC input logic high Vref + 0.220 Note 2 Vref + 0.300 Note 2 V 1,2 VILDQ(AC) AC input logic low Note 2 Vref - 0.220 Note 2 Vref - 0.300 V 1,2 VIHDQ(DC) DC input logic high Vref + 0.130 VDDQ Vref + 0.200 VDDQ V 1 VILDQ(DC) DC input logic low VSSQ Vref - 0.130 VSSQ Vref - 0.200 V 1 0.49 * VDDQ 0.51 * VDDQ 0.49 * VDDQ 0.51 * VDDQ V 3, 4 VRefDQ(DC) Reference Voltage for DQ, DM inputs Note 1. For DQ input only pins. Vref = VrefDQ(DC) 2. See "Overshoot and Undershoot Specifications" 3. The ac peak noise on VRefDQ may not allow VRefDQ to deviate from VRefDQ(DC) by more than +/-1% VDDQ (for reference: approx. +/- 12 mV) 4. For reference: approx. VDDQ/2 +/- 12 mV 7.2.4.2 Vref Tolerances The DC tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in.the Figure below. It shows a valid reference voltage VRef(t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise). VDD stands for VDDCA for VRefCA and VDDQ for VRefDQ. VRef(DC) is the linear average of VRef(t) over a very long period of time (e.g. 1 sec) and is specified as a fraction of the linear average of VDDQ or VDDCA also over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in Table of Single-Ended AC and DC Input Levels for CA and CS_n Inputs. Furthermore VRef(t) may temporarily deviate from VRef(DC) by no more than +/- 1% VDD. Vref(t) cannot track noise on VDDQ or VDDCA if this would send Vref outside these specifications. - 78 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.2.4.2.1 Figure of Illustration of VRef(DC) tolerance and VRef ac-noise limits voltage VDD VRef (t) VRef ac-noise VRef (DC)max VDD/2 VRef (DC)min VRef (DC) VSS time The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VRef. "VRef " shall be understood as VRef(DC), as defined in Figure above. This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. Devices will function correctly with appropriate timing deratings with VREF outside these specified levels so long as: VREF is maintained between 0.44 x VDDQ (or VDDCA) and 0.56 x VDDQ (or VDDCA) and so long as the controller achieves the required single-ended AC and DC input levels from instantaneous VREF (see the Single-Ended AC and DC Input Levels for CA and CS_n Inputs Table and Single-Ended AC and DC Input Levels for DQ and DM) Therefore, system timing and voltage budgets need to account for VRef deviations outside of this range. This also clarifies that the LPDDR2 setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD) are included in LPDDR2 timings and their associated deratings. - 79 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.2.4.3 Input Signal 7.2.4.3.1 LPDDR2-466 to LPDDR2-1066 Input Signal VIL and VIH Levels With Ringback 1.550V VDD + 0.35V 1.200V VDD 0.820V VIH(AC) 0.730V VIH(DC) 0.624V 0.612V 0.600V 0.588V 0.576V VREF + AC noise VREF + DC error VREF - DC error VREF - AC noise 0.470V VIL(DC) 0.380V VIL(AC) 0.000V VSS Minimum VIL and VIH Levels 0.820V 0.730V VIH(AC) VIH(DC) 0.624V 0.612V 0.600V 0.588V 0.576V 0.470V 0.380V VIL(DC) VIL(AC) -0.350V VSS - 0.35V Note :1. Numbers reflect nominal values. 2.For CA0-9, CK_t, CK_c, and CS_n, VDD stands for VDDCA. For DQ, DM, DQS_t, and DQS_c, VDD stands for VDDQ. 3. For CA0-9, CK_t, CK_c, and CS_n, VSS stands for VSSCA. For DQ, DM, DQS_t, and DQS_c, VSS stands for VSSQ. - 80 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.2.4.3.2 LPDDR2-200 to LPDDR2-400 Input Signal VIL and VIH Levels With Ringback 1.550V VDD + 0.35V 1.200V VDD 0.900V VIH(AC) 0.800V VIH(DC) Minimum VIL and VIH Levels 0.900V 0.800V VIH(AC) VIH(DC) 0.624V 0.624V 0.612V 0.600V 0.588V 0.576V 0.612V 0.600V 0.588V 0.576V 0.400V 0.300V VIL(DC) VIL(AC) VREF + AC noise VREF + DC error VREF - DC error VREF - AC noise 0.400V VIL(DC) 0.300V VIL(AC) 0.000V VSS -0.350V VSS - 0.35V Note :1. Numbers reflect nominal values. 2. For CA0-9, CK_t, CK_c, and CS_n, VDD stands for VDDCA. For DQ, DM, DQS_t, and DQS_c, VDD stands for VDDQ. 3. For CA0-9, CK_t, CK_c, and CS_n, VSS stands for VSSCA. For DQ, DM, DQS_t, and DQS_c, VSS stands for VSSQ. - 81 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.2.4.4 AC and DC Logic Input Levels for Differential Signals 7.2.4.4.1 Differential signal definition Figure of Definition of differential ac-swing and "time above ac-level" tDVAC Differntial voltage tDVAC VIHDIFF(AC)MIN VIHDIFF(DC)MIN CK_t-CK_c DQS_t-DQS_c 0.0 VILDIFF(DC)MAX VILDIFF(AC)MAX Half cycle tDVAC time 7.2.4.4.2 Differential swing requirements for clock and strobe Table of Differential AC and DC Input Levels LPDDR2-1066 to LPDDR2-466 Symbol Parameter Min Max VIHdiff(dc) Differential input 2 x (VIH(dc) - Vref) high VILdiff(dc) Differential input logic low VIHdiff(ac) Differential input 2 x (VIH(ac) - Vref) high ac VILdiff(ac) Differential input low ac Note 3 Note 3 LPDDR2-400 to LPDDR2-200 Unit Note Note 3 V 1 Note 3 2 x (Vref - VIL(dc)) V 1 Note 3 2 x (VIH(ac) - Vref) Note 3 V 2 2 x (Vref - VIL(ac)) Note 3 2 x (Vref - VIL(ac)) V 2 Min Max Note 3 2 x (VIH(dc) - Vref) 2 x (Vref - VIL(dc)) Note 1. Used to define a differential signal slew-rate. 2.For CK_t - CK_c use VIH/VIL(ac) of CA and VREFCA; for DQS_t - DQS_c, use VIH/VIL(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however the single-ended signals CK_t, CK_c, DQS_t, and DQS_c need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" . 4. For CK_t and CK_c, Vref = VrefCA(DC). For DQS_t and DQS_c, Vref = VrefDQ(DC). - 82 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb Table of Allowed time before ringback (tDVAC) for CK_t - CK_c and DQS_t - DQS_c Slew Rate [V/ns] tDVAC [ps] tDVAC [ps] @ |VIHdiff(ac) or VILdiff(ac)| = 440mV @ |VIHdiff(ac) or VILdiff(ac)| = 600mV > 4.0 175 75 4.0 170 57 3.0 167 50 2.0 163 38 1.8 162 34 1.6 161 29 1.4 159 22 1.2 155 13 1.0 150 0 < 1.0 150 0 7.2.4.5 Single-ended requirements for differential signals Each individual component of a differential signal (CK_t, DQS_t, CK_c, or DQS_c) has also to comply with certain requirements for single-ended signals. CK_t and CK_c shall meet VSEH(ac)min / VSEL(ac)max in every half-cycle. DQS_t, DQS_c shall meet VSEH(ac)min / VSEL(ac)max in every half-cycle preceeding and following a valid transition. Note that the applicable ac-levels for CA and DQ's are different per speed-bin. Figure of Single-ended requirement for differential signals VDDCA or VDDQ VSEH(ac) VSEH(ac)min VDDCA/2 or VDDQ/2 CK_t,CK_ DQS_t, or DQS_c VSEL(ac)max VSEL(ac) VSSCA or VSSQ time - 83 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb Note that while CA and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have a requirement with respect to VDDQ/2 for DQS and VDDCA/2 for CK; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSEL(ac)max, VSEH(ac)min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. The signal ended requirements for CK and DQS are found in tables of Single-Ended AC and DC Input Levels for CA and CS_n Inputs and table of Single-Ended AC and DC Input Levels for DQ and DM respectively. Table of Single-ended levels for CK_t, DQS_t, CK_c, DQS_c LPDDR2-1066 to LPDDR2-466 Symbol Parameter Min Max Single-ended high-level VSEH (AC) for strobes Single-ended high-level for CK_t, CK_c Single-ended low-level for VSEL strobes (AC) Single-ended low-level for CK_t, CK_c LPDDR2-400 to LPDDR2-200 Min Max Unit Note (VDDQ / 2) + 0.220 Note 3 (VDDQ / 2) + 0.300 Note 3 V 1, 2 (VDDCA / 2) + 0.220 Note 3 (VDDCA / 2) + 0.300 Note 3 V 1, 2 Note 3 (VDDDQ / 2) - 0.220 Note 3 (VDDQ / 2) - 0.300 V 1, 2 Note 3 (VDDCA / 2) - 0.220 Note 3 (VDDCA / 2) - 0.300 V 1, 2 Note : 1. For CK_t, CK_c use VSEH/VSEL(ac) of CA; for strobes (DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t, DQS3_c) use VIH/VIL(ac) of DQs. 2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VSEH(ac)/VSEL(ac) for CA is based on VREFCA; if a reduced ac-high or aclow level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however the single-ended signals CK_t, CK_c, DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t, DQS3_c need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications". 7.2.4.6 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK_t, CK_c and DQS_t, DQS_c) must meet the requirements of Single-ended levels for CK_t, DQS_t, CK_c, DQS_c. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS. Figure of Vix Definition VDDCA or VDDQ CK_c, DQS_c VIX VDDCA/2 or VDDQ/2 VIX VIX CK_t, DQS_t VSSCA or VSSQ - 84 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb Table of Cross point voltage for differential input signals (CK, DQS) Symbol LPDDR2-1066 to LPDDR2-200 Parameter Min Max Unit Note VIXCA Differential Input Cross Point Voltage relative to VDDCA/2 for CK_t, CK_c - 120 120 mV 1,2 VIXDQ Differential Input Cross Point Voltage relative to VDDQ/2 for DQS_t, DQS_c - 120 120 mV 1,2 Note :1. The typical value of VIX(AC) is expected to be about 0.5 x VDD of the transmitting device, and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which differential input signals must cross. 2. For CK_t and CK_c, Vref = VrefCA(DC). For DQS_t and DQS_c, Vref = VrefDQ(DC). 7.2.4.7 Slew Rate Definitions for Single-Ended Input Signals See "Address / Command CA and CS_n Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals. See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals. 7.2.4.8 Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK_t, CK_c and DQS_t, DQS_c) are defined and measured as shown in Table and Figure below. Table of Differential Input Slew Rate Definition Measured Description Differential input slew rate for rising edge (CK_t - CK_c and DQS_t - DQS_c). Differential input slew rate for falling edge from to VILdiffmax VIHdiffmin Defined by [VIHdiffmin - VILdiffmax] / DeltaTRdiff VIHdiffmin VILdiffmax [VIHdiffmin - VILdiffmax] / DeltaTFdiff (CK_t - CK_c and DQS_t - DQS_c). Note : The differential signal (i.e. CK_t - CK_c and DQS_t - DQS_c) must be linear between these thresholds Differential Input Voltage (i.e.DQS_t-DQS_c;CK_t-CK_c) Figure of Differential Input Slew Rate Definition for DQS_t, DQS_c and CK_t, CK_c Delta TRdiff VIHdiffmin 0 VILdiffmax Delta TFdiff - 85 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.2.5 AC and DC Output Measurement Levels 7.2.5.1 Single Ended AC and DC Output Levels Table of Single-ended AC and DC Output Levels Symbol Parameter LPDDR2-1066 to LPDDR2-200 Unit Note VOH(DC) DC output high measurement level (for IV curve linearity) 0.9 x VDDQ V 1 VOL(DC) DC output low measurement level (for IV curve linearity) 0.1 x VDDQ V 2 VOH(AC) AC output high measurement level (for output slew rate) VREFDQ + 0.12 V VOL(AC) AC output low measurement level (for output slew rate) VREFDQ - 0.12 V IOZ MMPUPD Output Leakage current (DQ, DM, DQS_t, DQS_c) Min: -5 (DQ, DQS_t, DQS_c are disabled;0VVoutVDDQ) Max: +5 Miin: -15 Max: +15 Delta RON between pull-up and pull-down for DQ/DM uA % Note 1. IOH = -0.1mA 2. IOL = 0.1mA 7.2.5.2 Differential AC and DC Output Levels Table of Differential AC and DC Output Levels of (DQS_t, DQS_c) Symbol Parameter LPDDR2-1066 to LPDDR2-200 Unit VOHdiff(AC) AC differential output high measurement level (for output SR) + 0.20 x VDDQ V VOLdiff(AC) AC differential output low measurement level (for output SR) - 0.20 x VDDQ V Note 7.2.5.3 Single Ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table and Figure below. Table of Single-ended Output Slew Rate Definition Measured Description Defined by from to Single-ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC) - VOL(AC)] / DeltaTRse Single-ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC) - VOL(AC)] / DeltaTFse Note:Output slew rate is verified by design and characterization, and may not be subject to production test. - 86 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb Figure of Single Ended Output Slew Rate Definiton Single Ended Output Vollage (i.e.DQ) Delta TRse VOH(AC) VREF VOL(AC) Delta TFse Table of Output Slew Rate (single-ended) Symbol LPDDR2-1066 to LPDDR2-200 Parameter Min Max Unit SRQse Single-ended Output Slew Rate (RON = 40 +/- 30%) 1.5 3.5 V/ns SRQse Single-ended Output Slew Rate (RON = 60 +/- 30%) 1.0 2.5 V/ns Output slew-rate matching Ratio (Pull-up to Pull-down) 0.7 1.4 Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals Note : 1. Measured with output reference load. 2. The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pulldown drivers due to process variation. 3. The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC). 4. Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving logic high and 1/2 of DQ signals per data byte driving logic low. - 87 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.2.5.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table and Figure below. Table of Differential Output Slew Rate Definition Measured Description Defined by from to Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC) [VOHdiff(AC) - VOLdiff(AC)] / DeltaTRdiff Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC) [VOHdiff(AC) - VOLdiff(AC)] / DeltaTFdiff Note: Output slew rate is verified by design and characterization, and may not be subject to production test. Figure of Differential Output Slew Rate Definition Differential Output VoltAge (i.e. DQS_t - DQS_c) Delta TRdiff VOHdiff(AC) 0 VOLdiff(AC) Delta TFdiff Table of Differential Output Slew Rate Symbol LPDDR2-1066 to LPDDR2-200 Parameter Min Max Unit SRQdiff Differential Output Slew Rate (RON = 40 +/- 30%) 3.0 7.0 V/ns SRQdiff Differential Output Slew Rate (RON = 60 +/- 30%) 2.0 5.0 V/ns Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: differential Signals Note :1. Measured with output reference load. 2. The output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC). 3. Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving logic-high and 1/2 of DQ signals per data byte driving logic-low. - 88 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.2.5.5 Overshoot and Undershoot Specifications Table of AC Overshoot/Undershoot Specification LPDDR2 Parameter Maximum peak amplitude allowed for overshoot area. (See Figure below) Maximum peak amplitude allowed for undershoot area. (See Figure below) Maximum area above VDD. (See Figure below) Maximum area below VSS. (See Figure below) 1066 933 800 667 533 400 333 Unit Max 0.35 V Max 0.35 V Max 0.15 0.17 0.20 0.24 0.30 0.40 0.48 V-ns Max 0.15 0.17 0.20 0.24 0.30 0.40 0.48 V-ns CA0-9, CS_n, CKE, CK_t, CK_c, DQ, DQS_t, DQS_c, DM Note : 1. For CA0-9, CK_t, CK_c, CS_n, and CKE, VDD stands for VDDCA. For DQ, DM, DQS_t, and DQS_c, VDD stands for VDDQ. 2. For CA0-9, CK_t, CK_c, CS_n, and CKE, VSS stands for VSSCA. For DQ, DM, DQS_t, and DQS_c, VSS stands for VSSQ. 3. Values are referenced from actual VDDQ, VDDCA, VSSQ, and VSSCA levels. Figure of Overshoot and Undershoot Definition Maximum Amplitude Overshoot Area Volts (V) VDD VSS Maximum Amplitude Undershoot Area Time (ns) Note : 1. For CA0-9, CK_t, CK_c, CS_n, and CKE, VDD stands for VDDCA. For DQ, DM, DQS_t, and DQS_c, VDD stands for VDDQ. 2. For CA0-9, CK_t, CK_c, CS_n, and CKE, VSS stands for VSSCA. For DQ, DM, DQS_t, and DQS_c, VSS stands for VSSQ. - 89 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.2.6 Output buffer characteristics 7.2.6.1 HSUL_12 Driver Output Timing Reference Load These `Timing Reference Loads' are not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. Figure of HSUL_12 Driver Output Reference Load for Timing and Slew Rate VREF 0.5 x VDDQ LPDDR2 SDRAM RTT = 50 Output VTT = 0.5 x VDDQ Cload = 5pF Note : All output timing parameter values (like tDQSCK, tDQSQ, tQHS, tHZ, tRPRE etc) are reported with respect to this reference load. This reference load is also used to report slew rate. 7.2.6.2 RONPU and RONPD Resistor Definition Note : This is under the condition that RONPD is turned off Note : This is under the condition that RONPU is turned off Figure of Output Driver Definition of Voltages and Currents Chip in Drive Mode Output Driver VDDQ IPU To Other Circuityrt Like RCV, ... RONPU IOut RONPD DQ VOut IPD VSSQ - 90 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.2.6.3 RONPU and RONPD Characteristics with ZQ Calibration Output driver impedance RON is defined by the value of the external reference resistor RZQ. Nominal RZQ is 240. Table -- Output Driver DC Electrical Characteristics with ZQ Calibration RONNOM 34.3 40.0 48.0 60.0 80.0 120.0 Mismatch between pull-up and pull-down Resistor Vout Min Nom Max Unit Note RON34PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/7 1,2,3,4 RON34PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/7 1,2,3,4 RON40PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/6 1,2,3,4 RON40PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/6 1,2,3,4 RON48PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/5 1,2,3,4 RON48PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/5 1,2,3,4 RON60PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/4 1,2,3,4 RON60PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/4 1,2,3,4 RON80PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/3 1,2,3,4 RON80PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/3 1,2,3,4 RON120PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/2 1,2,3,4 RON120PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/2 1,2,3,4 +15.00 % 1,2,3,4,5 MMPUPD -15.00 Note 1. Across entire operating temperature range, after calibration. 2. RZQ = 240. 3.The tolerance limits are specified after calibration with fixed voltage and temperature. For behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 4. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ. 5. Mesaurement definition for mismatch between pull-up and pull-down: MMPUPD: Measure RONPU and RONPD, both at 0.5 x VDDQ: For example, with MMPUPD(max) = 15% and RONPD = 0.85, RONPU must be less than 1.0. 7.2.6.3.1 Output Driver Temperature and Voltage Sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to the Tables shown Below Table of Output Driver Sensitivity Definition Resistor Vout RONPD 0.5 x RONPU VDDQ Min Max Unit Note 85 - (dR ONdT x|T| ) - (dRON d V x |V| ) 115 + (dRONdT x| T| )+(dRONdV x |V|) % 1,2 Note 1. T = T-T (@calibration), V=V-V(@ calibration) 2. dRONdT and dRONdV are not subject to production test but are verified by design and characterization. Table of Output Driver Temperature and Voltage Sensitivity Symbol Parameter Min Max Unit dRONdT RON Temperature Sensitivity 0.00 0.75 %/C dRONdV RON Voltage Sensitivity 0.00 0.20 % / mV - 91 - Note Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.2.6.4 RONPU and RONPD Characteristics without ZQ Calibration Output driver impedance RON is defined by design and characterization as default setting. Table of Output Driver DC Electrical Characteristics without ZQ Calibration RONNOM 34.3 40.0 48.0 60.0 80.0 120.0 Resistor Vout Min Nom Max Unit Note RON34PD 0.5 x VDDQ 24 34.3 44.6 1 RON34PU 0.5 x VDDQ 24 34.3 44.6 1 RON40PD 0.5 x VDDQ 28 40 52 1 RON40PU 0.5 x VDDQ 28 40 52 1 RON48PD 0.5 x VDDQ 33.6 48 62.4 1 RON48PU 0.5 x VDDQ 33.6 48 62.4 1 RON60PD 0.5 x VDDQ 42 60 78 1 RON60PU 0.5 x VDDQ 42 60 78 1 RON80PD 0.5 x VDDQ 56 80 104 1 RON80PU 0.5 x VDDQ 56 80 104 1 RON120PD 0.5 x VDDQ 84 120 156 1 RON120PU 0.5 x VDDQ 84 120 156 1 Note : Across entire operating temperature range, without calibration. - 92 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.2.6.5 RZQ I-V Curve Table of RZQ I-V Curve RON = 240 (RZQ) Voltage[V] Pull-Down Pull-Up Current [mA] / RON [Ohms] Current [mA] / RON [Ohms] default value after ZQReset With Calibration default value after ZQReset With Calibration Min Max Min Max Min Max Min Max [mA] [mA] [mA] [mA] [mA] [mA] [mA] [mA] 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.05 0.19 0.32 0.21 0.26 -0.19 -0.32 -0.21 -0.26 0.10 0.38 0.64 0.40 0.53 -0.38 -0.64 -0.40 -0.53 0.15 0.56 0.94 0.60 0.78 -0.56 -0.94 -0.60 -0.78 0.20 0.74 1.26 0.79 1.04 -0.74 -1.26 -0.79 -1.04 0.25 0.92 1.57 0.98 1.29 -0.92 -1.57 -0.98 -1.29 0.30 1.08 1.86 1.17 1.53 -1.08 -1.86 -1.17 -1.53 0.35 1.25 2.17 1.35 1.79 -1.25 -2.17 -1.35 -1.79 0.40 1.40 2.46 1.52 2.03 -1.40 -2.46 -1.52 -2.03 0.45 1.54 2.74 1.69 2.26 -1.54 -2.74 -1.69 -2.26 0.50 1.68 3.02 1.86 2.49 -1.68 -3.02 -1.86 -2.49 0.55 1.81 3.30 2.02 2.72 -1.81 -3.30 -2.02 -2.72 0.60 1.92 3.57 2.17 2.94 -1.92 -3.57 -2.17 -2.94 0.65 2.02 3.83 2.32 3.15 -2.02 -3.83 -2.32 -3.15 0.70 2.11 4.08 2.46 3.36 -2.11 -4.08 -2.46 -3.36 0.75 2.19 4.31 2.58 3.55 -2.19 -4.31 -2.58 -3.55 0.80 2.25 4.54 2.70 3.74 -2.25 -4.54 -2.70 -3.74 0.85 2.30 4.74 2.81 3.91 -2.30 -4.74 -2.81 -3.91 0.90 2.34 4.92 2.89 4.05 -2.34 -4.92 -2.89 -4.05 0.95 2.37 5.08 2.97 4.23 -2.37 -5.08 -2.97 -4.23 1.00 2.41 5.20 3.04 4.33 -2.41 -5.20 -3.04 -4.33 1.05 2.43 5.31 3.09 4.44 -2.43 -5.31 -3.09 -4.44 1.10 2.46 5.41 3.14 4.52 -2.46 -5.41 -3.14 -4.52 1.15 2.48 5.48 3.19 4.59 -2.48 -5.48 -3.19 -4.59 1.20 2.50 5.55 3.23 4.65 -2.50 -5.55 -3.23 -4.65 - 93 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb Figure of RON = 240 Ohms IV Curve after ZQReset 6 PD Max PD Min 4 PU Min PU Max mA 2 0 -2 -4 -6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.9 1.0 1.1 1.2 Voltage Figure of RON = 240 Ohms IV Curve after calibration 6 PD Max PD Min 4 PU Min PU Max mA 2 0 -2 -4 -6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Voltage - 94 - 0.8 1.1 1.2 Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.2.7 Input/Ouput Capacitance Table -- Input/output capacitance Parameter Input capacitance, CK_t and CK_c CCK Input capacitance delta, CK_t and CK_c CDCK Input capacitance, all other input-only pins CI Input capacitance delta, all other input-only pins CDI Input/output capacitance, DQ, DM, DQS_t, DQS_c CIO Input/output capacitance delta, DQS_t, DQS_c LPDDR2 1066-466 Symbol CDDQS Input/output capacitance delta, DQ, DM CDIO Input/output capacitance ZQ Pin CZQ LPDDR2 400-200 Units Note Min 1.0 pF 1,2 Max 2.0 pF 1,2 Min 0 pF 1,2,3 pF 1,2,3 Max 0.20 0.25 Min 1.0 pF 1,2,4 Max 2.0 pF 1,2,4 Min -0.40 -0.50 pF 1,2,5 Max 0.40 0.50 pF 1,2,5 Min 1.25 pF 1,2,6,7 Max 2.5 pF 1,2,6,7 Min 0 pF 1,2,7,8 Max 0.25 0.30 pF 1,2,7,8 Min -0.5 -0.6 pF 1,2,7,9 Max 0.5 0.6 pF 1,2,7,9 Min 0 pF 1,2 Max 2.5 pF 1,2 (TOPER; VDDQ = 1.14- 1.3V; VDDCA = 1.14-1.3V; VDD1 = 1.7-1.95V, LPDDR2-S4 VDD2 = 1.14-1.3V) Note 1. This parameter applies to die device only (does not include package capacitance). 2.This parameter is not subject to production test. It is verified by design. 3. Absolute value of CCK_t - CCK_c. 4. CI applies to CS_n, CKE, CA0-CA9. 5. CDI = CI - 0.5 * (CCK_t + CCK_c) 6. DM loading matches DQ and DQS. 7. MR3 I/O configuration DS OP3-OP0 = 0001B (34.3 Ohm typical) 8. Absolute value of CDQS_t and CDQS_c. 9. CDIO = CIO - 0.5 * (CDQS_t + CDQS_c) in byte-lane. - 95 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.3 IDD Specification Parameters and Test Conditions 7.3.1 IDD Measurement Conditions The following definitions are used within the IDD measurement tables: LOW: VIN VIL(DC) MAX HIGH: VIN VIH(DC) MIN STABLE: Inputs are stable at a HIGH or LOW level SWITCHING: See tables below. 7.3.1.1 Table of Definition of Switching for CA Input Signals Switching for CA CK_t CK_t CK_t CK_t CK_t CK_t CK_t CK_t (RISING) / (FALLING) / (RISING) / (FALLING) / (RISING) / (FALLING) / (RISING) / (FALLING) / Ck_C Ck_C Ck_C Ck_C Ck_C Ck_C Ck_C Ck_C (FALLING) (RISING) (FALLING) (RISING) (FALLING) (RISING) (FALLING) (RISING) Cycle N N+1 N+2 N+3 CS_n HIGH HIGH HIGH HIGH CA0 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA1 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA2 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA3 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA4 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA5 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA6 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA7 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA8 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA9 HIGH HIGH HIGH LOW LOW LOW LOW HIGH Note 1. CS_n must always be driven HIGH. 2. 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus. 3. The above pattern (N, N+1, N+2, N+3...) is used continuously during IDD measurement for IDD values that require SWITCHING on the CA bus. - 96 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.3.1.2 Table of Definition of Switching for IDD4R Clock CKE CS_n Clock Cycle Number Command CA0-CA2 CA3-CA9 All DQ Rising HIGH LOW N Read_Rising HLH LHLHLHL L Falling HIGH LOW N Read_Falling LLL LLLLLLL L Rising HIGH HIGH N+1 NOP LLL LLLLLLL H Falling HIGH HIGH N+1 NOP HLH HLHLLHL L Rising HIGH LOW N+2 Read_Rising HLH HLHLLHL H Falling HIGH LOW N+2 Read_Falling LLL HHHHHHH H Rising HIGH HIGH N+3 NOP LLL HHHHHHH H Falling HIGH HIGH N+3 NOP HLH LHLHLHL L Note 1. Data strobe (DQS) is changing between HIGH and LOW every clock cycle. 2. The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4R. 7.3.1.3 Table of Definition of Switching for IDD4W Clock CKE CS_n Clock Cycle Number Command CA0-CA2 CA3-CA9 All DQ Rising HIGH LOW N Write_Rising HLL LHLHLHL L Falling HIGH LOW N Write_Falling LLL LLLLLLL L Rising HIGH HIGH N+1 NOP LLL LLLLLLL H Falling HIGH HIGH N+1 NOP HLH HLHLLHL L Rising HIGH LOW N+2 Write_Rising HLL HLHLLHL H Falling HIGH LOW N+2 Write_Falling LLL HHHHHHH H Rising HIGH HIGH N+3 NOP LLL HHHHHHH H Falling HIGH HIGH N+3 NOP HLH LHLHLHL L Note 1.Data strobe (DQS) is changing between HIGH and LOW every clock cycle. 2.Data masking (DM) must always be driven LOW. 3.The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4W. - 97 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.3.2 IDD Specifications 7.3.2.1 Table of LPDDR2 IDD Specification Parameters and Operating Conditions Parameter/Condition Operating one bank active-precharge current: tCK = tCKmin; tRC = tRCmin; CKE is HIGH; CS_n is HIGH between valid commands; CA bus inputs are SWITCHING; Data bus inputs are STABLE Idle power-down standby current: tCK = tCKmin; CKE is LOW;CS_n is HIGH; All banks/RBs idle; CA bus inputs are SWITCHING; Data bus inputs are STABLE Idle power-down standby current with clock stop: CK_t =LOW, CK_c =HIGH; CKE is LOW;CS_n is HIGH; All banks/RBs idle; CA bus inputs are STABLE; Data bus inputs are STABLE Idle non power-down standby current: tCK = tCKmin; CKE is HIGH;CS_n is HIGH; All banks/RBs idle; CA bus inputs are SWITCHING; Data bus inputs are STABLE Idle non power-down standby current with clock stop: CK_t =LOW, CK_c =HIGH; CKE is HIGH;CS_n is HIGH; All banks/RBs idle; CA bus inputs are STABLE; Data bus inputs are STABLE Active power-down standby current tCK = tCKmin; CKE is LOW;CS_n is HIGH; One bank/RDB active; CA bus inputs are SWITCHING; Data bus inputs are STABLE Active power-down standby current with clock stop: CK_t=LOW, CK_c=HIGH; CKE is LOW;CS_n is HIGH; One bank/RDB active; CA bus inputs are STABLE; Data bus inputs are STABLE Active non power-down standby current: tCK = tCKmin; CKE is HIGH;CS_n is HIGH; One bank/RDB active; CA bus inputs are SWITCHING; Data bus inputs are STABLE Active non power-down standby current with clock stop: CK_t=LOW, CK_c=HIGH; CKE is HIGH;CS_n is HIGH; One bank/RDB active; CA bus inputs are STABLE; Data bus inputs are STABLE (x32) Symbol Power Supply 533 MHz 400 MHz Units Note IDD01 VDD1 TBD 8 mA 1 IDD02 VDD2 TBD 25 mA 1 IDD0IN VDDCA VDDQ TBD mA 1,2 IDD2P1 VDD1 TBD 0.9 mA 1 IDD2P2 VDD2 TBD 0.9 mA 1 IDD2PIN VDDCA VDDQ TBD 0.015 mA 1,2 IDD2PS1 VDD1 TBD 0.9 mA 1 IDD2PS2 VDD2 TBD 0.9 mA 1 IDD2PSIN VDDCA VDDQ TBD 0.015 mA 1,2 IDD2N1 VDD1 TBD 1.2 mA 1 IDD2N2 VDD2 TBD 10 mA 1 IDD2NIN VDDCA VDDQ TBD mA 1,2 IDD2NS1 VDD1 TBD 1.2 mA 1 IDD2NS2 VDD2 TBD 10 mA 1 IDD2NSIN VDDCA VDDQ TBD mA 1,2 IDD3P1 VDD1 TBD 2.3 mA 1 IDD3P2 VDD2 TBD 1.4 mA 1 IDD3PIN VDDCA VDDQ TBD 0.015 mA 1,2 IDD3PS1 VDD1 TBD 2.3 mA 1 IDD3PS2 VDD2 TBD 1.4 mA 1 IDD3PSIN VDDCA VDDQ TBD 0.015 mA 1,2 IDD3N1 VDD1 TBD 2 mA 1 IDD3N2 VDD2 TBD 14 mA 1 IDD3NIN VDDCA VDDQ TBD mA 1,2 IDD3NS1 VDD1 TBD 2 mA 1 IDD3NS2 VDD2 TBD 14 mA 1 IDD3NSIN VDDCA VDDQ TBD mA 1,2 - 98 - 3.5 1 3.5 0.05 3.5 0.05 3.5 0.05 3.5 0.05 Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb Parameter/Condition Operating burst read current: tCK = tCKmin; CS_n is HIGH; One bank/RDB active; BL = 4; RL = RLmin; CA bus inputs are SWITCHING; 50% data change each burst transfer Operating burst write current: tCK = tCKmin; CS_n is HIGH; One bank/RDB active; BL = 4; WL = WLmin; CA bus inputs are SWITCHING; 50% data change each burst transfer All Bank Refresh Burst current: tCK = tCKmin; CKE is HIGH; tRC = tRFCabmin; Burst refresh; CA bus inputs are SWITCHING; Data bus inputs are STABLE; All Bank Refresh Average current: tCK = tCKmin; CKE is HIGH; tRC = tREFI; CA bus inputs are SWITCHING; Data bus inputs are STABLE; Per Bank Refresh Average current: tCK = tCKmin; CKE is HIGH; tRC = tREFI/8; CA bus inputs are SWITCHING; Data bus inputs are STABLE; Deep Power-Down current: CK_t=LOW, CK_c=HIGH; CKE is LOW; CA bus inputs are STABLE; Data bus inputs are STABLE; Power Supply 533 400 Symbol MHz MHz IDD4R1 VDD1 TBD IDD4R2 VDD2 IDD4RIN Units Note 2 mA 1 TBD 160 mA 1 VDDCA TBD 3.5 mA 1 IDD4W1 VDD1 TBD 3 mA 1 IDD4W2 VDD2 TBD 200 mA 1 IDD4WIN VDDCA VDDQ TBD mA 1,2 IDD51 VDD1 TBD 50 mA 1 IDD52 VDD2 TBD 120 mA 1 IDD5IN VDDCA VDDQ TBD mA 1,2 IDD5AB1 VDD1 TBD 8 mA 1 IDD5AB2 VDD2 TBD 15 mA 1 IDD5ABIN VDDCA VDDQ TBD mA 1,2 IDD5PB1 VDD1 TBD 3 mA 1 IDD5PB2 VDD2 TBD 16 mA 1 IDD5PBIN VDDCA VDDQ TBD mA 1,2 IDD81 VDD1 TBD 15 uA 1 IDD82 VDD2 TBD 15 uA 1 IDD8IN VDDCA VDDQ TBD 15 uA 1,2 3.5 12 3.5 0.05 3.5 0.05 3.5 0.05 Note :1. IDD values published are the typical of the distribution of the arithmetic mean. 2. Measured currents are the summation of VDDQ and VDDCA. 3. Guaranteed by design with output reference load of 5pfFand RON = 40Ohm. 4. IDD current specifications are tested after the device is properly initialized. - 99 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.3.2.2 Table of IDD6 Partial Array Self-Refresh Current Power Parameter Symbol Supply Full Array 1/2 Array IDD6 Partial Array Self-Refresh Current 1/4 Array 1/8 Array 533 MHz 400 MHz Condition Unit IDD61 VDD1 TBD 900 IDD62 VDD2 TBD 1900 IDD6IN VDDCA VDDQ TBD 15 IDD61 VDD1 TBD 750 IDD62 VDD2 TBD 1100 IDD6IN VDDCA VDDQ TBD 15 IDD61 VDD1 TBD 650 CA bus inputs are STABLE; IDD62 VDD2 TBD 900 Data bus inputs are STABLE; IDD6IN VDDCA VDDQ TBD 15 IDD61 VDD1 TBD 600 IDD62 VDD2 TBD 750 IDD6IN VDDCA VDDQ TBD 15 uA Self refresh current uA CK_t=LOW, CK_c=HIGH; CKE is LOW; uA uA Note :1. LPDDR2-S4 SDRAM uses the same PASR scheme & IDD6 current value categorization as LPDDR (JESD209). 2. IDD values published are the typical of the distribution of the arithmetic mean. 7.4 Clock Specification The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the LPDDR2 device. 7.4.1 Definition for tCK(avg) and nCK tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge. Unit `tCK(avg)' represents the actual clock average tCK(avg) of the input clock under operation. Unit `nCK' represents one clock cycle of the input clock, counting the actual clock edges. tCK(avg) may change by up to +/-1% within a 100 clock cycle window, provided that all jitter and timing specs are met. 7.4.2 Definition for tCK(abs) tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to production test. - 100 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.4.3 Definition for tCH(avg) and tCL(avg) tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses. 7.4.4 Definition for tJIT(per) tJIT(per) is defined as the largest deviation of any signal tCK from tCK(avg). tJIT(per) = Min/max of {tCKi - tCK(avg) where i = 1 to 200}. tJIT(per) defines the single period jitter when the DLL is already locked. tJIT(per) is not subject to production test. 7.4.5 Definition for tJIT(cc) tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles. tJIT(cc) = Max of |{tCKi +1 - tCKi}|. tJIT(cc) defines the cycle to cycle jitter. tJIT(cc) is not subject to production test. 7.4.6 Definition for tERR(nper) tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR(nper),act is the actual clock jitter over n cycles for a given system. tERR(nper),allowed is the specified allowed clock period jitter over n cycles. tERR(nper) is not subject to production test. tERR(nper),min can be calculated by the formula shown below: tERR(nper),max can be calculated by the formula shown below: Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value. - 101 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.4.7 Definition for duty cycle jitter tJIT(duty) tJIT(duty) is defined with absolute and average specification of tCH / tCL. tJIT(duty),min=MIN((tCH(abs),min-tCH(avg),min),tCL(abs),min-tCL(avg),min)) x tCK(avg) tJIT(duty),max=MAX((tCH(abs),max-tCH(avg),max),tCL(abs),max-tCL(avg),max)) x tCK(avg) 7.4.8 Definition for tCK(abs), tCH(abs) and tCL(abs) These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. Table 100 -- Definition for tCK(abs), tCH(abs), and tCL(abs) Parameter Symbol Min Unit Absolute Clock Period tCK(abs) tCK(avg),min + tJIT(per),min PS Absolute Clock HIGH Pulse Width tCH(abs) tCH(avg),min + tJIT(duty),min / tCK(avg)min tCK(avg) Absolute Clock LOW Pulse Width tCL(abs) tCL(avg),min + tJIT(duty),min / tCK(avg)min tCK(avg) Note 1. tCK(avg),min is expressed is ps for this table. 2 .tJIT(duty),min is a negative value. 7.4.9 Period Clock Jitter LPDDR2 devices can tolerate some clock period jitter without core timing parameter de-rating. This section describes device timing requirements in the presence of clock period jitter (tJIT(per)) in excess of the values found in Table of AC timing and how to determine cycle time de-rating and clock cycle de-rating. 7.4.9.1 Clock period jitter effects on core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW ) Core timing parameters extend across multiple clock cycles. Period clock jitter will impact these parameters when measured in numbers of clock cycles. When the device is operated with clock jitter within the specification limits, the LPDDR2 device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}. When the device is operated with clock jitter outside specification limits, the number of clocks or tCK(avg) may need to be increased based on the values for each core timing parameter. 7.4.9.2 Cycle time de-rating for core timing parameters For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and actual cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative period error (tERR(tnPARAM),allowed), the equation below calculates the amount of cycle time de-rating (in ns) required if the equation results in a positive value for a core timing parameter (tCORE). A cycle time derating analysis should be conducted for each core timing parameter. The amount of cycle time derating required is the maximum of the cycle time de-ratings determined for each individual core timing parameter. - 102 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.4.9.3 Clock Cycle de-rating for core timing parameters For a given number of clocks (tnPARAM) for each core timing parameter, clock cycle de-rating should be specified with amount of period jitter (tJIT(per)). For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and actual cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative period error (tERR(tnPARAM),allowed), the equation below calculates the clock cycle derating (in clocks) required if the equation results in a positive value for a core timing parameter (tCORE). A clock cycle de-rating analysis should be conducted for each core timing parameter. 7.4.9.4 Clock jitter effects on C/A timing (tIS,tIH,tISCKE,tIHCKE,tISb, tIHb, tISCKEb, tIHCKEb) These parameters are measured from a command/address signal (CKE, CS, CA0 - CA9) transition edge to its respective clock signal (CK_t/CK_c) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), as the setup and hold are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values shall be met. Clock jitter effects on Read timing parameters 7.4.9.5 Clock jitter effects on Read timing tRPRE When the device is operated with input clock jitter, tRPRE needs to be de-rated by the actual period jitter (tJIT(per),act,max) of the input clock in excess of the allowed period jitter (tJIT(per),allowed,max). Output de-ratings are relative to the input clock. For example, if the measured jitter into a LPDDR2-800 device has tCK(avg) = 2500 ps, tJIT(per),act,min = -172 ps and tJIT(per),act,max = + 193 ps, then tRPRE,min,derated = 0.9 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (193 - 100)/2500= .8628 tCK(avg) 7.4.9.6 Clock jitter effects on Read timing tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) These parameters are measured from a specific clock edge to a data signal (DMn, DQm.: n=0,1,2,3. m=0-31) transition and will be met with respect to that clock edge. Therefore, they are not affected by the amount of clock jitter applied (i.e. tJIT(per). 7.4.9.7 Clock jitter effects on Read timing parameters tQSH, tQSL These parameters are affected by duty cycle jitter which is represented by tCH(abs)min and tCL(abs)min. Therefore tQSH(abs)min and tQSL(abs)min can be specified with tCH(abs)min and tCL(abs)min. tQSH(abs)min = tCH(abs)min - 0.05 tQSL(abs)min = tCL(abs)min - 0.05 These parameters determine absolute Data-Valid window at the LPDDR2 device pin. Absolute min data-valid window @ LPDDR2 device pin = min { ( tQSH(abs)min * tCK(avg)min - tDQSQmax - tQHSmax ) , ( tQSL(abs)min * tCK(avg)min - tDQSQmax - tQHSmax ) } This minimum data-valid window shall be met at the target frequency regardless of clock jitter. - 103 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.4.9.8 Clock jitter effects on Read timing parameters tRPST tRPST is affected by duty cycle jitter which is represented by tCL(abs). Therefore tRPST(abs)min can be specified by tCL(abs)min. tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min Clock jitter effects on Write timing parameters 7.4.9.9 Clock jitter effects on Write timing parameters tDS, tDH These parameters are measured from a data signal (DMn, DQm.: n=0,1,2,3. m=0 -31) transition edge to its respective data strobe signal (DQSn_t, DQSn_c : n=0,1,2,3) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), as the setup and hold are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values shall be met. 7.4.9.10 Clock jitter effects on Write timing parameters tDSS, tDSH These parameters are measured from a data strobe signal (DQSx_t, DQSx_c) crossing to its respective clock signal (CK_t/CK_c) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), as the setup and hold are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values shall be met. 7.4.9.11 Clock jitter effects on Write timing parameters tDQSS This parameter is measured from a data strobe signal (DQSx_t, DQSx_c) crossing to the subsequent clock signal (CK_t/CK_c) crossing. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual period jitter tJIT(per),act of the input clock in excess of the allowed period jitter tJIT(per),allowed. For example, if the measured jitter into a LPDDR2-800 device has tCK(avg)= 2500 ps, tJIT(per),act,min= -172 ps and tJIT(per),act,max= + 193 ps, then tDQSS,(min,derated) = 0.75 +(tJIT(per),act,min - tJIT(per),allowed,min)/tCK(avg) = 0.75 - (-172 + 100)/2500 = .7788 tCK(avg) and tDQSS,(max,derated) = 1.25 + (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 1.25 - (193 100)/2500 = 1.2128 tCK(avg) - 104 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.5 Refresh Requirements 7.5.1 LPDDR2-S4 Refresh Requirement Parameters Parameter Symbol Number of Banks 1 Gb Unit 8 Refresh WindowTj 85C tREFW 32 ms Refresh Window85C < Tj 105C ms tREFW 8 ms R 4,096 REFab tREFI 7.8 us REFpb tREFIpb 0.975 us Refresh Cycle time tRFCab 130 ns Per Bank Refresh Cycle time tRFCpb 60 ns Burst Refresh Window= 4 x 8 x tRFCab tREFBW 4.16 us Required number of REFRESH commands (min) Average time between REFRESH commands (for reference only) Tj 85C - 105 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6 AC Timings 7.6.1 Table of LPDDR2 AC Timing Parameter Symbol Max. Frequency*4 min / max ~ min tCK 1066 933 800 667 533 400 333 Unit 533 466 400 333 266 200 166 MHz 2.5 3 3.75 5 6 Clock Timing Average Clock Period tCK(avg) Average high pulse width tCH(avg) Average low pulse width tCL(avg) Absolute Clock Period tCK(abs) Absolute clock HIGH pulse width (with allowed jitter) tCH(abs) allowed Absolute clock LOW pulse width (with allowed jitter) tCL(abs) (allowed) Clock Period Jitter (with allowed jitter) tJIT(per) (allowed) Maximum Clock Jitter between two consecutive clock cycles (with allowed jitter) tJIT(cc) allowed min 1.875 2.15 ns max 100 min 0.45 max 0.55 min 0.45 max 0.55 tCK(av g) min tCK(avg)min + tJIT(per)min ps min 0.43 max 0.57 min 0.43 max 0.57 tCK(av g) tCK(av g) tCK(av g) min -90 -95 -100 -110 -120 -140 -150 max 90 95 100 110 120 140 150 max 180 190 200 220 240 280 300 ps min min((tCH(abs),min - tCH(avg),min), (tCL(abs),min tCL(avg),min)) * tCK(avg) ps max max((tCH(abs),max - tCH(avg),max), (tCL(abs),max tCL(avg),max)) * tCK(avg) ps min -132 -140 -147 -162 -177 -206 -221 max 132 140 147 162 177 206 221 min -157 -166 -175 -192 -210 -245 -262 max 157 166 175 192 210 245 262 min -175 -185 -194 -214 -233 -272 -291 max 175 185 194 214 233 272 291 Duty cycle Jitter (with allowed jitter) tJIT(duty), allowed Cumulative error across 2 cycles tERR(2per) (allowed) Cumulative error across 3 cycles tERR(3per) (allowed) Cumulative error across 4 cycles tERR(4per) (allowed) Cumulative error across 5 cycles tERR(5per) (allowed) min -188 -199 -209 -230 -251 -293 -314 max 188 199 209 230 251 293 314 Cumulative error tERR(6per) min -200 -211 -222 -244 -266 -311 -333 - 106 - ps ps ps ps ps ps Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb across 6 cycles (allowed) max 200 211 222 244 266 311 333 Cumulative error across 7 cycles tERR(7per) (allowed) min -209 -221 -232 -256 -279 -325 -348 max 209 221 232 256 279 325 348 Cumulative error across 8 cycles tERR(8per) (allowed) min -217 -229 -241 -266 -290 -338 -362 max 217 229 241 266 290 338 362 Cumulative error across 9 cycles tERR(9per) (allowed) min -224 -237 -249 -274 -299 -349 -374 max 224 237 249 274 299 349 374 Cumulative error across 10 cycles tERR(10per) (allowed) min -231 -244 -257 -282 -308 -359 -385 max 231 244 257 282 308 359 385 Cumulative error across 11 cycles tERR(11per) (allowed) min -237 -250 -263 -289 -316 -368 -395 max 237 250 263 289 316 368 395 Cumulative error across 12 cycles tERR(12per) (allowed) min -242 -256 -269 -296 -323 -377 -403 max 242 256 269 296 323 377 403 Cumulative error across n = 13, 14 . . . 49, 50 cycles tERR(nper) (allowed) min tERR(nper),allowed,min = (1 + 0.68ln(n)) * tJIT(per),allowed,min max tERR(nper),allowed,max = (1 + 0.68ln(n)) * tJIT(per),allowed,max - 107 - ps ps ps ps ps ps ps Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb Parameter Symbol min / max min tCK 1066 933 800 667 533 400 333 Unit ZQ Calibration Parameters Initialization Calibration Time*14 tZQINIT min Full Calibration Time*14 tZQCL min Short Calibration Time*14 tZQCS Calbration Reset Time*14 tZQRESET 1 us 6 360 ns min 6 90 ns min 3 50 ns Read Parameters*11 min 2500 max 5500 DQS output access time from CK_t/CK_c tDQSCK DQSCK Delta Short*15 tDQSCKDS max 330 380 450 540 670 900 1080 ps DQSCK Delta Medium*16 tDQSCKDM max 680 780 900 1050 1350 1800 1900 ps DQSCK Delta Long*17 tDQSCKDL max 920 1050 1200 1400 1800 2400 - ps DQS - DQ skew tDQSQ max 200 220 240 280 340 400 500 ps Data hold skew factor tQHS max 230 260 280 340 400 480 600 ps DQS Output High Pulse Width tQSH min tCH(abs) - 0.05 tCK(avg) DQS Output Low Pulse Width tQSL min tCL(abs) - 0.05 tCK(avg) Data Half Period tQHP min min(tQSH, tQSL) tCK(avg) DQ / DQS output hold time from DQS tQH min tQHP - tQHS ps Read preamble*11,*12 tRPRE min 0.9 tCK(avg) Read postamble*11,*13 tRPST min tCL(abs) - 0.05 tCK(avg) DQS low-Z from clock*11 tLZ(DQS) min tDQSCK(MIN) - 300 ps DQ low-Z from clock*11 tLZ(DQ) min tDQSCK(MIN) - (1.4 * tQHS(MAX)) ps DQS high-Z from clock*11 tHZ(DQS) max tDQSCK(MAX) - 100 ps DQ high-Z from clock*11 tHZ(DQ) max tDQSCK(MAX) + (1.4 * tDQSQ(MAX)) ps - 108 - ps Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb Parameter Symbol min / max min tCK 1066 933 800 667 533 400 333 Unit Write Parameters*11 DQ and DM input hold time (Vref based) tDH min 210 235 270 350 430 480 600 ps DQ and DM input setup time (Vref based) tDS min 210 235 270 350 430 480 600 ps DQ and DM input pulse width tDIPW min 0.35 Write command to 1st DQS latching transition tDQSS min 0.75 max 1.25 DQS input high-level width tDQSH min 0.4 tCK(avg) DQS input low-level width tDQSL min 0.4 tCK(avg) DQS falling edge to CK setup time tDSS min 0.2 tCK(avg) DQS falling edge hold time from CK tDSH min 0.2 tCK(avg) Write postamble tWPST min 0.4 tCK(avg) Write preamble tWPRE min 0.35 tCK(avg) 3 tCK(avg) tCK(avg) tCK(avg) CKE Input Parameters CKE min. pulse width (high and low pulse width) tCKE min CKE input setup time tISCKE*2 min 0.25 tCK(avg) CKE input hold time tIHCKE*3 min 0.25 tCK(avg) 3 Command Address Input Parameters*11 Address and control input setup time (Vref based) tIS*1 min 220 250 290 370 460 600 740 ps Address and control input hold time (Vref based) tIH*1 min 220 250 290 370 460 600 740 ps Address and control input pulse width tIPW min 0.40 - 109 - tCK(avg) Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb Parameter Symbol min / max min tCK LPDDR2 1066 933 800 667 533 400 333 Unit Boot Parameters (10 MHz - 55 MHz) *5,7 max 100 min 18 tISCKEb min 2.5 ns CKE Input Hold Time tIHCKEb min 2.5 ns Address & Control Input Setup Time tISb min 1150 ps Address & Control Input Hold Time tIHb min 1150 ps DQS Output Data Access Time from CK_t/CK_c min 2.0 tDQSCKb max 10.0 Data Strobe Edge to Ouput Data Edge tDQSQb 1.2 tDQSQb max 1.2 ns Data Hold Skew Factor tQHSb max 1.2 ns Clock Cycle Time tCKb CKE Input Setup Time - 110 - ns ns Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb Parameter Symbol min / max min tCK LPDDR2 Unit 1066 933 800 667 533 400 333 Mode Register Parameters ns MODE REGISTER Write command period tMRW min 5 5 tCK(avg) Mode Register Read command period tMRR min 2 2 tCK(avg) LPDDR2 SDRAM Core Parameters*9 Read Latency RL min 3 8 7 6 5 4 3 3 tCK(avg) Write Latency WL min 1 4 4 3 2 2 1 1 tCK(avg) ACTIVE to ACTIVE command period tRC min CKE min. pulse width during Self-Refresh (low pulse width during SelfRefresh) tCKESR min Self refresh exit to next valid command delay tXSR Exit power down to next valid command delay tRAS + tRPab (with all-bank Precharge) tRAS + tRPpb (with per-bank Precharge) ns 3 15 ns min 2 tRFCab + 10 ns tXP min 2 7.5 ns LPDDR2-S4 CAS to CAS delay tCCD min 2 2 tCK(avg) Internal Read to Precharge command delay tRTP min 2 7.5 ns RAS to CAS Delay tRCD Fast 3 15 ns Row Precharge Time (single bank) tRPpb Fast 3 15 ns Row Precharge Time (all banks) tRPab 8-bank Fast 3 18 ns Row Active Time tRAS min 3 42 ns 70 us Write Recovery Time tWR min 3 15 ns Internal Write to Read Command Delay tWTR min 2 Active bank A to Active bank B tRRD min 2 Four Bank Activate Window tFAW min 8 Minimum Deep Power Down Time tDPD min max 7.5 10 10 50 500 - 111 - ns ns 60 ns us Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb Parameter Symbol min / max min tCK LPDDR2 1066 933 800 667 533 400 333 Unit LPDDR2 Temperature De-Rating tDQSCK De-Rating Core Timings Temperature De-Rating tDQSCK (Derated) max tRCD (Derated) 5620 6000 ps min tRCD + 1.875 ns tRC (Derated) min tRC + 1.875 ns tRAS (Derated) min tRAS + 1.875 ns tRP (Derated) min tRP + 1.875 ns tRRD (Derated) min tRRD + 1.875 ns Note :1. Input set-up/hold time for signal(CA[0:n], CS_n) 2. CKE input setup time is measured from CKE reaching high/low voltage level to CK_t/CK_c crossing. 3. CKE input hold time is measured from CK_t/CK_c crossing to CKE reaching high/low voltage level 4. Frequency values are for reference only. Clock cycle time (tCK) shall be used to determine device capabilities. 5. To guarantee device operation before the LPDDR2 device is configured a number of AC boot timing parameters are defined in this Table. Boot parameter symbols have the letter b appended, e.g. tCK during boot is tCKb. 6. Frequency values are for reference only. Clock cycle time (tCK or tCKb) shall be used to determine device capabilities. 7. The SDRAM will set some Mode register default values upon receiving a RESET (MRW) command as specified in "Mode Register Definition". 8. The output skew parameters are measured with Ron default settings into the reference load. 9. The min tCK column applies only when tCK is greater than 6ns for LPDDR2-S4 devices . 10. All AC timings assume an input slew rate of 1V/ns. 11. Read, Write, and Input Setup and Hold values are referenced to Vref. 12. For low-to-high and high-to-low transitions, the timing reference will be at the point when the signal crosses VTT. tHZ and tLZ transitions occur in the same access time (with respect to clock) as valid data transitions. These parameters are not referenced to a specific voltage level but to the time when the device output is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ) ), or begins driving (for tRPRE, tLZ(DQS), tLZ(DQ) ). Figure below shows a method to calculate the point when device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. - 112 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb Figure of HSUL_12 Driver Output Reference Load for Timing and Slew Rate VOH X VOH - X mV 2x X VTT + 2x Y mV VOH - 2x X mV VTT + Y mV tLZ(DQS), tLZ(DQ) VTT VTT Y Actual waveform 2x Y VTT - Y mV tHZ(DQS), tHZ(DQ) VOL + 2x X mV VTT - 2x Y mV VOL + X mV T1 T2 VOL T1T2 Stop driving point = 2 x T1 - T2 begin driving point = 2 x T1 - T2 The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters tRPRE and tRPST are determined from the differential signal DQS_t-DQS_c. 13. Measured from the start driving of DQS_t - DQS_c to the start driving the first rising strobe edge. 14. Measured from the from start driving the last falling strobe edge to the stop driving DQS_t , DQS_c. 15. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 160ns rolling window. tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is < 10C/s. Values do not include clock jitter. 16. tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a 1.6us rolling window. tDQSCKDM is not tested and is guaranteed by design. Temperature drift in the system is < 10C/s. Values do not include clock jitter. 17. tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a 32ms rolling window. tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is < 10C/s. Values do not include clock jitter. . - 113 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6.2 CA and CS_n Setup, Hold and Derating For all input signals (CA and CS_n) the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the tIS and tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + tIS. Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded `VREF(dc) to ac region', use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded `VREF(dc) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value. Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded `dc to VREF(dc) region', use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to VREF(dc) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value. For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC. Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in Tablebelow, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. - 114 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6.2.1 Table of CA and CS_n Setup and Hold Base-Values for 1V/ns LPDDR2 unit [ps] reference 1066 933 800 667 533 tIS(base) 0 30 70 150 240 VIH/L(ac)=VREF(dc)+-220mV tIH(base) 90 120 160 240 330 VIH/L(dc)=VREF(dc)+-130mV LPDDR2 unit [ps] reference 400 333 tIS(base) 300 440 VIH/L(ac)=VREF(dc)+-300mV tIH(base) 400 540 VIH/L(dc)VREF(dc)+-200mV Note : ac/dc referenced for 1V/ns CA and CS_n slew rate and 2V/ns differential CK_t-CK_c slew rate. 7.6.2.2 Table of Derating values LPDDR2 tIS/tIH - ac/dc based AC220 tIS, tIH derating in [ps] AC/DC based AC220 Threshold -> VIH(ac)=VREF(dc)+220mV, VIL(ac)=VREF(dc)-220mV DC100 Threshold -> VIH(dc)=VREF(dc)+130mV, VIL(dc)=VREF(dc)-130mV CK_t,CK_c Differential Slew Ratee 4.0 V/ns 3.0 V/ns 2.0 V/ns tIS tIH tIS tIH tIS tIH 2.0 110 65 110 65 110 65 1.5 74 43 73 43 73 CA , 1.0 0 0 0 0 CS_n 0.9 -3 -5 Slew 0.8 1.8 V/ns 1.6 V/ns tIS tIH tIS tIH 43 89 59 0 0 16 16 32 32 -3 -5 13 11 29 -8 -13 8 3 2 -6 1.4 V/ns 1.2 V/ns tIS 1.0 V/ns tIS tIH tIH tIS tIH 27 45 43 24 19 40 35 56 55 18 10 34 26 50 46 66 78 10 -3 26 13 42 33 58 65 4 -4 20 16 36 48 -7 2 17 34 Rate V/ns 0.7 0.6 0.5 0.4 Note: Cell contents shaded in red are defined as `not supported'. - 115 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6.2.3 Table of Derating values LPDDR2 tIS/tIH - ac/dc based AC300 tIS, tIH derating in [ps] AC/DC based AC300 Threshold -> VIH(ac)=VREF(dc)+300mV, VIL(ac)=VREF(dc)-300mV DC200 Threshold -> VIH(dc)=VREF(dc)+200mV, VIL(dc)=VREF(dc)-200mV CK_t,CK_c Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns tIS tIH tIS tIH tIS tIH 2.0 150 100 150 100 150 100 1.5 100 67 100 67 100 CA, 1.0 0 0 0 0 CS_n 0.9 -4 -8 Slew 0.8 1.6 V/ns tIS tIH tIS 67 116 83 0 0 16 16 32 32 -4 -8 12 8 28 -12 -20 4 -4 -3 -18 1.2 V/ns 1.4 V/ns tIH tIS 1.0 V/ns tIS tIH tIH tIS tIH 24 44 40 20 12 36 28 52 48 13 -2 29 14 45 34 61 66 2 -21 18 -5 34 15 50 47 -12 -32 4 -12 20 20 -35 -40 -11 -8 Rate V/ns 0.7 0.6 0.5 0.4 Note: Cell contents shaded in red are defined as `not supported'. 7.6.2.4 Table of Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition Slew Rate [V/ns] tVAC @ 300mV [ps] tVAC @ 220mV [ps] min max min max > 2.0 75 - 175 - 2.0 57 - 170 - 1.5 50 - 167 - 1.0 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 150 - <0.5 0 - 150 - - 116 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6.2.5 Figure of nominal slew rate and tVAC for tIS for CA and CS_n with respect to clock. CK_c CK_t tIS tIS tIH tIH VDDCA tVAC VIH(ac) min VREF to ac region VIH(dc) min nominal Slew rate VREF(dc) nominal Slew rate VIL(dc) max VREF to ac region VIL(ac) max tVAC VssCA TF TR Setup Slew Rate = VREF(dc) - VIL(ac)max Setup Slew Rate = VIH(ac) min - VREF(dc) Falling Signal TF Rising Signal - 117 - TR Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6.2.6 Figure of nominal slew rate for hold time tIH for CA and CS_n with respect to clock CK_c CK_t tIS tIH tIS tIH VDDCA VIH(AC) min VIH(DC) min DC to VREF nominal region Slew rate VREF(DC) nominal Slew rate DC to VREF region VIL(DC) max VIL(AC) max VSSCA TR TF Hold Slew Rate = VREF(DC) - VIL(DC)max Hold Slew Rate = VIH(DC) min - VREF(DC) Rising Signal TR Falling Signal - 118 - TF Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6.2.7 Figure of tangent line for setup time tIS for CA and CS_n with respect to clock CK_c CK_t tIS tIH tIS tIH VDDCA nominal tVAC line VIH(AC) min VREF to AC region VIH(DC) min tangent line VREF(DC) tangent line VIL(DC) max VREF to AC region VIL(AC) max nominal line tVAC TR VSSCA Setup Slew Rate = tangent line[VIH(AC)min - VREF(DC)] Rising Signal TR TF Setup Slew Rate = tangent line[VREF(DC) - VIL(AC)max] Falling Signal TF - 119 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6.2.8 Figure of tangent line for for hold time tIH for CA and CS_n with respect to clock CK_c CK_t tIS tIS tIH tIH VDDCA VIH(AC) min nominal line VIH(DC) min DC to VREF tangent region line VREF(DC) DC to VREF tangent line region nominal line VIL(DC) max VIL(AC) max VSSCA TR TF Hold Slew Rate = tangent line [VREF(DC) - VIL(DC)max Rising Signal TR Hold Slew Rate = tangent line [VIH(DC)min - VREF(DC)] Falling Signal TF - 120 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6.3 Data Setup, Hold and Slew Rate Derating For all input signals (DQ, DM) the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value to the tDS and tDH derating value respectively. Example: tDS (total setup time) = tDS(base) + tDS. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded `VREF(dc) to ac region', use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded `VREF(dc) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value. Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling sig5nal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded `dc level to VREF(dc) region', use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to VREF(dc) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value. For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC. Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization 7.6.3.1 Table of Data Setup and Hold Base-Values [ps] tDS(base) tDH(base) unit [ps] 1066 LPDDR2 933 800 reference 667 533 -10 15 50 130 210 80 105 140 220 300 VIH/L(ac)=VREF(dc)+-220mV VIH/L(dc)=VREF(dc)+-130mV LPDDR2 reference 400 333 tDS(base) 180 300 VIH/L(ac)=VREF(dc)+-300mV tDH(base) 280 400 VIH/L(dc)VREF(dc)+-200mV Note : ac/dc referenced for 1V/ns DQ,DM slew rate and 2V/ns differential DQS_t-DQS_c slew rate - 121 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6.3.2 Table of Derating values LPDDR2 tDS/tDH - ac/dc based AC220 tDS, DH derating in [ps] AC/DC based a AC220 Threshold -> VIH(ac)=VREF(dc)+220mV, VIL(ac)=VREF(dc)-220mV DC130 Threshold -> VIH(dc)=VREF(dc)+130mV, VIL(dc)=VREF(dc)-130mV DQS_t, DQS_c Differential Slew Rate 4.0 V/ns DQ, DM 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH 2.0 110 65 110 65 110 65 - - - - - - - - - - 1.5 74 43 73 43 73 43 89 59 - - - - - - - - 1.0 0 0 0 0 0 0 16 16 32 32 - - - - - - 0.9 - - -3 -5 -3 -5 13 11 29 27 45 43 - - - - 0.8 - - - - -8 -13 8 3 24 19 40 35 56 55 - - 0.7 - - - - - - 2 -6 18 10 34 26 50 46 66 78 0.6 - - - - - - - - 10 -3 26 13 42 33 58 65 0.5 - - - - - - - - - - 4 -4 20 16 36 48 0.4 - - - - - - - - - - - - -7 2 17 34 Slew Rate V/ns Note: Cell contents shaded in red are defined as `not supported'. 7.6.3.3 Table of Derating values LPDDR2 tDS/tDH - ac/dc based AC300 tDS, DH derating in [ps] AC/DC based a AC300 Threshold -> VIH(ac)=VREF(dc)+300mV, VIL(ac)=VREF(dc)-300mV DC200 Threshold -> VIH(dc)=VREF(dc)+200mV, VIL(dc)=VREF(dc)-200mV DQS_t, DQS_c Differential Slew Rate 4.0 V/ns DQ, DM 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH 2.0 150 100 150 100 150 100 - - - - - - - - - - 1.5 100 67 100 67 100 67 116 83 - - - - - - - - 1.0 0 0 0 0 0 0 16 16 32 32 - - - - - - 0.9 - - -4 -8 -4 -8 12 8 28 24 44 40 - - - - 0.8 - - - - -12 -20 4 -4 20 12 36 28 52 48 - - 0.7 - - - - - - -3 -18 13 -2 29 14 45 34 61 66 0.6 - - - - - - - - 2 -21 18 -5 34 15 50 47 0.5 - - - - - - - - - - -12 -32 4 -12 20 20 0.4 - - - - - - - - - - - - -35 -40 -11 -8 Slew Rate V/ns Note: Cell contents shaded in red are defined as `not supported'. - 122 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6.3.4 Table of Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition tVAC @ 300mV [ps] tVAC @ 220mV [ps] Slew Rate [V/ns] min max min max > 2.0 75 - 175 - 2.0 57 - 170 - 1.5 50 - 167 - 1.0 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 150 - < 0.5 0 - 150 - - 123 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6.3.5 Figure of nominal slew rate and tVAC for setup time tDS for DQ with respect to strobe DQS_c DQS_t tDS tDS tDH tDH VDDQ tVAC VIH(AC) min VREF to AC region VIH(DC) min nominal Slew rate VREF(DC) nominal Slew rate VIL(DC) max VREF to AC region VIL(AC) max tVAC VssQ TR TF Setup Slew Rate = VREF(DC) - VIL(AC)max Falling Signal TF - 124 - Setup Slew Rate = VIH(AC)min - VREF(DC) Rising Signal TR Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6.3.6 Figure of nominal slew rate for hold time tDH for DQ with respect to strobe DQS_c DQS_t tDS tDS tDH tDH VDDQ VIH(AC) min VIH(DC) min DC to VREF region nominal Slew rate VREF(DC) nominal Slew rate DC to VREF region VIL(DC) max VIL(AC) max VssQ TR Hold Slew Rate = [VREF(DC) - VIL(DC)max Rising Signal TR TF Hold Slew Rate = [VIH(DC)min - VREF(DC) Falling Signal TF - 125 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6.3.7 Figure of tangent line for setup time tDS for DQ with respect to strobe DQS_c DQS_t tDS tDS tDH VDDQ nominal tDH tVAC line VIH(ac) min VREF to ac region VIH(dc) min tangent line VREF(dc) tangent line VIL(dc) max VREF to ac region VIL(ac) max nominal line tVAC TR VssQ Setup Slew Rate = tangent line[VIH(ac)min - VREF(dc) Rising Signal TR TF Setup Slew Rate = tangent line[VREF(dc) - VIL(ac)max] Falling Signal TF - 126 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 7.6.3.8 Figure of tangent line for for hold time tDH for DQ with respect to strobe DQS_c DQS_t tDS tDH tDS tDH VDDQ VIH(AC) min nominal line VIH(DC) min DC to VREF tangent region line VREF(DC) DC to VREF region tangent line nominal line VIL(DC) max VIL(AC) max VssQ TR TF Hold Slew Rate = tangent line [VREF(DC) - VIL(DC)max Rising Signal TR Hold Slew Rate = tangent line [VIH(DC)min - VREF(DC)] Falling Signal TF - 127 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb 8. REVISION HISTORY Version Date Page Description P01-001 05/18/2012 All P01-002 06/14/2013 1,9,78,99 2 15 36 59 1 1,45~48,78,106 8 100 P01-003 10/24/2013 99~101 Add IDDx value (400 MHz). P01-004 11/15/2013 99~101 Update typical IDDx value for 400MHz. P01-004A 7/15/2014 N/A New create document. Update Temp. Add ordering Info & update part#. Add tZQINIT(8.2.2) Add 6.4.7.2 note 2. Update 6.4.22.2 bank MRR:Idle to Active. Remove "option" text. Update Tc to Tj. Add DQ text. Remove IDD4RQ. Document modified for MCP implementation. - 128 - Publication Release : July 15, 2014 Revision : P01-004A PRELIMINARY W97AH2KK LPDDR2 S-4B 1Gb [DISCLAIMER] This specification and all associated documentation, comments or other information (collectively "SPECIFICATION") is provided "AS IS" without warranty of any kind. Winbond Electronics Corporation ("WEC") hereby disclaims all wa rranties express or implied, including but not limited to, noninfringement of third party rights, and any implied warranties of merchantability or fitness for any particular purpose. Wec does not warrant that the specification will meet your requirements. Furthermore, wec does not make any pepresentations regarding the use or the results of the use of the specification in terms of its correctness, accuracy, reliability, or otherwise. The entire risk arising out of use or performance of the specification shall remain with you. In no event shall wec, its affiliated companies or their suppliers be liable for any direct, indirect, consequential, incidental, or special damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of your use of or inability to use the specification, even if wec has been advised of the possibility of such damages. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. ------------------------------------------------------------------------------------------------------------------------------------------------Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in the datasheet belong to their respective owners. - 129 - Publication Release : July 15, 2014 Revision : P01-004A