W71NW20GF3FW - Winbond - Datasheet.Directory

W71NW20GF3FW

MULTI-CHIP P ACKAGE (MCP) MEMORY

1.8V 2G-BIT (16M-WORD x 8-BIT)

SLC NAND FLASH MEMORY

1.8V 1G-BIT (256K- WORD x 8 BANK x 32-BIT)

LOW POWER DDR2 (LPDDR2) SDRAM

Publication Release Date: June 09, 2015

- 1 - Preliminary – Revision C

W71NW20GF3FW

Table of Contents

1 GENER AL D E SCRIPTIO N .............................................................................................................. 3

2 FEATURES...................................................................................................................................... 3

3 BALL CONFIGURATION ................................................................................................................. 4

3.1 162-Ball Description for W29N02GZ NAND Flash Memory .................................................... 5

3.2 162-Ball Description for W97AH2KK Low Power DDR2 SDRAM ........................................... 5

4 Block Diagram ................................................................................................................................. 8

5 Package Specification ..................................................................................................................... 9

5.1 VFBGA162Ball (8x10.5mm^2, Ball pitch:0.5mm, Ø=0.3mm) .................................................. 9

6 MCP ORDERING INFORMATION ................................................................................................ 10

7 Revision History ............................................................................................................................. 11

Table of Table

Table 3-1 W29N02GZ VFBGA-162 Ball Descript ion ............................................................................... 5

Table 3-2 W97AH2KK VFBGA-162 Ball Descr ipt ion .............................................................................. 7

Table 7-1 Revision History .................................................................................................................... 11

Table of Figure

Figure 3-1 W71NW20GF3FW, 162 Ball VFBGA Package (Top View, balls facing down) ..................... 4

Figure 4-1 W71NW20GF3FW MCP Flash & LPDDR2 SDRAM Block Diagram ..................................... 8

Figure 5-1 162 Ball VFBGA 8x10.5mm Package .................................................................................... 9

Figure 6-1 MCP Ordering Information ................................................................................................... 10

Publication Release Date: June 09, 2015

- 2 - Preliminary – Revision C

W71NW20GF3FW

1 GENERAL DESCRIPTION

The W71NW series is a Multi-Chip Package (MCP) memory product family that consists of a 1.8V NAND

Flash Memory device and a 1.8V Low Power SDRAM device in one convenient Thin VFBGA package.

W71NW20GF3FW consists of:

• W29N02GZ - 1.8V 2G-Bit x8-BIT NAND Flash Mem ory

• W97AH2KK - 1.8V 1G-Bit x32-BIT L ow Po we r D D R 2 SDRAM

• 162 Ball VFBGA - Dimension 8x10.5x1.0mm, ball pitch 0.5 0-mm, ball diameter

0.30mm

2 FEATURES

W29N02GZ NAND Flash Memory W97AH2KK Low Power DDR2 SDRAM

• Basic Features

– Density : 2Gbit (Single chip solution)

– Vcc : 1.7V to 1.95V

– Bus width : x8

– Operating temperature

 Industrial: -40°C to 85°C

• Single-Level Cell (SLC) technology.

• Organization

– Density: 2G-bit/256M-byte

– Page size

 2,112 bytes (2048 + 64 bytes)

– Block size

 64 pages (128K + 4K bytes)

• Highest Performance

– Read performance (Max.)

 Random read: 25us

 Sequential read cycle: 25ns

– Write Erase performance

 Page program time: 250us(typ.)

 Block erase time: 2ms(typ.)

– Endurance 100,000 Er as e/Pr o gr am

Cycles(2)

– 10-years data retention

• Command set

– Standard NAND command set

– Additional command support

 Copy Back

 Two-plane opera tion

– Contact Winbond for OTP feature

– Contact Winbond for block Lock feature

• Lowest power consumption

– Read: 25mA(typ.3V),T.B.D(typ.1.8V)

– Program/Erase: 10mA(typ.1.8V)

– CMOS standby: 10uA(typ.)

• VDD1 = 1. 7~1.95V

• VDD2/VDDCA/VDDQ = 1.14V ~ 1.30V

• Data width: x32

• Clock rate: up to 533MHz

• Four-bit prefetch DDR architecture

• Eight internal banks for concur rent

operation

• Programmable READ and WRITE

latencies (RL/WL)

• Programmable burst lengths: 4, 8, or 16

• Per Bank Refresh

• Partial Array Self-Refresh(PASR)

• Deep Power Down Mode (DPD Mode)

• Programmable output buffer dri ver

strength

• Data mask (DM) for write data

• Clock Stop c apability during idl e

periods

• Double data rate for data output

• Differential clock inputs

• Bidirectional differenti al data strobe

• Interface: HSUL_12

• JEDEC LPDDR2-S4B com plian ce

• Operati ng Temperature Range

-40 ~ 85 °C

Note:

1. Endu rance speci ficati o n is based on 1bit/528 byte ECC (Error Correcting Code).

Publication Release Date: June 09, 2015

- 3 - Preliminary – Revision C

W71NW20GF3FW

3 BALL CONFIGURATION

Figure 3-1 W71NW20GF3FW, 162 Ball VFBGA Package (Top View, balls facing down)

1234567 10

8 9

DNUGND

GND

IO0

IO1

IO2

IO3

VCC

VCC VCCWP/

WE/

ALE

CLE

CE/

RE/

R/B

DNU

IO4

IO5

IO6

IO7

VDD2

VSS

VSSVSS

VSS

VDD1

CA9 CA8

CA7

VSSCA

VDDCA

CA6

CA5VREF(CA)

CK_c

CK_t

CKE

CS_n

CA4 CA3 CA2

CA1

CA0

VDDQ

VSSQ

DQ31

DQ30

DQ29

DQ28

DQ27

DQ26

DQ25

DQ24

DQ23

DQ22

DQ21

DQ20

DQS3_tDQS3_c

DM1

VREF(DQ)

DM0

DQS0_tDQS0_c DQ7DQ6DQ5

DQ4 DQ3DQ2DQ1

DQ0DM2

DQS2_tDQS2_c

DQ19

DQ18

DQ17

DQ16

DQ8

DQ9DQS1_t

DQS1_c DQ10

DQ11 DQ13 DQ12

DQ14

DQ15

DM3

LPDDR2 NAND NOT CONNECTED

NC NC

NC NC NC

NC NC

NC NC NC

NC NC NC NC

Publication Release Date: June 09, 2015

- 4 - Preliminary – Revision C

W71NW20GF3FW

3.1 162-Ball Description for W29N02GZ NAND Flash Memory

Ball NO. BALL

NAME

I/O FUNCTION

A3 WP# I Write Protect

C4 WE# I Write Enable

B4 ALE I Address Latch Enable

A4 CLE I Command Latch Enable

D4 CE# I Chip Enable

B5 RE# I Read Enab le

C5 R/B# I Ready/#Busy

D2 IO0 I/O Data Input Output 0

C2 IO1 I/O Data Input Output 1

D3 IO2 I/O Data Input Output 2

C3 IO3 I/O Data Input Output 3

A6 IO4 I/O Data Input Output 4

B6 IO5 I/O Data Input Output 5

C6 IO6 I/O Data Input Output 6

A7 IO7 I/O Data Input Output 7

B2,A5,A8 VCC Power Su pply NAND

E1,B9 VSSn Ground NAND

E3,F3 DNU Do Not Use

Multiple NC No Connection

Table 3-1 W29N02GZ VFBGA-162 Ball Description

3.2 162-Ball Description for W97AH2KK Low Power DDR2 SDRAM

BALL NO. BALL

NAME I/O FUNCTION

P1 CS_n I Chip Select

N1 CKE I Clock Enable

L3 CLK_c I CK_t and CK_c are differential clock inputs

M3 CLK_t I CK_t and CK_c are differential clock inputs

U3 CA0 I DDR Command/Address Input 9

T3 CA1 I DDR Command/Address Input

R3 CA2 I DDR Command/Address Input

R2 CA3 I DDR Command/Address Input

R1 CA4 I DDR Command/Address Input

K2 CA5 I DDR Command/Address Input

Publication Release Date: June 09, 2015

- 5 - Preliminary – Revision C

W71NW20GF3FW

BALL NO. BALL

NAME I/O FUNCTION

J2 CA6 I DDR Command/Address Input

J3 CA7 I DDR Command/Address Input

H3 CA8 I DDR Command/Address Input

H2 CA9 I DDR Command/Address Input

N5 DM0 I Input Data Mask

L5 DM1 I Input Data Mask

T7 DM2 I Input Data Mask

H7 DM3 I Input Data Mask

P5 DQS0_c I/O Data Strobe (Bi-directional, Differential)

P6 DQS0_t I/O Data Strobe (Bi-directional, Differential)

K5 DQS1_c I/O Data Strobe (Bi-directional, Differential)

K6 DQS1_t I/O Data Strobe (Bi-directional, Differential)

U9 DQS2_c I/O Data Strobe (Bi-directional, Differential)

U8 DQS2_t I/O Data Strobe (Bi-directional, Differential)

G9 DQS3_c I/O Data Strobe (Bi-directional, Differential)

G8 DQS3_t I/O Data Strobe (Bi-directional, Differential)

T8 DQ0 I/O Data Inputs/Output

R8 DQ1 I/O Data Inputs/Output

R7 DQ2 I/O Data Inputs/Output

R9 DQ3 I/O Data Inputs/Output

R6 DQ4 I/O Data Inputs/Output

P7 DQ5 I/O Data Inputs/Output

P8 DQ6 I/O Data Inputs/Output

P9 DQ7 I/O Data Inputs/Output

K9 DQ8 I/O Data Inputs/Output

K8 DQ9 I/O Data Inputs/Output

K7 DQ10 I/O Data Inputs/Output

J6 DQ11 I/O Data Inputs/Output

J9 DQ12 I/O Data Inputs/Output

J7 DQ13 I/O Data Inputs/Output

J8 DQ14 I/O Data Inputs/Output

H8 DQ15 I/O Data Inputs/Output

W7 DQ16 I/O Data Inputs/Output

U6 DQ17 I/O Data Inputs/Output

W8 DQ18 I/O Data Inputs/Output

T5 DQ19 I/O Data Inputs/Output

Publication Release Date: June 09, 2015

- 6 - Preliminary – Revision C

W71NW20GF3FW

BALL NO. BALL

NAME I/O FUNCTION

U7 DQ20 I/O Data Inputs/Output

W9 DQ21 I/O Data Inputs/Output

V8 DQ22 I/O Data Inputs/Output

T6 DQ23 I/O Data Inputs/Output

H6 DQ24 I/O Data Inputs/Output

F8 DQ25 I/O Data Inputs/Output

E9 DQ26 I/O Data Inputs/Output

G7 DQ27 I/O Data Inputs/Output

H5 DQ28 I/O Data Inputs/Output

E8 DQ29 I/O Data Inputs/Output

G6 DQ30 I/O Data Inputs/Output

E7 DQ31 I/O Data Inputs/Output

G3 ZQ I/O Reference Pin for Output Drive Strength Calibration

F1,V1,E6,W6 VDD1 Core Power Supply 1

K1,G2,U2,E5,W5,M7 VDD2 Core Power Supply 2

G5,U5,L6,M6,N6,F7,

V7,H9,T9,F10,J10,R1

0,V10 VDDQ I/O Power Supply

J1,L1,T2 VDDCA Input Receiver Power Supply

G1,U1,L2,V2,F5,F2,V

5,M8 VSS Ground

J5,M5,R5,F6,V6,F9,V

9,G10,H10,K10,P10,

T10,U10 VSSQ I/O Ground

H1,M1,T1 VSSCA Ground for CA Input Receivers

K3 VREF(CA) Reference Voltage for CA Command and Control

Input Receiver

M9 VREF(DQ) Reference Voltage for DQ Input Receiver

Table 3-2 W97AH2KK VFBGA-162 Ball Description

Publication Release Date: June 09, 2015

- 7 - Preliminary – Revision C

W71NW20GF3FW

4 Block Diagram

Figure 4-1 W71NW20GF3FW MCP F lash & LPD DR2 SDRAM Block Diagr am

Publication Release Date: June 09, 2015

- 8 - Preliminary – Revision C

W71NW20GF3FW

5 Package Specification

5.1 VFBGA162Ball (8x10.5mm^2, Ball pitch:0.5mm, Ø=0.3mm)

Figure 5-1 162 Ball VFBGA 8x10.5mm Package

Publication Release Date: June 09, 2015

- 9 - Preliminary – Revision C

W71NW20GF3FW

6 MCP ORDERING INFORMA TION

Figure 6-1 MCP Ordering Information

71 NW 2 0 G F 3 F W

Winbond Standard Product

W: Winbond

Product Family

71: MCP Product

Voltage

NW: 1.8V ONFI NAND Flash

Product Density

2: 2Gb

NAND I/O bits

0: 8 bit

Flash Generation

G= WEC 4X Tec hnolog y Node

RAM Density

F= 1Gb LPDDR 2

RAM Option Information

3: 4X Technology *32

Package Type

F: 162 Balls VFBGA

Grade & Temperature

W: Industrial: -40°C to +85°C

Publication Release Date: June 09, 2015

- 10 - Preliminary – Revision C

W71NW20GF3FW

7 Revision History

VERSION DATE PAGE DESCRIPTION

A 07/15/2014 New Create Preliminary

B 11/26/2014 3 Corrected W29N02GZ BUS Width to x8

C 06/09/2015 3

N/A

Added new W29N02GZ description

Temperature Grade Correction

Added updated W29N02GZ Datasheet

Table 7-1 Revision History

Preliminary Designation

The “Preliminary” designation on a Winbond datasheet indicates that the product is not fully

characterized. The specifications are subject to change and are not guaranteed. Winbond or an

authorized sales representative should be consulted for current information before using this product.

Trademarks

Winbond and SpiFlash are trademarks of Winbond Electronics Corporation.

All other marks are the property of their res p ec ti ve ow ner.

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components in

systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or

spaceship instruments, transportation instruments, traffic signal instruments, combustion control

instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products

are not i nte nde d f or ap pl ica t ions wher e in f ailure of Winbond pr o duc ts c ou ld r esult or lead to a situ ati on

wherein personal injury, death or severe property or environmental damage could occur.

Winbond c ustom ers using or selling these produc ts f or use in s uch app lica tions d o so at t heir own risk

and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

Publication Release Date: June 09, 2015

- 11 - Preliminary – Revision C

W29N02GW/Z

2G-BIT 1.8V

NAND FL ASH MEMORY

Release Date: May 19, 2015

1 Preliminary – Revision 0.3

W29N02GW/Z

Table of Contents

1. GEN ER AL D E SCR I PTION ............................................................................................................... 7

2. FEATURES ....................................................................................................................................... 7

3. PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 8

3.1 Pin Descriptions .................................................................................................................... 8

4. PIN DESCRITPIONS ........................................................................................................................ 9

4.1 Chip Enable (#CE) ................................................................................................................ 9

4.2 Write Enable (#WE) .............................................................................................................. 9

4.3 Read Enable (#RE) .............................................................................................................. 9

4.4 Address Latch Enable (ALE) ................................................................................................ 9

4.5 Command Latch Enable (CLE) ............................................................................................ 9

4.6 Write Protect (#WP) .............................................................................................................. 9

4.7 Ready/Busy (RY/#BY) .......................................................................................................... 9

4.8 Input and Output (I/Ox) ......................................................................................................... 9

5. BLOCK DIAGRAM .......................................................................................................................... 10

6. MEMORY ARRAY ORGANIZATION .............................................................................................. 11

6.1 Array Organization (x8) ...................................................................................................... 11

6.2 Array Organization (x16) .................................................................................................... 12

7. MODE SELECTION TABLE ........................................................................................................... 13

8. COMMAND TABLE......................................................................................................................... 14

9. DEVICE OPERATIONS .................................................................................................................. 15

9.1 READ operation .................................................................................................................. 15

9.1.1 PAGE READ (00h-30h) ........................................................................................................ 15

9.1.2 TWO PLANE READ (00h-00h-30h) ...................................................................................... 15

9.1.3 RANDOM DATA OUTPUT (05h-E0h) ................................................................................... 17

9.1.4 READ ID (90h) ...................................................................................................................... 18

9.1.5 READ PARAMETER PAGE (ECh) ....................................................................................... 19

9.1.6 READ STATUS (70h) ........................................................................................................... 21

9.1.7 READ STATUS ENHANCED (78h) ...................................................................................... 22

9.1.8 READ UNIQUE ID (EDh) ...................................................................................................... 24

9.2 PROGRAM operation ......................................................................................................... 25

9.2.1 PAGE PROGRAM (80h-10h) ................................................................................................ 25

9.2.2 SERIAL DATA INPUT (80h) ................................................................................................. 25

9.2.3 RANDOM DATA INPUT (85h) .............................................................................................. 26

9.2.4 TWO PLANE PAGE PROGRAM .......................................................................................... 26

9.3 COP Y BACK oper ati on ....................................................................................................... 28

9.3.1 READ for COPY BACK (00h-35h) ........................................................................................ 28

9.3.2 PROGRAM for COPY BACK (85h -10h) ................................................................................ 28

9.3.3 TWO PLANE READ for COPY BACK ................................................................................... 29

9.3.4 TWO PLANE PROGRAM for COPY BACK .......................................................................... 29

9.4 BLOCK ERASE operation .................................................................................................. 33

9.4.1 BLOCK ERASE (60h-D0h) ................................................................................................... 33

9.4.2 TWO PLANE BLOCK ERASE .................................................................................................. 34

9.5 RESET operation ................................................................................................................ 35

Release Date: May 19, 2015

2 Preliminary – Revision 0.3

W29N02GW/Z

9.5.1 RESET (FFh) ........................................................................................................................ 35

9.6 FEATURE OPERATION..................................................................................................... 36

9.6.1 GET FEATURES (EEh) ........................................................................................................ 39

9.6.2 SET FEATURES (EFh) ......................................................................................................... 40

9.7 ONE TIME PROGRAMMABLE (OTP) area ....................................................................... 41

9.8 WRITE PROTECT .............................................................................................................. 42

9.9 BLOCK LOCK ..................................................................................................................... 44

10. ELECTRICAL CHARACTERISTICS............................................................................................... 45

10.1 Absolute Maximum Ratings (1.8V) ..................................................................................... 45

10.2 Operating Ranges (1.8V) ................................................................................................... 45

10.3 Device power-up timing ...................................................................................................... 46

10.4 DC Electrical Characteristics (1.8V) ................................................................................... 47

10.5 AC Measurement Conditions (1.8V) ................................................................................... 48

10.6 AC timing characteristics for Command, Address and Data Input (1.8V) .......................... 49

10.7 AC timing characteristics for Operation (1.8V) ................................................................... 50

10.8 Program and Erase Characteristics ................................................................................... 51

11. TIMING DIAGRAMS ....................................................................................................................... 52

12. INVALID BLOCK MANAGEMENT .................................................................................................. 61

12.1 Invalid blocks ...................................................................................................................... 61

12.2 Initial invalid blocks ............................................................................................................. 61

12.3 Error in operation ................................................................................................................ 62

12.4 Addressing in program operation ....................................................................................... 63

13. REV ISI ON HI ST O RY ...................................................................................................................... 64

Release Date: May 19, 2015

3 Preliminary – Revision 0.3

W29N02GW/Z

List of Tables

Table 3-1 Pin Descriptions ............................................................................................................................ 8

Table 6-1 Addr es sing .................................................................................................................................. 11

Table 6-2 Addr es sing .................................................................................................................................. 12

Table 7-1 Mode Selection ........................................................................................................................... 13

Table 8-1 Command Table ......................................................................................................................... 14

Table 9-1 Device ID and configuration codes for Address 00h .................................................................. 18

Table 9-2 ONFI identifying codes for Address 20h ..................................................................................... 18

Table 9-3 Parameter Page Output Va lue .................................................................................................... 21

Table 9-4 Stat us Re gister Bit Def initi on ...................................................................................................... 22

Table 9-5 Features ...................................................................................................................................... 36

Table 9-6 Feature Address 80h .................................................................................................................. 37

Table 9-7 Feature Address 81h .................................................................................................................. 38

Table 10-1 Absolute Maximum Ratings ...................................................................................................... 45

Table 10-2 Operating Ranges ..................................................................................................................... 45

Table 10-3 DC Elect ric al C harac ter ist ic s .................................................................................................... 47

Table 10-4 AC Measurement Conditions .................................................................................................... 48

Table 10-5 AC timing characteristics for Command, Address and Data Input ........................................... 49

Table 10-6 AC timing characteristics for Operation .................................................................................... 50

Table 10-7 Program and Erase Characteristics .......................................................................................... 51

Table 12-1 Valid Block Number .................................................................................................................. 61

Table 12-2 Block failure .............................................................................................................................. 62

Table 16-1 History Table ............................................................................................................................. 64

Release Date: May 19, 2015

4 Preliminary – Revision 0.3

W29N02GW/Z

List of Figures

Figure 6-1 Array Organization ..................................................................................................................... 11

Figure 6-2 Array Organization ..................................................................................................................... 12

Figure 9-1 Page Read Operations .............................................................................................................. 15

Figure 9-2 Two Plane Read Page (00h-00h-30h) Operation ...................................................................... 16

Figure 9-3 Random Data Output ................................................................................................................. 17

Figure 9-4 Two Plane Random Data Read (06h-E0h) Operation ............................................................... 17

Figure 9-5 Read ID ...................................................................................................................................... 18

Figure 9-6 Read Parameter Page ............................................................................................................... 19

Figure 9-7 Read Status Operation .............................................................................................................. 21

Figure 9-8 Read Status Enhanced (78h) Operation ................................................................................... 23

Figure 9-9 Read Unique ID ......................................................................................................................... 24

Figure 9-10 Page Progr am.......................................................................................................................... 25

Figure 9-11 Random Data Input ................................................................................................................. 26

Figure 9-12 Two Plane Page Program ....................................................................................................... 27

Figure 9-13 Program for copy back Operation ............................................................................................ 30

Figure 9-14 Cop y Back Operat ion w ith Ran dom Data Input ....................................................................... 30

Figure 9-15 Two Plane Copy Back ............................................................................................................. 31

Figure 9-16 Two Plane Copy Back with Random Data Input ..................................................................... 31

Figure 9-17 Two Plane Program for copy back .......................................................................................... 32

Figure 9-18 Block Erase Operation ............................................................................................................. 33

Figure 9-19 Two Plane Block Erase Operation........................................................................................... 34

Figure 9-20 Reset Operation....................................................................................................................... 35

Figure 9-21 Get Feature Operation ............................................................................................................. 39

Figure 9-22 Set Feature Operation ............................................................................................................. 40

Figure 9-23 Erase Enable ........................................................................................................................... 42

Figure 9-24 Erase Disable .......................................................................................................................... 42

Figure 9-25 Program Enable ....................................................................................................................... 42

Figure 9-26 Program Disable ...................................................................................................................... 43

Figure 9-27 Program for Copy Back Enable ............................................................................................... 43

Figure 9-28 Program for Copy Back Disable .............................................................................................. 43

Figure 10-1 Power ON/OFF sequence ....................................................................................................... 46

Figure 11-1 Command Latch Cycle ............................................................................................................ 52

Figure 11-2 Addres s Latch C ycle ................................................................................................................ 52

Figure 11-3 Data Latch Cycle ..................................................................................................................... 53

Figure 11-4 Serial Access Cycle after Read ............................................................................................... 53

Figure 11-5 Serial Access Cycle after Read (EDO) .................................................................................... 54

Figure 11-6 Read Status Operation ............................................................................................................ 54

Figure 11-7 Page Read Operation .............................................................................................................. 55

Figure 11-8 #CE Don't Care Read Operation ............................................................................................. 55

Figure 11-9 Random Data Output Operation .............................................................................................. 56

Figure 11-10 Read ID .................................................................................................................................. 57

Figure 11-11 Page Program........................................................................................................................ 57

Figure 11-12 #CE Don't Care Page Program Operation ............................................................................ 58

Figure 11-13 Page Program with Random Data Input ................................................................................ 59

Release Date: May 19, 2015

5 Preliminary – Revision 0.3

W29N02GW/Z

Figure 11-14 Copy Back ............................................................................................................................. 59

Figure 11-15 Block Erase ............................................................................................................................ 60

Figure 11-16 Reset ..................................................................................................................................... 60

Figure 12-1 Flow chart of create initial invalid block table .......................................................................... 62

Figure 12-2 Bad block Replacement ........................................................................................................... 63

Release Date: May 19, 2015

6 Preliminary – Revision 0.3

W29N02GW/Z

1. GENERAL DESCRIPTION

The W29N02GW/Z (2G-bit) NAND Flash mem or y provides a stor age soluti on for embedded s ystems with

limited spac e, pins and pow er. It is ideal for code s hadowing to RAM, solid state applications and storing

media data s uch as, voice, video, tex t and photos. T he device oper ates on a sin gle 1.7 V to 1.95V power

suppl y with active curr e nt consumption as low as 13mA at 1.8V and 10uA for CMOS standby current.

The memory array totals 276,824,064bytes, and organized into 2,048 erasable blocks of 135,168 bytes

(135,168 words ) . Each block consists of 64 programmable pages of 2,112-bytes (1056 words) e ac h. Each

page cons ists of 2,048-bytes (1024 words) for the m ain data s tor age area an d 64-bytes (32words) for t he

spare data area (The spare area is typically used for error management functions).

The W29N02GW/Z supports the standard NAND flash memory interface using the multiplexed 8-bit (16-

bit) bus to trans fer dat a, addr esses, an d comm and instr uctions. T he five c ontrol s ignals, CLE, AL E, #C E,

#RE and #WE handle the bus interface protocol. Also, the device has two other signal pins, the #WP (Write

Protect) and the RY/#BY (Ready/Busy) for monitoring the device status.

2. FEATURES

• Basic Features

– Density : 2Gbit (Single chip solution)

– Vcc : 1.7V to 1.95V

– Bus width : x8 x16

– Operating temperature

 Industrial: -40°C to 85°C

• Single-Level Cell (SLC) technology.

• Organization

– Density: 2G-bit/256M-byte

– Page size

 2,112 bytes (2048 + 64 bytes)

 1,056 words ( 1 024 + 32 words)

– Block size

 64 pages (128K + 4K bytes)

 64 pages (64K + 2K words)

• Highest Performance

– Read performance (Max.)

 Random read: 25us

 Sequential read cycle: 25ns

– Write Erase performance

 Page program time: 250us(typ.)

 Block erase time: 2ms(typ.)

– Endurance 100,000 Erase/Program

Cycles(2)

– 10-years data retention

• Command set

– Standard NAND command set

– Additional command support

 Copy Back

 Two-plane opera tion

– Contact Winbond for OTP feature

– Contact Winbond for block Lock feature

• Lowest power consumption

– Read: 25mA(typ.3V),T.B.D(typ.1.8V)

– Program/Erase: 10mA(typ.1.8V)

– CMOS standby: 10uA(typ.)

• Space Efficient Packaging

– Contact Winbond for stacked

packages/KGD

Note:

1. Endu rance speci ficati o n is based on 1bit/528 byte ECC (Error Correcting Code).

Release Date: May 19, 2015

7 Preliminary – Revision 0.3

W29N02GW/Z

3. PACKAGE TYPES AND PIN CONFIGURATIONS

3.1 Pin Descriptions

PIN NAME I/O FUNCTION

#WP I Write Protect

ALE I Address Latch Enable

#CE I Chip Enable

#WE I Write Enable

RY/#BY O Ready/Busy

#RE I Read Enable

CLE I Command Latch Enable

I/O[0-7]

I/O[0-15] I/O Data Input/Output (x8,x16)

Vcc Supply Power supply

Vss Supply Ground

DNU - Do Not Use.

N.C - No Connect

Table 3-1 Pin Descriptions

Note:

1. Connect all Vcc and Vss pins to power supply or ground. Do not leave Vcc or Vss disconnected.

Release Date: May 19, 2015

8 Preliminary – Revision 0.3

W29N02GW/Z

4. PIN DESCRITPIONS

4.1 Chip Enable (#CE)

#CE pin enables and disables device operation. When #CE is high the device is disabled and the I/O

pins are set to high impeda nce and enter s into standb y mode if not busy. When #CE is set low the

device will be enabled, power c onsum ption will i ncrease to active l evels and the device is ready for

Read and Write operations.

4.2 Wri t e E nable (#WE)

#WE pin enables the device to control write operations to input pins of the device. Such as, command

instructions, addresses and data that are latched on the rising edge of #WE.

4.3 Read Enable (#RE)

#RE p in controls serial data output f rom the pre-loaded Data Register. Valid dat a is present on the

I/O bus af ter the t REA period f rom the f alling edge of #RE. Colum n address es are incremented for

each #RE pulse.

4.4 Addres s Latch Enabl e (ALE)

ALE pin controls address input to the address register of the device. When ALE is active high,

addresses are latched via the I/O pins on the rising edge of #WE.

4.5 Comman d Latch Enable (CLE)

CLE pin controls command input to the comm and register of the device. W hen CLE is active high,

commands are latched into the command register via I/O pins on the rising edge of #WE.

4.6 Wri t e P rotect (#WP)

#WP pin can be used to prevent the inadvertent program/erase to the device. When #WP pin is active

low, all program/erase operations are disabled.

4.7 Ready/Busy (RY/#BY)

RY/#BY pin indicates the device status. When RY/#BY output is low, it indicates that the device is

processing either a program, erase or read operations. When it returns to high, those operations have

completed. RY/#BY pin is an open drain.

4.8 Input and Output (I/Ox)

I/Ox bi-directional pins are used for the following; command, address and data operations.

Release Date: May 19, 2015

9 Preliminary – Revision 0.3

W29N02GW/Z

5. BLOCK DIAGR AM

Logic

Control

Status

Command

Resister

Address

High Voltage

Generator

NAND Flash

Array

Row Decoder

Column Decoder

Cache Register

Data Register

I/O

Control

#CE

ALE

CLE

#RE

#WE

#WP

I/Ox

RY/#BY

Figure 5-1 NAND Flash Memory Block Diagram

Release Date: May 19, 2015

10 Preliminary – Revision 0.3

W29N02GW/Z

6. ME M O R Y ARRAY ORGANIZATION

6.1 Array Organization (x8)

Figure 6-1 Array Organization

I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

1st cycle A7 A6 A5 A4 A3 A2 A1 A0

2nd cycle L L L L A11 A10 A9 A8

3rd cycle A19 A18 A17 A16 A15 A14 A13 A12

4th cycle A27 A26 A25 A24 A23 A22 A21 A20

5th cycle L L L L L L L A28

Table 6-1 Addressing

Notes:

1. “L” indicates a low condition, which must be held during the address cycle to insure correct processing.

2. A0 to A11 during the 1st and 2nd cy cles are column addresses. A12 to A28 during t he 3rd, 4th and 5th cycles

are row addresses.

3. A18 is plane address

4. The device ignor es an y additional address inputs that exceed the device’s requirem ent.

Plane of even

numbered blocks Plane of odd

numbered blocks

1024

blocks

Per plane

2048

blocks

Per device

Data Register

Cache Register 2048

2048

2112 bytes2112 bytes

1 block

1page = (2k+64bytes)

1block = (2k+64）bytes×64 pages

= (128k+4k)byte

1plane = (128k+4k)byte×1024blocks

= 1056Mb

1device = 1056M ×2planes

= 2112Mb

DQ7

DQ0

Release Date: May 19, 2015

11 Preliminary – Revision 0.3

W29N02GW/Z

6.2 Array Org anization (x16)

Figure 6-2 Array Organization

I/O[15:8] I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

1st cycle L A7 A6 A5 A4 A3 A2 A1 A0

2ndcycle L L L L L L A10 A9 A8

3rd cycle L A18 A17 A16 A15 A14 A13 A12 A11

4th cycle L A26 A25 A24 A23 A22 A21 A20 A19

5th cycle L L L L L L L L A27

Table 6-2 Addressing

Notes:

1. “L” indicates a low conditio n, which mu st be held during the address cycle to insure correct processing.

2. A0 to A10 during the 1st and 2nd cy cles are column addresses. A11 to A27 during the 3rd, 4th and 5th cycles

are row addresses.

3. A17 is plane address

4. The device ignor es an y additional address inputs that exceed the device’s requirem ent.

1block = (1k+32）words×64 pages

= (64k+2k)words

1plane = (64k+2k)words×1024blocks

1device= 1056M ×2planes

= 2112Mb

Plane of even

numbered blocks Plane of odd

numbered blocks

1024

blocks

Per plane

2048

blocks

Per device

Data Register

Cache Register 1024

1024

1056 words 1056 words

1 block

1page = (1k+32words)

= 1056Mb

DQ15

DQ0

(0,2,4,6...,1020,1022)(1,3,5,7...,1021,1023)

Release Date: May 19, 2015

12 Preliminary – Revision 0.3

W29N02GW/Z

7. MODE SELECTION TABLE

MODE CLE ALE #CE #WE #RE #WP

Read

mode Command inpu t H L L H X

Address input L H L H X

Program

Erase

mode

Command input H L L H H

Address input L H L H H

Data input L L L H H

Sequential Read and Data output L L L H X

During read (busy) X X X X H X

During program (busy) X X X X X H

During erase (busy) X X X X X H

Write protect X X X X X L

Standby X X H X X 0V/Vcc

Table 7-1 Mode Selection

Notes:

1. “H” indicates a HIGH input level, “L” indicates a LOW input level, and “X” indicates a Don’t Care Level.

2. #WP should be biased to CMOS HIGH or LOW for standby.

Release Date: May 19, 2015

13 Preliminary – Revision 0.3

W29N02GW/Z

8. COMMAND TABLE

COMMAND 1ST

CYCLE 2ND

CYCLE 3rd

CYCLE 4th

CYCLE Acceptable

during

busy

PAGE READ 00h 30h

READ for COPY BACK 00h 35h

READ ID 90h

READ STATUS 70h Yes

RESET FFh Yes

PAGE PROGRAM 80h 10h

PROGRAM for COPY BACK 85h 10h

BLOCK ERASE 60h D0h

RANDOM DATA INPUT*1 85h

RANDOM DATA OUTPUT*1 05h E0h

READ PARAMETER PAGE ECh

READ UNIQUE ID EDh

GET FEATURES EEh

SET FEATURES EFh

READ STATUS ENHANCED 78h Yes

TWO PLANE READ PAGE 00h 00h 30h

TWO PLANE READ FOR COP Y BACK 00h 00h 35h

TWO PLANE RANDOM DATA READ 06h E0h

TWO PLANE PROGRAM(TRADITIONAL) 80h 11h 81h 10h

TWO PLANE PROGRAM(ONFI) 80h 11h 80h 10h

TWO PLANE

PROGRAM FOR COPY

BACK(TRADITIONAL) 85h 11h 81h 10h

TWO PLANE

PROGRAM FOR COPY

BACK(ONFI) 85h 11h 85h 10h

TWO PLANE BLOCK ERASE(TRADITIONAL) 60h 60h D0h

TWO PLANE BLOCK ERASE(ONFI) 60h D1h 60h D0h

Table 8-1 Command Table

Notes:

1. RANDOM DATA INPUT and RANDOM DATA OUTPUT command is only to be used within a page.

2. Any commands that are not in the above table are considered as undefined and are prohibited as inputs.

3. Do not cross plane address boundaries when using Copy Back Read and Program for copy back.

Release Date: May 19, 2015

14 Preliminary – Revision 0.3

W29N02GW/Z

9. DEVICE OPERATIONS

9.1 READ operation

9.1.1 PAGE READ (00h-30h)

When the dev ice po wers on, 00h com m and is la tched to command register . Ther ef ore, s ystem only

issues five address cycles and 30h command for initial read from the device. This operation can also

be entered by writing 00h command to the command register, and then write five address cycles,

followed by writing 30h command. After writing 30h command, the data is transferred from NAND

array to Da ta Re gist er during tR. Data trans f er pr ogr e ss c an be done by monitori ng the st at us of the

RY/#BY signal output. RY/#BY signal will be LOW during data transfer. Also, there is an alternate

method by using the READ STATUS (70h) command. If the READ STATUS command is issued

during read operation, the Read (00h) command m ust be re-issued to read out the data from Data

from Data Register by toggling #RE. Read is sequential from initial column address to the end of the

page. (See Figure 9-1)

Figure 9-1 Page Read Operations

9.1.2 TWO PLANE READ (00h-00h-30h)

TWO PLANE READ (00h-00h-30h) transfers two pages data from the NAND array to the data

registers. Each page address have to be indicated different plane address.

To set the TWO PLANE READ mode, write the 00h command to the command register, and then

write five address cycles for plane 0. Secondly, write the 00h command to the command register, and

five address cycles for plane 1. Finally, the 30h command is issued. The first-plane and second-plane

addresses must be identical for all of issued address except plane address.

After the 30 h com m and is written , page d ata is transf err ed from both planes to their respec tive da ta

registers in tR. RY/#BY goes LOW While these are transfered,. When the transfers are complete,

RY/#BY goes HIGH. To read out the data, at first, system writes TWO PLANE RAMDOM DATA READ

(06h-E0h) command to select a plane, next, repeatedly pulse #RE to read out the data from selected

plane. To change the plane address, issues TWO PLANE RANDOM DATA READ (06h-E0h)

Address (5cycles)30hData Output ( Serial Access )

Don’t care

l/Ox

#RE

RY/#BY

ALE

#WE

#CE

CLE

00h

Release Date: May 19, 2015

15 Preliminary – Revision 0.3

W29N02GW/Z

comm and to select t he another plane addres s, then re peatedl y pulse #RE to r ead out th e data f rom

the selected plane data register.

Alternat ively, data tra nsfer s can be monitor ed by the R EAD STAT US (70h). W hen the transf ers are

complete, status register bit 6 is set to 1. To read data from the first of the two planes even when

READ STATUS ENHANCED (78h) command is used, the system must issue the TWO PLANE

RANDOM DATA READ (06h-E0h) command at first and pulse #RE repeatedly.

Write a TWO PLANE RANDOM DATA READ (06h-E0h) command to select the other plane ,after the

data cycle is complete. pulse #RE repeatedly to output the data beginning at the specified column

address. Dur ing TW O PLANE READ o peration ,the READ STAT US ENHAN CED (78h) c omman d is

prohibited .

Figure 9-2 Two Plane Read Page (00h-00h-30h) Operation

CLE

#WE

ALE

#RE

I/O×

RY/#BY

Col

Add1

Col

Add2Row

Add1

Row

Add2

Row

Add3

30h

00h

Column address J Plane 1 address

Plane address M

Column address J Plane 0 address

CLE

#WE

ALE

#RE

I/O× E0h

06h D

OUT

Selected Plane data

RY/#BY

Plane 0 or Plane 1 address

Address (5cycles)

Col

Add1Col

Add2

Row

Add1

Row

Add2

Row

Add3

Release Date: May 19, 2015

16 Preliminary – Revision 0.3

W29N02GW/Z

9.1.3 RANDOM DA TA OUTPU T (05h-E0h)

The RANDOM DATA OUTPUT allows the selection of random column addresses to read out data

from a single or multiple of addresses. The use of the RANDOM DATA OUTPUT command is

available after the PAGE READ (00h-30h) sequence by writing the 05h command following by the

two cycle column address and then the E0h comm and. Toggling #RE will output data sequentially.

The RANDOM DATA OUTPUT command can be issued multiple times, but limited to the current

loaded page.

Figure 9-3 Random Data Output

9.1.3.1. TWO PLANE RANDOM DATA OUTPUT (06h-E0h)

TWO PLANE RANDOM DATA READ (06h-E0h) command can indicate to specified plane and

column address on data register . This command is accepted b y a device when it is read y.

Issuing 06h to the command register, two column address cycles, three row address cycles, E0h are

followed, this enables data output mode on the address device’s data register at the specified column

address. After the E0h command , the host have to wait at least tWHR before requesting data output.

The selected device is in data output mode until another valid command is issued.

The TWO PLANE RANDO M D ATA READ ( 06 h-E 0h) comm and is used to s el ec t the da ta r eg ister to

be enabled for dat a output. W hen the dat a output is complete o n the s elected plane, the com mand

can be issued again to start data output on another plane.

If there is a n eed t o u pdat e the c ol umn address with out selecting a new data r egis t er , the R ANDOM

DATA READ (05h-E0h) command can be used instead.

Figure 9-4 Two Plane Random Data Read (06h-E0h) Operation

#RE

RY/#BY

I/Ox

05hE0h

Address(2cycles)

30h

Address(5cycles)

Data out Data out

00h

CLE

ALE

#RE

I/O×

E0h

06hData Out

Data Out

#WE

#CE

Address (5cycles)

Release Date: May 19, 2015

17 Preliminary – Revision 0.3

W29N02GW/Z

9.1.4 READ ID (90h)

READ ID command is comprised of two modes determined by the input address, device (00h) or

ONFI (20h) identification information. To enter the READ ID mode, write 90h to the Command

The pre-programmed code includes the Manufacturer ID, Device ID, and Product-Specific Information

(see Table 9.1). If the READ ID command is followed by 20h address, the output code includes 4

single b yte c ycles of O NFI ident if ying inf ormat ion (See Table 9.2). The device rem ains in th e R EAD

ID Mode until the next valid command is issued.

#WE

CLE

#CE

ALE

#RE

I/Ox

90h

00h

(or 20h)

Address 1 Cycle

tAR

t RE A

tWHR

Byte0

Byte1 Byte2 Byte3 Byte4

Figure 9-5 R ead ID

# of

Byte/Cycles 1st

Byte/Cycle 2nd

Byte/Cycle 3rd

Byte/Cycle 4th

Byte/Cycle 5th

Byte/Cycle

W29N02GZ EFh AAh 90h 15h 04h

W29N02GW EFh BAh 90h 55h 04h

Description MFR ID Device ID Cache

Programming

not Supported

Page Size:2KB

Spare Area Size:64b

BLK Size w/o Spare:128KB

Organized:x8 or x16

Serial Acces s :25ns

x16 device : the ID is outputted at word units, and defined lower-byte (IO0-7). ID table shows only lower-byte ID.

Table 9-1 Device ID and configuration codes for Address 00h

# of Byte/Cycles 1st

Byte/Cycle 2nd

Byte/Cycle 3rd

Byte/Cycle 4th

Byte/Cycle

Code 4Fh 4Eh 46h 49h

Table 9-2 ONFI identifying codes for Address 20h

Release Date: May 19, 2015

18 Preliminary – Revision 0.3

W29N02GW/Z

9.1.5 READ PARAMETER PAGE (ECh)

READ PARAMETER PAGE can read out the device’s parameter data structure, such as,

manufacturer information, device organization, timing parameters, key features, and other pertinent

device par am eters. T he data s tructure is s tored wit h at least t hree copies i n the dev ice’s param eter

page. Figure 9-9 shows the READ PARAMETER PAGE timing. The RANDOM DATA OUTPUT (05h-

E0h) command is supported during data output.

I/Ox

CLE

#WE

ALE

#RE

RY/#BY

ECh P0

00h

・・・

Figure 9-6 Read Parameter Page

Byte Description Value

0-3 Parameter page sig natur e 4Fh, 4Eh, 46h, 49h

4-5 Revision number 02h, 00h

6-7 Features

supported W29N02GZ 18h,00h

W29N02GW 19h,00h

8-9 Optiona l command s supp orted 3Fh,00h

10-31 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h

32-43 Device manufacturer 57h, 49h, 4Eh, 42h, 4Fh, 4Eh, 44h, 20h, 20h, 20h, 20h,

20h

44-63 Device model W29N02GZ 57h,32h,39h,4Eh,30h,32h,47h,5Ah,20h,20h,20h,20h,20

h,20h,20h,20h,20h,20h,20h,20h,20h

W29N02GW 57h,32h,39h,4Eh,30h,32h,47h,57h,20h,20h,20h,20h,20

h,20h,20h,20h,20h,20h,20h,20h,20h

64 Manufacturer ID EFh

65-66 Date code 00h, 00h

67-79 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h

80-83 # of data bytes per page 00h, 08h, 00h, 00h

Release Date: May 19, 2015

19 Preliminary – Revision 0.3

W29N02GW/Z

Byte Description Value

84-85 # of spare bytes per page 40h, 00h

86-89 # of data bytes per partial page 00h, 02h, 00h, 00h

90-91 # of spare bytes per parti al pa ge 10h, 00h

92-95 # of pages per block 40h, 00h, 00h, 00h

96-99 # of blocks per unit 00h, 08h, 00h, 00h

100 # of logical units 01h

101 # of address cycles 23h

102 # of bits per cell 01h

103-104 Bad blocks maximum per unit 28h, 00h

105-106 Block endurance 01h, 05h

107 Guaranteed valid blocks at beginning of

target 01h

108-109 Block endurance for guaranteed valid

blocks 00h, 00h

110 # of programs per page 04h

111 Partial programming attributes 00h

112 # of ECC bits 01h

113 # of interleaved address bits 01h

114 Interl eav ed operation attribut e s 0Ch

115-127 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h

128 I/O pin capaci tan ce 0Ah

129-130 Timing mode support 1Fh, 00h

131-132 Program cache timing 00h, 00h

133-134 Maximum page program time BCh, 02h

135-136 Maximum block erase time 10h, 27h

137-138 Maximum random read time 19h, 00h

139-140 tCCS minimum 46h, 00h

141-163 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h

164-165 Vendor specific revision # 01h,00h

166-253 Vendor specific 00h

254-255 Integrity CRC Set at shipme nt

256-511 Value of bytes 0-255

Release Date: May 19, 2015

20 Preliminary – Revision 0.3

W29N02GW/Z

Byte Description Value

512-767 Value of bytes 0-255

>767 Additional redundant parameter pages

x16 device : the ID is outputted at word units, and defined lower-byte (IO0-7). ID table shows only lower-byte ID.

Table 9-3 Par ameter Page Output Va lue

9.1.6 READ STATUS (70h)

The W29N02GW/Z has an 8-bit Status Register which can be read during device operation. Refer to

Table 9.3 for specific Status Register definitions. After writing 70h command to the Command

outputs, as long as #CE and #RE are LOW. Note; #RE does not need to be toggled for Status Register

read. The Command Register remains in status read mode until another command is issued. To

change to normal read mode, issue the PAGE READ (00h) command. After the PAGE READ

command is issued, data output starts from the initial column address.

#CE

CLE

#WE

#RE

tCLR

I/Ox

70h Status Output

tREA

Figure 9-7 Read Status Operation

Release Date: May 19, 2015

21 Preliminary – Revision 0.3

W29N02GW/Z

SR bit Page Read Page Program Block Erase Definition

I/O 0 Not Use Pass/Fail Pass/Fail

0=Successful

Program/Erase

1=Error

in Program/Erase

I/O 2 Not Use Not Use Not Use 0

I/O 3 Not Use Not Use Not Use 0

I/O 4 Not Use Not Use Not Use 0

I/O 5 Ready/Busy Ready/Busy Ready/Busy Ready = 1

Busy = 0

I/O 6 Ready/Busy Ready/Busy Ready/Busy Ready = 1

Busy = 0

I/O 7 Write Protect Write Pr otect Write Protect Unprotected = 1

Protected = 0

Table 9-4 Status Register Bit Def ini ti on

9.1.7 READ STATUS ENHANCED (78h)

The READ STATUS ENHANCED (78h) command returns the status of the addressed plane on a

target even when it is busy (SR BIT 6 = 0).

Writing 78h to the command register, followed by three row address cycles containing the page, plane

and block addresses that is same as executed addresses, puts the device into read status mode. The

device stays in this mode until another valid command is issued

The device status is returned when the host requests data output. The SR BIT 6 and SR bit 5 bits of

the status register are shared for all planes on the device. The SR BIT 1 and SR BIT 0 (SR bit0) bits

are specific to the plane specified in the row address.

The READ STAT US ENHANCED (78h) command als o enab les the device for data output. T o beg in

data output following a READ operation after the device is ready (SR BIT 6 = 1), issue the READ

MODE (00h) command, then begin data output. If the host needs to change the data register that will

output data, use the TW O PLANE RANDOMDATA READ (06h-E0h) command after the device is

ready.

Use of the READ STATUS ENHANCED (78h) command is prohibited when OTP mode is enabled. It

is also prohibited following some of the other reset, identification.

Release Date: May 19, 2015

22 Preliminary – Revision 0.3

W29N02GW/Z

Figure 9-8 Read Status Enhanced (78h) Operation

CLE

ALE

#RE

I/O× Status Output

78h

#WE

#CE

Address (3cycles)

Release Date: May 19, 2015

23 Preliminary – Revision 0.3

W29N02GW/Z

9.1.8 READ UNIQUE ID (EDh)

The W29N02GW/Z NAND Flash d evice h as a m ethod to uni quely id entif y each N AND F lash device

by using the READ UNIQUE ID command. The format of the ID is limitless, but the ID for every NAND

Flash device manufactured, will be guaranteed to be unique.

Numerous NAND controllers typically use proprietary error correction code (ECC) schemes. In these

cases Winbond cannot protect unique ID data with factory programmed ECC. However, to ensure

data reliability, Winbond will program the NAND Flash devices with 16 bytes of unique ID code,

starting at byte 0 on the page, immediately followed by 16 bytes of the complement of that unique ID.

The combination of these two actions is then repeated 16 times. This means the final copy of the

unique ID will resides at location byte 511. At this point an XOR or exclusive operation can be

performed on the first copy of the unique ID and its complement. If the unique ID is good, the results

should yield all the bits as 1s. In the event that any of the bits are 0 after the XOR operation, the

procedure can be repeated on a subsequent copy of the unique ID data.

I/Ox

CLE

#WE

ALE

#RE

RY/#BY

EDh

Unique ID data

Byte0 Byte1 Byte14 Byte15

00h

Figure 9-9 Read Unique ID

Release Date: May 19, 2015

24 Preliminary – Revision 0.3

W29N02GW/Z

9.2 PROGRAM operation

9.2.1 PAGE PROGRAM (80h-10h)

The W29N02GW/Z Page Program command will program pages sequentially within a block, from the

lower order page address to higher order page address. Programming pages out of sequence is

prohibited. The W29N02GW/Z supports partial-page programming operations up to 4 times before

an erase is required if partitioning a page. Note; programming a single bit more than once without

first erasing it is not supported.

9.2.2 SERIAL DATA INPUT (8 0h)

Page Program operation starts with the execution of the Serial Data Input command (80h) to the

Command Register, following next by inputting five address cy cles and then the data is loaded. Serial

data is lo ade d to Data Register with each #WE cycle. The Pr ogram com mand (10h) is written to the

Command Register after the serial data input is finished. At this time the internal write state controller

automatically executes the algorithms for program and verifies operations. Once the programming

starts, determining the completion of the program process can be done by monitoring the RY/#BY

output or the Status Register Bit 6, which will follow the RY/#BY signal. RY/#BY will stay LOW during

the internal array programming operation during the period of (tPROG). During page program

operation, only two commands are available, READ STATUS (70h) and RESET (FFh). When the

device status goes to the ready state, Status Register Bit 0 (I/O0) indicates whether the program

operation passed (Bit0=0) or failed (Bit0=1), (see Figure 9-13). The Command Register remains in

read status mode until the next command is issued.

Figure 9-10 Pa ge Progr am

tPROG

Address (5cycles)

RY/#BY

I/Ox

Din80h10h70hStatus

I/O0

=0 pass

I/O0 =1 fail

Release Date: May 19, 2015

25 Preliminary – Revision 0.3

W29N02GW/Z

9.2.3 RANDO M DATA INPUT (8 5h)

After the Pag e Progr am (80h) ex ecution of the init ia l dat a has bee n loaded into the Data Regist er , if

the need for additional writing of data is required, using the RANDOM DATA INPUT (85h) command

can perform this function to a new column address prior to the Program (10h) command. The

RANDOM DATA INPUT command can be issued multiple times in the same page (See Figure 9-14).

Figure 9-11 Random Data Input

9.2.4 TWO PLANE PAGE PROGRAM

TW O PLANE P AGE PR OGR AM comm and m ake it pos sible for hos t to inp ut data t o the ad dressed

plane's data register and queue the data register to be moved to the NAND Flash array.

This c ommand c an be iss ued severa l tim es. Each tim e a new p lane addr ess is s pecified that pla ne

is also queu ed for data tr an sfer. To input data for the fi nal plane and to begin t he pr ogr am operation

for all previously queued planes, the PAGE PROGRAM command has to be issued. All of the queued

planes will move the data to the NAND Flash array. when it is ready (SR BIT 6 = 1),this command is

accepted.

At the block and page address is specified, input a page to the data register and queue it to be moved

to the NAND Flash array ,the 80h is issued to the command register. Unless this command has been

precede d by a TWO PLANE PAGE PROG R AM command, iss ui ng t he 80h to the command register

clears al l of the data regist ers' contents on the s elected t arget. W rite f ive address cycles conta ining

the colum n address an d row addres s; data input c ycles f ollow. Ser ial data is in put beginning a t the

colum n addres s s pecif ied. At any time, whi le t he da ta i nput c yc le, th e RA ND OM DATA INPUT ( 85h)

command can be issued. When data input is complete, write 11h to the command register. The device

will go busy (SR BIT 6 = 0, SR BIT 5 = 0) for tDBSY.

To ascertain the progress of tDBSY, the host can monitor the target's R Y/#BY signal or, the status

operatio ns (70h, 78h) can be used a lternat ively,. W hen the device st atus shows t hat it is read y (SR

BIT 6 = 1), additional TWO PLANE PAGE PROGRAM commands can be issued to queue additional

planes for data transfer, then, the PAGE PROGRAM commands can be issued.

When the PAGE PROGRAM command is used as the final command of a two plane program

operation, data is transferred from the data registers to the NAND Flash array for all of the addressed

RY/#BY

I/Ox

#WE

ALE

#RE

#CE

Din 70hStatus

Address (5cycles)

80h10h

Address

(2cycles)

85hDin

tPROG

Don’t care

CLE

Release Date: May 19, 2015

26 Preliminary – Revision 0.3

W29N02GW/Z

planes during tPROG. When the device is ready (SR BIT 6 = 1, SR BIT 5 = 1), the host should check

the status of the SR BIT 0 for each of the planes to verify that programming completed successfully.

When system issues TWO PLANE PAGE PROGRAM and PAGE PROGRAM commands, READ

STATUS (70h) comm and can confirm whether the operation(s) passed or failed. If the status after

READ STATUS (70h) command indicates an error (SR BIT 0 = 1 and/or SR BIT 1 = 1), READ

STATUS ENHANCED (78h) command can be determined which plane is failed.

TWO PLANE PROGRAM commands require five-cycle addresses, one address indicates the

operational plane. These addresses are subject to the following requirements:

• The column address bits must be valid address for each plane

• The plane select bit, A18, must be set to “L” for 1st address input, and set to “H” for 2nd address input.

• The page address (A17-A12) and block address (A28-A19) of first input are don’t care. It follows

secondary inputted page address and block address.

Two plane operations must be same type operation across the planes; for example, it is not possible

to perform a PROGRAM operation on one plane with an ERASE operation on another.

Figure 9-12 Two Plane Page Program

RY/#BY

Data

Input

FirstPlane

(1024 block)

Block 0

Block 2

Block 2044

Block 2046

Second Plane

(1024 block)

Block 1

Block 3

Block 2045

Block 2047

80h

Page program

Setup code

A0-A11=Valid

A12-A17=set to `Low`

A18=set to `Low`

A19-A28=set to `Low`

Confirm

Code

Multiplane Page

Program setup

code

A0-A11=Valid

A12-A17=Valid

A18=set to `High`

A19-A28=Valid

Confirm

Code

Read Status

11h81h10h70hSR0

1)The same row address, except for A18, is applied to the two blocks.

2)Any command between 11h and 81h is prohibited except 70h,78h,and FFh

tDBSY tPROG

(Program busy time)

Busy Busy

Address Inputs Data Input Data Input

Address Inputs

l/Ox

80h11h

81h10h

※81h:Traditional Protocol 80h:ONFI Protocol

※

Release Date: May 19, 2015

27 Preliminary – Revision 0.3

W29N02GW/Z

9.3 COPY B ACK operation

Copy Back operations require two command sets. Issue a READ for COPY BACK (00h-35h)

command first, then the PROGRAM for COPY BACK (85h-10h) command. Copy back operations are

only supported within a same plane.

9.3.1 READ fo r COPY BACK (00h-35h)

The R EAD for C OPY BAC K comm and is used togeth er with the PRO GRAM for COPY BACK ( 85h-

10h) command. To start execution, READ for COPY BACK (00h) command is written to the Command

page data from the memory array to the data register, write the 35h command to the Command

After execution of the READ for COPY BACK command sequence and RY/#BY returns to HIGH

marking the completion of the operation, the transferred data from the source page into the Data

was originally specified with the READ for COPY BACK command. RANDOM DATA OUTPUT (05h-

E0h) commands can be issued multiple times without any limitation after READ for COPY BACK

command has been executed (see Figures 9-19 and 9-20).

At this point the device is in ready state to accept the PROGRAM for COPY BACK command.

9.3.2 PROGRAM for COPY BACK (85 h-10h)

After the RE AD f or CO P Y BACK c om mand operation has bee n c ompleted and R Y/# B Y goes HIG H,

the PROGRAM for COPY BACK command can be written to the Command Register. The command

results in the transf er of data to the Data R egister, then int er na l o perat ions st art p r ogr am ming of the

new destination page. The sequence would be, write 85h to the Command Register, followed by the

five cy cle destination page address to the NAND array . Next write the 10h command to the Command

destinati on page. Dur ing this pro gramm ing time, RY/# BY will LOW . The READ STATUS com mand

can be used instead of the RY/#BY signal to determine when the program is complete. When Status

successful or not.

The RANDOM DATA INPU T (85h) command can be used during the PROGRAM for COPY BACK

command for modifying the original data. Once the data is copied into the Data Register using the

READ for COPY BACK (00h-35h) command, follow by writing the RANDOM DATA INPUT (85h)

comm and, along with t he address of the data to be change d. The data to be changed is placed o n

the external data pins. This operation copies the data into the Data Register. Once the 10h command

is written to the Command Register, the original data and the modified data are transferred to the

Data Register, and programming of the new page commences. The RANDOM DATA INPUT

command can be issued numerous times without limitation, as necessary before starting the

programming sequence with 10h command.

Since COPY BACK operations do not use external memory and the data of source page might include

a bit error s, a com petent ECC s cheme s hould be dev eloped to chec k the data befor e programm ing

data to a new destination page.

Release Date: May 19, 2015

28 Preliminary – Revision 0.3

W29N02GW/Z

9.3.3 TWO PLANE READ for COPY BA CK

To improve read through rate, TWO PLANE READ for COPY BACK operation is copied data

concurrently from one or two plane to the specified data registers.

TWO PLANE PROGRAM for CO P Y B AC K command can move the data in two pages from the data

registers to different pages. This operation improves system performance than PROGRAM for COPY

BACK operation.

9.3.4 TWO PLANE PROGRA M f o r COPY BACK

Function of TWO PLANE PROGRAM for COPY BACK command is equal to TWO-PLANE PAGE

PROGRAM com mand, except t hat when 85h is writte n to the comm and register , then data register

contents are not cleared. Refer to TWO-PLANE PAGE PROGRAM for more details features.

Release Date: May 19, 2015

29 Preliminary – Revision 0.3

W29N02GW/Z

Optional No limitation

RY/#BY

I/Ox

CLE

#WE

ALE

#RE

#CE

00h 35h 85h 10h

tPROG

70h

Status

Output

Address(5cycles)

DataOutput Address

(2cycles)

85h

Don’t care

Address(5Cycles)

Data Input Data Input

Figure 9-13 Program for copy back Operation

Figure 9-14 Copy Back Operation with Random Data Input

Optional

Data output

No limitation

RY / # BY

I/ Ox

tR tPROG

CLE

#WE

ALE

#RE

#CE

Data Output

00hAddress (5cycles)

35h

05hAddress

(2cycles)E0h

85h

Address(5cycles)

10h70h

Status

Output

Don’t care

Release Date: May 19, 2015

30 Preliminary – Revision 0.3

W29N02GW/Z

RY/#BY

I/O× 00h Address(5cycles)

Plane 0 source

00h Address(5cycles)

Plane 1 source

35h

RY/#BY

I/O×

85h Address(5cycles)

Plane 0 destination

11h

tDBSY

06h Address(5cycles)

Plane 0 or Plane 1 source address

E0h

#RE

Data Output 06h Address(2cycles)

Data from selected Plane Selected Plane

column address

E0h

#RE

Data Output

Data from selected plane

From new column address

85h Address(5cycles) 10h 70h Status

Plane 1 destination

RY/#BY

#RE

I/O×

Optional

tPROG

Figure 9-15 Two Plane Cop y Back

Figure 9-16 Two Plane Copy Back with Random Data Input

00h

I/O× Address(5cycles)

Plane 0 source

00hAddress(5cycles)

Plane 1 source

35h

tDBSY

data

Plane 0 destination optional

Unlimited number

of repetitions

85hAddress(5cycles)10h70hStatus

Plane 1 destination

RY/#BY

I/O×

85hData 11h

tPROG

85h

RY/#BY

Address(5cycles)Address(2cycles)

Release Date: May 19, 2015

31 Preliminary – Revision 0.3

W29N02GW/Z

Figure 9-17 Two Plane Program for copy back

RY/#BY

tR tDBSY

Busy Busy Busy Busy

tPROG

00h 35h 00h 35h 35h

Address

(5 cycles)

10h 70h SR0

Col Add.1,2

Row Add.1,2,3

Row Add1,2,3

Col Add1,2

Source address on Plane0 Source address on Plane1

Col Add1,2

Row Add.1,2,3

- A11 = set to `Low’

A12-A17 = Valid

A18 = set to `High’

A19-A28 = Valid

Read

code

Read

code

Copy back

code

Copy back

code Read Status Register

85h 11h

Col Add.1,2

Source address on Plane1

Row Add1, 2,3

Destination address on Plane0

l/O

Address

(5 cycles)

Address

(5 cycles)

Address

(5 cycles)

85h

※

Spare area

SourcePage

TargetPage

Main area

First plane

SourcePage

TargetPage

Main area Spare area

Second plane

(1):Read for copy back on first plane

(2):Read for copy back on second plane

(3):Two-plane copy back program

(1) (3) (2) (3)

※85h:ONFI Protocol

81h:Traditional Protocol

- A11 = don’t care

A12-A17 = don’t care

A18 = set to `Low’

A19- A28 = don’t care

Single plane copy back read can be used to two plane operation.

Release Date: May 19, 2015

32 Preliminary – Revision 0.3

W29N02GW/Z

9.4 BLOCK ERASE operation

9.4.1 BLOCK ERASE ( 6 0 h-D0h)

Erase oper ations happen a t th e architectural block unit. T his W29N02GW/Z has 2048 er ase block s .

Each block is organized into 64 pages (x8:2112 bytes/page, x16:1056 words/page), 132K bytes

(x8:128K + 4K bytes, x16:64 K+ 2Kwords)/block. The BLOCK ERASE command operates on a block

by block basis.

Erase Setup command (60h) is written to the Command Register. Next, the three cycle block address

is written to the device. The page address bits are loaded during address block address c ycle, but

are ignored. The Erase Confirm command (D0h) is written to the Command Register at the rising

edge of #W E, RY/#BY goes LOW and the internal controller autom atically handles the block erase

sequence of operation. RY/#BY goes LOW during Block Erase internal operations for a period of

tBERS,

The READ STATUS (70h) command can be used for confirm block erase status. When Status

indicate a pass/fail condition (see Figure 9-24).

CLE

#WE

ALE

RY/#BY

#CE

#RE

I/Ox

t BE RS

I/ O 0 =0 pass

I/ O 0 =1 fail

Ad dr es s Input (3cycles)

60h

D0h

Status Output

70h

Don’t c a re

Figure 9-18 Block Erase Operation

Release Date: May 19, 2015

33 Preliminary – Revision 0.3

W29N02GW/Z

9.4.2 TW O PLANE BL OCK ERASE

TWO PLA NE BLOC K ERAS E (60h-D1h) command indicates two blocks in the specified plane that is

to be erased. To start ERASE operation for indicated blocks in the specified plan e, write the BLOCK

ERASE (60h-D0h) command.

To indicate a block to be erased, writing 60h to the command register, then, write three address cy cles

containing the row address, the page address is ignored. By writing D1h command to command

To confirm bus y status duri ng tDB S Y, the hos t c an monitor R Y/#BY signal. I ns tea d, syst em can use

READ STATUS (70h) or READ STATUS ENHANCED (78h) commands. When the status shows

ready (SR BIT 6 = 1, SR BIT 5 = 1), additional TWO PLANE BLOCK ERASE commands can be

issued for erasing two blocks in a specified plane.

When system issues TWO PLANE BLOCK ERASE (60h-D1h), and BLOCK ERASE (60h-D0h)

commands, READ ST ATU S (70 h) c omm a nd can conf irm whether the operation(s) passed or f ailed .

If the status after READ STATUS (70h) command indicates an error (SR BIT 0 = 1), READ STATUS

ENHANCED (78h) command can be determined which plane is failed.

TWO PLANE BLOCK ERASE commands require three cycles of row addresses; one address

indicates the operational plane. These addresses are subject to the following requirements:

• The plane select bit, A18, must be different for each issued address.

• Block address (A28-A19) of first input is don’t care. It follows secondary inputted block address .

Two plane operations must be same type operation across the planes; for example, it is not possible

to perform a PROGRAM operation on one plane with an ERASE operation on another.

Figure 9-19 Two Plane Block Erase Operation

RY/#BY

CLE

#WE

ALE

#RE

I/Ox

Busy

R1A R2A R3A 60hR1B R2B D0h

D1h R3B

tBERS

Busy

tDBSY

#CE

60h

Don’t care

Release Date: May 19, 2015

34 Preliminary – Revision 0.3

W29N02GW/Z

9.5 RESET operation

9.5.1 RESET (FFh)

READ, PR OGRAM, and ERASE comm ands can be a borted by the RES ET (FFh) c omm and during

the time the W29N02GW/Z is in the busy state. The Reset operation puts the device into known

status. The data that is processed in either the programming or erasing operations are no longer

valid. This means the dat a c an be part ia lly programmed or erased and th erefore data is inv al id. T he

Command Register is cleared and is ready to accept next command. The Data Register contents are

marked invalid.

The Status Register indicates a value of E0h when #WP is HIGH; otherwise a value of 60h is written

when #W P is L OW. After RESET comm and is written to the c omm and register, RY/#BY goes LOW

for a period of tRST (see Figure 9-26).

CLE

#WE

RY/#BY

#CE

I/Ox

RESET

command

tRST

tWB

FFh

Figure 9-20 Reset Operation

Release Date: May 19, 2015

35 Preliminary – Revision 0.3

W29N02GW/Z

9.6 FEATURE OPERATION

The GET FEAT U RES ( EEh) an d SET FE AT URES ( EFh) c omm ands are used to change the NAND

Flash dev ice beha vior from the def ault po wer on settings. These c omm ands use a one-b yte featur e

address to determine which feature is to be read or modified. A range of 0 to 255 defines all features;

each is described in the features table (see Table 9.5 thru 9.7). The GET FEATURES (EEh) command

reads 4-Byte param eter in t he features table (See GET FEATURES function). The SET FEATURES

(EFh) command places the 4-Byte parameter in the features table (See SET FEATURES function).

W hen a featur e is set, m eaning it rem ains active b y default unt il the device is powered off. The s et

feature remains the set even if a RESET (FFh) command is issued.

Feature address Description

00h N.A

02h-7Fh Reserved

80h Vendor specific par ameter : Programmable I/O drive strength

81h Vendor specific parameter : Programmable RY/#BY pull-down strength

82h-FFh Reserved

Table 9-5 Features

Release Date: May 19, 2015

36 Preliminary – Revision 0.3

W29N02GW/Z

Feature Address 80h: Programmable I/O Drive Strength

Sub feature

parameter

Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes

I/O

drive strength

Full (default) Reserved (0) 0 0 00h 1

Three-quarters Reserved (0) 0 1 01h

One-half Reserved (0) 1 0 02h

One-quarter Reserved (0) 1 1 03h

Reserved (0) 00h

Table 9-6 Feature Address 80h

Note:

1. The default drive strength setting is Full strength. The Programmable I/O Drive Strength mode is u sed to

change from the def a ult I/O driv e strength. Drive strength should be selected based on expected loading of

the memory bus. This table shows the four supported output drive-strength settings. The device returns to

the default drive strength mode when a power cycle has occurred. AC timin g parameters ma y need to be

relaxed if I/O drive strength is not set to ful l.

Release Date: May 19, 2015

37 Preliminary – Revision 0.3

W29N02GW/Z

Feature Address 81h: Programmable RY/#BY Pull-down Strength

Sub feature

parameter

Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes

RY/#BY

pull-down

strength

Full (default) Reserved (0) 0 0 00h 1

Three-quarters Reserved (0) 0 1 01h

One-half Reserved (0) 1 0 02h

One-quarter Reserved (0) 1 1 03h

Reserved (0) 00h

Table 9-7 Feature Address 81h

Note:

1. The default pr ogrammable RY/#BY pull-down strength is set to Full strength . The pul l-down strength is used

to change the RY/#BY pull-down st rength. RY/#BY pull-down strength should be selected based on expected

loading of RY/#BY. The four supported pull-down strength settings are shown. The device returns to the

default pull-down strength w hen a power cycle has occurred.

Release Date: May 19, 2015

38 Preliminary – Revision 0.3

W29N02GW/Z

9.6.1 GET FEATURES (EEh)

The GET FEATURES command returns the device feature settings including those previously set by

the SET FEATURES command. To use the Get Feature mode write the command (EEh) to the

Command Register followed by the single cy cle byte Feature Address. RY/#BY will goes LOW for the

period of tFEAT. If Read Status (70h) command is issued for monitoring the process completion

status, Read Comm and (00h) has t o be executed t o re-establish data output m ode. Once, RY/#BY

goes HIGH, the device feature settings can be read by toggling #RE. The device remains in Feature

Mode until another valid command is issued to Command Register. See Figure 9-27.

I/Ox

CLE

#WE

ALE

#RE

RY/#BY

Feature address

1 cycle

#CE

EEh

tFEAT

P1 P2 P4P3

Figure 9-21 Get Feature Operation

Release Date: May 19, 2015

39 Preliminary – Revision 0.3

W29N02GW/Z

9.6.2 SET FEATURES (EFh)

The SET FEATURES command sets the behavior parameters by selecting a specified feature

address. To change device behavioral parameters, execute Set Feature command b y writ in g EFh to

the Command Register, followed b y the single c ycle feature address. Each feature param eter (P1-

P4) is latch ed at the rising edge of each #WE. The RY/#BY s ign al wil l go LOW durin g th e period of

tFEAT while the four feature parameters are stored. The Read Status (70h) command can be issued

for monitoring the progress status of this operation. The parameters are stored in device until the

device goes through a power on cycle. The device remains in feature mode until another valid

command is issued to Command Register.

I/Ox

CLE

#WE

ALE

#RE

RY/#BY

#CE

EFh

tFEAT

P1 P2 P4P3

tWB

tADL

Figure 9-22 Set Feature Operation

Release Date: May 19, 2015

40 Preliminary – Revision 0.3

W29N02GW/Z

9.7 ONE TIME PROGRAMMABLE (OTP) area

The device has One-Time Programmable (OTP) memory area comprised of a number of pages (2112

bytes/page) (1056words/page). T his entire r ange of pages is func tionall y guarant eed. Only the OTP

commands can acces s the OT P area. When the de vice ships f rom Winbond, the OT P area is in an

erase state (all bits equal “1”). The OTP area cannot be erased, therefore protecting the area only

prevent further programming. Contact to Winbond for using this feature.

Release Date: May 19, 2015

41 Preliminary – Revision 0.3

W29N02GW/Z

9.8 WRITE PROTECT

#WP pin can enable or disable program and erase comm ands preventing or allowing program and

erase operations. Figure 9-29 to 9-34 shows the enabling or disabling timing with #WP setup time

(tWW) that is fr om rising or falling ed ge of #W P to latch th e first commands. After first command is

latched, #W P pin must not toggle u ntil the com mand operation is complete an d the device is in the

ready state. (Status Register Bit5 (I/O5) equal 1)

I /Ox

#WE

#WP

tWW

RY/#BY

60h D0h

Figure 9-23 Erase Enable

I/Ox

#WE

#WP

tWW

RY/#BY

60hD0h

Figure 9-24 Erase Disable

I/Ox

#WE

#WP

tWW

RY/#BY

10 h

(or 15h)

Figure 9-25 Program Enable

Release Date: May 19, 2015

42 Preliminary – Revision 0.3

W29N02GW/Z

I/Ox

#WE

#WP

80 h

tWW

RY/#BY

10 h

(or 15h)

Figure 9-26 Program Disable

#WE

#WP

85h

tWW

RY/#BY

10h

Figure 9-27 Program for Copy Back Enable

I/Ox

#WE

#WP

85 h

tWW

RY/#BY

10 h

Figure 9-28 Program for Copy Back Disable

Release Date: May 19, 2015

43 Preliminary – Revision 0.3

W29N02GW/Z

9.9 BLOCK LO CK

The dev ice has block lock feature that c a n pr otec t the entire d ev ice or user can indicate a ranges of

blocks from program and erase operations. Using this feature offers increased functionality and

flexibility dat a protection to preve nt unexpect ed pro gra m and erase operations. Contact to Winbond

for using this feature.

Release Date: May 19, 2015

44 Preliminary – Revision 0.3

W29N02GW/Z

10. ELECTRICAL CHARACTERISTICS

10.1 Abso lute Maximum Ratings (1.8V)

PARAMETERS SYMBOL CONDITIONS RANGE UNIT

Suppl y Voltage VCC –0.6 to +2.4 V

Voltage Applied to Any Pin VIN Relative to Ground –0.6 to +2.4 V

Storage Temperature TSTG –65 to +150 °C

Short circuit output current, I/Os 5 mA

Table 10-1 Absolute Maximum Ratings

Notes:

1. S pecifi cation for W29N02GW/Z is prelimin ary. See prelimin ary designation at the end of this document.

2. This device has been designed and tested for the speci fied operation ranges. Proper operation outside of

these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability.

Exposure be yond absolute maximum ratings may cause permanent damage.

10.2 Operating Ran ges (1.8V)

PARAMETER SYMBOL CONDITIONS SPEC UNIT

MIN MAX

Suppl y Voltage VCC 1.7 1.95 V

Ambient Temperature,

Operating TA Industrial -40 +85 °C

Table 10-2 Operating Ranges

Release Date: May 19, 2015

45 Preliminary – Revision 0.3

W29N02GW/Z

10.3 Device power-up timing

The device is designed to avoid unexpected program/erase operations during power transitions.

W hen the device is powere d on, an i nternal vo ltage de tector dis ables all f unctions whene ver Vcc is

below about 1.1V at 1.8V device. Write Protect (#WP) pin provides hardware protection and is

recommended to be kept at VIL during power up and power down. A recovery time of minimum 1ms

is required before internal circuit gets ready for any command sequences (See Figure 10-1).

Figure 10-1 Power ON/OFF sequence

5 ms (Max)

Vcc

RY/#BY

1ms

(Min)

Undefined

#WP

#WE

Release Date: May 19, 2015

46 Preliminary – Revision 0.3

W29N02GW/Z

10.4 DC E lectrical Characteristi cs (1.8V)

PARAMETER SYMBOL CONDITIONS SPEC UNIT

MIN TYP MAX

Sequential Read current Icc1

tRC= tRC MIN

#CE=VIL

IOUT=0mA - 13 20 mA

Program current Icc2 - - 10 20 mA

Erase current Icc3 - - 10 20 mA

Standby current (TTL) ISB1 #CE=VIH

#WP=0V/Vcc - - 1 mA

Standby current (CMOS) ISB2 #CE=Vcc – 0.2V

#WP=0V/Vcc - 10 50 µA

Input l eakage current ILI VIN= 0 V to Vcc - - ±10 µA

Output leakage cur rent ILO VOUT=0V to Vcc - - ±10 µA

Input hi gh voltage VIH I/O15~0, #CE,#WE,#RE,

#WP,CLE,ALE 0.8 x Vcc - Vcc + 0.3 V

Input l ow voltage VIL - -0.3 - 0.2 x Vcc V

Output high voltage(1) VOH IOH=-100µA Vcc -0.1 - - V

Output low voltag e(1) VOL IOL=+100µA - - 0.1 V

Output low curr ent IOL(RY/#BY) VOL=0.2V 3 4 mA

Table 10-3 DC Electrical C har ac teris t ics

Note:

1. VOH and VOL may need to be relaxed if I/O drive strength is not set to full.

Release Date: May 19, 2015

47 Preliminary – Revision 0.3

W29N02GW/Z

10.5 AC Measurement C ondition s ( 1.8V)

PARAMETER SYMBOL SPEC UNIT

MIN MAX

Input Capacitance(1), (2) CIN - 10 pF

Input/Output Capacitance(1), (2) CIO - 10 pF

Input Rise and Fall Times TR/TF - 2.5 ns

Input Pulse Voltages - 0 to VCC V

Input/Output timing Voltage - Vcc/2 V

Output load (1) CL 1TTL GATE and CL=30pF -

Table 10-4 AC Measurement Conditions

Notes:

1. Veri fi ed on device characterization , not 100% tested

2. Test conditi o ns TA=25’C, f=1M Hz, VIN=0V

Release Date: May 19, 2015

48 Preliminary – Revision 0.3

W29N02GW/Z

10.6 AC timing charact eristics for Command, Address and Data Input (1.8V)

PARAMETER SYMBOL SPEC UNIT

MIN MAX

ALE to Data Loading Time tADL 70 - ns

ALE Hold Ti m e tALH 5 - ns

ALE setup T ime tALS 10 - ns

#CE Hold Ti m e tCH 5 - ns

CLE Hold Ti m e tCLH 5 - ns

CLE set up Time tCLS 10 - ns

#CE set up Time tCS 20 - ns

Data Hold Time tDH 5 - ns

Data setup Time tDS 10 - ns

Write Cycle Time tWC 25 - ns

#WE High Hold Time tWH 10 - ns

#WE Pulse Width tWP 12 - ns

#WP setup Time tWW 100 - ns

Table 10-5 AC timing characteristics for Command, Address and Data Input

Note:

1. tADL is the time from the #WE rising edge of final address cycle to the #WE rising edge of first data cycle.

Release Date: May 19, 2015

49 Preliminary – Revision 0.3

W29N02GW/Z

10.7 AC timing charact eristics for Operation (1.8V)

PARAMETER SYMBOL SPEC UNIT

MIN MAX

ALE to #RE Delay tAR 10 - ns

#CE Access Time tCEA - 25 ns

#CE HIGH to Output H igh-Z(1) tCHZ - 50 ns

CLE to #RE Delay tCLR 10 - ns

#CE HIGH to Output Hold tCOH 15 - ns

Output High-Z to #RE LOW tIR 0 - ns

Data Transfer from Cell to Data Register tR - 25 µs

READ Cycle Time tRC 25 - ns

#RE Access Time tREA - 22 ns

#RE HIGH Hold Time tREH 10 - ns

#RE HIGH to Output Hol d tRHOH 15 - ns

#RE HIGH to #WE LOW tRHW 100 - ns

#RE HIGH to Output Hi gh-Z(1) tRHZ - 100 ns

#RE LOW to output hold tRLOH 3 - ns

#RE Pulse Width tRP 12 - ns

Ready to #R E LOW tRR 20 - ns

Reset Tim e (READ/PROGRAM/ ER ASE)(2) tRST - 5/10/500 µs

#WE HIGH t o Busy(3) tWB - 100 ns

#WE HIGH to #RE LOW tWHR 80 - ns

Table 10-6 AC timing characteristics for Operation

Notes: AC characteristics may need to be relaxed if I/O drive strength is not set to “full.”

1. Transition is measured ±200mV from steady-state voltage with load. This parameter is sampled and not

100 % tested

2. Do not issue new command during tWB, even if RY/#BY is ready.

Release Date: May 19, 2015

50 Preliminary – Revision 0.3

W29N02GW/Z

10.8 Program and E rase Characteristics

PARAMETER SYMBOL SPEC UNIT

TYP MAX

Number of partial page programs NoP - 4 cycles

Page Pro gram time tPROG 250 700 µs

Busy Time for SET FEATURES /GET FEATURES tFEAT - 1 µs

Busy Tim e for progr am /erase at locked bl ock tLBSY - 3 µs

Busy Tim e for OTP program when OTP is protected tOBSY - 30 µs

Block Erase Time tBERS 2 10 ms

Last Page Program time (1) tLPROG - - -

Busy Time for Two Plane page program and Two Plane Block

Erase tDBSY 0.5 1 µs

Table 10-7 Program and Erase Characteristics

Note:

1. tLPROG = Last Page program time (tPROG) + Last -1 Page program time (tPROG) – Last page Address,

Command and Data load time.

Release Date: May 19, 2015

51 Preliminary – Revision 0.3

W29N02GW/Z

11. TIMING DIAGRAMS

Figure 11-1 Command Latch Cycle

Figure 11-2 Address Latch Cycle

tCS

Command

tWP

tCLHtCLS

tCH

tALS tALH

tDS tDH

Don’t care

CLE

#WE

ALE

I/Ox

#CE

tCS

Address

tWP

tWC

tALS tALH

tDS tDH

tCLS

tWH

Don’t care Undefined

CLE

#CE

I/Ox

#WE

ALE

Release Date: May 19, 2015

52 Preliminary – Revision 0.3

W29N02GW/Z

Figure 11-3 Data Latch Cycle

Note:

1. Din Final = 2,111(x8)

Figure 11-4 Serial Access Cycle after Read

Din 0

tWP

tCLH

tALS

tDS tDH

tWP tWP

Din 1

tDS tDH

tWH

Din Final

tDS tDH

tCH

tWC

Don’t care

CLE

#CE

I/Ox

#WE

ALE

tCHZ

tCEA

tRP

tRHZ

Dout Dout

tREA

tREH

tREA

Dout

tREA

tRHOH

tCOH

tRHZ

tRR tRC

Don’t care

#CE

I/Ox

#RE

RY/#BY

Release Date: May 19, 2015

53 Preliminary – Revision 0.3

W29N02GW/Z

Figure 11-5 Serial Access Cycle after Read (EDO)

Figure 11-6 Read Status Operation

tCHZ

tCEA

tRP

Dout

tREA

tREH

tREA

tCOH

tRHZ

tRR

tRC

Dout

tRHOH

tRLOH

Don’t care

I/Ox

RY/#BY

#RE

#CE

Dout

#CE

#RE

#WE

tWP tCH

tRHZ

tCHZ

CLE

I/Ox

tCOH

Status

output

tRHOH

tRP

tCEA

tCS

tCLR

tCLS tCLH

70h

tDS tDH tIR tREA

tWHR

Don’t care

Release Date: May 19, 2015

54 Preliminary – Revision 0.3

W29N02GW/Z

Busy

Dout

n+1

Dout

00h 30h

tAR

tWB

tCLR

tRC

tRR

tWC

tRP

tRHZ

I/Ox

#WE

ALE

#RE

RY/#BY

CLE

#CE

Don’t care

Address(5Cycles)

Figure 11-7 Page Read Operation

CLE

#WE

ALE

RY/#BY

#CE

#RE

I/Ox

Out

tCEA

t RE A

tCOH

tCHZ

#CE

#RE

I/Ox

00hAddress (4 cycles)30hData outpu t

Don’t c a re

Figure 11-8 #CE Don't Care Read Operation

Release Date: May 19, 2015

55 Preliminary – Revision 0.3

W29N02GW/Z

t RC

t RR

Colu mn address n

t RE A

Colu mn address m

t CL R

tAR

tWB

tWC

tWHR

00h30h05hE0h

Bu sy

#WE

ALE

#RE

RY/#BY

CLE

#CE

I/Ox

Don’t c a re

Figure 11-9 Random Data Output Operation

Release Date: May 19, 2015

56 Preliminary – Revision 0.3

W29N02GW/Z

I/Ox

#WE

#RE

CLE

#CE

ALE

tAR

90h

(or 20h)

Address, 1 cy cle

00hByte 1

Byte 0

t RE A

Byte 2Byte 4

Byte 3

tWHR

Figure 11-10 Read ID

I/Ox

#WE

ALE

#RE

RY/#BY

CLE

#CE

80hCol

add 1Col

add 2

tWC

Ro w

add 1Ro w

add 2S ta t us

S E RIA L DATA

INPUT c omman d

70h

tPROGtWB

tADL

10h

1 up to m By t e

serial input

PRO GRAM

co mmand

READ STATUS

co mmand

x8 device:m = 2112 b y t es

tWHR

Don’t c a re

Figure 11-11 Page Pro gr a m

Release Date: May 19, 2015

57 Preliminary – Revision 0.3

W29N02GW/Z

I/Ox

CLE

#WE

ALE

#CE

80hAddress(4 cy cl es)Data input Data input 10h

#WE

#CE

tCS t CH

tWP

Don’t c a re

Figure 11-12 #CE Don't Care Page Program Operation

Release Date: May 19, 2015

58 Preliminary – Revision 0.3

W29N02GW/Z

I/Ox

CLE

#WE

ALE

#RE

#CE

80hCol

add 2

Col

add 1

ｔWC

Din

ｎ

Din

N+1

Serial Data

Inpu t Co mmand

85hSt atu s

70h

10h

Din

N+1

Serial INPUT

Com ma nd

Program

C om ma nd

tADL

tWB

tPROG

Rand om Data Input

Com ma nd

RY/#BY

Colu mn address Serial INPUT

Ro w

add2

tADL

Col

add1Col

add2Din

ｎ

Don’t c a re

Ro w

add1

Figure 11-13 Page Program with Random Data Input

Figure 11-14 Copy Back

00h

ｔWC

Serial data INPUT

Command

tADL

Program

Command

tWB

tPROG

I/Ox

CLE

#WE

ALE

#RE

#CE

RY/#BY

tWB

Busy

Col

add 1 Col

add 2 Row

add1Row

add235h85hCol

add 1 Col

add 2 Row

add1Row

add2Din

1Din

n10hStatus

70h

Don’t care

Release Date: May 19, 2015

59 Preliminary – Revision 0.3

W29N02GW/Z

#RE

RY/#BY

CLE

#CE

#WE

ALE

Busy

60h D0h

tBERS

tWC

Status

70h

BLOCK ERASE SETUP

command

ERASE

command READ STATUS

command

tWB

I/Ox

Don’t care

Address(3cycles)

Figure 11-15 Block Erase

I/Ox

#WE

RY/#BY

CLE

#CE

F Fh

t RS T

RESET

co mmand

tWB

Figure 11-16 Reset

Release Date: May 19, 2015

60 Preliminary – Revision 0.3

W29N02GW/Z

12. INVALID BLOCK MANAGEMENT

12.1 Invalid blocks

The W29N02GW/Z m ay have initial invalid blocks when it ships from factory. Als o , additional invalid

blocks may develop during the use of the device. Nvb represents the minimum number of valid blocks

in the total number of available blocks (See Table 12.1). An invalid block is defined as blocks that

contain one or more bad bits. Block 0, block address 00h is guaranteed to be a valid block at the time

of shipment.

Parameter Symbol Min Max Unit

Valid block number Nvb 2008 2048 blocks

Table 12-1 Valid Block Number

12.2 Initial invalid blocks

Initial invalid blocks are defined as blocks that contain one or more invalid bits when shipped from

factory.

Although the device contains init ial invalid blocks, a valid block of the device is of the same quality

and reliability as all valid blocks in the device with reference to AC and DC specifications. The

W29N02GW/Z has inter nal cir cuits to iso late each b lock from other block s and therefore, the invalid

blocks will not affect the performance of the entire device.

Before the device is shipped from the factory, it will be erased and invalid blocks are marked. All initial

invalid blocks are marked with non-FFh at the first byte of spare area on the 1st or 2nd page. The initial

invalid bloc k inform ation cannot b e recov ered if ina dve rtentl y erased. T heref ore, sof tware shoul d be

created to initially check for invalid blocks by reading the marked locations before performing any

program or erase operation, and create a table of initial invalid blocks as following flow chart

Release Date: May 19, 2015

61 Preliminary – Revision 0.3

W29N02GW/Z

Figure 12-1 Flow chart of create initial invalid block table

12.3 Error in operation

Additional invalid blocks may develop in the device during its life cycle. Following the procedures

herein is required to guarantee reliable data in the de vic e.

After each program and erase operation, check the status read to determine if the operation failed. In

case of failure, a block replacement should be done with a bad-block management algorithm. The

system has to use a minimum 1-bit ECC per 528 bytes of data to ensure data recovery.

Operation Detection and recommended procedure

Erase Status read after erase  Block Replacement

Program Status read after program  Block Replacement

Read Ver ify ECC  ECC correction

Table 12-2 Block failure

Release Date: May 19, 2015

62 Preliminary – Revision 0.3

W29N02GW/Z

Figure 12-2 Bad block Replacement

Note:

1. An error happens in the nth page of block A during program or erase operation.

2. Copy the data in block A to the same location of block B which is valid block.

3. Copy the nth page data of block A in the buffer memory to the nth page of block B

4. Creating or updating bad block table for preventing furth er program or erase to block A

12.4 Addressing i n pr ogr am opera t ion

The pages within the block have to be programmed sequentially from LSB (least significant bit) page

to the M SB (m ost significa nt bit) within the block. The LS B is defined as the start page to pr ogram,

does not need to be page 0 in the block. Random page programming is prohibited.

Release Date: May 19, 2015

63 Preliminary – Revision 0.3

W29N02GW/Z

13. REVISION HISTORY

VERSION DATE PAGE DESCRIPTION

0.1 8/22/14 New Create as preliminary

0.2 10/23/14 77

79 Update POD

Correct Valid Part Numbers

0.3 05/19/15 Remove Cache operation mode

06/08/2015 Modified for MCP Datasheet.

Table 16-1 History Table

Preliminary Designation

The “Preliminary” designation on a Winbond datasheet indicates that the product is not fully

characterized. The specifications are subject to change and are not guaranteed. Winbond or an

authorized sales representative should be consulted for current information before using this product.

Trademarks

Winbond is trademark of Winbond Electronics Corporation.

All other marks are the property of their respective owner.

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components in

systems or equipment intended for surgical implantation, atomic energy control instruments, airplane

or spaceship instrum ents, transportation instruments, traffic signal instruments, com bustion control

instruments, or for other applications intended to support or sustain life. Furthermore, Winbond

products are not intended for applications wherein failure of Winbond products could result or lead to

a situation where in personal injury, death or severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their own

risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

Release Date: May 19, 2015

64 Preliminary – Revision 0.3

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 1 - Revision : P01-004A

1. GENERAL DESCR IPTION

LPDDR2 is a high-speed SDRAM device internally configured as a 8-Bank memory.These devices

contain 1 Gb has 1,073,741,824 bits.

All LPDDR2 devices use a double data rate architecture on the Command/Address (CA) bus to reduce

the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row

Buffer information. Each command uses one clock cycle, during which command information is

transferred on both the positive and negative edge of the clock.

For LPDDR2 devices, accesses begin with the registration of an Activate command, which is then

followed by a Read or Write command. The address and BA bits registered coincident with the Activate

command are used to select the row and the Bank to be accessed. The address bits registered

coincident with the Read or Write command are used to select the Bank and the starting column location

for the burst access.

2. FEATURES

• VDD1 = 1.7~1.95V

• VDD2/VDDCA/VDDQ = 1.14V ~ 1.30V

• Data width: x32

• Clock rate: up to 533MHz

• Four-bit prefetch DDR archite ct ure

• Eight internal ban ks for concurrent opera tion

• Programmabl e RE AD and WRITE latencies (RL/WL)

• Programmabl e burst lengths: 4, 8, or 16

• Per Bank Refresh

• Partial Array Self-Refresh(PASR)

• Deep Power Do wn Mode (DPD Mode)

• Programmabl e output buffer driver st rength

• Data mask (DM) f or write data

• Clock Stop capability during idle periods

• Double data rat e for data output

• Differential clock inputs

• Bidirectional di fferential data strobe

• Interface: HSUL_12

• JEDEC LPDDR2-S4B compliance

• Support KGD (Kno wn Good Die) form

• Operating Temperature Ra nge

Tj :

-25 ~ 85 °C

-40 ~ 85 °C

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 2 - Revision : P01-004A

TABLE OF CONTENTS

1. GENERAL DESCRIPTION ....................................................................................................... 1

2. FEATURES .............................................................................................................................. 1

4. PIN DESCRIPTION .................................................................................................................. 7

4.1 Signal Description ............................................................................................................................. 7

5. BLOCK DIAGRAM ................................................................................................................... 9

6. FUNCTIONAL DESCRIPTION ............................................................................................... 10

6.1 Simplified LPDDR2 State Diagram ................................................................................................. 10

6.1.1 Figure of Sim pl i fied LPDDR2 Bus Interface State Diagram ................................................................. 11

6.2 Power-up, Initialization, and Power-Off ........................................................................................... 12

6.2.1 Power Ramp and Device Initialization ................................................................................................. 12

6.2.2 Timing Param eters for initialization ...................................................................................................... 14

6.2.3 Figure of P ower Ramp and Initializati on S equence ............................................................................. 14

6.2.4 Initialization after Reset (without Power ramp) .................................................................................... 15

6.2.5 Power-off Sequence ............................................................................................................................. 15

6.2.6 Timing Param eters Power-Off ............................................................................................................. 15

6.2.7 Uncontrolled P ower-Off Sequence ...................................................................................................... 15

6.3 Mode Register Definition ................................................................................................................. 16

6.3.1 Mode Register Assignment and Definiti on ........................................................................................... 16

6.3.1.1 Tabl e of Mode Register A ssignment........................................................................................................... 16

6.3.2 MR0_Devi ce I nformation (MA[7:0] = 00H) ........................................................................................... 17

6.3.3 MR1_Devi ce Feature 1 (MA[7:0] = 01H ) ............................................................................................. 17

6.3.3.1 1 Tabl e of Burst Sequence by Burs t Length (BL), Bur s t Type (BT), and Warp Control (WC) ..................... 18

6.3.3.2 Tabl e of Non Wrap Restric tions .................................................................................................................. 18

6.3.4 MR2_Devi ce Feature 2 (MA[7:0] = 02H ) ............................................................................................. 19

6.3.5 MR3_I/O Conf i guration 1 (MA[7:0] = 03H) ........................................................................................... 19

6.3.6 MR4_Devi ce Temperature (MA[7: 0] = 04H ) ....................................................................................... 19

6.3.7 MR5_Basic Configuration 1 (MA[7:0] = 05H) ....................................................................................... 20

6.3.8 MR6_Basic Configuration 2 (MA[7:0] = 06H) ....................................................................................... 20

6.3.9 MR7_Basic Configuration 3 (MA[7:0] = 07H) ....................................................................................... 20

6.3.10 MR8_Basic Configurat ion 4 (MA[7:0] = 08H ) ..................................................................................... 20

6.3.11 MR9_Test M ode (MA[7:0] = 09H) ...................................................................................................... 20

6.3.12 MR10_Calibration (MA[7:0] = 0AH) ................................................................................................. 20

6.3.13 MR16_P A SR_Bank Mask (MA[7: 0] = 10H) ....................................................................................... 21

6.3.14 MR17_P A SR_Segment Mask (MA [7:0] = 11H) ................................................................................. 21

6.3.15 MR32_DQ Calibration Pattern A (MA[7:0] = 20H) ............................................................................. 22

6.3.16 MR40_DQ Calibration Pattern B (MA[7:0] = 28H) ............................................................................. 22

6.3.17 MR63_Reset (MA[7:0] = 3FH): MRW only ......................................................................................... 22

6.4 Command Definitions and Timing Diagram .................................................................................... 23

6.4.1 LPDDR2-S4: Activate Command . ............................................................................................... 23

6.4.1.1 Figure of LPDDR2-S4 : Ac tivate command cycle : tRCD =3,tRP=3,tRRD= 2 .............................................. 23

6.4.1.2 Figure of LPDDR2-S4: tFAW timing ........................................................................................................... 24

6.4.1.3 Figure of LPDDR2 Command I nput Setup and Hold Timing ...................................................................... 24

6.4.1.4 Figure of LPDDR2 CKE Input Setup and Hold Tim ing................................................................................ 25

6.4.2 LPDDR2-S4: Read and Write access modes ...................................................................................... 25

6.4.3 Burst Read com m and .......................................................................................................................... 25

6.4.3.1 Figure of Data output(read)timing(tDQSCKmax) ........................................................................................ 26

6.4.3.2 Figure of Data output(read)timing(tDQSCK min) ......................................................................................... 27

6.4.3.3 Figure of LPDDR2-S4 : Bur s t read : RL = 5. BL = 4. tDQSCK > tCK ......................................................... 27

6.4.3.4 Figure of LPDDR2-S4 : Burst read : RL = 3. BL = 8. tDQSCK < tCK ....................................................... 28

6.4.3.5 Figure of LPDDR2: tDQSCKDL timing ....................................................................................................... 28

6.4.3.6 Figure of LPDDR2: tDQSCKDM timing ...................................................................................................... 29

6.4.3.7 Figure of LPDDR2: tDQSCKDS timing ....................................................................................................... 29

6.4.3.8 LPDDR2-S4 : Burst read followed by burst write: RL = 3, WL = 1, BL = 4 ................................................. 30

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 3 - Revision : P01-004A

6.4.3.9 Figure of LPDDR2-S4 : Seam less burst read : RL = 3, BL= 4, tCCD=2 ..................................................... 30

6.4.4 Reads int errupted by a read ................................................................................................................ 31

6.4.4.1 Figure of LPDDR2-S4 : Read burs t interrupt example : RL = 3, BL= 8, tCCD=2 ........................................ 31

6.4.5 Burst Write operation ........................................................................................................................... 31

6.4.5.1 Data i nput (write) timing .............................................................................................................................. 32

6.4.5.2 LPDDR2-S4 : Burst write : WL = 1, BL= 4 .................................................................................................. 32

6.4.5.3 LPDDR2-S4 : Burst wirte followed by burst read : R L = 3, WL= 1, BL=4 ................................................... 33

6.4.5.4 LPDDR2-S4 : Seamless burst write : WL= 1, BL=4, tCCD=2 ..................................................................... 33

6.4.6 Writes i nterrupted by a write ................................................................................................................ 34

6.4.6.1 LPDDR2-S4 : Write burst i nterrupt timing : WL= 1, BL=8, tCCD=2 ............................................................ 34

6.4.7 Burst Terminate .................................................................................................................................... 34

6.4.7.1 LPDDR2-S4 : Write burst truncated by BST : WL= 1, BL=16 ..................................................................... 35

6.4.7.2 LPDDR2-S4 : Burst Read truncated by BST : RL= 3, BL=16 ..................................................................... 35

6.4.8 Write data m ask ................................................................................................................................... 36

6.4.8.1 LPDDR2-S4 : Write data mask ................................................................................................................... 36

6.4.9 LPDDR2-S4: P recharge operation ....................................................................................................... 37

6.4.9.1 Tabl e of Bank selection for Precharge by address bits ............................................................................... 37

6.4.10 LPDDR2-S4: Burst Read ope rat ion followed by Precharge .............................................................. 37

6.4.10.1 Fig ur e of LPDDR2-S4 Burst r ead followed by Precharge : RL= 3, BL=8, RU(t RTP(min)/tCK) = 2 ........... 38

6.4.10.2 Fig ur e of LPDDR2-S4 : Burst read followed by Precharge : RL= 3, BL= 4, RU(tRTP(min)/tCK)=3 ........... 38

6.4.11 LPDDR2-S4: Burst Write followed by Precharge ............................................................................... 39

6.4.11.1 Figur e of LPDDR2-S4 : Burst write follwed by precharge : WL = 1, BL= 4 ............................................... 39

6.4.12 LPDDR2-S4: Auto Precharge operation ............................................................................................ 40

6.4.13 LPDDR2-S 4: Burst Read with Auto-Precharge.................................................................................. 40

6.4.13.1 Fig ur e of LPDDR2-S4 : Burst read with Auto-Precharge : RL= 3, BL=4, RU(tRTP(min)/tCK)=2 .............. 40

6.4.14 LPDDR2-S 4: Burst write with Auto-Precharge................................................................................... 41

6.4.14.1 Fig ur e of LPDDR2-S4 : Burst write w/Auto prech arge : WL = 1, BL= 4 .................................................... 41

6.4.14.2 Tabl e of LPDDR2-S4 Prec har ge & Auto Precharge C larification ............................................................. 42

6.4.15 LPDDR2-S4: Refresh command ........................................................................................................ 43

6.4.15.1 Tabl e of Command Scheduling Separations r el ated to Refresh ............................................................... 44

6.4.16 LPDDR2 SDRAM Refresh Requirements .......................................................................................... 44

6.4.16.1 Fig ure of LPDDR2-S4 : Definition of tSRF ................................................................................................ 45

6.4.16.2 Fig ur e of LPDDR2-S4 Regular, D istributed Refresh Pattern vs. Repetitive Burst Refresh with Subsequent

Refresh Pause ........................................................................................................................................................ 46

6.4.16.3 Fig ur e of LPDDR2-S4: Allowable Transition f r om Repetitive Burst Refresh with Subse quent Refresh

Pause to Regular, Distributed Refresh Pattern ....................................................................................................... 47

6.4.16.4 Fig ur e of LPDDR2-S4: NOT-Allowable Transition from Repet itive Burst Refresh with Subsequent

Refresh Pause to Regular, Dist ributed Refresh Pat tern ......................................................................................... 47

6.4.16.5 Fig ur e of LPDDR2-S4: Recommended Self-refresh ent ry and exit in conjunction with a Burst/P ause

Refresh patt erns. .................................................................................................................................................... 48

6.4.16.6 Fig ur e of LPDDR2-S4 All Bank Refresh Operation .................................................................................. 48

6.4.16.7 Fig ur e of LPDDR2-S4 Per Bank Refresh Operation ................................................................................. 49

6.4.17 LPDDR2-S4: Self Refresh operation ................................................................................................. 50

6.4.17.1 Figur e of LPDDR2-S4 : Self Refresh Operation ....................................................................................... 51

6.4.18 LPDDR2-S 4: Partial Array Self-Refresh: Bank Masking .................................................................... 51

6.4.19 LPDDR2-S 4: Partial Array Self-Refresh: Segment Masking ............................................................. 51

6.4.20 Mode Register Read Command ........................................................................................................ 52

6.4.20.1 Fig ur e of Mode Register R ead timing example : R L = 3, tMRR = 2 .......................................................... 53

6.4.20.2 Fig ur e of LPDDR2 Read to MRR timing example : RL = 3, tMRR = 2 ...................................................... 54

6.4.20.3 Fig ur e of LPDDR2 : Burst W r i te Followed by MRR : RL = 3, WL = 1, BL = 4 ........................................... 54

6.4.21 Temperature Sensor .......................................................................................................................... 55

6.4.21.1 Fig ur e of Temp Sensor Timing ................................................................................................................. 56

6.4.21.2 DQ C al ibration .......................................................................................................................................... 56

6.4.21.3 Fig ur e of MR32 and MR40 DQ Calibration timing example: RL = 3, tMR R = 2 ........................................ 57

6.4.22 Mode Register Write Comm and ......................................................................................................... 58

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 4 - Revision : P01-004A

6.4.22.1 Fig ur e of Mode Register Write timing example : R L = 3, tMRW = 5 ......................................................... 58

6.4.22.2 Truth Table for Mode Regis ter Read (MRR) and M ode Register Write ( MRW) ........................................ 58

6.4.23 Mode Regi st er Write Reset (MR W Reset) ......................................................................................... 59

6.4.24 Mode Regi st er Write ZQ Calibration Command ................................................................................ 59

6.4.24.1 Fig ur e of ZQ Calibration Initialization timing example ............................................................................... 60

6.4.24.2 Fig ur e of ZQ Calibration S hort timing example ......................................................................................... 60

6.4.24.3 Fig ur e of ZQ Calibration Long timing exampl e ......................................................................................... 61

6.4.24.4 Fig ur e of ZQ Calibration Reset timing example ........................................................................................ 61

6.4.25 ZQ External Resistor Value, Tolerance, and Capacit i ve Loading...................................................... 62

6.4.26 Power-down ....................................................................................................................................... 62

6.4.26.1 Fig ur e of LPDDR2-S4 : Basic power down entry and exit timing diagram ................................................ 62

6.4.26.2 Fig ur e of Example of CKE intensive environme nt .................................................................................... 63

6.4.26.3 Fig ur e of Refresh to Refresh timing with CKE intensive environment for LPDR2 SDR A M ....................... 63

6.4.26.4 Fig ur e of Read to power – down entry ...................................................................................................... 64

6.4.26.5 Fig ur e of LPDDR2 SDRAM Rea d with auto precharge to power-do wn entry ........................................... 64

6.4.26.6 Fig ur e of Write to power-down entry ......................................................................................................... 65

6.4.26.7 Fig ur e of LPDDR2-S4: Write with autoprecharge to power-down entr y .................................................... 65

6.4.26.8 Fig ur e of LPDDR2-S4 Refresh command to power -down entry ............................................................... 66

6.4.26.9 Fig ur e of Activate command to power-down entry ................................................................................... 66

6.4.26.10 Fi gure of Precharge/Precharge-all command to power-d o wn entr y ..................................................... 66

6.4.26.11 Fi gure of Mode Register R ead to power-do wn entr y .............................................................................. 67

6.4.26.12 Fi gure of MRW command to power-down entry ..................................................................................... 67

6.4.27 LPDDR2-S4: Deep Power-Down ....................................................................................................... 67

6.4.27.1 Fig ur e of LPDDR2-S4 Deep power down entry and e xit timing diagram .................................................. 68

6.4.28 Input clock stop and frequency ch ange ............................................................................................. 68

6.4.29 No Operati on command ..................................................................................................................... 69

6.4.30 Truth tabl es ........................................................................................................................................ 69

6.4.31 Command truth table .......................................................................................................................... 70

6.4.32 LPDDR2-SDRAM Truth Tables ......................................................................................................... 71

6.4.32.1 Tabl e of LPDDR2-S4 : CKE Table............................................................................................................ 71

6.4.32.2 Tabl e of Current State Bank n - Command to Bank n .............................................................................. 72

6.4.32.3 Tabl eof Current State Bank n - Command to Bank m .............................................................................. 74

6.4.33 Data mask truth table ......................................................................................................................... 75

7. ELECTRICAL CHA RACTERISTIC ........................................................................................ 76

7.1 Absolute Maximum DC Ratings ...................................................................................................... 76

7.2 AC & DC operating conditions ........................................................................................................ 76

7.2.1 Recommended DC Operating Condit i ons ............................................................................................ 76

7.2.1.1 Recom mended DC Operating Conditions .................................................................................................. 76

7.2.2 Input Leakage Current ......................................................................................................................... 77

7.2.3 Operating Temperature Conditio ns ...................................................................................................... 77

7.2.4 AC and DC Input Measurement Levels ............................................................................................... 77

7.2.4.1 AC and DC Logic Input Levels for Single-Ended Signals ........................................................................... 77

7.2.4.1.1 Table of Single-Ended AC and DC Input Levels for CA and CS_n Inputs............................................................. 77

7.2.4.1.2 Table of Single-Ended AC and DC Input Levels for CKE ...................................................................................... 78

7.2.4.1.3 Table of Single-Ended AC and DC Input Levels for DQ and DM .......................................................................... 78

7.2.4.2 Vref Tolerances .......................................................................................................................................... 78

7.2.4.2.1 Figure of Illustration of VRef(DC) tolerance and VRef ac-noise limits ................................................................... 79

7.2.4.3 Input S ignal ................................................................................................................................................ 80

7.2.4.3.1 LPDDR2-466 to LPDDR2-1066 Input Signal ......................................................................................................... 80

7.2.4.3.2 LPDDR2-200 to LPDDR2-400 Input Signal ........................................................................................................... 81

7.2.4.4 AC and DC Logic Input Levels for Differential Signals................................................................................ 82

7.2.4.4.1 Differential signal definition .................................................................................................................................... 82

7.2.4.4.2 Differential swing requirements for clock and strobe ............................................................................................. 82

7.2.4.5 Single-ended requirement s for differential signals ...................................................................................... 83

7.2.4.6 Differential Input Cross Point Voltage ......................................................................................................... 84

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 5 - Revision : P01-004A

7.2.4.7 Slew Rate Definitions f or Single-Ended Input Si gnals ................................................................................ 85

7.2.4.8 Slew Rate Definitions f or D ifferential Input Signals .................................................................................... 85

7.2.5 AC and DC Output Measurement Levels ............................................................................................. 86

7.2.5.1 Single Ended AC and DC Output Levels .................................................................................................... 86

7.2.5.2 Differential AC and DC Output Levels ........................................................................................................ 86

7.2.5.3 Single Ended Output Slew Rate ................................................................................................................. 86

7.2.5.4 Differential Output Sl ew Rate ..................................................................................................................... 88

7.2.5.5 Overs hoot and Undershoot Specifications ................................................................................................. 89

7.2.6 Output buffer characteristics ................................................................................................................ 90

7.2.6.1 HSUL_12 Driver Output Timing Reference Load ....................................................................................... 90

7.2.6.2 RONP U and R ONPD Resistor Def inition .................................................................................................... 90

7.2.6.3 RONPU and RONPD Characteristics with ZQ Cal ibration .......................................................................... 91

7.2.6.3.1 Output Driver Temperature and Voltage Sensitivity .............................................................................................. 91

7.2.6.4 RONPU and RONPD Characteristics without ZQ Calibration ..................................................................... 92

7.2.6.5 RZQ I-V Curve ............................................................................................................................................ 93

7.2.7 Input/Ouput Capacitance ..................................................................................................................... 95

7.3 IDD Specification Parameters and Test Conditions ........................................................................ 96

7.3.1 IDD Measurement Conditions .............................................................................................................. 96

7.3.1.1 Tabl e of Definition of S witching for CA Input Signals ................................................................................. 96

7.3.1.2 Tabl e of Definition of Switching for IDD4R ................................................................................................. 97

7.3.1.3 Tabl e of Definition of Switching for IDD4W ................................................................................................. 97

7.3.2 IDD Specifications ................................................................................................................................ 98

7.3.2.1 Tabl e of LPDDR2 IDD Specification Parameter s and Operating Conditions (x32) ................................ 98

7.3.2.2 Tabl e of IDD6 Partial Ar ray Self-Refresh Current ..................................................................................... 100

7.4 Clock Specification ........................................................................................................................ 100

7.4.1 Definition for tCK(avg) and nCK ......................................................................................................... 100

7.4.2 Definition for tCK(abs) ........................................................................................................................ 100

7.4.3 Definition for tCH(avg) and tCL (av g) .................................................................................................. 101

7.4.4 Definition for tJIT(per) ........................................................................................................................ 101

7.4.5 Definition for tJIT(cc) .......................................................................................................................... 101

7.4.6 Definition for tERR(nper) .................................................................................................................... 101

7.4.7 Definition for duty cycle jitter tJIT(duty) .............................................................................................. 102

7.4.8 Definition for tCK(abs), tCH(abs) and tCL(abs) ................................................................................. 102

7.4.9 Period Clock Jitter .............................................................................................................................. 102

7.4.9.1 Clock period jitter effects on core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS,

tRRD, tFAW ) ....................................................................................................................................................... 102

7.4.9.2 Cycle t ime de-rating for c ore timing parameters ....................................................................................... 102

7.4.9.3 Clock Cycle de-rating for core timing parameters ..................................................................................... 103

7.4.9.4 Clock jitter effects on C/A timing (tIS,tIH,tISCKE,tIHCKE,tISb, tIHb, tISCKEb, tIHCKEb) ........................ 103

7.4.9.5 Clock jitter effect s on Rea d timing tRPRE ................................................................................................ 103

7.4.9.6 Clock jitter effects on Read timing tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) ............................ 103

7.4.9.7 Clock jitter effect s on Rea d timing parameters tQSH, tQSL ..................................................................... 103

7.4.9.8 Clock jitter effect s on Rea d timing parameters tRPST.............................................................................. 104

7.4.9.9 Clock jitter effect s on Wr i te timing parameters t DS, tDH .......................................................................... 104

7.4.9.10 Clock jitter effect s on Write timing paramet er s tDSS, tDSH ................................................................... 104

7.4.9.11 Clock jitter effect s on Write timing paramet er s tDQSS ........................................................................... 104

7.5 Refresh Requirements .................................................................................................................. 105

7.5.1 LPDDR2-S4 Refresh Requirement Parameters ................................................................................ 105

7.6 AC Timings ................................................................................................................................... 106

7.6.1 Table of LPDDR2 AC Timing ............................................................................................................. 106

7.6.2 CA and CS_n Setup, Hold and Der ating ............................................................................................ 114

7.6.2.1 Tabl e of CA and CS_n Setup and Hold Base-Values for 1V/ns ............................................................... 115

7.6.2.2 Tabl e of Derating values LPDDR2 tIS/tIH - ac/dc based AC220 ............................................................ 115

7.6.2.3 Tabl e of Derating values LPDDR2 tIS/tIH - ac/dc based AC300 .............................................................. 116

7.6.2.4 Tabl e of Required time t VAC above VIH(ac) {below VIL(ac)} for valid transition ...................................... 116

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 6 - Revision : P01-004A

7.6.2.5 Figure of nominal slew rate and tVAC for tIS for CA and C S _n with respect to clock. ............................. 117

7.6.2.6 Figure of nominal slew rate for hold time tIH for C A and CS_n with respect to clock ............................... 118

7.6.2.7 Figure of tangent line for s etup time tIS for CA and CS _n with respect to clock ....................................... 119

7.6.2.8 Figure of tangent line for for hold time tIH for CA and CS_n with respect to clock ................................... 120

7.6.3 Data Set up, Hold and Slew Rate D erat i ng ......................................................................................... 121

7.6.3.1 Tabl e of Data Setup and Hold B ase-Values ............................................................................................. 121

7.6.3.2 Tabl e of Derating values LPDDR2 tDS/tDH - ac/dc based AC220 ........................................................... 122

7.6.3.3 Tabl e of Derating values LPDDR2 tDS/tDH - ac/dc based AC300 ........................................................... 122

7.6.3.4 Tabl e of Required time t VAC above VIH(ac) {below VIL(ac)} for valid transition ...................................... 123

7.6.3.5 Figure of nominal slew rate and tVAC for setup tim e tDS for DQ with respect to strobe .......................... 124

7.6.3.6 Figure of nominal slew rate for hold time tDH for DQ with respect to strobe ............................................ 125

7.6.3.7 Figure of tangent line for s etup time tDS for DQ with r espect to strobe .................................................... 126

7.6.3.8 Figure of tangent line for for hold time tDH for DQ with respect to strobe ................................................ 127

8. REVISION HI STORY ............................................................................................................ 128

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 7 - Revision : P01-004A

4. PIN DESCRIPTIO N

4.1 Signal Description

Name

Type

Description

CK_t, CK_c Input

Clock: CK_t and CK_c are differential clock inputs. All D ouble Data Rate (DDR) CA inputs are sampled

on both positive and negative edge of CK_t. Single Data Rate (SDR) inputs, CS_n and CKE, are sampled

at the positive Clock edge.

Clock is defined as the differential pair, CK_t and CK_c. The positive Clock edge is defined by the

crosspoint of a rising CK_t and a falling CK_c. The negative Clock edge is defined by the crosspoint of a

falling CK_t and a rising CK_c.

CKE Input Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device

input buffers and output drivers. Power savings modes are entered and exited through CKE

transitions.CKE is considered part of the command code. CKE is sampled at the positive Clock edge.

CS_n Input Chip Select: CS_n is considered part of the command code and CS_n is sampled at the positive Clock

edge.

CA[n:0] Input DDR Command /Addre ss Inputs:

Uni-directional command/address bus inputs.

CA is considered part of the command code.

DQ[n:0] I/O Data Inputs/Output: Bi-directional data bus. n=15 for 16 bits DQ; n=31 for 32 bits DQ.

DQSn_t,

DQSn_c

I/O

Data Strobe (Bi-directional, Differential):

The data s trobe i s bi-directi onal (us ed for read and wri te data) and differential (DQS_t and DQS_c ). It is

output with read data and input with write data. DQS_t is edge-aligned to read data and centered with

write data.

For x32 DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7, DQS1_t and

DQS1_c to the data on DQ8 - DQ15, DQS2_t and DQS2_c to the data on DQ16 - DQ23,

DQS3_t and DQS3_c to the data on DQ24 - DQ31.

DMn

Input

Input Data Mask:

DM is the input mask signal for write data. Input data is masked when DM is sampled HIGH coincident

with that input data during a Write access. DM is sampled on both edges of DQS_t. Although DM is for

input only, the DM loading shall match the DQ and DQS (or DQS_c).

DM0 is the input data mask signal for the data on DQ0-7.

For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is

the inpu t data mask s igna l for th e dat a on DQ24 -31.

DD1

Supply Core Power S upply 1: Power supply for core.

DD2

Supply Core Power S upply 2: Power supply for core.

DDCA

Supply

Input Rece iv er P ower Supply:

Power supply for CA[n:0], CKE, CS_n, CK_t, and CK_c input buffers.

DDQ

Supply I/O Power Supply: Power supply for Data input/output buffers.

REF(CA)

Supply Reference Voltage for CA Command and Control Input Receiver: Reference voltage for all

CA[n:0], CKE, CS_n, CK_t, and CK_c input buffers.

REF(DQ)

Supply Reference Voltage for DQ Input Receiver: Reference voltage for all DQ input buffers:

Referen ce vo lta ge for all Data input buffers.

Supply Ground

SSCA

Supply Ground for CA Input Receivers

SSQ

Supply I/O Ground

I/O

Reference Pin for Output Drive Strength Calibration

TQ (option) Output

Temperature sensor output: Asynchronous, HSUL_12 level output. It is logic-HIGH when

device temperature equals or exceeds 85°C. It is logic-LOW when device temperature is

less than 85°C.The drive strength is s ame as DQ (40 ohm).

GOHIZ

(option) Input

Asynchronous, HSUL_12 level input. When logic High, all outputs of device are in Hi-Z

state, when Low, device is in normal operation. When GOHIZ pad transitions from Low to

High, all outputs will enter Hi-z within tgo-hiz. When GOHIZ pad transitions from High to

Low, all output s will ret urn to normal funct io n withi n te xit -hiz . The tgo-hiz and texit-hiz ar e to

be defined. I nternal pulld own is impl emented. E -fuse option is pr ovided to chan ge GOHIZ ’s

polarity(from active HIGH t o active Low).

Note : Data includes DQ and DM.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 8 - Revision : P01-004A

4.2 Addressing T abl e

Density 1Gb

Number of Banks 8

Bank Addresses BA0-BA2

tREFI(us) (*2) 7.8

X32 Row Addresses R0-R12

Column Addresse s*1 C0-C8

Note 1.The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero.

2. tREFI values for all bank refresh is Tj = -40~85°C.

3. Row and Column Address values on the CA bus that are not used are “don’t care.”

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 9 - Revision : P01-004A

5. BLOCK DIAGRAM

CK_c

CKE

CA0

CLOCK

BUFFER

COMMAND

DECODER

ADDRESS

BUFFER

REFRESH

COUNTER COLUMN

COUNTER

CONTROL

SIGNAL

GENERATOR

MODE

COLUMN DECODER

SENSE AMPLIFIER

CELL ARRAY

BANK #0

DATA CONTROL

CIRCUIT DQ

BUFFER

DQ , DQS_t ,

DQS_c

CK_t

CA9

BANK #7

Power

GND

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 10 - Revision : P01-004A

6. FUNCTIONAL DE SCRIPTION

LPDDR2-S4 devices use a double data rate architecture on the DQ pins to achieve highspeed operation. The

double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data

bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR2-S4 effectively consists

of a single 4n-bit-wide, one-clock-cycle data transfer at the internal SDRAM core and four corresponding n-bit-wide,

one-half-clock-cycle data transfer s at the I/O pins.

Read and write accesses are burst oriented; accesses start at a selected location and continue for a programmed

number of locations i n a programmed sequence.

Prior to normal operation, the LPDDR2 device must be initialized. The following section provides detailed

information covering device i ni tialization, register def inition, command description and device operation.

6.1 Simplified LPDDR2 State Diagram

LPDDR2-SDRAM state diagram provides a simplified illustration of allowed state transitions and the related

commands to control them. For a complete definition of the device behavior, the information provided by the state

diagram should be i ntegrated with the truth tables and timing speci fication.

The truth tables provide complementary information to the state diagram, they clarify the device behavior and the

applied restrict ions when considering t he actual state of all the banks.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 11 - Revision : P01-004A

6.1.1 Figure of Simplified LPDDR2 Bus Interface State Di agram

Precharging

Writing

With

Autoprecharge

Reading

With

Autoprecharge

ReadingWriting

Active*1

Active

Power

Down

Active

Reading

Writing

Idle

Power

Down

Idle

Reading

Resetting

Refreshing

Self

Refreshing

Deep

Power

Down

Power

Resetting

Reading

Resetting

Power

Down

Automatic Sequence

Command Sequence

Power

Applied

Reset

MRR

PDX

BST

WRA

PDX

Reset

DPDX

MRR

MRW

MRR

PDX

RD RD

BST

DPD

SREF

SREFX

REF

ACT

RDA

PR,PRA

PR(A)=Precharge (All)

ACT=Activate

WR(A)=Write(with Autoprecharge)

RD(A)=Read (with Autoprecharge)

BST=Burst Terminate

Reset=Reset is achieved through MRW command

MRW=Mode Register Write

MRR=Mode Register Read

PD=Enter Power Down

PDX=Exit Power Down

SREF=Enter Self Refresh

SREFX=Exit Self Refresh

DPD=Enter Deep Power Down

DPDX=Exit Deep Power Down

REF=Refresh

PR,PRA

Note : For LPDDR2-SDRAM in the Idle state, all banks are precharged

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 12 - Revision : P01-004A

6.2 Power-up, Initialization, and Power-Off

The LPDDR2 Devices must be powered up and initialized in a predefined manner. Operational procedures other

than those specified m ay result in undefi ned operation.

6.2.1 Power Ramp and Device I ni tialization

The following sequence shall be used to power up an LPDDR2 device. Unless specified otherwise, these s teps are

mandatory.

1. Power Ramp

While applying power (after Ta), CKE shall be held at a logic low level (=<0.2xVDDCA), all other inputs shall be

between VILmin and VIHmax. The LPDDR2 device will only guarantee that outputs are in a high impedance state

while CKE is held low.

On or before the completion of the powe r ramp (Tb) CKE must be held low.

DQ, DM, DQS_t and DQS_c voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid

latchup. CK_t, CK_c, CS_n, and CA input levels must be between VSSCA and VDDCA during voltage ramp to

avoid latch-up.

The following condit ions apply:

Ta is the point where any power supply first reaches 300mV.

After Ta is reached, VDD1 must be greater than VDD2 - 200mV.

After Ta is reached, VDD1 and VDD2 m ust be greater than VDDCA - 200mV.

After Ta is reached, VDD1 and VDD2 must be greater than VD DQ - 200mV.

After Ta is reached, VREF must always be less than all other s upply voltages.

The voltage difference between any of VSS, VSSQ, and VSSCA pins may not exceed 100m V .

The above conditi ons apply between Ta and power-off (controlled or uncontrolled).

Tb is the point when all supply voltages are within their respective min/max operating conditions. Reference

voltages shall be within their respective min/max operating condit ions a minimum of 5 clocks before CKE goes high.

Power ramp duratio n tINIT0 (Tb - Ta) must be no greater than 20 ms.

2. CKE and clock

Beginning at Tb, CKE must remain low for at least tINIT1 = 100 ns, after which it may be asserted high. Clock must

be stable at least tINIT2 = 5 x tCK prior to the first low to high transition of CKE (Tc). CKE, CS_n and CA inputs

must observe setup and hold time (tIS, tIH) requirements with respect to the first rising clock edge (as well as to the

subsequent fall i ng and rising edges).

The clock period shall be within the range defined for tCKb (18 ns to 100 ns), if any Mode Register Reads are

performed. Mode Register Writes can be sent at normal clock operating frequencies so long as all AC Timings are

met. Furthermore, some AC parameters (e.g. tDQSCK) may have relaxed timings (e.g. tDQSCKb) before the

system is approp riately configured.

While keeping CKE high, issue NOP command s f or at least tINIT3 = 200 us. (Td).

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 13 - Revision : P01-004A

3. Reset command

After tINIT3 is s atisfied, a MRW(Reset) command shall be issued (Td). The memory controller may optionally issue

a Precharge-All command prior to the MRW Reset command. Wait for at least tINIT4 = 1 μs while keeping CKE

asserted and issuing NOP commands.

4. Mode Registers Reads and Device Aut o-Initialization (DAI ) poll ing:

After tINIT4 is satisfied (Te) only MRR commands and power-down entry/exit commands are allowed. Therefore,

after Te, CKE may go low i n accordance to Power-Down ent ry and exit specification.

The MRR command may be used to poll the DAI-bit to acknowledge when Device Auto-Initialization is complete or

the memory controller shall wait a mi ni mum of tINIT5 before proceeding.

As the memory output buffers are not properly configured yet, some AC parameters may have relaxed timings

before the system is appropriately conf i gured.

After the DAI-bit (MR#0, “DAI”) is set to zero “DAI complete“ by the memory device, the device is in idle state (Tf).

The state of the DAI st atus bit can be determi ned by an MRR command to MR#0.

The LPDDR2 SDRAM device will set the DAI-bit no later than tINIT5 (10 us) after the Reset command. The memory

controller shall wait a minimum of tINIT5 or until the DAI-bit is set before proceeding.

After the DAI-Bit is set, it is recommended to determine the device type and other device characteristics by issuing

MRR commands (M R0 “Device Information” etc.).

5. ZQ Calibrati on:

After tINIT5 (Tf), an MRW ZQ Initialization Calibration command may be issued to the memory. This command is

used to calibrate the LPDDR2 output drivers (RON) over process, voltage, and temperature variations. Optionally,

the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connection. In systems in

which more than one LPDDR2 device exists on the same bus, the controller must not overlap ZQ Calibration

commands. The device is ready for normal operation after tZQINIT.

6. Normal Operati on:

After tZQINIT (Tg), MRW commands may be used to properly configure the memory, for example the out put buffer

driver strength, latencies etc. Specifically, MR1, MR2, and MR3 shall be set to configure the memory for the target

frequency and memory configuration. The LPDDR2 device will now be in IDLE state and ready for any valid

command.

After Tg, the clock frequency may be changed according to t he clock frequency change procedure.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 14 - Revision : P01-004A

6.2.2 Timing Parameters for initialization

Symbol Value Unit Comment

min max

tINIT0

Maximum Power Ramp Time

tINIT1

100

Minimum CKE low t i m e after completion of power ramp

tINIT2

tCK

Minimum stable clock before first CKE high

tINIT3

200

μs

Minimum Idle time after first CKE assertion

tINIT4

μs

Minimum Idle time after Reset command

tINIT5

μs

Maximum duration of Dev ice Auto-Initialization

tZQINIT

μs

ZQ Initial Cali bration for LPDDR2-S4

tCKb

100

Clock cycle tim e during boot

6.2.3 Figure of Power Ramp and Initialization Seq uence

*Midlevel on CA bus means : valid NOP

INIT2

INIT3

INIT1

INIT0

INIT4

ISCKE

INIT5

Ta Tb Tc Tg

TeTd

RESET

ZQC Valid

CK_t / CK_c

Supplies

CKE

CA*

MRR

ZQINIT

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 15 - Revision : P01-004A

6.2.4 Initialization af ter Reset (without Po wer ramp)

If the RESET command is issued outside the power up initialization sequence, the reinitialization procedure shall

begin with step 3 (Td).

6.2.5 Power-off S equence

The following sequ ence shall be used to power off the LPDDR2 device.

While removing power, CKE shall be held at a logic low level (=< 0.2 x VDDCA), all other inputs shall be between

VILmin and VIHmax. The LPDDR2 device will only guarantee that outputs are in a high impedance state while CKE

is held low.

DQ, DM, DQS_t and DQS_c voltage levels must be between VSSQ and VDDQ during power off sequence to avoid

latch-up. CK_t, CK_c, CS_n and CA input levels must be between VSSCA and VDDCA during power off sequence

to avoid latch-up.

Tx is the point where any power supply decreases under its minimum value specified in the DC operating condition

table.

Tz is the point where all power supplies are below 300 mV. Af ter Tz, the device is powered of f.

The time between Tx and Tz (tPOFF) shall be less than 2s.

The following conditi ons apply:

Between Tx and Tz, VDD1 must be great er than VDD2 - 200 mV.

Between Tx and Tz, VDD1 and VDD2 must be greater than VDDCA - 200 mV.

Between Tx and Tz, VDD1 and VDD2 must be greater than VDDQ - 200 mV .

Between Tx and Tz, VREF must always be l ess than all other supply voltages.

The voltage difference between any of VSS, VSSQ, and VSSCA pins may not exceed 100 m V .

6.2.6 Timing Parameter s Power-Off

Symbol Value Unit Comment

min max

tPOFF

Maximum Power-Off Ramp Time

6.2.7 Uncontrolled Power -Off Sequence

The following sequ ence shall be used to power off the LPDDR2 device under uncontrolled condition.

Tx is the point where any power supply decreases under its minimum value specified in the DC operating condition

table. After turning off all power supplies, any power supply current capacity must be zero, except for any static

charge remaining in the system.

Tz is the point where all power supply first reaches 300 mV. After Tz, the device is powered of f.

The time between Tx and Tz shall be less than 2s. The relative level between supply voltages are uncontrolled

during this period.

VDD1 and VDD2 sh al l decrease with a slope lo wer than 0.5 V/us betwe en Tx and Tz.

Uncontrolled pow er off sequence can be appli ed only up to 400 times in t he l ife of the device.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 16 - Revision : P01-004A

6.3 Mode Register Definition

6.3.1 Mode Register Assig nm ent and Definition

Each register is denoted as “R” if it can be read but not written, “W” if it can be written but not read, and “R/W” if it

can be read and writ ten.

Mode Register Read command shall be used to read a register. Mode Register Write command shall be used to

write a register.

6.3.1.1 Table of Mode Register Assignment

MR# MA[7:0] Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Link

0 00

Device Info. R (RFU) RZQI

DNVI

DI DAI go to MR0

1 01

Device Feature 1 W nWR (for AP) WC BT BL go to MR1

2 02

Device Feature 2 W (RFU) RL & WL go to MR2

3 03

I/O Config-1 W (RFU) DS go to MR3

4 04

Refresh Rate R TUF (RFU) Refresh Rate go to MR4

5 05

Basic Config-1 R LPDDR2 Manufacturer ID go to MR5

6 06

Basic Config-2 R Revision ID1 go to MR6

7 07

Basic Config-3 R Revision ID2 go to MR7

8 08

Basic Config-4 R I/O width Density Type go to MR8

9 09

Test Mode W Vendor-Specific Test Mode go to MR9

10 0A

I/O Calibration W Calibration Code go to MR10

11-15 0B

~0F

(reserved) - (RFU)

16 10

PASR_Bank W Bank Mask go to MR16

PASR_Seg

Segment Mask

go to MR17

18-19

12H

~13

(Reserved) - (RFU)

20-31 14h–1Fh Reserved f or NVM

32 20H DQ Calibrat ion

Pattern A

R See “DQ Calibration” go to MR32

33-39

21H

~27

(Do Not Use) -

40 28H DQ Calibrat ion

Pattern B

R See “DQ Calibration” go to MR40

41-47

29H

~2F

(Do Not Use) -

48-62

30H

~3E

(Reserved)

(RFU)

63 3FH Reset W X go to MR63

64-126

40H

~7E

(Reserved)

(RFU)

127 7FH ( Do N ot Use) -

128-190

80H

~BE

(Reserved for

Vendor Use)

- (RFU)

191 BFH (Do Not Use) -

192-254

C0H

~FE

(Reserved for

Vendor Use)

- (RFU)

255 FFH (Do Not Us e) -

Note 1. RFU bits shall be set to ‘0’ during Mode Register writes.

2. RFU bits shall be read as ‘0’ during Mode Register reads.

3. All Mode Registers that are specified as RFU or write-only shall return undefined data when read and DQS shall be toggled.

4. All Mode Registers that are specified as RFU shall not be written.

5. Writes to read-only registers shall have no impact on the functionality of the device.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 17 - Revision : P01-004A

6.3.2 MR0_Device Information (MA[7:0] = 00H)

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

(RFU) RZQI

DNVI

DI DAI

DAI (Device Auto-Initialization Status) Read-only OP0 0

: DAI complete

: DAI still in progress

DI (Device Information) Read-only OP1 0

: SDRAM

: NVM

DNVI (Data Not Valid Information) Read-only OP2 LPDDR2 SDRAM will not implement DNV functionalit

RZQI (Built in Self Test for RZQ

Information) Read-only OP[4:3]

00b: RZQ self test not executed.

01b: ZQ-pin may connect to VDDCA or float

10b: ZQ-pin may short to GND

11b: ZQ-pin self test completed, no error condition detected

(ZQ-pin m ay not conne ct to VDDCA or float nor short to GND)

Note 1. RZQI will be set upon completion of the MRW ZQ Initialization Calibration command.

2.If ZQ is connected to VDDCA to set default calibration, OP[4:3] s hall be set to 01. If ZQ is not connec ted to VDDCA, either OP [4:3]=01 or

OP[4:3]=10 might indicate a ZQ-pin assembly error. It is recommended that the assembly error is corrected.

3. In the case of possible assembly error (either OP[4:3]=01 or OP[4:3]=10 per Note 4), the LPDDR2 device

will default to factory trim settings for RON, and will ignore ZQ calibration commands. In either case, the system may not function as

intended.

4. In the case of the ZQ self-test returning a value of 11b, this result indicates that the device has detected a

resistor connection to the ZQ pin. However, this res ult cannot be used to validate the Z Q resistor value or that the ZQ resi stor tolerance

meets the specified limits (i.e. 240-ohm +/-1%).

6.3.3 MR1_Device Featu re 1 (MA[7:0] = 01H)

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

nWR (for AP) WC BT BL

BL Write-only OP[2:0]

010

: BL4 (default)

011

: BL8

100

: BL16

All others: reserved

BT Write-only OP3 0

: Sequential (default)

: Interleaved

WC Write-only OP4 0

: Wrap (default)

: No wrap (allowed for SDRAM BL4 only)

nWR Write-only OP[7:5]

001

nWR=3 (default)

010

: nWR=4

011b: nWR=5

100

: nWR=6

101

: nWR=7

110

: nWR=8

All others: reserved

Note 1. Programmed val ue in nWR register is the number of clock cycles which determines when to start internal precharge operation for a write

burst with AP enabled. It is determined by RU(tWR/tCK).

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 18 - Revision : P01-004A

6.3.3.1 1 Table of Burst Sequence by Burst Length (BL), Burst Type (BT), and Warp Control (WC)

C3 C2 C1 C0 WC BT BL Burst Cycle Number and Burst Address Sequence

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

X X 0

wrap any 4

0 1 2 3

X X 1

2 3 0 1

X X X 0

nw any y y+1 y+2 y+3

X 0

wrap

seq

0 1 2 3 4 5 6 7

X 0

2 3 4 5 6 7 0 1

X 1

4 5 6 7 0 1 2 3

X 1

6 7 0 1 2 3 4 5

X 0

int

0 1 2 3 4 5 6 7

X 0

2 3 0 1 6 7 4 5

X 1

4 5 6 7 0 1 2 3

X 1

6 7 4 5 2 3 0 1

X X X 0

nw any illegal (not allowed)

wrap seq

0 1 2 3 4 5 6 7 8 9 A B C D E F

2 3 4 5 6 7 8 9 A B C D E F 0 1

4 5 6 7 8 9 A B C D E F 0 1 2 3

6 7 8 9 A B C D E F 0 1 2 3 4 5

8 9 A B C D E F 0 1 2 3 4 5 6 7

A B C D E F 0 1 2 3 4 5 6 7 8 9

C D E F 0 1 2 3 4 5 6 7 8 9 A B

E F 0 1 2 3 4 5 6 7 8 9 A B C D

X X X 0

int illegal (not allowed)

X X X 0

nw any illegal (not allowed)

Note:1. C0 input is not present on CA bus. It is implied zero.

2. For BL=4, the burst address represents C[1: 0].

3. For BL=8, the burst address represents C[2:0].

4. For BL=16, the burst address represents C[3:0].

5. For no-wrap (nw), BL4, the burst shall not cross the page boundar y and shall not cross sub-page boundary. The variable y may start at

any address with C0 equal to 0 and may not start at any address in table below for the respective density and bus width combinations.

6.3.3.2 Table of Non Wrap Re s trictions

Bus Width

1Gb

Not across full page boundary

x32

1FE, 1FF, 000, 001

Not across sub page boundary

X32

None

Note : Non-wrap BL=4 data-orders shown above are prohibited.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 19 - Revision : P01-004A

6.3.4 MR2_Device Featu re 2 (MA[7:0] = 02H)

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

(RFU) RL & WL

RL & WL Write-only OP[3:0]

0001b: RL = 3 / WL = 1 (default)

0010b: RL = 4 / WL = 2

0011b: RL = 5 / WL = 2

0100b: RL = 6 / WL = 3

0101b: RL = 7 / WL = 4

0110b: RL = 8 / WL = 4

All others: reserv ed

6.3.5 MR3_I/O Configuration 1 (MA[7:0] = 03H)

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

(RFU) DS

DS Write-only OP[3:0]

0000

reserved

0001

: 3

4.3

-ohm typical

0010

: 40-ohm typical (default)

0011

: 4

-ohm typical

0100

-ohm typical

0101

: reserved for

68.6

-ohm typical

0110

-ohm typical

0111

120

-ohm typical

All others: reserved

6.3.6 MR4_Device Temperature (MA[7:0] = 04H )

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

TUF (RFU) SDRAM Refresh Rate

SDRAM

Refresh Rate Read-only OP[2:0]

000

: SDRAM Low temperature operating limit exceeded

001b: 4x tREFI, 4x t REFIpb, 4x tREFW

010

: 2x tREFI, 2x tREFIpb, 2x tREFW

011

: 1x tREFI, 1x tREFIpb, 1x tREFW (<=85°C)

100

: Reserved

101

: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW, do not de-rate

SDRAM AC timing

110

: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW, de-rate

SDRAM AC timing

111

: SDRAM High temperature operating limit exceeded

Temperature

Update Flag (TUF) Read-only OP7

: OP[2:0] value has not changed since last read of MR4 .

: OP[2:0] value has changed since last read of MR4.

Note 1. A Mode Register Read from MR4 will reset OP7 to ‘0’.

2. OP7 is reset to ‘0’ at power-up

3. If OP2 equals ‘1’, the device temperature is greater than 85’C

4. OP7 is set to ‘1’ if OP2:OP0 has changed at any time since the last read of MR4.

5. LPDDR2 might not operate properly when OP[2:0] = 000b or 111b.

6. LPDDR2 devices must be derated by adding 1.875ns to the following core timing parameters: tRCD, tRC, tRAS, tRP, and

tRRD. tDQSCK shall be de-rated accordi ng to the tDQSCK de-rating value in AC timi ng table. Prevailing clock frequenc y spec

and related setup and hold timings shall remain unchanged.

7. The recommended frequency for reading MR4 is provided in Temperature Sensor

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 20 - Revision : P01-004A

6.3.7 MR5_Basic Configuration 1 (MA[7:0] = 05H)

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

LPDDR2 Manufacturer ID

LPDDR2 Manufacturer ID Read-only OP[7:0] 0000 1000b : Winbond

6.3.8 MR6_Basic Configuration 2 (MA[7:0] = 06H)

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

Revision ID1

Revision ID1 Read-only OP[7:0] 00000000

: A-version

6.3.9 MR7_Basic Configuration 3 (MA[7:0] = 07H)

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

Revision ID2

Revision ID2 Read-only OP[7:0] 00000000

: A-version

6.3.10 MR8_Basic Configurati on 4 (MA[7:0] = 08H)

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

I/O width Density Type

Type Read-only OP[1:0] 00

: S4 SDRAM

Density Read-only OP[5:2] 0100

: 1Gb

I/O width Read-only OP[7:6] 00

: x32

6.3.11 MR9_Test Mode (MA[7:0] = 09H)

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

Vendor-specific Test Mode

6.3.12 MR10_Calibration (MA[7:0] = 0AH)

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

Calibration Code

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 21 - Revision : P01-004A

Calibration Code Write-only OP[7:0]

0xFF: Calibrat ion command after i nitialization

0xAB: Long calibration

0x56: Short ca libration

0xC3: ZQ Reset

others: Reserved

Note: 1. Host processor shall not write MR10 with “Reserved” values

2. LPDDR2 devices shall ignore calibration command when a “Reserved” value is written into MR10.

3. See AC timing table for the calibration latency.

4. If ZQ is c onnected to VSSCA through RZQ, eit her the ZQ calibr ation function or default calibration (through t he ZQreset comm and) is

supported. If ZQ is connected to VDDCA, the device operates with default calibration, and ZQ calibration commands are ignor ed. In

both cases, the ZQ connection shall not change after power is applied to the device.

5. Optionally, the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connec-tion.

6.3.13 MR16_PASR_Bank Mask (MA[7:0] = 10H)

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

S4 SDRAM Bank Mask (8-bank)

Bank [7:0] Mask Write-only OP[7:0] 0b: ref resh enable to the bank ( =unmasked, default )

1b: refresh blocked (=masked)

OP Bank Mask 8-Bank S4 SDRAM

0 XXXXXXX1 Bank 0

1 XXXXXX1X Bank 1

2 XXXXX1XX Bank 2

3 XXXX1XXX Bank 3

4 XXX1XXXX Bank 4

5 XX1XXXXX Bank 5

6 X1XXXXXX Bank 6

7 1XXXXXXX Bank 7

6.3.14 MR17_PASR_Seg m ent Mask (MA[7:0] = 11H)

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

Segment Mask

Segment [7:0] Mask Write-only OP[7:0] 0b: refre sh enable to the segment (=unmasked, default )

1b: refresh blocked (=masked)

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 22 - Revision : P01-004A

Segment

OP Segment Mask R[12:10]

0 0 XXXXXXX1 000b

1 1 XXXXXX1X 001b

2 2 XXXXX1XX 010b

3 3 XXXX1XXX 011b

4 4 XXX1XXXX 100b

5 5 XX1XXXXX 101b

6 6 X1XXXXXX 110b

7 7 1XXXXXXX 111b

6.3.15 MR32_DQ Calibrat ion Pattern A (MA[7:0] = 20H)

Reads to MR32 retu rn DQ Calibration Pat tern “A”. See “DQ Calibration”.

6.3.16 MR40_DQ Calibrat ion Pattern B (MA[7:0] = 28H)

Reads to MR40 retu rn DQ Calibration Pat tern “B”. See “DQ Calibration”.

6.3.17 MR63_Reset (MA[7:0] = 3FH): MRW only

OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

For additonal information on MRW RESET see “Mode Regi st er Write Command”.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 23 - Revision : P01-004A

6.4 Command Definitions and Timing Diagram

6.4.1 LPDDR2-S4: Activate Command .

The SDRAM Activate command is issued by holding CS_n LOW, CA0 LOW, and CA1 HIGH at the rising edge of

the clock. The bank addresses are used to select the desir ed bank. The row addresses are used to determine which

row to activate in the selected bank. The Activate command must be applied before any Read or Write operation

can be executed. The LPDDR2 SDRAM can accept a read or write command at time tRCD after the activate

command is sent. Once a bank has been activated it must be precharged before another Activate command can be

applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The

minimum time interval between successive Activate commands to the same bank is determined by the RAS cycle

time of the device (t RC). The minimum tim e i nterval between Activ ate commands to diff erent banks is tRRD.

Certain restrictions on operation of the 8-bank devices must be observed. There are two rules. One for restricting

the number of sequential Activate commands that can be issued and another for allowing more time for RAS

precharge for a Precharge All command. T he rules are as follows:

8-bank device Sequential Bank Activation Restriction : No more than 4 banks may be activated (or refreshed, in the

case of REFpb) in a rolling tFAW window. Converting to clocks is done by dividing tFAW[ns] by tCK[ns], and

rounding up to next integer value. As an example of the rolling window, if RU{ (tFAW / tCK) } is 10 clocks, and an

activate command is issued in clock N, no more than three further activate commands may be issued at or between

clock N+1 and N+9. REFpb also counts as bank-activation for the purposes of tFAW.

8-bank device Precharge All Allowance : tRP for a Precharge All command for an 8-bank device shall equal tRPab,

which is greater t han tRPpb.

6.4.1.1 Figure of LPDDR2-S4 : Activate c ommand cycle : tRCD=3,tRP=3,tRRD=2

T0 T1 T2 T3 Tn Tn+3Tn+2Tn+1

CK_t / CK_c

CA0-9

[Cmd] Activate Nop Activate Read

RAS-CAS delay=t

RCD

RAS-RAS delay time=tRRD Bank Precharge time=tRP

Bank Active=tRAS

Row Cycle time=tRC

Read Begins

Precharge Nop Nop Activate

Bank A

Row Addr Row Addr Bank B

Row Addr Row Addr Bank A

Col Addr Col Addr Bank A Bank A

Row Addr Row Addr

Note: A Precharge-All command uses tRPab timing, while a Single Bank Precharge command uses tRPpb timing. In this figure, tRP is used to

denote either an All-bank Precharge or a Single Bank Precharge

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 24 - Revision : P01-004A

6.4.1.2 Figure of LPDDR2-S4: tFAW timing

CA0-9

[Cmd]

CK_t / CK_c Tz+2

Tz+1

tRRD

tFAW

tRRD

Ty+2

Ty+1

TxTx+

Tm+

TmTn+Tn

Bank E Bank E

tRRD

Bank A Bank A Bank B Bank B Bank C Bank C Bank D Bank D

ACT NopNopNop NopACT

ACT

ACTACT

Note : tFAW is for 8-bank devices only.

6.4.1.3 Figure of LPDDR2 Command Input Setup and Hold Timing

Nop

CK_t / CK_c

CA0-9

[Cmd]

T1 T2 T3

CS_n

Command Nop Command

Rise

Fall

IL(AC)

IL(DC)

IH(AC)

IH(DC)

HIGH or LOW (but a defined logic level)

Note: Setup and hold conditions also apply to the CKE pin. See section related to power down for timing diagrams related to the CKE pin.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 25 - Revision : P01-004A

6.4.1.4 Figur e of LPDDR2 CKE Input S etup and Hold Timing

HIGH or LOW (but a defined logic level)

T0 T1 Tx Tx+1

CK_t / CK_c

CKE

tISCKE tISCKE

tIHCKE tIHCKE

VIHCKE

VILCKE VIHCKE

VILCKE

Note: 1.After CKE is registered LOW, CKE signal level shall be maintained below VILCKE for tCKE specification (LOW pulse width).

2.After CKE is registered HIGH, CKE signal level shall be maintained above VIHCKE for tCKE specification (HIGH pulse width)

6.4.2 LPDDR2-S4: Read and Write access modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting CS_n LOW,

CA0 HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this time to determine

whether the acces s cycle is a READ operation (CA2 HIGH) or a WRITE operation (CA2 LOW).

The LPDDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a

burst read or write operation on successive clock cycles.

For LPDDR2 -S4 devices, a new burst a ccess must not interrupt the previous 4-bit burst operation in case of B L = 4

setting. In case of BL = 8 and BL = 16 settings, Reads may be interrupted by Reads and Writes may be interrupted

by Writes provi ded that this occurs on e ven clock cycles after the Read or Write command and tCCD is met .

6.4.3 Burst Read command

The Burst Read command is initiated by having CS_n LOW, CA0 HIGH, CA1 LOW and CA2 HIGH at the rising

edge of the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column

address for the burst. The Read Latency (RL) is defined from the rising edge of the clock on which the Read

Command is issued to the rising edge of the clock from which the tDQSCK delay is measured. The first valid datum

is available RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Read Command is issued.

The data strobe output is driven LOW tRPRE before the first rising valid strobe edge. The first bit of the burst is

synchronized with the first rising edge of the data strobe. Each subsequent data-out appears on each DQ pin edge

aligned with the dat a strobe. The RL is programmed in the mode regist ers.

Timings for the data strobe are measured relat ive to the crosspoint of DQS_t and its complement, DQS_c.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 26 - Revision : P01-004A

6.4.3.1 Figure of Data output(read)timing(tDQSCK max)

DQS_c

CK_t

CK_c

RL-1 RL

DQS_t

DQS_c

RL+BL/2

QQ Q Q

tQH

tHZ(DQ)

tDQSQmax

tDQSCKmax

tLZ(DQ)

tLZ(DQS)

tRPRE

tHZ(DQs)

tRPST

tQH

tCH tCL

DQS_t

tQSH tQSL

Note : 1. tDQSCK may span multiple clock periods.

2. An effective Burst Length of 4 is shown

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 27 - Revision : P01-004A

6.4.3.2 Figure of Data output(read)timing(tDQSCKmin)

QQQQ

tDQSQmax

tDQSCKmin

RL+BL/2

tHZ(DQs)

tRPST

tQH

tHZ(DQ)

tQH

tLZ(DQ)

tDQSQmax

tRPRE

tLZ(DQS)

CK_t

CK_c RL-1 RL

tCH tCL

DQS_t

DQS_c

DQS_t

tQSL

tQSH

Note: An effective Burst Length of 4 is shown

6.4.3.3 Figure of LPDDR2-S4 : Burst r ead : RL = 5. BL = 4. tDQSCK > tCK

CK_t / CK_c

CA0-9

[Cmd]

Nop Nop Nop Nop Nop Nop Nop Nop

Read

T0 T1 T2 T3 T4 T5 T6 T7 T8

DQS_c

DQS

DQSCK

RL = 5

Bank A

Col Addr Col Addr

DOUT A0 DOUT A1 DOUT A2 DOUT A3

DQS_t

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 28 - Revision : P01-004A

6.4.3.4 Figure of LPDDR2-S4 : Burst read : RL = 3. BL = 8. tDQSCK < tCK

CK_t / CK_c

CA0-9

[Cmd]

Nop Nop Nop Nop Nop Nop Nop NopRead

T0 T1 T2 T3 T4 T5 T6 T7 T8

DQS_c

DQS

DQSCK

RL = 3

Bank A

Col Addr Col Addr

DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7

DQS_t

6.4.3.5 Figure of LPDDR2: tDQSCKDL timing

CA0-9

[Cmd]

DQS

Tm+8

32ms maximum

RL = 5

CK_t / CK_c

DQS_c

DQS_t

DOUT A3

Tm+7

Tm+6Tm+5

Tm+4Tm+3Tm+2Tm+1Tm

tDQSCKm

DOUT A2DOUT A1DOUT A0

Tn+8

RL = 5

DOUT A3

Tn+7

Tn+6

Tn+5

Tn+4

Tn+3Tn+2Tn+1

tDQSCKn

DOUT A2DOUT A1DOUT A0

tDQSCKDL = l tDQSCKn – tDQSCKm l

Col

Addr

Read Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop

Read

Col

Addr Col

Addr

Nop

Note : tDQSCKDLmax is defined as the maximum of ABS(tDQSCKn - tDQSCKm) for any {tDQSCKn ,tDQSCKm} pair within any 32ms rolling

window.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 29 - Revision : P01-004A

6.4.3.6 Figure of LPDDR2: tDQSCKDM tim ing

CA0-9

[Cmd]

Tm+8

1.6us maximum

RL = 5

CK_t / CK_c

DQS_c

DQS_t

Tm+7

Tm+6Tm+5

Tm+4Tm+3Tm+2Tm+1Tm

tDQSCKm

Tn+8

RL = 5

Tn+7

Tn+6

Tn+5

Tn+4

Tn+3Tn+2Tn+1

tDQSCKn

DOUT A0

tDQSCKDM = l tDQSCKn – tDQSCKm l

Nop

Col

Addr

Read Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop

Read

Col

Addr Col

Addr

Nop

DOUT A1DOUT A2DOUT A3DOUT A0DOUT A1DOUT A2DOUT A3

Note : tDQSCKDMmax is defined as the maximum of ABS(tDQSCKn - tDQSCKm) for any {tDQSCKn,tDQSCKm} pair within any 1.6us rolling

window.

6.4.3.7 Figure of LPDDR2: tDQSCKDS tim ing

CA0-9

[Cmd]

Tm+8

160ns maximum

RL = 5

CK_t / CK_c

DQS_c

DQS_t

Tm+7

Tm+6Tm+5

Tm+4Tm+3Tm+2Tm+1Tm

tDQSCKm

Tn+8

RL = 5

Tn+7

Tn+6

Tn+5

Tn+4

Tn+3Tn+2Tn+1

tDQSCKn

DOUT A0

DQSCKDS = l

DQSCKn –

DQSCKm l

Nop

Col

Addr

Read Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop Nop

Read

Col

Addr Col

Addr

Nop

DOUT A1 DOUT A2 DOUT A3 DOUT A0 A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2

Nop

Note : tDQSCKDSmax is defined as the maximum of ABS(tDQSCKn - tDQSCKm) for any {tDQSCKn ,tDQSCKm} pair for reads within a

consecutive burst within any 160ns rolling window.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 30 - Revision : P01-004A

6.4.3.8 LPDDR2-S4 : Burst read followed by burst write: RL = 3, WL = 1, BL = 4

CK_t / CK_c

CA0-9

[Cmd]

Nop Nop Nop Nop Nop Write Nop NopRead

T0 T1 T2 T3 T4 T5 T6 T7 T8

DQS_c

DQSCK

RL = 3

Bank A

Col Addr Col Addr

DOUT A0 DOUT A1 DOUT A2 DOUT A3 DIN A0 DIN A1 DIN A2

WL=1

DQSSmin

BL / 2

Bank A

Col Addr Col Addr

DQS_t

The minimum time from the burst read command to the burst write command is defined by the Read Latency (RL)

and the Burst Length (BL). Minimum read to write latency is RL + RU(tDQSCKmax/tCK) + BL/2 + 1 - WL clock

cycles. Note that i f a read burst is truncated with a Burst T ermi nate (BST) command, the effective burst lengt h of the

truncated read burst should be used a s “BL” to calculate the mini mum read to write del ay

6.4.3.9 Figure of LPDDR2-S4 : Seamless bu r st read : RL = 3, BL= 4, tCCD =2

CK_t / CK_c

CA0-9

[Cmd] Nop Read Nop Nop Nop Nop Nop Nop

Read

DQS_c

RL = 3

Bank N

Col Addr A Col Addr A

DOUT A0

T0 T1 T2 T3 T4 T5 T6 T7 T8

CCD = 2

Bank N

Col Addr B Col Addr B

DQS_t

DOUT A1DOUT A2DOUT A3DOUT B0 DOUT B1 DOUT B2 DOUT B3

The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4

operation, every 4 clocks for BL = 8 operation, and every 8 clocks for BL=16 operation.

For LPDDR2-SDRAM, this operation is allowed regardless of whether the accesses read the same or different

banks as long as the banks are activated.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 31 - Revision : P01-004A

6.4.4 Reads interrupted by a read

For LPDDR2-S4 device, burst read can be interrupted by another read on even clock cycles after the Read

command, provided that tCCD is met.

6.4.4.1 Figure of LPDDR2-S4 : Read burst interrupt exampl e : RL = 3, BL= 8, tCCD=2

RL = 3

tCCD=2

Nop Read Nop Nop Nop Nop Nop Nop

Col Addr A

DOUT A0

T7T6

T5T4T3T2T1

Bank N

Col Addr A

Read

Bank N

Col Addr B Col Addr B

CA0-9

[Cmd]

CK_t / CK_c

DQS_c

DQS_t

DOUT A1 DOUT A2 DOUT A3 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B4 DOUT B5

Note : 1. For LPDDR2-S4 devices, read burst interrupt function is only allowed on burst of 8 and burst of 16.

2. For LPDDR2-S4 devices, read burst interrupt may only occur on even clock cycles after the previous commands, provided that tCCD is

met.

3. Reads can only be interrupted by other reads or the BST command.

4. Read burst interruption is allowed to any bank inside DRAM.

5. Read burst with Auto-Precharge is not allowed to be interrupted.

6.The effective burst length of the first read equals two times the number of clock cycles between the first read and the interrupting

read.

6.4.5 Burst Write operati on

The Burst Write command is initiated by having CS_n LOW, CA0 HIGH, CA1 LOW and CA2 LOW at the rising edge

of the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address

for the burst. The Write Latency (WL) is defined from the rising edge of the clock on which the Write Command is

issued to the rising edge of the clock from which the tDQSS delay is measured. The first valid data must be driven

WL * tCK + tDQSS from the rising edge of the clock from which the Write command is issued. The data strobe

signal (DQS) should be driven LOW tWPRE prior to the data input. The data bits of the burst cycle must be applied

to the DQ pins tDS prior to the respective edge of the DQS and held valid until tDH after that edge. The burst data

are sampled on su ccessive edges of the DQS until the burst length is completed, which is 4, 8, or 16 bit burst.

For LPDDR2-SDRAM devices, tWR must be satisfied before a precharge command to the same bank may be

issued after a burst write operation.

Input timings are measured relative to the crosspoint of DQS_t and its complement, DQS_c.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 32 - Revision : P01-004A

6.4.5.1 Data i nput (write) timing

DQS_c

DQS_t

DQS_c

D D D D

DMin

DMin DMin DMin

tDQSH tDQSL

tWPRE tWPST

tDH

tDS

(dc)

(ac)

tDH

6.4.5.2 LPDDR2-S4 : Burst write : WL = 1, BL= 4

CA0-9

[Cmd]

DQS_c

CK_t / CK_c

DQS_c

T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1

tRP

tWR

tDSH

tDSS

DSS

Bank A

Col Addr Col Addr Bank A

Row Addr

Bank A Row Addr

Nop

NopNop

NopWrite Precharge Activate

DIN A0 DIN A1 DIN A2 DIN A3

tDQSSmax

tDQSSmin

Completion of Burst Write

Case 1:with t

DQSS

(max)

Case 2:with t

DQSS

(min)

WL = 1

DQS_t

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 33 - Revision : P01-004A

6.4.5.3 LPDDR2-S4 : Burst wirte followed by burst read : RL = 3, WL= 1, BL=4

CK_t / CK_c

CA0-9

[Cmd]

Nop Read

Nop Nop Nop

Write

DQS_c

DQS

tWTR

Bank M

Col Addr A Col Addr A

DIN A0 DIN A1 DIN A2 DIN A3

T0 T1 T2 T3 T4 T5 T6 T7 T8

WL = 1

Bank N

Col Addr B Col Addr B

RL = 3

DQS_t

Note :1.The minimum number of clock cycles from the burst write command to the burst read command for any bank is [WL + 1 + BL/2 +

RU( tWTR/tCK)].

2. tWTR starts at the rising edge of the clock after the last valid input datum.

3. If a write burst is truncated with a Burst Terminate (BST) command, the eff ective burst length of the truncated write burst should be

used as “BL” to calculate the minimum write to read delay.

6.4.5.4 LPDDR2-S4 : Seamless burst write : WL= 1, BL=4, tCCD=2

CK_t / CK_c

CA0-9

[Cmd]

Nop Write Nop Nop Nop Nop Nop Nop

Write

DQS_c

DQS

WL=1

Bank M

Col Addr A Col Addr A

DIN A0 DIN A1 DIN A2 DIN A3

T0 T1 T2 T3 T4 T5 T6 T7 T8

tCCD = 2

Bank N

Col Addr B Col Addr B

DIN B0 DIN B1 DIN B2 DIN B3

DQS_t

Note: Th e seamless burst write o peration is supported by enabl ing a write command ever y other clock for BL = 4 operati on, every four clocks

for BL = 8 operation, or every eight cl ocks for BL=16 operation. This operation is al lowed regardless of same or different banks as l ong

as the banks are activated.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 34 - Revision : P01-004A

6.4.6 Writes interrupt ed by a write

For LPDDR2-S4 devices, burst writes can only be interrupted by another write on even clock cycles after the write

command, provided that tCCD(min) is met.

6.4.6.1 LPDDR2-S4 : Write burst interr upt timing : WL= 1, BL=8, tCCD=2

CK_t / CK_c

CA0-9

[Cmd]

Nop Write Nop Nop Nop Nop Nop Nop

Write

DQS_c

DQS

WL=1

Bank M

Col Addr A Col Addr A

DIN A0 DIN A1

T0 T1 T2 T3 T4 T5 T6 T7 T8

tCCD = 2

Bank N

Col Addr B Col Addr B

DIN B2 DIN B3 DIN B5

DIN B4

DIN B1

DIN B0 DIN B6 DIN B7DIN A2 DIN A3

DQS_t

Note : 1. For LPDDR2-S4 devices, write burst interrupt function is only allowed on burst of 8 and burst of 16.

2. For LPDDR2-S4 devices, write burst interrupt may only occur on even clock cycles after the previous write commands, provided that

tCCD(min) is met.

3. Writes can only be interrupted by other writes or the BST command.

4. Write burst interruption is allowed to any bank inside DRAM.

5. Write burst with Auto-Precharge is not allowed to be interrupted.

6. The effective burst length of the first write equals two times the number of clock cycles between the first write and the interrupting

write.

6.4.7 Burst Terminate

The Burst Terminate (BST) command is initiated by having CS_n LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and

CA3 LOW at the rising edge of clock. A Burst Teminate command may only be issued to terminate an active Read

or Write burst. Therefore, a Burst Terminate command may only be issued up to and including BL/2 - 1 clock cycles

after a Read or Write command. The effective burst length of a Read or Write command truncated by a BST

command is as follows:

Effective burst length = 2 x {Number of clock cycles from the Read or Write Command to the BST command}

Note that if a read or write burst is truncated with a Burst Terminate (BST) command, the effective burst length of

the truncated burst should be used as “BL” to calculate the m ini m um read to write or w ri te to read delay.

The BST command only affects the most recent read or write command. The BST command truncates an ongoing

read burst RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Burst Terminate command is

issued. The BST command truncates an on going write burst WL * tCK + tDQSS after the rising edge of the clock

where the Burst Terminate command is i ss ued.

For LPDD R2-S4 devices, the 4-bit prefetch architecture allows the BST command to be issued on an even number

of clock cycles after a Write or Read command. Therefore, the effective burst length of a Read or Write command

truncated by a BST command is an integer mul tiple of 4.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 35 - Revision : P01-004A

6.4.7.1 LPDDR2-S4 : Write burst trunc ated by BST : WL= 1, BL=16

CA0-9

[Cmd]

Nop BST

Nop

Nop Nop Nop Nop Nop

Write

DQS

WL=1

Bank M

Col Addr A Col Addr A

DIN A0 DIN A1

T0 T1 T2 T3 T4 T5 T6 T7 T8

WL*tCK+tDQSS

CK_t / CK_c

DQS_c

DQS_t

DIN A2 DIN A3 DIN A4 DIN A5 DIN A6 DIN A7

BST not allowed

Note :1. The BST command truncates an ongoing write burst WL * tCK + tDQSS after the rising edge of the clock where the Burst Terminate

command is issued.

2. Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write command.

6.4.7.2 LPDDR2-S4 : Burst Read truncated by BST : RL= 3, BL=16

CA0-9

[Cmd]

Nop BST

Nop

Nop Nop Nop Nop Nop

Read

RL = 3

Bank N

Col Addr A Col Addr A

T0 T1 T2 T3 T4 T5 T6 T7 T8

RL*tCK+tDQSCK+tDQSQ

CK_t / CK_c

DQS_c

DQS_t

DOUT A2DOUT A1DOUT A0 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7

BST not allowed

Note :1. The BS T command truncates an ongoing read burst RL * tCK + tDQSCK + tDQSQ after the ris ing edge of the clock where the Burst

Terminate command is issued.

2. For LPDDR2-S4 devices, BST can only be issued at even number of clock cycles after the Write command.

3. Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write command.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 36 - Revision : P01-004A

6.4.8 Write data mask

One write data mask (DM) pin for each data byte (DQ) will be supported on LPDDR2 devices, consistent with the

implementation on LPDDR SDRAMs. Each data mask (DM) may mask its respective data byte (DQ) for any given

cycle of the burst. Data mask has identical timings on write operations as the data bits, though used as input only, is

internally loaded identically to data bi ts to insure matched syst em timing.

6.4.8.1 LPDDR2-S4 : Write data mask

Data Mask Timing

DHtDStDS tDH

(ac)

(ac) V

(dc)

(dc) V

(ac)

(ac) V

(dc)

[Cmd]

WL = 2

Wirte t

DQSSmin

tDQSSmax

tWR

tWTR

01 2 3

0123

Case 2: max tDQSS

Case 1: min tDQSS

Data Mask Function,WL= 2, BL=4 shown,second DQ masked

DQS_c

DQS_t

CK_c

CK_t

DQS_c

DQS_t

DQS_c

DQS_t

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 37 - Revision : P01-004A

6.4.9 LPDDR2-S4: Precharge operation

The Precharge command is used to precharge or close a bank that has been activated. The P recharge command is

initiated by having CS_n LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 HIGH at the rising edge of the clock.

The Precharge Command can be used to precharge each bank independently or all banks simultaneously. For 8-

bank devices, the AB flag, and the bank address bits, BA0, BA1, and BA2, are used to determine which bank(s) to

precharge. The bank(s) will be available for a subsequent row access tRPab after an All-Bank Pr echarge com mand

is issued and tRPpb after a Single-Bank Precharge command is issued.

In order to ensure that 8-bank devices do not exceed the instantaneous current supplying capability of 4-bank

devices, the Row Precharge time (tRP) for an All-Bank Precharge for 8-bank devices (tRPab) will be longer than the

Row Precharge t i m e for a Single-Bank Precharge (t RPpb).

6.4.9.1 Table of Bank selection for Precharge by address bits

AB (CA4r) BA2 (CA9r) BA1 (CA8r) BA0 (CA7r) Precharged Bank(s)

8-bank device

0 0 0 0 Bank 0 only

Bank 1 only

0 0 1 0 Bank 2 only

0 0 1 1 Bank 3 only

Bank 4 only

0 1 0 1 Bank 5 only

Bank 6 only

Bank 7 only

1 DON’T CARE DON’T CARE DON’ T CARE All Banks

6.4.10 LPDDR2-S4: Burst Read operation followed b y Precharge

For the earliest possible precharge, the precharge command may be issued BL/2 clock cycles after a Read

command. For an untruncated burst, BL is the value from the Mode Register. For a truncated burst, BL is the

effective burst length. A new bank active (command) may be issued to the same bank after the Row Precharge time

(tRP). A precharge command cannot be issued until after t RA S i s sa tisfied.

For LPDDR2-S4 devices, the minimum Read to Precharge spacing has also to satisfy a minimum analog time from

the rising clock edge that initiates the last 4-bit prefetch of a Read command.This time is called tRTP (Read to

Precharge).

For LPDDR2-S4 devices, tRTP begins BL/2 - 2 clock cycles after the Read command. If the burst is truncated by a

BST command or a Read command to a different bank, , the effective “BL” shall be used to calculate when tRTP

begins.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 38 - Revision : P01-004A

6.4.10.1 Fig ur e of LPDDR2-S4 Burst r ead followed by Prechar ge : RL= 3, BL=8, RU(tRTP(min)/tCK) = 2

CA0-9

[Cmd] Nop

Nop Nop Precharge Nop Nop Activate Nop

Read

DQS

RL = 3

Bank M

Col Addr A Col Addr A

DOUT A0 DOUT A1

T0 T1 T2 T3 T4 T5 T6 T7 T8

DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7

Bank M Bank M

Row Addr Row Addr

BL / 2 tRTP

tRP

CK_t / CK_c

DQS_c

DQS_t

6.4.10.2 Fig ur e of LPDDR2-S4 : Burst read followed by Precharge : RL= 3, BL=4, RU(tRTP(min)/tCK)=3

CA0-9

[Cmd]

Nop

Nop NopPrecharge Nop NopActivate Nop

Read

DQS

RL = 3

Bank M

Col Addr A Col Addr A

DOUT A0 DOUT A1

T0 T1 T2 T3 T4 T5 T6 T7 T8

DOUT A2 DOUT A3

Bank M Bank M

Row Addr Row Addr

BL / 2

tRTP=3 tRP

CK_t / CK_c

DQS_c

DQS_t

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 39 - Revision : P01-004A

6.4.11 LPDDR2-S4: Burst Write followed by P recharge

For write cycles, a delay must be satisfied from the time of the last valid burst input data until the Precharge

command may be issued. This delay is known as the write recovery time (tWR) referenced from the completion of

the burst write to the precharge command. No Precharge command should be issued prior to the tWR delay.

These devices write data to the array in prefetch quadruples (prefetch = 4). The beginning of an internal write

operation may onl y begin after a prefetch group has been latched completely.

The minimum Write to Precharge command spacing to the same bank is WL + BL/2 + 1 + RU(tWR/tCK) clock

cycles. For an untruncated burst, BL is the value from the Mode Register. For an truncated burst, BL is the effective

burst length.

6.4.11.1 Fig ur e of LPDDR2-S4 : Burst write follwed by precharge : WL = 1, BL= 4

CA0-9

[Cmd]

DQS

T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1

>=tRP

tWR

Bank A

Col Addr Col Addr Bank A

Row Addr

Bank A Row Addr

Nop

NopNop

Nop

Nop Precharge Activate

DIN A0 DIN A1 DIN A2 DIN A3

tDQSSmax

tDQSSmin

Completion of Burst Write

Case 1:with t

DQSS

(max)

Case 2:with t

DQSS

(min)

WL = 1

Write

CK_t / CK_c

DQS_c

DQS_t

DQS_c

DQS_t

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 40 - Revision : P01-004A

6.4.12 LPDDR2-S4: Auto Precharge operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge

command or the auto-precharge function. When a Read or a Write command is given to the LPDDR2 SDRAM, the

AP bit (CA0f) may be set to allow the active bank to automatically begin precharge at the earliest possible moment

during the burst re ad or write cycle.

If AP is LOW when the Read or Write command is issued, then normal Read or Write burst operation is executed

and the bank remai ns active at the complet i on of the burst.

If AP is HIGH when the Read or Write command is issued, then the auto-precharge function is engaged. This

feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent

upon Read or Write l atency) thus improv ing system performance for random data access.

6.4.13 LPDDR2-S4: Burst Read with Auto-Precharge

If AP (CA0f) is HIGH when a Read Command is issued, the Read with Auto-Precharge function is engaged.

LPDDR2-S4 devices start an Auto-Precharge operation on the rising edge of the clock BL/2 or BL/2 - 2 +

RU(tRTP/tCK) clock cycles later than the Read with AP command.

A new bank Activate command may be issued to the same bank if both of the following two conditions are satisfied

simultaneously.

■ The RAS precharg e time (tRP) has been satisfied from the clock at which the auto prechar ge begins.

■ The RAS cycle ti m e (t RC) from the previous bank activation ha s been satisfied

6.4.13.1 Figur e of LPDDR2-S4 : Burst read with Auto-Precharge : RL= 3, BL=4, RU(tRTP(min)/tCK)=2

CA0-9

[Cmd] NopNop Nop

Nop Nop Nop

Activate Nop

Read

DQS

RL = 3

Bank M

Col Addr A Col Addr A

DOUT A0 DOUT A1

T0 T1 T2 T3 T4 T5 T6 T7 T8

DOUT A2 DOUT A3

Bank M

Row Addr Row Addr

BL / 2

tRTP >=tRPpb

CK_t / CK_c

DQS_c

DQS_t

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 41 - Revision : P01-004A

6.4.14 LPDDR2-S4: Burst write with Auto-Precharge

If AP (CA0f) is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged. The

LPDDR2 SDRAM starts an Auto Precharge operation on the rising edge which is tWR cycles after the completion of

the burst write.

A new bank activate (command) may be issued to the same bank if both of the following two conditions are satisfied.

■ The RAS precharg e time (tRP) has been sati sf i ed from the clock at which the auto precharge begins.

■ RAS cycle tim e (tRC) from the previou s bank activation has been sati sf ied.

6.4.14.1 Figure of LPDDR2-S4 : Burst write w/Auto precharge : WL = 1, BL= 4

CA0-9

[Cmd]

DQS

T0 T1 T2 T3 T4

tRPpb

tWR

Bank A

Col Addr Col Addr Bank A

Row Addr Row Addr

Nop

Nop Nop Activate

DIN A0 DIN A1 DIN A2 DIN A3

WL = 1

Write

T5 T6 T7 T8

Nop Nop

CK_t / CK_c

DQS_c

DQS_t

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 42 - Revision : P01-004A

6.4.14.2 Table of LPDDR2-S4 Prechar ge & Auto Precharge Clarification

From

Command

To Command

Minimum Delay between

“From Command” to “To Command”

Unit

Note

Read Precharge (to same Bank as Read)

BL/2 + max(2, RU(tRTP/tCK)) - 2 CLK 1

Precharge ALL

BL/2 + max(2, RU(tRTP/tCK)) - 2 CLK 1

BST

(for Reads)

Precharge ( to same Bank a s Read) 1 CLK 1

Precharge ALL 1 CLK 1

Read w/AP

Precharge (to same Bank as Read w/AP)

BL/2 + max(2, RU(tRTP/tCK)) - 2 CLK 1,2

Precharge ALL

BL/2 + max(2, RU(tRTP/tCK)) - 2 CLK 1

Activate (to same Bank as Rea d w/AP)

BL/2 + max(2, RU(tRTP/tCK)) - 2 + RU(tRPpb/tCK) CLK 1

Write or Write w/AP (same bank) lllegal CLK 3

Write or Write w/AP (different bank) RL + BL/2 + RU(tDQSCKmax/tCK) - WL + 1 CLK 3

Read or Read w/AP (same bank) lllegal CLK 3

Read or Read w/AP ( di f fe ren t bank) BL/2 CLK 3

Write

Precharge (to same Bank as Write)

WL + BL/2 + RU(tWR/tCK) + 1 CLK 1

Precharge ALL

WL + BL/2 + RU(tWR/tCK) + 1 CLK 1

BST

(for Writes)

Precharge (to same Bank as Write) WL + RU(tWR/tCK) + 1 CLK 1

Precharge ALL WL + RU(tWR/tCK) + 1 CLK 1

Write w/AP

Precharge (to same Bank as Write w/AP)

WL + BL/2+ RU(tWR/tCK) + 1 CLK 1

Precharge ALL

WL + BL/2 + RU(tWR/tCK) + 1 CLK 1

Activate (to same Bank as Write w/AP)

WL + BL/2 + RU(tWR/tCK) + 1 + RU( tRPpb /tCK) CLK 1

Write or Write w/AP (same bank) lllegal CLK 3

Write or Write w/AP (different bank) BL/2 CLK 3

Read or Read w/AP (same bank) lllegal CLK 3

Read or Read w/AP ( di f fe ren t bank) WL + BL/2 + RU(tWTR/tCK) + 1 CLK 3

Precharge

Precharge (to same Bank as Precharge)

1 CLK 1

Precharge ALL

1 CLK 1

Precharge All

Precharge

1 CLK 1

Precharge ALL

1 CLK 1

Note :1. For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or

precharge all, issued to that bank. The precharge period is satisfied after tRP depending on the latest precharge command

issued to that bank.

2. Any command issued durin g the minimu m delay time i s illegal.

3. After Read with AP, seamless read operations to different banks are supported. After Write with AP, seamless write operations

to different banks are supported. Read w/AP and Write w/AP may not be interrupted or truncated.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 43 - Revision : P01-004A

6.4.15 LPDDR2-S4: Refresh command

The Refresh command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of

clock. Per Bank Refresh is initiated by having CA3 LOW at the rising edge of clock and All Bank Refresh is initiated

by having CA3 HIGH at the rising edge of cloc k. Per Bank Refresh is only all owed in devices with 8 banks.

A Per Bank Refresh co m mand, REFpb perform s a refresh operation to the bank which is scheduled by the bank

counter in the memory device. The bank sequence of Per Bank Refresh is fixed to be a sequential round-robin: “0-

1-2-3-4-5-6-7-0-1-...”. The bank count is synchronized between the controller and the SDRAM upon issuing a

RESET command or at every exit from self refresh, by resetting bank count to zero. The bank addressing for the

Per Bank Refresh count is the same as established in the single-bank Precharge command. A bank must be idle

before it can be refreshed. It is the responsibility of the controller to track the bank being refreshed by the Per Bank

Refresh command.

The REFpb comman d m ay not be issued to the m em ory until the following conditions are met:

a) tRFCab has been satisified after the prior REFab command

b) tRFCpb has been satisfied after the prior REFpb comm and

c) tRP has been satisified after the prior Pre charge command to that gi ven bank

tRRD has been satisfied after the prior ACTIVATE command (if applicable, for example after activating a row in a

different bank than affected by the REF pb command).

The target bank is inaccessable during the Per Bank Refresh cycle time (tRFCpb), however other banks within the

device are accessable and may be addressed during the Per Bank Refresh cycle. During the REFpb operation, any

of the banks other than the one being refreshed can be maintained in active state or accessed by a read or a write

command.

When the Per Bank refresh cycle has completed, the affected bank will be in the Idle st ate.after issuing REFpb:

a) tRFCpb must be satisified before issuing a REFab comm and

b) tRFCpb must be satisfied before issuing an ACTIVATE comm and to the same bank

c) tRRD must be satisified before issuing an ACTIVATE comm and to a differen t bank

d) tRFCpb must be satisified before issuing another RE Fpb command

An All Bank Refresh command, REFab performs a refresh operation to all banks. All banks have to be in Idle state

when REFab is issued (for instance, by Precharge all-bank command). REFab also synchronizes the bank count

between the controller and the SDRAM to zero. the REFab command may not be issued to the memory until the

following conditi ons have been met:

a) tRFCab has been satisified after the prior REFab command

b) tRFCpb has been satisified after the prior REFpb command

c) tRP has been satisified after prior PRECHARGE commands

When the All Bank r efresh cycle has compl eted, all banks will be i n the Idle state. after iss ui ng REFab:

a) the tRFCab latency must be satisfie d before issuing an ACTIVATE command

b) the tRFCab latency must be satisfie d before issuing a REFab or RE Fpb command

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 44 - Revision : P01-004A

6.4.15.1 Table of Command Scheduling Separations related to Refresh

Symbol minimum delay

from to Note

tRFCab REFab

REFab

Activate cmd to any bank

REFpb

tRFCpb REFpb

REFab

Activate cmd to same bank as REFpb

REFpb

tRRD

REFpb Activate cmd to different bank than REFpb

Activate REFpb affecting an idle bank (different bank than Activate) 1

Activate cmd to different bank than prior Activate

Note : A bank must b e in the Idl e state bef ore it is refr eshed. Ther efore, after Activate,REFab is not allowed and REFpb

is allowed only if i t af fects a ban k w hich is in the Idle state ..

6.4.16 LPDDR2 S DRAM Refresh Requirements

(1) Minimum number of Refresh commands:

The LPDDR2 SDRAM requires a minimum number of R Refresh (REFab) commands within any rolling Refresh

Window (tREFW = 32 ms @ MR4[2:0] = “011” or Tj ≤ 85 °C). The minimum number R depends on density. The

resulting average refresh interval (t RE FI) also depends on density.

See Mode Register 4 f or tREFW and tREFI refresh multipliers at di fferent MR4 set tings.

(2) Burst Refresh li m i tation:

To limit maximum current consumption, a maximum of 8 REFab commands may be issued in any rolling tREFBW

(tREFBW = 4 x 8 x tRFCab).

(3) Refresh Requireme nts and Self-Refresh:

If any time within a refresh window is spent in Self-Refresh Mode, the number of required Refresh commands in this

particular window is reduced to:

R* = R - RU{tSRF / tREFI} = R - RU{R * tSRF / tREF W}; where RU stands for the round-up function

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 45 - Revision : P01-004A

6.4.16.1 Figure of LPDDR2-S4 : Definition of tSRF

CKE

tREFW

tSRF

Enter Self-Refresh

Exit Self-Refresh

Exit Self-Refresh Enter Self-Refresh

Enter Self-Refresh

Exit Self-Refresh

tREFW tSRF

tSRF

tSRF1 tSRF2

tREFW

tSRF=tSRF1+tSRF2

Several examples on how tSRF is caclul ated:

A: with the time spe nt in Self-Refresh Mode fully enclosed in the R efresh Window (tREFW),

B: at Self-Refresh entry

C: at Self-Refresh exit

D: with several different invervals spent in Self Refresh du ring one tREFW interval

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 46 - Revision : P01-004A

In contrast to JESD79 and JESD79-2 and JESD79-3 compliant SDRAM devices, LPDDR2-S4 devices allow

significant flexibiliy in scheduling RE F RESH commands, as long as the boundary condit i ons above are met.

In the most straight forward case a REFRESH command should be scheduled every tREFI. In this case Self-

Refresh may be entered at any time.

The users may choose to deviate from this regular refresh pattern e.g., to enable a period where no refreshes are

required. In the extreme the user may choose to issue a refresh burst of 4096 REFRESH commands with the

maximum allowable rate (limited by tREFBW) followed by a long time without any REFRESH commands, until the

refresh window is complete, then repeating this sequence. The achieveable time without REFRESH commands is

given by tREFW - (R / 8) * tREFBW = tREFW - R * 4 * tRFCab.@ Tj <= 85℃ this can be up to 32 ms - 4096 * 4 *

130 ns ~ 30 ms.

While both - the regular and the burst/pause - patterns can satisfy the refresh requirements per rolling refresh

interval, if they are repeated in every subsequent 32 ms window, extreme care must be taken when transitioning

from one pattern to another to satisfy the refresh requirement in every rolling refresh window during the transition. If

this transition happens directly after the burst refresh phase, all rolling tREFW intervalls will have at least the

required number of refreshes.

As an example of a non-allowable transition, the regular refresh pattern starts after the completion of the pause-

phase of the burst/pause refresh pattern. For several rolling tREFW intervals the minimmun number of REFRESH

commands is not sat i sf i ed.

The understanding of the pattern transition is extremly relevant (even if in normal operation only one pattern is

employed), as in Self-Refresh-Mode a regular, distributed refresh pattern has to be assumed, which is reflected in

the equation for R* above. Therefore it is recommended to enter Self-Refresh-Mode ONLY directly after the burst-

phase of a burst/pause refresh pattern and begin with the burst phase upon exit f rom Self-Refresh.

6.4.16.2 Figure of LPDDR2-S4 Regular, Distributed Refresh P attern vs. Repetitive Burst Refresh wit h S ubsequent Refresh

Pause

tREFI tREFI

tREFBW tREFBW

0 ms 32 ms 64 ms 96 ms

Note : For a device @ Tj less than or equal to 85 C the distributed refresh pattern would have one REFRESH command per 7.8 us; the burst

refresh pattern would have one refresh command per 0.52 us followed by ~30 ms without any REFRESH command .

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 47 - Revision : P01-004A

6.4.16.3 Figure of LPDDR2-S4: Allowable Transition from Repet itive Burst Refresh with Subsequent Refresh Pause to Reg ul ar ,

Distributed Refresh Pattern

tREFI tREFI

tREFBW tREFBW

0 ms 32 ms 64 ms 96 ms

Note : in a 1Gb LPDDR2 device @ Tj less than or equal to 85 C the distributed refresh pattern would have one REFRESH command per 7.8

us; the burst refresh pattern would have one refresh command per 0.52us followed by ~30 ms without any REFRESH command.

6.4.16.4 Figure of LPDDR2-S4: NOT-Allowable Transition fr om Repetitive Burst Refresh with Subs equent Refresh Pause to

Regular, Distributed Refresh Pattern

tREFI tREFI

tREFBW tREFBW

0 ms 32 ms 64 ms 96 ms

tREFW=32ms

Not enough Refresh commands

In this refresh window!!

Note : Only ~2048 REFRESH commands (<R which is 4096) in the indicated tREFW window.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 48 - Revision : P01-004A

6.4.16.5 Figure of LPDDR2-S4: Recommended Self-refresh entry and exit in conjunct ion with a Burst/Pause Refresh patterns.

REFBW

32 ms

0 ms

Self-Refresh

6.4.16.6 Fig ur e of LPDDR2-S4 All Bank Refresh Oper ation

T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1

>=tRPab >=tRFCab >=tRFCab

Precharge Nop Nop Nop NopREFab REFab ANY

CA0-9

[Cmd]

CK_t / CK_c

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 49 - Revision : P01-004A

6.4.16.7 Figur e of LPDDR2-S4 Per Bank Refresh Oper ation

CA0-9

[Cmd]

CK_t / CK_c

T0 T1 Tx Tx+1 Tx+2 Ty Ty+1 Tz Tz+1

>=tRPab >=tRFCpb >=tRFCpb

Activate command to Bank 1

Refresh to Bank 1

Refresh to Bank 0

ACT

AB Row A

Bank 1

Row A

REFpb

NOPNOPPrecharge

Note : 1.In the beginning of this example, the REFpb bank is pointing to Bank 0.

2.Operations to other banks than the bank being refreshed are allowed during the tRFCpb period.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 50 - Revision : P01-004A

6.4.17 LPDDR2-S4: Self Refresh operation

The Self Refresh command can be used to retain data in the LPDDR2 SDRAM, even if the rest of the system is

powered down. When in the Self Refresh mode, the LPDDR2 SDRAM retains data without external clocking. The

LPDDR2 SDRAM device has a bui lt -in timer to accommodate Self Refresh ope rat i on. The Self Refresh Command is

defined by having CKE LOW, CS_n LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock.

CKE must be HIGH during the previous clock cycle. A NOP command must be driven in the clock cycle following

the power-down command. Once the command is registered, CKE must be held LOW to keep the device in Self

Refresh mode.

LPDDR2-S4 devices can operate in Self Refresh in both the Standard or Extended Temperature Ranges. LPDDR2-

S4 devices will also manage Self Refresh power consumption when the operating temperature changes, lower at

low temperatures and higher temperatu res.

Once the LPDDR2 SDRAM has entered Self Refresh mode, all of the external signals except CKE, are “don’t care”.

For proper self refresh operation, power supply pins (VDD1, VDD2, and VDDCA) must be at valid levels.

VDDQ may be t urned off during Self-Refresh. Prior to exiting Self-Refresh, VDD Q m ust be within specified limi ts.

VrefDQ and VrefCA may be at any level within minimum and maximum levels. However prior to exit Self-Refresh,

VrefDQ and VrefCA must be within specified limits. The SDRAM initiates a minimum of one all-bank refresh

command internally within tCKESR period once it enters Self Refresh mode. The clock is internally disabled during

Self Refresh Operation to save power. The minimum time that the LPDDR2 SDRAM must remain in Self Refresh

mode is tCKESR. The user may change the external clock frequency or halt the external clock one clock after Self

Refresh entry is registered; however, the clock must be restarted and stable before the device can exit Self Refresh

operation.

The procedure for exiting Self Refresh requires a sequence of commands.First, the clock shall be stable and within

specified limits for a minmum of 2 clock cycles prior to CKE going back HIGH. Once Self Refresh Exit is registered,

a delay of at least tXSR must be satisfied before a valid command can be issued to the device to allow for any

internal refres h i n progress. CKE must remain HIGH for the entire Self Refresh exi t period tXSR for proper operation

except for self refresh re-entry. NOP commands must be registered on each positive clock edge during the Self

Refresh exit interval tXSR.

The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when

CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, it is required that at least one Refresh

command (8 per-bank or 1 all-bank) is issued before entry i nto a subsequent Self Ref resh.

For LPDDR2 SDRAM, the maximum duration in power-down mode is only limited by the refresh requirements

outlined in section “LPDDR2 SDRAM Refresh Requirements”, since no refresh operations are performed in power-

down mode.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 51 - Revision : P01-004A

6.4.17.1 Figure of LPDDR2-S4 : Self Refresh Operat ion

2 tCK(min)

tIHCKE

tCKESR(min)

tISCKE

tIHCKE

Valid Enter SR NOP NOP NOP Valid

Exit SR

Input clock frequency may be changed

or stopped during Self-Refresh

Enter Self-Refresh Exit Self-Refresh

tXSR(min)

tISCKE

CKE

[Cmd]

CK_c

CK_t

CS_n

Note :1. Input clock frequency may be changed or stopped during self-refresh, provided that upon exiting self-refresh, a minimum of 5 clocks

(tINIT2) of stable clock are provided and the clock frequency is between the minimum and maximum frequency for the particular speed

grade.

2. Device must be in the “All banks idle” state prior to entering Self Refresh mode.

3. tXSR begins at the rising edge of the clock after CKE is driven HIGH.

4. A valid command may be issued only after tXSR is satisfied. NOPs shall be issued during tXSR.

6.4.18 LPDDR2-S4: Partial Array Self-Refresh: Bank Masking

Each bank of LPDDR2 SDRAM can be independently configured whether a self refresh operation is taking place.

One mode register unit of 8 bits accessible via MRW command is assigned to program the bank masking status of

each bank up to 8 banks. For bank masking bit assignments, see Mode Register 16

The mask bit to the bank controls a refresh operation of entire memory within the bank. If a bank is masked via

MRW, a refresh operation to the entire bank is blocked and data retention by a bank is not guaranteed in self

refresh mode. To enable a refresh operation to a bank, a coupled mask bit has to be programmed, “unmasked”.

When a bank mask bit is unmasked, a refresh to a bank is determined by the programmed status of segment mask

bits, which is dec ribed in the following chapter.

6.4.19 LPDDR2-S4: Partial Array Self-Refresh: Segment Masking

Segment masking scheme may be used in place of or in combination with bank masking scheme in LPDDR2-S4

SDRAM. The number of segments differ by the density and the setting of each segment mask bit is applied across

all the banks. For segment masking bit assignments, see Mode Register 17.

For those refresh-enabled banks, a refresh operation to the address range which is represented by a segment is

blocked when the mask bit to this segment is programmed, “masked”. Programming of segment mask bits is similar

to the one of bank mask bits.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 52 - Revision : P01-004A

Example of Bank and S egment Masking use in LPDDR2-S4 devic es

Segment Mask

(MR17) Bank 0 Bank 1 Bank 2

Bank 3 Bank 4

Bank 5 Bank 6

Bank 7

Segment Mask

(MR16) 0 1 0 0 0 0 0 1

Segment 0 0 - M - - - - - M

Segment 1 0 - M - - - - - M

Segment 2 1 M M M M M M M M

Segment 3 0 - M - - - - - M

Segment 4 0 - M - - - - - M

Segment 5 0 - M - - - - - M

Segment 6 0 - M - - - - - M

Segment 7 1 M M M M M M M M

Note : This table ill ustrates an example of an 8-bank LPDDR2-S4 devi ce, when a refresh ope ration to bank 1 a nd bank 7, as well as s egment

2 and segment 7 are masked.

6.4.20 Mode Register Read Command

The Mode Register Read command is used to read configuration and status data from mode registers. The Mode

at the rising edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r- CA4r}. The mode register

contents are available on the first data beat of DQ[0:7], RL * tCK + tDQSCK + tDQSQ after the rising edge of the

clock where the Mode Register Read Command is issued. Subsequent data beats contain valid, but undefined

content.

The MRR command has a burst length of four. The Mode Register Read operation (consisting of the MRR

command and the corresponding data traffic) shall not be interrupted. The MRR command period (tMRR) is 2 clock

cycles. Mode Register Reads to reserved and write-only registers shall return valid, but undefined content on all

data beats and DQS shall be toggled.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 53 - Revision : P01-004A

6.4.20.1 Figure of Mode Register Read tim ing example : RL = 3, tMRR = 2

CMD not allowed

T0 T1 T2 T3 T4 T5 T6 T7 T8

CA0-9

[Cmd]

DQ[0-7]

DQ[8-max]

tMRR = 2 tMRR = 2

RL = 3

Reg A Reg A Reg B Reg B

MRR MRR

DOUT A UNDEF DOUT B

UNDEF UNDEF UNDEF UNDEF UNDEF

UNDEFUNDEF

UNDEF

CK_t / CK_c

DQS_t

DQS_c

Note:1. Mode Register Read has a burst length of four.

2. Mode Register Read operation shall not be interrupted.

3. M ode Register data is val id only on DQ[0-7] on the first beat. Subsequent beats contain valid, but undefined data. DQ[8-max] c ontain

valid, but undefined data for the duration of the MRR burst.

4. The Mode Register Command period is tMRR. No command (other than Nop) is allowed during this period.

5. Mode Register Reads to DQ Calibration registers MR32 and MR40 are described in the section on DQ Calibration.

6. Minimum Mode Register Read to write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 - WL clock cycles.

7. Minimum Mode Register Read to Mode Register Write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 clock cycles.

The MRR command shall not be issued earlier than BL/2 clock cycles after a prior Read command and WL + 1 +

BL/2 + RU( tWTR/tCK) clock cycles after a prior Write command, because read-bursts and write-bursts shall not be

truncated by MRR. Note that if a read or write burst is truncated with a Burst Terminate (BST) command, the

effective burs t length of the truncated burst should be used as “BL.

”

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 54 - Revision : P01-004A

6.4.20.2 Figure of LPDDR2 Read to MRR tim i ng example : RL = 3, tMRR = 2

CMD not allowed

T0 T1 T2 T3 T4 T5 T6 T7 T8

CA0-9

[Cmd]

[0-7]

[8-max]

BL / 2 tMRR = 2

RL = 3

BA M

Col Addr A Reg B Reg B

Read MRR

DOUT A0 DOUT B UNDEF UNDEF UNDEF

UNDEFUNDEF

Col Addr A

DOUT A1 DOUT A2 DOUT A3

DOUT A0 DOUT A1 DOUT A2 DOUT A3

CK_t / CK_c

DQS_c

DQS_t

Note :1.The minimum number of clocks from the burst read command to the Mode Register Read command is BL/2.

2.The Mode Register Read Command period is tMRR. No command (other than Nop) is allowed during this period

6.4.20.3 Fig ur e of LPDDR2 : Burst W r i te Followed by MRR : RL = 3, WL = 1, BL = 4

T0 T1 T2 T3 T4 T5 T6 T7 T8

CA0-9

[Cmd]

BA N

Col Addr A Reg B Reg B

Write MRR

Col Addr A

DIN A0 DIN A1 DIN A2 DIN A3

CMD not allowed

WL = 1 tWTR

RL = 3

tMRR = 2

CK_t / CK_c

DQS_c

DQS_t

Note :1.The minimum number of clock cycles from the burst write command to the Mode Register Read command is [WL + 1 + BL/2 +

RU( tWTR/tCK)].

2.The Mode Register Read Command period is tMRR. No command (other than No) is allowed during this period

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 55 - Revision : P01-004A

6.4.21 Temperature Sensor

LPDDR2 SDRAM features a temperature sensor whose status can be read from MR4. This sensor can be used to

determine an appropriate refresh rate (SDRAM), determine whether AC timing derating is required in the Extended

Temperature Range and/or monitor the operating temperature. Either the temperature sensor or the device TOPER

(See “Operating Temperature Conditions”) may be used to determine whether operating temperature requirements

are being met.

LPDDR2 devices shall monitor device temperature and update MR4 according to tTSI. Upon exiting self-refresh or

power-down, the device temperature status bits shall be no older than tTSI.

When using the temperature sensor, the actual device temperature may be higher than the TOPER specification

(See “Operating Temperature Conditions” that applies for the Standard or Extended Temperature Ranges. For

example, Tj may be above 85 ºC when MR4[2: 0] equals 011b.

To assure proper operation using the temperature sensor, applications should consider the following factors:

TempGradient is the maximum temperature gradient experienced by the memory device at the temperature of

interest over a range of 2ºC.

ReadInterval i s t he time period between MR4 reads from the system.

TempSensorI nterval (tTSI) is maxi m um delay between int ernal updates of MR4.

SysRespDelay i s the maximum time between a read of MR4 and t he response by the syste m .

TempMargin: LPDDR2 devices shall allow for a 2ºC temperature margin between the point at which the device

temperature enters the Extended Temperature Range and point at which the controller re-configures the system

accordingly.

Symbol Parameter Max/Min Value Unit

TempGradient System Temperature Gradient Max System Dependent ºC/s

ReadInterval MR4 Read Interval Max System Dependent ms

tTSI Temperature Sensor Interv al Max 32 ms

SysRespDelay System Response Delay Max System Dependent ms

TempMargin Dev i ce Temperature Margin Max 2 ºC

In order to determine the required frequency of polling MR4, the system shall use the maximum TempGradient and

the maximum response time of the sy st em using the followin g equation:

TempGradient x (ReadInterval + tTSI + SysRe spDelay) ≤ 2C

For example, if Tem pG radient is 10ºC/s and the SysRespDelay is 1 ms:

10ºC/s * (ReadInterval+32ms+1ms) ≤ 2C

In this case, ReadI nterval shall be no great er than 167ms.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 56 - Revision : P01-004A

6.4.21.1 Figure of Temp Sensor Timing

Temp

Device

Temp

Margin

MR4

Trip Level

Temperature

Sensor

Update

Host

MR4 Read MRR MR4=0x03

MR4=0x03 MR4=0x86 MR4=0x86 MR4=0x86 MR4=0x86 MR4=0x06

Readlnterval

MRR MR4=0x86

tTSI

Time

SysRespDelay

2°C

< (tTSI + Readlnterval + SysRespDelay)

TempGradient

6.4.21.2 DQ Calibration

LPDDR2-S4 device features a DQ Calibration function that outputs one of two predefined system timing calibration

patterns. A Mode Register Read to MR32 (Pattern “A”) or MR40 (Pattern “B”) will return the specified pattern on

DQ[0], DQ[8], DQ[16], and DQ[24] for x32 devices.

For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] may optionally drive the same information as DQ[0]

or may drive 0b during the MRR burst.

For LPDDR2 -S4 devices, MRR DQ Calibration commands m ay only occur in the Idle state.

Pattern MR# Bit Time 0 Bit Time 1 Bit Time 2 Bi t Time 3 Description

Pattern A MR32 1 0 1 0 Read to MR32 return DQ calibration

pattern A

Pattern B MR40 0 0 1 1 Read to MR32 return DQ c al ibration

pattern B

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 57 - Revision : P01-004A

6.4.21.3 Figure of MR32 and MR40 DQ C alibration timing example: RL = 3, tMRR = 2

CK_t / CK_c

CA0-9

[Cmd]

DQS_t

DQS_c

DQ[0]

DQ[7:1]

DQ[8]

DQ[16]

DQ[24]

DQ[15:9]

DQ[23:17]

DQ[31:25]

T0 T1 T2 T3 T4 T5 T6 T7 T8

x16

x32

Pattern “A”Pattern “B”

RL=3

tMRR=2 tMRR=2

CMD not allowed Optionally driven the same as DQ0 or to 0b

Reg 32 Reg 32 Reg 40 Reg 40

MRR40

MRR32

11 1 1

1 1 11

1 1

0 0 0 0

0000

0 0 0 0

NOTE : 1. Mode Register Read has a burst length of four.

2. Mode Register Read operation shall not be interrupted.

3. Mode Register Reads to MR32 and MR40 drive valid data on DQ[0] during the entire burst. For x32 devices, DQ[8], DQ[16], and

DQ[24] shall drive the same information as DQ[0] during the burst.

4.For x8 devices, DQ[7:1] may optionally drive the same information as DQ[0] or they may drive 0b during the burst. For x32 devices,

DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] may optionally drive the same information as DQ[0] or they may drive 0b during the

burst.

5. The Mode Register Command period is tMRR. No command (other than Nop) is allowed during this period.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 58 - Revision : P01-004A

6.4.22 Mode Register Write Command

The Mode Register Write command is used to write configuration data to mode registers. The Mode Register Write

(MRW) command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 LOW at the rising

edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r-CA4r}. The data to be written to the mode

only registers shall have no impact on the f unct i onality of the devi ce.

For LPDDR2-S4 devices, the MRW may only be issued when all banks are in the idle precharge state. One method

of ensuring that the banks are in the idle prec harge state is to issue a Precharge-All command

6.4.22.1 Figure of Mode Register Write timing ex ample : RL = 3, tMRW = 5

CMD not allowed

CA0-9

[Cmd]

CK_t / CK_c

T0 Tx Tx + 1 Tx + 2 Ty + 1 Ty + 2

MRW MRW ANY

MR Addr MR Data MR Data

MR Addr

tMRW

Note :1. The Mode Register Write Command period is tMRW. No command (other than Nop )is allowed during this period

2. At time Ty, the device is in the idle state

6.4.22.2 Truth Table for Mode Register Read (MRR) and Mode Register Write (MRW)

Current State Command Intermediate State Next State

All Banks Idle

MRR Mode Register Reading (All Banks Idle) All Banks Idle

MRW Mode Register Writing (All Banks Idle) All Banks Idle

MRW (RESET) Resetting (Device Auto-Init) All Banks Idle

Bank(s) Active

MRR Mode Register Reading (Bank(s) Active) Bank(s) Active

MRW Not Allowed Not Allowed

MRW (RESET) Not Allowed Not Allowed

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 59 - Revision : P01-004A

6.4.23 Mode Register Write Reset (MRW Reset)

Any MRW command issued to MRW63 ini tiates an MRW Reset. The MRW Reset comm and brings the device to the

Device Auto-Initialization (Resetting) State in the Power-On Initialization sequence. The MRW Reset command may

be issued from the Idle state for LPDDR2-S4 devices. This command resets all Mode Registers to their default

values. No commands other than NOP may be issued to the LPDDR2 device during the MRW Reset period (tINIT4).

After MRW Reset, boot timings must be observed until the device initialization sequence is complete and the device

is in the Idle state. Array data for LPDDR2-S4 devices are undefined after the MRW Reset command.

6.4.24 Mode Register Write ZQ Calibration Command

The MRW command is also used to initiate the ZQ Calibration command. The ZQ Calibration command is used to

calibrate the LPDDR2 ouput drivers (RON) over process, temperature, and voltage. LPDDR2-S4 devices support

ZQ Calibration.

There are four ZQ Calibration commands and related timings times, tZQINIT, tZQRESET, tZQCL, and tZQCS.

tZQINIT corresponds to the initialization calibration, tZQRESET for resetting ZQ setting to default, tZQCL is for long

calibration, and tZQCS is for short cali bration.

The Initialization ZQ Calibration (ZQINIT) shall be performed for LPDDR2-S4 devices. This Initialization Calibration

achieves a RON accuracy of +/-15%. After initialization, the ZQ Long Calibration may be used to re-calibrate the

system to a RON accuracy of +/-15%. A ZQ Short Calibration may be used periodically to compensate for

temperature and v ol tage drift in the system .

The ZQReset Command resets the RON calibration to a default accuracy of +/-30% across process, voltage, and

temperature. Thi s command is used to ensure RON accuracy t o +/-30% when ZQCS and ZQCL are not used.

One ZQCS command can effectively correct a minimum of 1.5% (ZQCorrection) of RON impedance error within

tZQCS for all speed bins assuming the maximum sensitivities specified in the ‘Output Driver Voltage and

Temperature Sensitivity’. The appropriate interval between ZQCS commands can be determined from these tables

and other application-specific paramet ers.

One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage

(Vdriftrate) drift rates that the LPDDR2 is subject to in the application, is illustrated. The interval could be defined by

the following formula:

where TSens = max(dRONdT) and VSens = max(dRONdV) define the LPDDR2 temperature and voltage

sensitivities.

For example, if TSens = 0.75% / oC, VSens = 0.20% / mV, Tdriftrate = 1 oC / sec and Vdriftr ate = 15 mV / sec, then

the interval bet ween ZQCS commands is calculated as:

For LPDDR2-S4 devices, a ZQ Calibration command may only be issued when the device is in Idle state with all

banks precharged.

No other activities can be performed on the LPDDR2 data bus during the calibration period (tZQINIT, tZQCL,

tZQCS). The quiet time on the LPDDR2 data bus helps to accurately calibrate RON. There is no required quiet time

after the ZQ Reset command. If multiple devices share a single ZQ Resistor, only one device may be calibrating at

any given time. After calibration is achieved, the LPDDR2 device shall disable the ZQ ball’s current consumption

path to reduce pow er.

In systems that share the ZQ resistor between devices, the controller must not allow overlap of tZQINIT, tZQCS, or

tZQCL between the devices. ZQ Reset overlap is allowed. If the ZQ resistor is absent from the system, ZQ shall be

connected to VDDCA. In this case, the LPDDR2 device shall ignore ZQ calibration commands and the device will

use the default cali brat i on settings.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 60 - Revision : P01-004A

6.4.24.1 Figure of ZQ Calibration Initialization timing example

CK_t / CK_c

CA0-9

[Cmd]

T0 T1 T2 T3 T4 T5 Tx Tx+1 Tx+2

tZQINIT

CMD not allowed

MRW ANY

MR Addr MR Data

Note 1. The ZQ Calibration Initialization period is tZQINIT. No command (other than Nop) is allowed during this period.

2. CKE must be continuously registered HIGH during the calibration period.

3. All devices connected to the DQ bus should be high impedance during the calibration process.

6.4.24.2 Figure of ZQ Calibration Short timing exam ple

CK_t / CK_c

CA0-9

[Cmd]

T0 T1 T2 T3 T

4 T5 Tx Tx+1 Tx+2

tZQCS

CMD not allowed

MRW ANY

MR Addr MR Data

Note 1. The ZQ Calibration Short period is tZQCS. No command (other than Nop) is allowed during this period.

2. CKE must be continuously registered HIGH during the calibration period.

3. All devices connected to the DQ bus should be high impedance during the calibration process.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 61 - Revision : P01-004A

6.4.24.3 Figure of ZQ Calibrat i on Long timing examp le

CK_t / CK_c

CA0-9

[Cmd]

T0 T1 T2 T3 T4 T5 Tx Tx+1 Tx+2

tZQCL

CMD not allowed

MRW ANY

MR Addr MR Data

Note 1. The ZQ Calibration Long period is tZQCL. No command (other than Nop) is allowed during this period.

2. CKE must be continuously registered HIGH during the calibration period.

3. All devices connected to the DQ bus should be high impedance during the calibration process.

6.4.24.4 Figure of ZQ Calibrat i on Reset timing example

CK_t / CK_c

CA0-9

[Cmd]

T0 T1 T2 T3 T4 T5 Tx Tx+1 Tx+2

tZQRESET

CMD not allowed

MRW ANY

MR Addr MR Data

Note 1. The ZQ Calibration Reset period is tZQRESET. No command (other than Nop) is allowed during this period

2. CKE must be continuously registered HIGH during the calibration period.

3. All devices connected to the DQ bus should be high impedance during the calibration process.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 62 - Revision : P01-004A

6.4.25 ZQ External Resi st or Value, Toleranc e, and Capacitive Loading

To use the ZQ Calibration function, a 240 Ohm +/- 1% tolerance external resistor must be connected between the

ZQ pin and ground. A single resistor can be used for each LPDDR2 device or one resistor can be shared between

multiple LPDDR2 devices if the ZQ calibration timings for each LPDDR2 device do not overlap. The total capacitive

loading on the Z Q pi n m ust be limited.

6.4.26 Power-down

For LPDDR2 SDRAM, power-down is synchronously entered when CKE is registered LOW and CS_n HIGH at the

rising edge of clock. CKE must be registered HIGH in the previous clock cycle. A NOP command must be driven in

the clock cycle following the power-down command. CKE is not allowed to go LOW while mode register, read, or

write operations are in progress. CKE is allowed to go LOW while any of other operations such as row activation,

precharge, autoprecharge, or refresh is in progress, but power-down IDD spec will not be applied until finishing

those operations.

For LPDDR2 SDRAM, if power-down occurs when all banks are idle, this mode is referred to as idle power- down; if

power-down oc cur s when there is a row act ive in any bank, this mo de is ref erred to as active pow er-down.

Entering power-down deactivates the input and output buffers, excluding CK_t, CK_c, and CKE. In power-down

mode, CKE must be maintained LOW while all other input signals are “Don’t Care”. CKE LOW must be maintained

until tCKE has been sat isfied. VREF must be m ai ntained at a valid l evel during power down.,

VDDQ may be turned off during power down. If VDDQ is turned off, then VREFDQ must also be turned off. Prior to

exiting power down, both VDDQ and VRE F DQ m ust be within their res pective min/max oper ating ranges.

For LPDDR2 SDRAM, the maximum duration in power-down mode is only limited by the refresh requirements, as

no refresh operati ons are performed in power-down mode.

The power-down state is exited when CKE is registered HIGH. The controller shall drive CS_n HIGH in conjunction

with CKE HIGH when exiting the power-down state. CKE HIGH must be maintained until tCKE has been satisfied. A

valid, executabl e command can be appli ed with power-down exit l atency, tXP after CKE goes HIGH.

6.4.26.1 Figure of LPDDR2-S4 : Basic power down entry and exit t iming diagram

CK(min)

IHCKE

CKE(min)

ISCKE

IHCKE

Valid Enter

PD NOP Valid

Exit

Input clock frequency may be changed

or the input clock stopped during Power-Down

Enter Power-Down mode Exit Power-Down mode

XP(min)

ISCKE

CKE

[CMD]

CK_c

CK_t

CS_n

cKE(min)

Valid

NOP

Note :1. Input clock frequency may be changed or the input clock stopped during power-down, provided that upon exiting power-down, the clock

is stable and within specified limits for a minmum of 2 clock cycles prior to power-down exit and the clock frequency is between the

minimum and maximum frequency for the particular speed grade

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 63 - Revision : P01-004A

6.4.26.2 Figure of Example of CKE intensive environment

CKE

tCKE

CK_c

CK_t

6.4.26.3 Figure of Refresh to Refresh timing with CKE intensive environment for LPD R2 SDRAM

CKE tCKE

tCKE

[Cmd]

tXP tXP

tREFI

REF

CK_c

CK_t

Note : The pattern shown above can repeat over a long period of time. With this pattern, LPDDR2 SDRAM guarantees all AC and DC timing &

voltage specifications with temperature and voltage drift

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 64 - Revision : P01-004A

6.4.26.4 Figure of Read to power – down entry

T0 T1 T2 Tx Tx+1 Tx+2 Tx+9

Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8

Tx+9Tx+8Tx+7Tx+6Tx+5Tx+4Tx+3Tx+2Tx+1

TxT2T1T0

tISCKE

Q Q Q Q

Read operation starts with a read command and

CKE should be kept HIGH until the end of burst operation.

CKE

[Cmd]

CKE

[Cmd]

CK_c

CK_t

DQS_t

DQS_c

DQS_t

DQS_c

Note : CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1 clock cycles after the clock on which the Read command is

registered

6.4.26.5 Figure of LPDDR2 SDRAM Read with auto precharge to power-down entry

T0 T1 T2 Tx Tx+1 Tx+2 Tx+9Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8

QQQQ

QQQQ Q Q Q Q

RDA

RDA PRE

PRE

Tx+9Tx+8Tx+7Tx+6Tx+4 Tx+5Tx+3Tx+2Tx+1

TxT2T1

[Cmd]

CKE

[Cmd]

CKE should be kept HIGH

until the end of burst operation.

CKE should be kept HIGH

until the end of burst operation.

BL = 4

BL = 8

Start internal precharge

BL/2

With tRTP = 7.5ns

& tRAS min satisfied

BL/2

With tRTP = 7.5ns

& tRAS min satisfied

ISCKE

CK_c

CK_t

DQS_t

DQS_c

DQS_t

DQS_c

Note : CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK)+ BL/2 + 1 clock cycles after the clock on which the Read command is

registered

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 65 - Revision : P01-004A

6.4.26.6 Figure of Write to power-down entry

BL = 4

D D D D

DDD

BL = 8

ISCKE

[Cmd]

CKE

[Cmd]

CKE

T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx+6Tx Tx+1 Tx+2 Tx+4 Tx+5

Tx+2 Tx+3 Tx+4Tx+1TxTm+5Tm+4Tm+3Tm+2

Tm+1

T1T0

CK_c

CK_t

DQS_t

DQS_c

DQS_t

DQS_c

Tx+3

Note : CKE may be registered LOW WL + 1 + BL/2 + RU(tWR/tCK)clock cycles after the clock on which the Write command is registered

6.4.26.7 Figure of LPDDR2-S4: Writ e with autoprecharge to power-down entry

WRA

BL = 4

D D D D

DDD

WRA

BL = 8

ISCKE

[Cmd]

CKE

[Cmd]

CKE

T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx Tx+1 Tx+2

Tx+2 Tx+3 Tx+4

Tx+1Tx

Tm+5Tm+4

Tm+3

Tm+2

Tm+1

TmT1

Tx+3 Tx+4 Tx+5 Tx+6

PRE

Start Internal Precharge

CK_c

CK_t

CK_c

CK_t

DQS_t

DQS_c

DQS_t

DQS_c

Note : CKE may be registered LOW WL + 1 + BL/2 + RU(tWR/tCK) + 1 clock cycles after the Write command is registered

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 66 - Revision : P01-004A

6.4.26.8 Figure of LPDDR2-S4 Refresh c ommand to power-down entry

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

REF

IHCKE

ISCKE

CKE

[Cmd]

CK_c

CK_t

Note : CKE may go LOW tIHCKE after the clock on which the Refresh command is registered

6.4.26.9 Figure of Activate command to power -down entry

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

ACT

IHCKE

ISCKE

CKE

[Cmd]

CK_c

CK_t

Note : CKE may go LOW tIHCKE after the clock on which the Activate command is registered

6.4.26.10 Figure of Precharge/Precharge-all command to p ower-down entry

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

PRE

IHCKE

ISCKE

CKE

[Cmd]

CK_c

CK_t

Note : CKE may go LOW tIHCKE after the clock on which the Preactive/Precharge/Precharge-All command is registered

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 67 - Revision : P01-004A

6.4.26.11 Figure of Mode Register Read to power-down entry

T0 T1 T2 Tx Tx+1 Tx+2 Tx+9

Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8

RL t

ISCKE

MRR

Q Q Q Q

Mode Register Read operation starts with a MRR command and

CKE should be kept HIGH until the end of burst operation.

CK_c

CK_t

DQS_t

DQS_c

[Cmd]

CKE

Note : CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK)+ BL/2 + 1 clock cycles after the clock on which the Mode Register Read

command is registered

6.4.26.12 Figure of MRW command to power-down entry

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

MRW

ISCKE

CKE can go to LOW tMRW after a Mode Register Write command

CKE

[Cmd]

tMRW

CK_c

CK_t

Note : CKE may be registered LOW tMRW after the clock on which the Mode Register Write command is registered

6.4.27 LPDDR2-S4: Deep Powe r-Down

Deep Power-Down is entered when CKE is registered LOW with CS_n LOW, CA0 HIGH, CA1 HIGH, and CA2 LOW

at the rising edge of clock. A NOP command must be driven in the clock cycle following the power-down command.

CKE is not allowed to go LOW while mode register, read, or write operations are in progress.All banks must be in

idle state with no activity on the data bus prior to entering the Deep Power Down mode. During Deep Power-Down,

CKE must be held LOW.

In Deep Power-Down mode, all input buffers except CKE, all output buffers, and the power supply to internal

circuitry may be disabled within the SDRAM. All power supplies must be within specified limits prior to exiting Deep

Power-Down. VrefDQ and VrefCA may be at any level within minimum and maximum levels (See "Absolute

Maximum DC Ratings"). However prior to exiting Deep Power-Down, Vref must be within specified limits (See

"Recommended DC Ope rating Conditions").

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 68 - Revision : P01-004A

The contents of the SDRAM may be lost upon entry into Deep Power-Down mode.

The Deep Power-Down state is exited when CKE is registered HIGH, while meeting tISCKE with a stable clock

input. The SDRAM must be fully re-initialized by controller as described in the Power up initialization Sequence. The

SDRAM is ready for normal operation after the initialization seq uence.

6.4.27.1 Figure of LPDDR2-S4 Deep power down entry and exit timing diagram

2 t

CK(min)

DPD

ISCKE

IHCKE

NOP Enter

DPD NOP Reset

Exit

Input clock frequency may be changed

or the input clock stopped during Deep Power-Down

Enter Deep Power-Down mode Exit Deep Power-Down mode

ISCKE

CKE

[Cmd]

CS_n

NOP

INIT3

=200us

(min)

NOP

CK_c

CK_t

Note :1. Initialization sequence may start at any time after Tc.

2. tINIT2, tINIT3, and Tc refer to timings in the LPDDR2 initialization sequence. For more detail, see “Power- up, Initialization, and

Power-down”.

3. Input clock frequency may be changed or the input clock stopped during deep power-down, provided that upon exiting deep power-

down, the clock is stable and within specified limits for a minmum of 2 clock cycles prior to deep power-down exit and the clock

frequency is between the minimum and maximum frequency for the particular speed grade

6.4.28 Input clock stop and frequency change

LPDDR2 devices support input clock fre quency change during CKE LOW under the foll owing conditions:

• tCK(MIN) and tCK(MAX) are met for each clock cycle;

• Refresh Requirements apply during cl ock frequency change;

• During clock frequency change, only REFab or REFpb command s m ay be executing;

• Any Activate, or Precharge commands have executed t o compl etion prior to changing the frequency;

• The related tim i ng conditions (tRCD, tRP) hav e been met prior to changing the frequency;

• The initial clock frequency shall be maint ai ned for a minimum of 2 clock cycles after CKE goes LOW;

• The clock sati sf i es t CH(abs) and tCL(a bs) f or a minimum of 2 clo ck cycles prior to CKE goi ng HIGH.

After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may be required to

set the WR, RL etc. These settings may need to be adjusted to meet minimum timing requirements at the target

clock frequency.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 69 - Revision : P01-004A

LPDDR2 devices su pport clock stop duri ng CKE LOW under the following conditions:

• CK_t is held LOW and CK_c is held HIGH du ri ng clock stop;

• Refresh Requirements apply during cl ock stop;

• During clock stop, onl y REFab or REFpb commands may be exe cut i ng;

• Any Activate, or Precharge commands have executed t o compl etion prior to stoppin g the clock;

• The related timi ng conditions (tRCD, tRP) have been met prior to st opping the clock;

• The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW;

• The clock sati sf i es t CH(abs) and tCL(a bs) f or a minimum of 2 clo ck cycles prior to CKE going HI GH.

LPDDR2 devices su pport input clock fre quency change during CK E HIGH under the foll owing conditions:

• tCK(MIN) and tCK(MAX) are met for each clock cycle;

• Refresh Requirements apply during cl ock frequency change;

• Any Activate, Read, Write, Precharge, Mode Register Write, or Mode Register Read commands must have

executed to compl etion, including any associated data burst s prior to changing t he frequency;

• The related timing conditions (tRCD, tWR, tWRA, tRP, tMRW, tMRR, etc.) have been met prior to changing the

frequency;

• CS_n shall be held HIGH during clock freque ncy change;

• During clock frequency change, only REFab or REFpb command s m ay be executing;

• The LPDDR2 device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs) for a minimum of

2tCK + tXP.

After the input clock frequency is changed, additional MRW commands may be required to set the WR, RL etc.

These settings may need to be adjusted to m eet minimum timing requirements at the target clock frequency.

LPDDR2 devices su pport clock stop duri ng CKE HIGH under the following conditions:

• CK_t is held LOW and CK_c is held HIGH du ri ng clock stop;

• CS_n shall be held HIGH during clock clock stop;

• Refresh Requirements apply during cl ock stop;

• During clock stop, onl y REFab or REFpb commands may be executing;

• Any Activate, Read, Write, Precharge, Mode Register Write, or Mode Register Read commands must have

executed to compl etion, including any associated data burst s prior to stopping the clock;

• The related timing conditions (tRCD, tWR, tWRA, tRP, tMRW, tMRR, etc.) have been met prior to stopping the

clock;

• The LPDDR2 device is ready for normal operation after the clock is restarted and satisfies tCH(abs) and tCL(abs)

for a minimum of 2tCK + tXP.

6.4.29 No Operation command

The purpose of the No Operation command (NOP) is to prevent the LPDDR2 device from registering any unwanted

command between operations. Only when the CKE level is constant for clock cycle N-1 and clock cycle N, a NOP

command may be i ssu ed at clock cycle N. A NOP command has two possibl e encodings:

1. CS_n HIGH at t he clock rising edge N.

2. CS_n LOW and CA0, CA1, CA2 HIGH at the clock rising edge N.

The No Operation command will not terminate a previous operation that is still executing, such as a burst read or

write cycle.

6.4.30 Truth tables

Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation,

the LPDDR2 device must be powered down and then restarted through the specified initialization sequence before

normal operat i on can continue.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 70 - Revision : P01-004A

6.4.31 Command trut h table

Command

Command Pins DDR CA pins (10)

EDGE

CKE CS_N CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CK_t(n-1) CK_t(n)

MRW H H L L L L L MA0 MA1 MA2 MA3 MA4 MA5

X MA6 MA7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7

MRR H H L L L L H MA0 MA1 MA2 MA3 MA4 MA5

X MA6 MA7 X

Refresh

(per bank)11 H H L L L H L X

X X

Refresh

(all bank) H H L L L H H X

X X

Enter

Self Refresh

H L L L L H X

X X X

Activate

(bank) H H L L H R8 R9 R10 R11 R12 BA0 BA1 BA2

X R0 R1 R2 R3 R4 R5 R6 R7 R13 R14

Write

(bank) H H L H L L RFU RFU C1 C2 BA0 BA1 BA2

X AP3,4 C3 C4 C5 C6 C7 C8 C9 C10 C11

Read

(bank) H H L H L H RFU RFU C1 C2 BA0 BA1 BA2

X AP3,4 C3 C4 C5 C6 C7 C8 C9 C10 C11

Precharge

(per bank, all b ank) H H L H H L H AB X X BA0 BA1 BA2

X X

BST H H L H H L L X

X X

Enter Deep

Power Down

H L L H H L X

X X X

NOP H H L H H H X

X X

Maintain PD,

SREF,DPD(NOP) L L L H H H X

X X

NOP H H H X

X X

Maintain PD,

SREF,DPD(NOP) L L H X

X X

Enter

Power Down

H L H X

X X X

Exit PD,

SREF,DPD

L H H X

X X X

Note :1. All LPDDR2 commands are defined by states of CS_n, CA0, CA1, CA2, CA3, and CKE at the rising edge of the clock.

2. For LPDDR2 SDRAM, Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon.

3. AP is significant only to SDRAM.

4. AP “high” during a READ or W RITE command indicates that an auto-precharge will occur to the bank as sociated with the READ or

WRITE command.

5. “X” means “H or L (but a defined logic level)”

6. Self refresh exit and Deep Power Down exit are asynchronous.

7. VREF must be between 0 and VDDQ during Self Refresh and Deep Power Down operation.

8. CAxr refers to command/address bit “x” on the rising edge of clock.

9. CAxf refers to command/address bit “x” on the falling edge of clock.

10. CS_n and CKE are sampled at the rising edge of clock.

11. Per Bank Refresh is only allowed in devices with 8 banks.

12. The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero.

13. AB “high”during Precharge command indicates that all bank Precharge will occur. In this case, Bank Address is do-not-care.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 71 - Revision : P01-004A

6.4.32 LPDDR2-SDRAM Truth Tables

The truth tables provide complementary information to the state diagram, they clarify the device behavior and the

applied restrict ions when considering the actual state of al l the Banks.

6.4.32.1 Table of LPDDR2-S4 : CKE Table

Note :1. “CKEn” is the logic state of CKE at clock rising edge n; “CKEn-1” was the state of CKE at the previous clock edge.

2. “CS_n” is the logic state of CS_n at the clock rising edge n;

3. “Current state” is the state of the LPDDR2 device immediately prior to clock edge n.

4. “Command n” is the command registered at clock edge N, and “Operation n” is a result of “Command n”.

5. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.

6. Power Down exit time (tXP) should elapse before a command other than NOP is issued.

7. Self-Refresh exit time (tXSR) should elapse before a command other than NOP is issued.

8.The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Func tional

Description.

9. The clock must toggle at least once during the tXP period.

10. The clock must toggle at least once during the tXSR time.

11. X’ means ‘Don’t care’.

12. Upon exiting Resetting Power Down, the device will return to the Idle state if tINIT5 has expired.

Device Current State

CKEn-1

CKEn

CS_n

Command n

Operation n

Device Next State Note

Active Power Down

Maintain Ac tive Pow er Dow n

Active Power Down

NOP

Exit Active Power Down Active

6, 9

Idle Power Down

Maintain Idle Pow er Dow n

Idle Pow er Down

NOP

Exit Idle Pow er Dow n Idle

6, 9

Resetting Power

Down

Maintain Resetting Power Down

Resetting Power Down

NOP

Exit Resetting Power Down Idle or Resetting

6, 9, 12

Deep Power Down

(DPD)

Maintain Deep Power Down

Deep Power Dow n

NOP

Exit Deep Power Down Power On

Self Refresh

Maintain Self Refresh

Self Refresh

NOP

Exit Self Refresh Idle

7, 10

Bank(s) Active

NOP

Enter Active Power Down

Active Power Down

All Banks Idle

NOP

Enter Idle Power Down Idle Power D ow

Self-Refresh

Enter Self Refresh

Self Refresh

DPD

Enter Deep Power Down Deep Pow er Dow n

Resetting

NOP

Enter Resetting Power Down

Resetting Power Down

Others states

Refer to the Command Truth Table

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 72 - Revision : P01-004A

6.4.32.2 Table of Current State Bank n - Com m and to Bank n

Current

State Command Operation Next State Note

Any NOP Continue previous operation Current State

Idle

ACTIVATE Select and activate row Active

Refresh (Per Bank) Begin to refresh Refreshing (Per Bank) 6

Refresh (All Bank) Begin to refresh Refreshing(All Bank ) 7

MRW Load value to Mode Regis ter MR Writing 7

MRR Read value from Mode Regis ter Idle MR Reading

Reset Begin Device Auto-Initialization Resetting 7, 8

Precharge D eac tivate row in bank or banks Precharging 9, 15

Row

Active

Read Select col um n, and start read burst Reading

Write Select column, an d s tar t write burst Writing

MRR Read value from Mode Regis ter Active M R Reading

Precharge Deactivate row in bank or banks Precharging 9

Reading

Read Select col um n, and start new read bu r s t Reading 10, 11

Write Select column, an d s tar t write burst Writing 10, 11, 12

BST Read burst terminate Active 13

Writing

Write Select column, an d s tar t new write bur s t Writing 10, 11

Read Select col um n, and start read burst Reading 10, 11, 14

BST Write burst terminate Active 13

Power On Reset Begin Device Auto-Initialization Resetting 7, 9

Resetting MRR Read value from Mode Regi ster R ese tting MR Reading

Note : 1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Power

Down.

2. All states and sequences not shown are illegal or reserved.

3. Current State Definitions:

Idle: The bank or banks have been precharged, and tRP has been met.

Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accessesare in

progress.

Reading: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Writing: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

4.The following states must not be interrupted b y a command i ssued to the same b ank. NOP comm ands or all owable commands to the

other bank should be issued on any clock edge occurring during these states. Allowable commands to the other banks are

determined by its current state, and according to Table of Current State Bank n - Command to Bank m.

Precharging: starts with the registration of a Precharge c ommand an d ends when tRP is met. Once tRP i s met, the bank will be in the

idle state.

Row Activating: starts with regis tration of an Activate command and ends when tRCD is met. Once tRCD i s met, the bank will be in

the ‘Active’ state.

Read with AP Enabled: starts with the registration of the Read com m and with Auto Precharge enabl ed and ends when tRP has bee n

met. Once tRP has been met, the bank will be in the idle state.

Write with AP Enabled: starts with registration of a Wri te command with Auto Precharge enabled and ends when tRP has been met.

Once tRP is met, the bank will be in the idle state.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 73 - Revision : P01-004A

5. The following states must not be interrupted by any executable command; NOP commands must be applied to each positive clock

edge during these states.

Refreshing (Per Bank): starts with registration of an Refresh (Per Bank) command and ends when tRFCpb is met. Once tRFCpb is

met, the bank will be in an ‘idle’ state.

Refreshing (All Bank): starts with registration of an Refresh (All Bank) command and ends when tRFCab is met. Once tRFCab is

met, the device will be in an ‘all banks idle’ state.

Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met,

the bank will be in the Idle state.

Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been

met, the bank will be in the Resetting state.

Active MR Reading: starts with the registration of a MRR c ommand and ends when tMRR has be en met. Once tMR R has been met,

the bank will be in the Active state.

MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met, the

bank will be in the Idle state.

Precharging All: starts with the registration of a Precharge-All command and ends when tRP is met. Once tRP is met, the bank will

be in the idle state.

6. Bank-specific; requires that the bank is idle and no bursts are in progress.

7. Not bank-specific; requires that all banks are idle and no bursts are in progress.

8. Not bank-specific reset command is achieved through Mode Register Write command.

9. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for pre- charging.

10. A command other than NOP should not be issued to the same bank while a Read or Write burst with Auto Precharge is enabled.

11. The new Read or Write command could be Auto Precharge enabled or Auto Precharge disabled.

12. A Write command may be applied after the compl etion of the Read burst; otherwise, a BST must be used to end the Read prior t o

asserting a Write command.

13. Not bank -specific. Burst Term inate (BST) command affec ts the most recent r ead/write burst started b y the most recent Read/ Write

command, regardless of bank. A Read command may be applied after the completion of the Write burst; othe r- wise, a BST must

be used to end the Write prior to asserting a Read command.

14. A Read command may be applied after the co mpletion of the Write burst; othe rwise, a BST must be used to end the Wri te prior t o

asserting a Read command.

15. If a Precharge command is issued to a bank in the Idle state, tRP shall still apply.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 74 - Revision : P01-004A

6.4.32.3 Tableof Current State Bank n - Comm and to Bank m

Current State of

Bank n

Command

for

Bank m Operation Next State for

NOTES

Bank m

Note

Any NOP Continue previous operation Current State of Bank m

Idle Any Any command allowed to Bank m - 18

Row Activa t ing ,

Active, or

Precharging

Activate Select and activate row in Bank m Active 7

Read Select column, and start read burst from Bank m Reading 8

Write Select column, and start write burst to Bank m Writing 8

Precharge Deactivate row in bank or banks Precharging 9

MRR Read value from Mode Regis ter Idle MR Reading or

Active MR Readin 10, 11,

BST Read or Write burst terminate an ongoing

Read/Write from/to Bank m Active 18

Reading

(Autoprecharge

disabled)

Read Select column, and start read burst from Bank m Reading 8

Write Select column, and start write burst to Bank m Writing 8, 14

Activate Select and activate row in Bank m Active

Precharge Deactivate row in bank or banks Precharging 9

Writing

(Autoprecharge

disabled)

Read Select column, and start read burst from Bank m Reading 8, 16

Write Select column, and start write burst to Bank m Writing 8

Activate Select and activate row in Bank m Active

Precharge Deactivate row in bank or banks Precharging 9

Reading with

Autoprecharge

Read Select column, and start read burst from Bank m Reading 8, 15

Write Select column, and start write burst to Bank m Writing 8, 14, 15

Activate Select and activate row in Bank m Active

Precharge Deactivate row in bank or banks Precharging 9

Writing with

Autoprecharge

Read Select column, and start read burst from Bank m Reading 8, 15, 16

Write Select column, and start write burst to Bank m Writing 8, 15

Activate Select and activate row in Bank m Active

Precharge Deactivate row in bank or banks Precharging 9

Power On Reset Begin Device Auto-Initialization Resetting 12, 17

Resetting MRR Read value from Mode Register Resetting MR Reading

Note : 1.The table applies when both CKEn-1 and CKEn are HIGH, and afte r tXSR or tXP has be en met i f the p revious state was Self Refre s h

or Power Down.

2. All states and sequences not shown are illegal or reserved.

3. Current State Definitions:

Idle: the bank has been precharged, and tRP has been met.

Active: a row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in

progress.

Reading: a Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Writing: a Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 75 - Revision : P01-004A

4. Refresh, Self-Refresh, and Mode Register Write commands may only be issued when all bank are idle.

5. A Burst Terminate (BST) command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. The following states mus t not be interrupted by any executable command; NOP commands mus t be applied during each clock c ycle while

in these states:

Idle MR Reading: starts with the regis tration of a MRR c ommand and ends when t MRR has been met. Once tMR R has been met, the bank

will be in the Idle state.

Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has

been met, the bank will be in the Resetting state.

Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the

bank will be in the Active state.

MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met, the bank will

be in the Idle state.

7. tRRD must be met between Activate command to Bank n and a subsequent Activate command to Bank m.

8. Reads or Writes listed in the Command column include Reads and Writes with Auto Precharge enabled and Reads and Writes with Auto

Precharge disabled.

9. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for pre- charging.

10. MRR is allo wed during the Row Activating s tate (Row Activating starts with regis tration of an Activate command and ends when tRCD is

met.)

11. MRR is allowed during the Precharging state. (Precharging starts with registration of a Precharge command and ends when tRP is met.

12. Not bank-specific; requires that all banks are idle and no bursts are in progress.

13. The next state for Bank m depends on the current state of Bank m (Idle, Row Activating, Precharging, or Active). The reader shall note

that the state may be in transition when a MRR is issued. Therefore, if Bank m is in the Row Activating state and Precharging, the next

state may be Active and Precharge dependent upon tRCD and tRP respectively.

14. A Write command may be applied after the completion of the Read burst, otherwise a BST must be issued to end the Read prior to

asserting a Write command.

15. Read with auto precharge enabled or a Write with auto precharge enabled may be followed by any valid command to other banks provided

that the timing restrictions of auto precharge are followed.

16. A Read command may be applied after the completion of the Write burst; otherwise, a BST must be issued to end the Write prior to

asserting a Read command.

17. Reset command is achieved through Mode Register Write command.

18. BST is allowed only if a Read or Write burst is ongoing.

6.4.33 Data mask truth table

Table below provides the data mask truth table.

Name (Functional) DM DQs Note

Write enable L Valid 1

Write inhibit H X 1

Note : Used to mask write data, provided coincident with the corresponding data

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 76 - Revision : P01-004A

7. ELECTRICAL CHARACTERISTIC

7.1 Absolute Maximum DC Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and

functional operation of the device at these or any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

reliability.

Parameter Symbol Min Max Units Notes

VDD1 supply voltage relative to VSS VDD1 -0.4 +2.3 V 2

VDD2 supply voltage relative to VSS VDD2 -0.4 +1.6 V 2

VDDCA supply voltage relative to VSSCA VDDCA -0.4 +1.6 V 2,4

VDDQ supply voltage relative to VSSQ VDDQ -0.4 +1.6 V 2,3

Voltage on any ball relative to VSS VIN, VOUT -0.4 +1.6 V

Storage Temperature TSTG -55 +125 °C 5

Note :1. Stresses greater than those listed under “Absolute Maximum Ratings” ma y cause permanent damage to the device. This is a stress

rating only and functional operation of the d ev ic e at these or a n y o ther conditi ons a bov e those i ndic ated in the ope ra tional sections of

this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability

2. See “Power-Ramp” section in “Power-up, Initialization, and Power-Off” for relationships between power supplies.

3. VREFDQ ≦ 0.6 x VDDQ; however, VREFDQ may be ≧VDDQ provided that VREFDQ ≦300mV.

4. VREFCA ≦ 0.6 x VDDCA; however, VREFCA may be ≧VDDCA provided that VREFCA ≦ 300mV.

5.Storage Temperature is the case surface temperature on the center/top side of the LPDDR2 device. For the measurement conditions,

please refer to JESD51-2 standard.

7.2 AC & DC operating conditions

Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation,

the LPDDR2 Device must be powered down and then restarted through the specialized initialization sequence

before normal operation can continue.

7.2.1 Recommended DC Operating Conditions

7.2.1.1 Recom mended DC Operating Conditions

Symbol LPDDR2-S4B DRAM Unit

Min Typ Max

VDD1 1.70 1.80 1.95 Core Power1 V

VDD2 1.14 1.20 1.30 Core Power2 V

VDDCA 1.14 1.20 1.30 Input Buffer Power V

VDDQ 1.14 1.20 1.30 I/O Buffer Power V

Note :1. When VDD2 is used, VDD1 uses significantly less current than VDD2;

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 77 - Revision : P01-004A

7.2.2 Input Leakage Current

Parameter/Condition Symbol Min Max Unit Note

Input Leakage current

For CA, CKE, CS_n, CK_t, CK_c

Any input 0V≦ VIN ≦ VDDCA

(All other pins not under test = 0V)

IL -2 2 uA 2

VREF supply leakage current

VREFDQ = VDDQ/2 or VREFCA = VDDCA/2

(All other pins not under test = 0V)

IVREF -1 1 uA 1

Note :1. The minimum limit requirement is for testing purposes. The leakage current on VREFCA and VREFDQ pins should be minimal.

2. Although DM is for input only, the DM leakage shall match the DQ and DQS_t/DQS_c output leakage specification.

7.2.3 Operating Temperature Conditions

Parameter/Condition Symbol Min Max Unit

Standard TOPER -40 85 ℃

Extended 85 105 ℃

Note :1. Operating Temperature is the case surface temperature on the center/top side of the LPDDR2 device. For the measurement

conditions, please refer to JESD51-2 standard.

2. Some applications require operation of LPDDR2 in the maximum temperature conditons in the Extended Temperature Range

between 85℃ and 105℃ temperature. For LPDDR2 devices, some derating is neccessary to operate in this range. (see the MR4

Device Temperature (MA[7:0] = 04h) table).

3. Either the device temperature rating or the temperature sensor (See “Temperature Sensor” ) may be used to set an appropriate

refresh rate (SDRAM), determine the need for AC timing derating (SDRAM ) and/or monitor the operating temperature (SDRAM).

When using the temperature sensor, the actual device temperature may be higher than the TOPER rating that applies for the

Standard or Extended Temperature Ranges. For example, Tj may be above 85ºC when the temperature sensor indicates a

temperature of less than 85ºC.

7.2.4 AC and DC Input M easurement Levels

7.2.4.1 AC and DC Logic Input Levels for Sin gle-Ended Signals

7.2.4.1.1 Table of Single-Ended AC and DC Input Levels for CA and CS_n Inputs

Symbol Parameter LPDDR2-1066 to LPDDR 2-466 LPDDR2-400 to LPDDR2-200 Unit Note

Min Max Min Max

VIHCA(AC) AC input logic h igh Vref + 0.220 Note 2 Vref + 0.300 Note 2 V 1, 2

VILCA(AC) AC input logic low Note 2 Vref - 0.220 Note 2 Vref - 0.300 V 1, 2

VIHCA(DC) DC input logic high Vref + 0.130 VDDCA Vref + 0.200 VDDCA V 1

VILCA(DC) DC input logic low VSSCA Vref - 0.130 VSSCA Vref - 0.200 V 1

VRefCA(DC) Reference Voltage for CA and

CS_n inputs 0.49 * VDDCA 0.51 * VDDCA 0.49 * VDDCA 0.51 * VDDCA V 3, 4

Note 1. For CA and CS_n input only pins. Vref = VrefCA(DC).

2. See “Overshoot and Undershoot Specifications”

3. The ac peak noise on VRefCA may not allow V RefCA to deviate from VRefCA (DC) by more than +/-1% V DDCA (for reference: ap prox. +/-

12 mV)

4. For reference: approx. VDDCA/2 +/- 12 mV

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 78 - Revision : P01-004A

7.2.4.1.2 Table of Single-Ended AC and DC Input Levels for CKE

Symbol Parameter Min Max Unit Note

VIHCKE CKE Input High Leve l 0.8 * VDDCA Note 1 V 1

VILCKE CKE Input Low Level Note 1 0.2 * VDDCA V 1

Note : See “Overshoot and Undershoot Specifications”

7.2.4.1.3 Table of Single-Ended AC and DC Input Levels for DQ and DM

Symbol Parameter LPDDR2-1066 to LPDDR 2-466 LPDDR2-400 to LPDD R2 -200 Unit Note

Min Max Min Max

VIHDQ(AC) AC input logic h igh Vref + 0.220 Note 2 Vref + 0.300 Note 2 V 1,2

VILDQ(AC) AC input logic low Note 2 Vref - 0.220 Note 2 Vref - 0.300 V 1,2

VIHDQ(DC) DC input logic high Vref + 0.130 VDDQ Vref + 0.200 VDDQ V 1

VILDQ(DC) DC input logic low VSSQ Vref - 0.130 VSSQ Vref - 0.200 V 1

VRefDQ(DC) Reference Voltage for

DQ, DM inputs 0.49 * VDDQ 0.51 * VDDQ 0.49 * VDDQ 0.51 * VDDQ V 3, 4

Note 1. For DQ input only pins. Vref = VrefDQ(DC)

2. See “Overshoot and Undershoot Specifications”

3. The ac peak noise on VRefDQ may not allow VRefDQ to deviate from VRefDQ(DC) by more than +/-1% VDDQ

(for reference: approx. +/- 12 mV)

4. For reference: approx. VDDQ/2 +/- 12 mV

7.2.4.2 Vref Tolerances

The DC tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in.the

Figure below. It shows a valid reference voltage VRef(t) as a function of time. (VRef stands for VRefCA and

VRefDQ likewise). VDD stands for VDDCA for VRefCA and VDDQ for VRefDQ. VRef(DC) is the linear average of

VRef(t) over a very long period of time (e.g. 1 sec) and is specified as a fraction of the linear average of VDDQ or

VDDCA also over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in

Table of Single-Ended AC and DC Input Levels for CA and CS_n Inputs. Furthermore VRef(t) may temporarily

deviate from VRef(DC) by no more than +/- 1% VDD. Vref(t) cannot track noise on VDDQ or VDDCA if this would

send Vref outside t hese specifications.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 79 - Revision : P01-004A

7.2.4.2.1 Figure of Illustration of VRef(DC) tolerance and VRef ac-noise limits

VRef ac-noise VRef (DC)max

VRef (DC)min

VRef (t)

VDD

VSS

VRef (DC)

voltage

time

VDD/2

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent

on VRef.

“VRef “ shall be understood as VRef(DC), as defined in Figure above.

This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or

low level and therefore the time to which setup and hold is measured. Devices will function correctly with

appropriate tim ing deratings with VREF outside these specifi ed l evels so long as:

VREF is maintained between 0.44 x VDDQ (or VDDCA) and 0.56 x VDDQ (or VDDCA) and so long as the controller

achieves the required single-ended AC and DC input levels from instantaneous VREF (see the Single-Ended AC

and DC Input Levels for CA and CS_n Inputs Table and Single-Ended AC and DC Input Levels for DQ and DM)

Therefore, system timing and voltage bu dgets need to account for VRef deviations outside of this range.

This also clarifies that the LPDDR2 setup/hold specification and derating values need to include time and voltage

associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1%

of VDD) are included in LPDDR2 timings and their associated deratings.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 80 - Revision : P01-004A

7.2.4.3 Input Signal

7.2.4.3.1 LPDDR2-466 to LPDDR2-1066 Input Signal

VIL and VIH Levels With Ringback

1.550V

1.200V

0.820V

0.730V

0.624V

0.612V

0.600V

0.588V

0.576V

0.470V

0.380V

0.000V

-0.350V VSS – 0.35V

VSS

VIL(AC)

VIL(DC)

VREF – AC noise

VREF – DC error

VREF + DC error

VREF + AC noise

VIH(DC)

VIH(AC)

VDD

VDD + 0.35V

Minimum VIL and VIH Levels

VIH(AC)

0.820V

0.730V VIH(DC)

0.624V

0.612V

0.600V

0.588V

0.576V

0.470V

0.380V

VIL(DC)

VIL(AC)

Note :1. Numbers reflect nominal values.

2.For CA0-9, CK_t, CK_c, and CS_n, VDD stands for VDDCA. For DQ, DM, DQS_t, and DQS_c, VDD stands for VDDQ.

3. For CA0-9, CK_t, CK_c, and CS_n, VSS stands for VSSCA. For DQ, DM, DQS_t, and DQS_c, VSS stands for VSSQ.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 81 - Revision : P01-004A

7.2.4.3.2 LPDDR2-200 to LPDDR2-400 Input Signal

VIL and VIH Levels With Ringback

1.550V

1.200V

0.900V

0.800V

0.624V

0.612V

0.600V

0.588V

0.576V

0.400V

0.300V

0.000V

-0.350V VSS – 0.35V

VSS

VIL(AC)

VIL(DC)

VREF – AC noise

VREF – DC error

VREF + DC error

VREF + AC noise

VIH(DC)

VIH(AC)

VDD

VDD + 0.35V

Minimum VIL and VIH Levels

VIH(AC)

0.900V

0.800V VIH(DC)

0.624V

0.612V

0.600V

0.588V

0.576V

0.400V

0.300V

VIL(DC)

VIL(AC)

Note :1. Numbers reflect nominal values.

2. For CA0-9, CK_t, CK_c, and CS_n, VDD stands for VDDCA. For DQ, DM, DQS_t, and DQS_c, VDD stands for VDDQ.

3. For CA0-9, CK_t, CK_c, and CS_n, VSS stands for VSSCA. For DQ, DM, DQS_t, and DQS_c, VSS stands for VSSQ.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 82 - Revision : P01-004A

7.2.4.4 AC and DC Logic Input Levels for Diff erential Signal s

7.2.4.4.1 Differential signal definition

Figure of Definition of differential ac-swing and “time above ac-level” tDVAC

VIHDIFF(AC)MIN

Half cycle

Differntial

voltage

VILDIFF(DC)MAX

VILDIFF(AC)MAX

VIHDIFF(DC)MIN

tDVAC time

CK_t-CK_c

DQS_t-DQS_c

tDVAC

0.0

7.2.4.4.2 Differential swing requirements for clock and strobe

Table of Differential AC and DC Inp ut Levels

Symbol Parameter LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200 Unit Note

Min Max Min Max

VIHdiff(dc)

Differential input

high 2 x (VIH(dc) - Vref) Note 3 2 x (VIH(dc) - Vref) Note 3 V 1

VILdiff(dc)

Differential input

logic low Note 3 2 x (Vref - VIL(dc)) Note 3 2 x (Vref - VIL(dc)) V 1

VIHdiff(ac)

Differential input

high ac 2 x (VIH(ac) - Vref) Note 3 2 x (VIH(ac) - Vref)

Note 3 V 2

VILdiff(ac)

Differential input

low ac Note 3 2 x (Vref - VIL(ac)) Note 3 2 x (Vref - VIL(ac)) V 2

Note 1. Used to define a differential signal slew-rate.

2.For CK_t - CK_c use VIH/VIL(ac) of CA and VREFCA; for DQS_t - DQS_c, use VIH/VIL(ac) of D Qs and VREFDQ; if a reduced ac-high

or ac-low level is used for a signal group, then the reduced level applies also here.

3. These values are not defined, ho wever the sing l e-ended si gnals CK_t, CK_c , DQS _t, and DQS_c need to be within the respecti ve l imits

(VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to “Overshoot and

Undershoot Specifications” .

4. For CK_t and CK_c, Vref = VrefCA(DC). For DQS_t and DQS_c, Vref = VrefDQ(DC).

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 83 - Revision : P01-004A

Table of Allowed time before ringback (tDVAC) for CK_t - CK_c and DQS_t - DQS_c

Slew Rate [V/ns] tDVAC [ps]

@ |VIHdiff(ac) or VILdiff(ac)| = 440mV

tDVAC [ps]

@ |VIHdiff(ac) or VILdiff(ac)| = 600m V

> 4.0 175 75

4.0 170 57

3.0 167 50

2.0 163 38

1.8 162 34

1.6 161 29

1.4 159 22

1.2 155 13

1.0 150 0

< 1.0 150 0

7.2.4.5 Single-end ed r equirements for di fferential signals

Each individual component of a differential signal (CK_t, DQS_t, CK_c, or DQS_c) has also to comply with certain

requirements for single-ended signals.

CK_t and CK_c shall meet VSEH(ac)min / VSEL(ac)max in every hal f-cycle.

DQS_t, DQS_c shall meet VSEH(ac)min / VSEL(ac)max in every half-cycle preceeding and following a valid

transition.

Note that the applicable ac-levels for CA and DQ’s are different per speed-bin.

Figure of Single-ended requi rement for different i al signals

VSEL(ac) time

CK_t,CK_

DQS_t, or DQS_c

VSEH(ac)

VDDCA or VDDQ

VSEH(ac)min

VDDCA/2 or VDDQ/2

VSSCA or VSSQ

VSEL(ac)max

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 84 - Revision : P01-004A

Note that while CA and DQ signal requirem ents are with respect to Vref, the single-ended components of differential

signals have a requi rement with respect to VDDQ/2 for DQS and VDDCA /2 for CK; this is nom inal l y the same.

The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended

components of differential signals the requirement to reach VSEL(ac)max, VSEH(ac)min has no bearing on timing,

but adds a restri ct i on on the common mode characteristics of these signals.

The signal ended requi rements for CK and DQS are found i n tables of Single-Ended AC and DC Input Levels f or CA

and CS_n Inputs and table of Single-Ended AC and DC Input Levels for DQ and DM respectively.

Table of Single-en ded l evels for CK_t, DQS _t, CK_c, DQS_c

Symbol Parameter LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200 Unit Note

Min Max Min Max

VSEH

(AC)

Single-ended high-level

for strobes (VDDQ / 2) + 0.220 Note 3 (VDDQ / 2) + 0.300 Note 3 V 1, 2

Single-ended high-level

for CK_t, CK_c (VDDCA / 2) + 0.220 Note 3 (VDDCA / 2) + 0.300 Note 3 V 1, 2

VSEL

(AC)

Single-ended low-

level for

strobes Note 3 (VDDDQ / 2) - 0.220 Note 3 (VDDQ / 2) - 0.300 V 1, 2

Single-ended low-

level for

CK_t, CK_c Note 3 (VDDCA / 2) - 0.220 Note 3 (VDDCA / 2) - 0.300 V 1, 2

Note :

1. For CK_t, CK_c use VSEH/VSEL(ac) of CA; for strobes (DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t,

DQS3_c) use VIH/VIL(ac) of DQs.

2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VSEH(ac)/VSEL(ac) for CA is based on VREFCA; if a reduced ac-high or ac-

low level is us ed for a signal group, then the reduced level applies also here.

3. These values are not defined, however the single-ended signals CK_t, CK _c, DQS0_t, DQS 0_c , DQS1_t, DQS1_c, DQS2_t,

DQS2_c, DQS3_t, DQS3_c need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well

as the limitations for overshoot and undershoot. Ref er to “Overshoot and Undershoot Specif ications”.

7.2.4.6 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each

cross point voltage of differential input signals (CK_t, CK_c and DQS_t, DQS_c) must meet the requirements of

Single-ended levels for CK_t, DQS_t, CK_c, DQS_c. The differential input cross point voltage VIX is measured from

the actual cross point of true and complement signals to the midlevel between of VDD and VSS.

Figure of Vix Definition

VDDCA/2 or VDDQ/2

VSSCA or VSSQ

VDDCA or VDDQ

CK_c, DQS_c

CK_t, DQS_t

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 85 - Revision : P01-004A

Table of Cross point voltage for differential input signals (CK, DQS)

Symbol Parameter LPDDR2-1066 to LPDDR2-200 Unit Note

Min Max

VIXCA Differential Input Cross Point Voltage relative to

VDDCA/2 for CK_t, CK_c - 120 120 mV 1,2

VIXDQ Differential Input Cross Point Voltage relativ e to

VDDQ/2 for DQS_t, DQS_c - 120 120 mV 1,2

Note :1. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device, and VIX(AC) is expected to track variations

in VDD. VIX(AC) indicates the voltage at which differential input signals must cross.

2. For CK_t and CK_c, Vref = VrefCA(DC). For DQS_t and DQS_c, Vref = VrefDQ(DC).

7.2.4.7 Slew Rate Definitions f or Single-Ended Input Si gnals

See “Address / Command CA and CS_n Setup, Hold and Derating” for single-ended slew rate definitions for

address and command signals.

See “Data Setup, Hold and Slew Rate Derating ” for single-ended slew rate d efinitions for data signals.

7.2.4.8 Slew Rate Definitions f or D ifferential Input Signals

Input slew rate for differential signals (CK_t, CK_c and DQS_t, DQS_c) are defined and measured as shown in

Table and Figure below.

Table of Differenti al Input S lew Rate Def init ion

Description Measured Defin ed by

from to

Differenti al i nput slew rate for rising edge

(CK_t - CK_c and DQS_t - DQS_c). VILdiffmax VIHdiffmin [VIHdiffmin - VILdiffmax] / DeltaTRdiff

Differenti al i nput slew rate for falling edge

(CK_t - CK_c and DQS_t - DQS_c). VIHdiffmin

VILdiffmax [VIHdiffmin - VILdiffmax] / DeltaTFdiff

Note : The differential signal (i.e. CK_t - CK_c and DQS_t - DQ S_c) must be linear between these thresholds

Figure of Differential Input Slew Rate De finition for DQS_t, DQS _c and CK_t, CK_c

Delta TFdiff

Delta TRdiff

ILdiffmax

IHdiffmin

Differential Input Voltage (i.e.DQS_t-DQS_c;CK_t-CK_c)

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 86 - Revision : P01-004A

7.2.5 AC and DC Output Measurement Lev el s

7.2.5.1 Single Ended A C and DC Output Levels

Table of Single-en ded AC and DC Output Lev els

Symbol Parameter LPDDR2-1066 to

LPDDR2-200 Unit Note

VOH(DC) DC out put high measurement level (for IV curve linearity) 0.9 x VDDQ V 1

VOL(DC) DC output low measurement level (for IV curv e l inearity) 0.1 x VDDQ V 2

VOH(AC) AC output high m eas urement level (for output slew rate) VREFDQ + 0.12 V

VOL(AC) AC output low measurement level (for output slew rate) VREFDQ - 0.12 V

IOZ Output Leak age current (DQ, DM, DQS_t, DQS_c)

(DQ, DQS_t, DQS_c are disabled;0V≦Vout≦VDDQ)

Min: -5

Max: +5

MMPUPD Delta RON b etween pull-up and pu l l -d own for DQ/DM Miin: -15

Max: +15

Note 1. IOH = -0.1mA

2. IOL = 0.1mA

7.2.5.2 Differential A C and DC Output Levels

Table of Differenti al A C and DC Output Levels of ( DQS_t, DQS_c)

Symbol Parameter LPDDR2-1066 to

LPDDR2-200 Unit Note

VOHdiff(AC)

AC differential output high measurement level (for output S R)

+ 0.20 x VDDQ

VOLdiff(AC)

AC differential output low measurement level (for output SR)

- 0.20 x VDDQ

7.2.5.3 Single Ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and

measured between VOL(AC) and VOH( AC) for single ended sign als as shown in Table and Figure below.

Table of Single-en ded Output Slew Rate Definition

Description Measured Defin ed by

from to

Single-ended output sle w rate for rising edge VOL(AC) VOH(AC) [VOH(AC) - V OL(AC)] / DeltaTRse

Single-ended output sle w rate for falling edge VOH(AC) VOL(AC) [VOH(AC) - VOL(AC)] / DeltaTFse

Note:Output slew rate is verified by design and characterization, and may not be subject to production test.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 87 - Revision : P01-004A

Figure of Single Ended Output Slew Rate Definiton

Delta TFse

Delta TRse

VREF

VOL(AC)

Single Ended Output Vollage (i.e.DQ)

VOH(AC)

Table of Output S l ew Rat e (single-ended)

Symbol Parameter LPDDR2-1066 to LPDDR2-200 Unit

Min Max

SRQse Single-ended Output Slew Rate (RON = 40Ω +/- 30%)

1.5 3.5 V/ns

SRQse

Single-ended Output Slew Rate (RON = 60Ω +/- 30%)

1.0 2.5 V/ns

Output slew-rate matching Ratio (Pull-up to Pull-down)

0.7 1.4

Description:

SR: Slew Rate

Q: Query Output (like in DQ, which sta nds for Data-in, Query-Output)

se: Single-ended Signals

Note : 1. Measured with output reference load.

2. The ratio of pull -up to pull-down sl ew rate is specified for the same temperatu re and vol tage, over the entire temperature and vol tage

range. For a given output, it represents the maximum difference between pull-up and pulldown drivers due to process variation.

3. The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC).

4. Slew rates are meas ured under normal SSO condi tions, with 1/2 of DQ si gnals per data b yte driving logic high and 1/2 of DQ signals

per data byte driving logic low.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 88 - Revision : P01-004A

7.2.5.4 Differential Output Sl ew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and

measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table and Figure below

Table of Differenti al Output Slew Rate Defi ni tion

Description Measured Defined by

from to

Differenti al output slew rate fo r rising edge VOLdiff(AC) VOHdiff(AC) [VOHdiff(AC) - VOLdiff(AC)] / DeltaTRdiff

Differenti al output slew rate fo r falling edge VOHdiff(AC) VOLdiff(AC) [VOHdiff(AC) - VOLdiff(AC)] / De l ta TFdi ff

Note: Output slew rate is verified by design and characterization, and may not be subject to production test.

Figure of Differential Output Slew Rate Definition

Delta TFdiff

Delta TRdiff

VOLdiff(AC)

Differential Output VoltAge (i.e. DQS_t – DQS_c)

VOHdiff(AC)

Table of Differenti al Output Slew Rate

Symbol Parameter LPDDR2-1066 to LPDDR2-200 Unit

Min Max

SRQdiff Differential Output Slew Rate (RON = 40Ω +/- 30%)

3.0 7.0 V/ns

SRQdiff

Differential Output Slew Rate (RON = 60Ω +/- 30%)

2.0 5.0 V/ns

Description:

SR: Slew Rate

Q: Query Output (like in DQ, which sta nds for Data-in, Query-Output)

diff: differential Signals

Note :1. Measured with output reference load.

2. The output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC).

3. Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving logic-high and 1/2 of DQ signals

per data byte driving logic-low.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 89 - Revision : P01-004A

7.2.5.5 Overshoot and Undershoot Specifications

Table of AC Overshoot/ Under shoot Specif icat ion

Parameter LPDDR2 Unit

1066 933 800 667 533 400 333

Maximum peak amplitude

allowed for overshoot area.

(See Figure below)

Max 0.35 V

Maximum peak amplitude

allowed for undershoot

area.

(See Figure below) Max 0.35 V

Maximum area above VDD.

(See Figure below)

Max 0.15 0.17 0.20 0.24 0.30 0.40 0.48 V-ns

Maximum area below VSS.

(See Figure below) Max 0.15 0.17 0.20 0.24 0.30 0.40 0.48 V-ns

CA0-9, CS_n, CKE, CK_t, CK_c, DQ, DQS_t, DQS_c, DM

Note : 1. For CA0-9, CK_t, CK_c, CS_n, and CKE, VDD stands for VDDCA. For DQ, DM, DQS_t, and DQS_c, VDD stands for VDDQ.

2. For CA0-9, CK_t, CK_c, CS_n, and CKE, VSS stands for VSSCA. For DQ, DM, DQS_t, and DQS_c, VSS stands for VSSQ.

3. Values are referenced from actual VDDQ, VDDCA, VSSQ, and VSSCA levels.

Figure of Overshoot and Undershoot Definition

VDD

VSS

Overshoot Area

Undershoot Area

Maximum Amplitude

Time (ns)

Volts

(V)

Note : 1. For CA0-9, CK_t, CK_c, CS_n, and CKE, VDD stands for VDDCA. For DQ, DM, DQS_t, and DQS_c, VDD stands for VDDQ.

2. For CA0-9, CK_t, CK_c, CS_n, and CKE, VSS stands for VSSCA. For DQ, DM, DQS_t, and DQS_c, VSS stands for VSSQ.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 90 - Revision : P01-004A

7.2.6 Output buffer characteristics

7.2.6.1 HSUL_12 Driver Output Timing Refe rence Load

These ‘Timing Reference Loads’ are not intended as a precise representation of any particular system environment

or a depiction of the actual load presented by a production tester. System designers should use IBIS or other

simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their

production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.

Figure of HSUL_12 Driver Output Refer ence Load for Timing and Slew Rate

0.5 x VDDQ

Cload = 5pF

VREF

Output

LPDDR2

SDRAM

VTT = 0.5 x VDDQ

RTT = 50 Ω

Note : All output timing parameter values (like tDQSCK, tDQSQ, tQHS, tHZ, tRPRE etc) are reported with respect to this reference load. This

reference load is also used to report slew rate.

7.2.6.2 RONPU and RONPD Resistor Definition

Note : This is under the condition that RONPD is turned off

Note : This is under the condition that RONPU is turned off

Figure of Output Driv er Definition of V oltages and Currents

Chip in Drive Mode

VDDQ

VSSQ

Output Driver

RON

Out

Other

Circuityrt

RCV,

...

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 91 - Revision : P01-004A

7.2.6.3 RONPU and RONPD Charact eristics with ZQ Calibr ation

Output driver impedance RON is defined by the value of the external reference resistor RZQ. Nominal RZQ is 240Ω.

Table — Output Driv er DC Electrical Ch aracteristics with ZQ Calibration

RON

NOM

Resistor Vout Min Nom Max Unit Note

34.3

RON34PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/7 1,2,3,4

RON34PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/7 1,2,3,4

40.0

RON40PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/6 1,2,3,4

RON40PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/6 1,2,3,4

48.0

RON48PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/5 1,2,3,4

RON48PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/5 1,2,3,4

60.0

RON60PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/4 1,2,3,4

RON60PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/4 1,2,3,4

80.0

RON80PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/3 1,2,3,4

RON80PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/3 1,2,3,4

120.0

RON120PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/2 1,2,3,4

RON120PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/2 1,2,3,4

Mismatch between pull-up

and pull-down

MMPUPD -15.00 +15.00 % 1,2,3,4,5

Note 1. Across entire operating temperature range, after calibration.

2. RZQ = 240Ω.

3.The tolerance limits are specified after calibration with fixed voltage and temperature. For behavior of the tolerance limits if

temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.

4. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ.

5. Mesaurement definition for mismatch between pull-up and pull-down: MMPUPD: Measure RONPU and RONPD, both at 0.5 x VDDQ:

For example, with M M PUPD(max) = 15% and RONPD = 0.85, RONP U m ust be less than 1.0.

7.2.6.3.1 Output Driver Temperature and Voltage Sensitivity

If temperature and/or voltage change after calibration, the tolerance limits widen according to the Tables shown

Below

Table of Output Driver Sensitivity Definition

Resistor Vout Min Max Unit Note

RONPD 0.5 x

VDDQ 85 – (dR ONdT ×|ΔT| ) – (dRON d V × |ΔV| ) 115 + (dRONdT ×| ΔT| )+(dRONdV × |ΔV|) % 1,2

RONPU

Note 1. ΔT = T–T (@calibration), ΔV=V–V(@ calibration)

2. dRONdT and dRONdV are not subject to production test but are verified by design and characterization.

Table of Output Driv er Temperature and Voltage Sensit i vity

Symbol Parameter Min Max Unit Note

dRONdT RON Temp erature Sensitivity 0.00 0.75 % / C

dRONdV RON Voltage Sensitivity 0.00 0.20 % / mV

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 92 - Revision : P01-004A

7.2.6.4 RONPU and RONP D Characteristics without ZQ Calibration

Output driver impedance RON is defined by design and characterization as default setting.

Table of Output Driver DC E lect ri cal Ch ara ct eri stic s wit hout ZQ Cal ibratio n

RON

NOM

Resistor Vout Min Nom Max Unit Note

34.3Ω RON34PD 0.5 x VDDQ 24 34.3 44.6 Ω 1

RON34PU 0.5 x VDDQ 24 34.3 44.6 Ω 1

40.0Ω RON40PD 0.5 x VDDQ 28 40 52 Ω 1

RON40PU 0.5 x VDDQ 28 40 52 Ω 1

48.0Ω RON48PD 0.5 x VDDQ 33.6 48 62.4 Ω 1

RON48PU 0.5 x VDDQ 33.6 48 62.4 Ω 1

60.0Ω RON60PD 0.5 x VDDQ 42 60 78 Ω 1

RON60PU 0.5 x VDDQ 42 60 78 Ω 1

80.0Ω RON80PD 0.5 x VDDQ 56 80 104 Ω 1

RON80PU 0.5 x VDDQ 56 80 104 Ω 1

120.0Ω RON120PD 0.5 x VDDQ 84 120 156 Ω 1

RON120PU 0.5 x VDDQ 84 120 156 Ω 1

Note : Across entire operating temperature range, without calibration.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 93 - Revision : P01-004A

7.2.6.5 RZQ I-V Curve

Table of RZQ I-V Curve

Voltage[V]

RON = 240

(RZQ)

Pull-Down

Pull-Up

Current [mA ] / RON [Ohms]

Current [mA] / R ON [Ohms]

default value after

ZQReset

With Calibration default value after

ZQReset

With Calibration

Min Max Min Max Min Max Min Max

[mA] [mA] [mA] [mA] [mA] [mA] [mA] [mA]

0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00

0.05 0.19 0.32 0.21 0.26 -0.19 -0.32 -0.21 -0.26

0.10 0.38 0.64 0.40 0.53 -0.38 -0.64 -0.40 -0.53

0.15 0.56 0.94 0.60 0.78 -0.56 -0.94 -0.60 -0.78

0.20 0.74 1.26 0.79 1.04 -0.74 -1.26 -0.79 -1.04

0.25 0.92 1.57 0.98 1.29 -0.92 -1.57 -0.98 -1.29

0.30 1.08 1.86 1.17 1.53 -1.08 -1.86 -1.17 -1.53

0.35 1.25 2.17 1.35 1.79 -1.25 -2.17 -1.35 -1.79

0.40 1.40 2.46 1.52 2.03 -1.40 -2.46 -1.52 -2.03

0.45 1.54 2.74 1.69 2.26 -1.54 -2.74 -1.69 -2.26

0.50 1.68 3.02 1.86 2.49 -1.68 -3.02 -1.86 -2.49

0.55 1.81 3.30 2.02 2.72 -1.81 -3.30 -2.02 -2.72

0.60 1.92 3.57 2.17 2.94 -1.92 -3.57 -2.17 -2.94

0.65 2.02 3.83 2.32 3.15 -2.02 -3.83 -2.32 -3.15

0.70 2.11 4.08 2.46 3.36 -2.11 -4.08 -2.46 -3.36

0.75 2.19 4.31 2.58 3.55 -2.19 -4.31 -2.58 -3.55

0.80 2.25 4.54 2.70 3.74 -2.25 -4.54 -2.70 -3.74

0.85 2.30 4.74 2.81 3.91 -2.30 -4.74 -2.81 -3.91

0.90 2.34 4.92 2.89 4.05 -2.34 -4.92 -2.89 -4.05

0.95 2.37 5.08 2.97 4.23 -2.37 -5.08 -2.97 -4.23

1.00 2.41 5.20 3.04 4.33 -2.41 -5.20 -3.04 -4.33

1.05 2.43 5.31 3.09 4.44 -2.43 -5.31 -3.09 -4.44

1.10 2.46 5.41 3.14 4.52 -2.46 -5.41 -3.14 -4.52

1.15 2.48 5.48 3.19 4.59 -2.48 -5.48 -3.19 -4.59

1.20 2.50 5.55 3.23 4.65 -2.50 -5.55 -3.23 -4.65

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 94 - Revision : P01-004A

Figure of RON = 240 Ohms IV Curve after ZQReset

PD Min

PD Max

PU Min

PU Max

-2

-4

-6

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

Voltage

Figure of RON = 240 Ohms IV Curve after calibration

PD Min

PD Max

PU Min

PU Max

-2

-4

-6

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

Voltage

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 95 - Revision : P01-004A

7.2.7 Input/Ouput Capacitance

Table — Input/output capacitance

Parameter Symbol LPDDR2

1066-466

LPDDR2

400-200

Units Note

Input capacitance, CK_t and CK_c CCK Min 1.0 pF 1,2

Max 2.0 pF 1,2

Input capacitance delta, CK_t and

CK_c CDCK Min 0 pF 1,2,3

Max 0.20 0.25 pF 1,2,3

Input capacitance, all other input-only

pins CI Min 1.0 pF 1,2,4

Max 2.0 pF 1,2,4

Input capacitance delta, all other

input-only pins CDI Min -0.40 -0.50 pF 1,2,5

Max 0.40 0.50 pF 1,2,5

Input/output c apacitance, DQ, DM,

DQS_t, DQS_c CIO Min 1.25 pF 1,2,6,7

Max 2.5 pF 1,2,6,7

Input/output c apacitance delta,

DQS_t, DQS_c CDDQS Min 0 pF 1,2,7,8

Max 0.25 0.30 pF 1,2,7,8

Input/output c apacitance delta, DQ,

DM CDIO Min -0.5 -0.6 pF 1,2,7,9

Max 0.5 0.6 pF 1,2,7,9

Input/output c apacitance ZQ Pin CZQ Min 0 pF 1,2

Max 2.5 pF 1,2

(

OPER

; V

DDQ

= 1.14- 1.3V; V

DDCA

= 1.14-1.3V; V

DD1

= 1.7-1.95V,

LPDDR2-S4 V

DD2

= 1.14-

1.3V

)

Note 1. This parameter applies to die device only (does not include package capacitance).

2.This parameter is not subject to production test. It is verified by design.

3. Absolute value of CCK_t - CCK_c.

4. CI applies to CS_n, CKE, CA0-CA9.

5. CDI = CI - 0.5 * (CCK_t + CCK_c)

6. DM loading matches DQ and DQS.

7. MR3 I/O configuration DS OP3-OP0 = 0001B (34.3 Ohm typical)

8. Absolute value of CDQS_t and CDQS_c.

9. CDIO = CIO - 0.5 * (CDQS_t + CDQS_c) in byte-lane.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 96 - Revision : P01-004A

7.3 IDD Specification Parameters and Test Conditions

7.3.1 IDD Measurement Conditions

The following def i ni tions are used within the IDD measurement tables:

LOW: VIN ≦VIL(DC) MAX

HIGH: VIN ≧VIH(DC) MIN

STABLE: Input s are stable at a HIGH or LO W l evel

SWITCHING: See tables below.

7.3.1.1 Table of Definition of Switching for CA Input Signals

Switching for CA

CK_t

(RISING) /

Ck_C

(FALLING)

CK_t

(FALLING) /

Ck_C

(RISING)

CK_t

(RISING) /

Ck_C

(FALLING)

CK_t

(FALLING) /

Ck_C

(RISING)

CK_t

(RISING) /

Ck_C

(FALLING)

CK_t

(FALLING) /

Ck_C

(RISING)

CK_t

(RISING) /

Ck_C

(FALLING)

CK_t

(FALLING) /

Ck_C

(RISING)

Cycle N N+1 N+2 N+3

CS_n HIGH HIGH HIGH HIGH

CA0 HIGH LOW LOW LOW LOW HIGH HIGH HIGH

CA1 HIGH HIGH HIGH LOW LOW LOW LOW HIGH

CA2 HIGH LOW LOW LOW LOW HIGH HIGH HIGH

CA3 HIGH HIGH HIGH LOW LOW LOW LOW HIGH

CA4 HIGH LOW LOW LOW LOW HIGH HIGH HIGH

CA5 HIGH HIGH HIGH LOW LOW LOW LOW HIGH

CA6 HIGH LOW LOW LOW LOW HIGH HIGH HIGH

CA7 HIGH HIGH HIGH LOW LOW LOW LOW HIGH

CA8 HIGH LOW LOW LOW LOW HIGH HIGH HIGH

CA9 HIGH HIGH HIGH LOW LOW LOW LOW HIGH

Note 1. CS_n must always be driven HIGH.

2. 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus.

3. The above pa ttern (N, N+1, N+2, N+3...) is used continuously during IDD measurement for IDD values that require SWITCHING on

the CA bus.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 97 - Revision : P01-004A

7.3.1.2 Table of Definition of Switching for IDD4R

Clock CKE CS_n Clock Cycle Number Command CA0-CA2 CA3-CA9 All DQ

Rising HIGH LOW N Read_Rising HLH LHLHLHL L

Falling HIGH LOW N Read_Falling LLL LLLLLLL L

Rising HIGH HIGH N + 1 NOP LLL LLLLLLL H

Falling HIGH HIGH N + 1 NOP HLH HLHLLHL L

Rising HIGH LOW N + 2 Read_Rising HLH HLHLLHL H

Falling HIGH LOW N + 2 Read_Falling LLL HHHHHHH H

Rising HIGH HIGH N + 3 NOP LLL HHHHHHH H

Falling HIGH HIGH N + 3 NOP HLH LHLHLHL L

Note 1. Data strobe (DQS) is changing between HIGH and LOW every clock cycle.

2. The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4R.

7.3.1.3 Tabl e of Definition of Switching for IDD4W

Clock CKE CS_n Clock Cycle Number Command CA0-CA2 CA3-CA9 All DQ

Rising HIGH LOW N Write_Rising HLL LHLHLHL L

Falling HIGH LOW N Write_Falling LLL LLLLLLL L

Rising HIGH HIGH N + 1 NOP LLL LLLLLLL H

Falling HIGH HIGH N + 1 NOP HLH HLHLLHL L

Rising HIGH LOW N + 2 Write_Rising HLL HLHLLHL H

Falling HIGH LOW N + 2 Write_Falling LLL HHHHHHH H

Rising HIGH HIGH N + 3 NOP LLL HHHHHHH H

Falling HIGH HIGH N + 3 NOP HLH LHLHLHL L

Note 1.Data strobe (DQS) is changing between HIGH and LOW every clock cycle.

2.Data masking (DM) must always be driven LOW.

3.The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4W.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 98 - Revision : P01-004A

7.3.2 IDD Specifications

7.3.2.1 Table of LPDDR2 IDD Specification Parameters and Operating Condi tions

(x32)

Parameter/Condition Symbol Power

Supply 533

MHz 400

MHz Units Note

Operating one bank ac tive-precharge cu rrent :

tCK = tCKmin; tRC = tRCmin;

CKE is HIGH;

CS_n is HIGH betw een valid co mmands ;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD01 VDD1 TBD 8 mA 1

IDD02 VDD2 TBD 25 mA 1

IDD0IN VDDCA

VDDQ TBD 3.5

1 mA 1,2

Idle power-down s tandby current :

tCK = tCKmin;

CKE is LOW;CS_n is HIGH;

All banks/RBs idle ;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD2P1 VDD1 TBD 0.9 mA 1

IDD2P2 VDD2 TBD 0.9 mA 1

IDD2PIN VDDCA

VDDQ TBD 0.015 mA 1,2

Idle pow er-down standby current with clock s top :

CK_t =LOW, CK_c =HIGH;

CKE is LOW;CS_n is HIGH;

All banks/RBs idle ;

CA bus inputs are STABLE;

Data bus inputs are STABLE

IDD2PS1 VDD1 TBD 0.9 mA 1

IDD2PS2 VDD2 TBD 0.9 mA 1

IDD2PSIN VDDCA

VDDQ TBD 0.015 mA 1,2

Idle non power-down standby cur rent:

tCK = tCKmin;

CKE is HIGH;CS_n is HIGH;

All banks/RBs idle ;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD2N1 VDD1 TBD 1.2 mA 1

IDD2N2 VDD2 TBD 10 mA 1

IDD2NIN VDDCA

VDDQ TBD 3.5

0.05 mA 1,2

Idle non power-down standby cu rren t with clock stop :

CK_t =LOW, CK_c =HIGH;

CKE is HIGH;CS_n is HIGH;

All banks/RBs idle ;

CA bus inputs are STABLE;

Data bus inputs are STABLE

IDD2NS1 VDD1 TBD 1.2 mA 1

IDD2NS2 VDD2 TBD 10 mA 1

IDD2NSIN VDDCA

VDDQ TBD 3.5

0.05 mA 1,2

Active power-down standby curren t

tCK = tCKmin;

CKE is LOW;CS_n is HIGH;

One bank/RDB active;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD3P1 VDD1 TBD 2.3 mA 1

IDD3P2 VDD2 TBD 1.4 mA 1

IDD3PIN VDDCA

VDDQ TBD 0.015 mA 1,2

Active power-dow n stand by curr ent with clo ck stop :

CK_t=LOW, CK_c=HIGH;

CKE is LOW;CS_n is HIGH;

One bank/RDB active;

CA bus inputs are STABLE;

Data bus inputs are STABLE

IDD3PS1 VDD1 TBD 2.3 mA 1

IDD3PS2 VDD2 TBD 1.4 mA 1

IDD3PSIN VDDCA

VDDQ TBD 0.015 mA 1,2

Active non powe r-down standby c ur re n t :

tCK = tCKmin;

CKE is HIGH;CS_n is HIGH;

One bank/RDB active;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD3N1 VDD1 TBD 2 mA 1

IDD3N2 VDD2 TBD 14 mA 1

IDD3NIN VDDCA

VDDQ TBD 3.5

0.05 mA 1,2

Active non power-down standby c ur re nt with clock stop:

CK_t=LOW, CK_c=HIGH;

CKE is HIGH;CS_n is HIGH;

One bank/RDB active;

CA bus inputs are STABLE;

Data bus inputs are STABLE

IDD3NS1 VDD1 TBD 2 mA 1

IDD3NS2 VDD2 TBD 14 mA 1

IDD3NSIN VDDCA

VDDQ TBD 3.5

0.05 mA 1,2

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 99 - Revision : P01-004A

Parameter/Condition Symbol Power

Supply

533

MHz

400

MHz Units Note

Operating burst read current:

= t

CKmin

;

CS_n is HIGH;

One bank/RDB active;

BL = 4; RL = RLmin;

bus inputs are SWITCHING;

50% data change each burst transfer

IDD4R

VDD1 TBD 2 mA 1

IDD4R

VDD2 TBD 160 mA 1

IDD4R

VDDCA TBD 3.5 mA 1

Operating burst writ e current:

= t

CKmin

;

CS_n is HIGH;

One bank/RDB active;

BL = 4; WL = WLmin;

CA bus inputs are SWITCHING;

50% data change each burst transfer

IDD4W

VDD1 TBD 3 mA 1

IDD4W

VDD2 TBD 200 mA 1

IDD4W

VDDCA

VDDQ TBD 3.5

12 mA 1,2

All Bank Refresh Burst current:

= t

CKmin

;

CKE is HIGH;

= t

RFCabmin

;

Burst refresh;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE;

IDD5

VDD1 TBD 50 mA 1

IDD5

VDD2 TBD 120 mA 1

IDD5

VDDCA

VDDQ TBD 3.5

0.05 mA 1,2

All Bank Refresh Average current:

= t

CKmin

;

CKE is HIGH;

= t

REFI;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE;

IDD5AB

VDD1 TBD 8 mA 1

IDD5AB

VDD2 TBD 15 mA 1

IDD5AB

VDDCA

VDDQ TBD 3.5

0.05 mA 1,2

Per Bank Refresh Average current:

= t

CKmin

;

CKE is HIGH;

= t

REFI/8;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE;

IDD5PB

VDD1 TBD 3 mA 1

IDD5PB

VDD2 TBD 16 mA 1

IDD5PB

VDDCA

VDDQ TBD 3.5

0.05 mA 1,2

Deep Power-Down current:

CK_t=LOW, CK_c=HIGH;

CKE is LOW;

CA bus inputs are STABLE;

Data bus input s are STABLE;

IDD8

VDD1 TBD 15 uA 1

IDD8

VDD2 TBD 15 uA 1

IDD8

VDDCA

VDDQ TBD 15 uA 1,2

Note :1. IDD values published are the typical of the distribution of the arithmetic mean.

2. Measured currents are the summation of VDDQ and VDDCA.

3. Guaranteed by design with output reference load of 5pfFand RON = 40Ohm.

4. IDD current specifications are tested after the device is properly initialized.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 100 - Revision : P01-004A

7.3.2.2 Table of IDD6 Partial Array Self-Refresh Current

Parameter Symbol Power

Supply

533 MHz 400 MHz Condition Unit

IDD6 Partial Array

Self-Refresh

Current

Full Array

IDD6

VDD1 TBD 900

Self refresh current 

CK_t=LOW, CK_c=HIGH;

CKE is LOW; 

CA bus inputs are STABLE;



Data bus inputs are STABLE;

IDD6

VDD2 TBD 1900

IDD6

VDDCA

VDDQ TBD 15

1/2 Array

IDD6

VDD1 TBD 750

IDD6

VDD2 TBD 1100

IDD6

VDDCA

VDDQ

TBD 15

1/4 Array

IDD6

VDD1 TBD 650

IDD6

VDD2 TBD 900

IDD6

VDDCA

VDDQ

TBD 15

1/8 Array

IDD6

VDD1 TBD 600

IDD6

VDD2 TBD 750

IDD6

VDDCA

VDDQ TBD 15

Note :1. LPDDR2-S4 SDRAM uses the same PASR scheme & IDD6 current value categorization as LPDDR (JESD209).

2. IDD values published are the typical of the distribution of the arithmetic mean.

7.4 Clock Specification

The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may

result in malfunction of the LPDDR2 device.

7.4.1 Definition for tCK(avg) and nCK

tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock

period is calculated from rising edge to rising edge.

Unit ‘tCK(avg)’ represents the actual clock average tCK(avg) of the input clock under operation. Unit ‘nCK’

represents one clock cycle of the input clock, counting the act ual clock edges.

tCK(avg) may change by up to +/-1% within a 100 clock cycle window, provided that all jitter and timing specs are

met.

7.4.2 Definition for tCK(abs)

tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising

edge.

tCK(abs) is not subject to production t est .

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 101 - Revision : P01-004A

7.4.3 Definition for t CH(avg) and tCL(avg)

tCH(avg) is def i ned as the average high puls e width, as calculated across any consecutive 200 high pulses

tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.

7.4.4 Definition for tJIT(per)

tJIT(per) is defined as the largest dev i ation of any signal tCK from tCK(avg).

tJIT(per) = Min/max of {tCKi - tCK(avg) where i = 1 to 200}.

tJIT(per) defines t he single period jitter when the DLL is already loc ked.

tJIT(per) is not subject to production test.

7.4.5 Definition for tJIT(cc)

tJIT(cc) is defi ned as the absolute difference in clock period between two conse cut i ve clock cycles.

tJIT(cc) = Max of |{tCKi +1 - tCKi}|.

tJIT(cc) defin es t he cycle to cycle jitter.

tJIT(cc) is not subject to production test .

7.4.6 Definition for t ERR(nper)

tERR is defined as the cumulative error acro ss n multiple consecutive cycles from t CK (av g).

tERR(nper),act i s t he act ual clock jitter over n cycles for a given syst em .

tERR(nper),all owed is the specified allowed clock period jitter over n cycles.

tERR(nper) is not subject to production test.

tERR(nper),m i n can be calculated by the formula shown below:

tERR(nper),m ax can be calculated by t he formula shown below:

Using these equati ons, tERR(nper) table s can be generated for ea ch t JI T (per),act value.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 102 - Revision : P01-004A

7.4.7 Definition for duty cycle jitter tJIT(duty)

tJIT(duty) is d efined with absolute and average specificati on of tCH / tCL.

tJIT(duty),min=MIN((tCH(abs),min–tCH(avg),min),tCL(abs),min–tCL(avg),min)) x tCK(avg)

tJIT(duty),max=MAX((tCH(abs),max–tCH(avg),max),tCL(abs),max–tCL(avg),max)) x tCK(avg)

7.4.8 Definition for t CK (abs), tCH(abs) and t CL(abs)

These parameters are specified per their average values, however it is understood that the following relationship

between the av erage timing and the ab solute instantaneou s timing holds at all times.

Table 100 — Definiti on for tCK(abs), tCH(a bs), and tCL(abs)

Parameter Symbol Min Unit

Absolute Clock Period tCK(abs) t CK(avg),min + tJIT(per),min PS

Absolute Clock HIGH Pulse Width tCH(abs) tCH(avg),min + tJIT(duty),min / tCK(avg)min tCK(avg)

Absolute Clock LOW Pulse Width tCL(abs) tCL(avg),min + tJIT(duty),min / tCK(avg)min tCK(avg)

Note 1. tCK(avg),min is expressed is ps for this table.

2 .tJIT(duty),min is a negative value.

7.4.9 Period Clock Jitter

LPDDR2 devices can tolerate some clock period jitter without core timing parameter de-rating. This section

describes device timing requirements in the presence of clock period jitter (tJIT(per)) in excess of the values found

in Table of AC timing and how to determine cycl e time de-rating and clock cycle de-rating.

7.4.9.1 Clock period jitter eff ec ts on core timing param eters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW )

Core timing parameters extend across multiple clock cycles. Period clock jitter will impact these parameters when

measured in numbers of clock cycles. When the device is operated with clock jitter within the specification limits, the

LPDDR2 device is characterized and verified to support tnPARAM = R U{tPARAM / tCK(av g)}.

When the device is operated with clock jitter outside specification limits, the number of clocks or tCK(avg) may need

to be increased based on the values for eac h core timing parameter.

7.4.9.2 Cycle time de-rating for c or e timing parameters

For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and

actual cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative period error

(tERR(tnPARAM),allowed), the equation below calculates the amount of cycle time de-rating (in ns) required if the

equation result s in a positive value for a core timing parameter (tCORE).

A cycle time derating analysis should be conducted for each core timing parameter. The amount of cycle time

derating required i s t he maximum of t he cy cle time de-ratings deter m ined for each individual core t i m i ng parameter.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 103 - Revision : P01-004A

7.4.9.3 Clock C ycle de-rating for core t i m i ng parameters

For a given number of clocks (tnPARAM) for each core timing parameter, clock cycle de-rating should be specified

with amount of period ji tter (tJIT(per)).

For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and

actual cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative period error

(tERR(tnPARAM),allowed), the equation below calculates the clock cycle derating (in clocks) required if the

equation result s in a positive value for a core timing parameter (tCORE).

A clock cycle de-rating analysis should b e conducted for each core timing parameter.

7.4.9.4 Clock jitter effects on C/A timing (tIS,tIH,tISCKE,tIHCKE,tISb, tIHb, tISCKEb, tIHCKEb)

These parameters are measured from a command/address signal (CKE, CS, CA0 - CA9) transition edge to its

respective clock signal (CK_t/CK_c) crossing. The spec values are not affected by the amount of clock jitter applied

(i.e. tJIT(per), as the setup and hold are relative to the clock signal crossing that latches the command/address.

Regardless of cloc k ji tter values, these values shall be met.

Clock jitter effects on Read timi ng parameters

7.4.9.5 Clock j itter effects on Read timing tRPRE

When the device is operated with input clock jitter, tRPRE needs to be de-rated by the actual period jitter

(tJIT(per),act,max) of the input clock in excess of the allowed period jitter (tJIT(per),allowed,max). Output de-ratings

are relative to t he i nput clock.

For example,

if the measured jitter into a LPDDR2-800 device has tCK(avg) = 2500 ps, tJIT(per),act,min = -172 ps and

tJIT(per),act,max = + 193 ps, then

tRPRE,min,derated = 0.9 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (193 - 100)/2500= .8628

tCK(avg)

7.4.9.6 Clock j itter effects on Read timing tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS)

These parameters are measured from a specific clock edge to a data signal (DMn, DQm.: n=0,1,2,3. m=0–31)

transition and will be met with respect to that clock edge. Therefore, they are not affected by the amount of clock

jitter applied ( i .e. tJIT(per).

7.4.9.7 Clock j itter effects on Read timing parameters tQSH, tQSL

These parameters are affected by duty cycle jitter which is represented by tCH(abs)min and tCL(abs)min. Therefore

tQSH(abs)min and tQSL(abs)min can be specified with tCH(abs)min and tCL(ab s)min.

tQSH(abs)min = tCH(abs)min – 0.05

tQSL(abs)mi n = t CL(abs)min – 0.05

These parameters determine absolute Data-Valid window at the LPDDR2 device pin.

Absolute min data-v al i d window @ LPDDR2 device pin =

min { ( tQSH(abs)min * tCK(avg)min – tDQSQmax – tQHSmax ) , ( tQSL(abs)min * tCK(avg)min – tDQSQmax –

tQHSmax ) }

This minimum data-valid window shall be met at the target frequency regardless of clock jitter.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 104 - Revision : P01-004A

7.4.9.8 Clock j itter effects on Read timing parameters tRPST

tRPST is affected by duty cycle jitter which is represented by tCL(abs). Therefore tRPST(abs)min can be specified

by tCL(abs)min.

tRPST(abs)min = tCL(abs)min – 0.05 = tQS L(abs)min

Clock jitter effects on Write t i m i ng parameters

7.4.9.9 Clock j itter effects on Wr ite timing parameters tDS, tDH

These parameters are measured from a data signal (DMn, DQm.: n=0,1,2,3. m=0 –31) transition edge to its

respective data strobe signal (DQSn_t, DQSn_c : n=0,1,2,3) crossing. The spec values are not affected by the

amount of clock jitter applied (i.e. tJIT(per), as the setup and hold are relative to the clock signal crossing that

latches the command/address. Regardless of clock jitt er values, these values shall be met.

7.4.9.10 Clock jitter effects on Write timing paramet er s tDSS, tDSH

These parameters are measured from a data strobe signal (DQSx_t, DQSx_c) crossing to its respective clock signal

(CK_t/CK_c) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), as the

setup and hold are rel ative to the clock signal crossing that lat ches the command/address. Regardless of clock jitter

values, these values shall be met.

7.4.9.11 Clock jitter eff ects on Write timing pa r ameters tDQSS

This parameter is measured from a data strobe signal (DQSx_t, DQSx_c) crossing to the subsequent clock signal

(CK_t/CK_c) crossing. When the device is operated with input clock jitter, this parameter needs to be de-rated by

the actual peri od j i tter tJIT(per),act of the input clock in excess of the allowed period jitt er tJIT(per),allow ed.

For example,

if the measured jitter into a LPDDR2-800 device has tCK(avg)= 2500 ps, tJIT(per),act,min= -172 ps and

tJIT(per),act,max= + 193 ps, then

tDQSS,(min,derated) = 0.75 +(tJIT(per),act,min - tJIT(per),allowed,min)/tCK(avg) = 0 .75 - (-172 + 100)/2500 = .7788

tCK(avg) and tDQSS,(max,derated) = 1.25 + (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 1.25 - (193 -

100)/2500 = 1.2128 tCK(avg)

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 105 - Revision : P01-004A

7.5 Refresh Requirements

7.5.1 LPDDR2-S4 Refresh Requirement P aram eters

Parameter Symbol 1 Gb Unit

Number of Banks 8

Refresh WindowTj ≤ 85°C tREFW 32 ms

Refresh Window85°C < Tj ≤ 105°C ms tREFW 8 ms

Required number of RE FRESH commands (min) R 4,096

Average time between REFRESH commands

(for reference only) Tj ≤ 85°C

REFab tREFI 7.8 us

REFpb tREFIpb 0.975 us

Refresh Cycle time tRFCab 130 ns

Per Bank Refresh Cycle time tRFCpb 60 ns

Burst Refresh Window= 4 x 8 x tRFCab tREFBW 4.16 us

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 106 - Revision : P01-004A

7.6 AC Timings

7.6.1 Table of LPDDR2 AC Timing

Parameter Symbol min /

max min

tCK 1066 933 800 667 533 400 333 Unit

Max. Frequency*4 ~ 533 466 400 333 266 200 166 MHz

Clock Timing

Average Clock

Period tCK(avg) min 1.875 2.15 2.5 3 3.75 5 6 ns

max 100

Average high

pulse width tCH(avg) min 0.45 tCK(av

max 0.55

Average low pulse

width tCL(avg) min 0.45 tCK(av

max 0.55

Absolute Clock

Period tCK(abs) min tCK(avg)min + tJIT(per)min ps

Absolute clock

HIGH pulse width

(with allowed

jitter)

tCH(abs)

allowed

min 0.43 tCK(av

max 0.57

Absolute clock

LOW pulse width

(with allowed

jitter)

tCL(abs)

(allowed)

min 0.43 tCK(av

max 0.57

Clock Period Jitter

(with allowed

jitter)

tJIT(per)

(allowed)

min -90 -95 -100 -110 -120 -140 -150 ps

max 90 95 100 110 120 140 150

Maximum Clock

Jitter between two

consecutive cloc k

cycles ( w i th

allowed jitter)

tJIT(cc)

allowed max 180 190 200 220 240 280 300 ps

Duty cycle Jitter

(with allowed

jitter)

tJIT(duty),

allowed

min min((tCH(abs),min - tCH(avg), min), (tCL(abs),min -

tCL(avg),m i n)) * tCK(avg) ps

max max((tCH(abs),max - tCH(avg), m ax), (tCL(abs),max -

tCL(avg),m a x)) * tCK(avg) ps

Cumulative error

across 2 cycles tERR(2per)

(allowed) min -132 -140 -147 -162 -177 -206 -221 ps

max 132 140 147 162 177 206 221

Cumulative error

across 3 cycles tERR(3per)

(allowed) min -157 -166 -175 -192 -210 -245 -262 ps

max 157 166 175 192 210 245 262

Cumulative error

across 4 cycles tERR(4per)

(allowed) min -175 -185 -194 -214 -233 -272 -291 ps

max 175 185 194 214 233 272 291

Cumulative error

across 5 cycles tERR(5per)

(allowed) min -188 -199 -209 -230 -251 -293 -314 ps

max 188 199 209 230 251 293 314

Cumulative error tERR(6per) min -200 -211 -222 -244 -266 -311 -333 ps

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 107 - Revision : P01-004A

across 6 cycles

(allowed)

max 200 211 222 244 266 311 333

Cumulative error

across 7 cycles tERR(7per)

(allowed) min -209 -221 -232 -256 -279 -325 -348 ps

max 209 221 232 256 279 325 348

Cumulative error

across 8 cycles tERR(8per)

(allowed) min -217 -229 -241 -266 -290 -338 -362 ps

max 217 229 241 266 290 338 362

Cumulative error

across 9 cycles tERR(9per)

(allowed) min -224 -237 -249 -274 -299 -349 -374 ps

max 224 237 249 274 299 349 374

Cumulative error

across 10 cycles tERR(10per)

(allowed) min -231 -244 -257 -282 -308 -359 -385 ps

max 231 244 257 282 308 359 385

Cumulative error

across 11 cycles tERR(11per)

(allowed) min -237 -250 -263 -289 -316 -368 -395 ps

max 237 250 263 289 316 368 395

Cumulative error

across 12 cycles tERR(12per)

(allowed) min -242 -256 -269 -296 -323 -377 -403 ps

max 242 256 269 296 323 377 403

Cumulative error

across n = 13,

14 . . . 49, 50

cycles

tERR(nper)

(allowed)

min tERR(nper),allowed,min = (1 + 0.68ln(n)) *

tJIT(per),allowed,min ps

max tERR(nper),allowed, m ax = (1 + 0.68ln(n)) *

tJIT(per),allowed,max

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 108 - Revision : P01-004A

Parameter Symbol min /

max min

tCK 1066 933 800 667 533 400 333 Unit

ZQ Calibration Parameters

Initialization

Calibration Time*14 tZQINIT min 1 us

Full Calibration

Time*14 tZQCL min 6 360 ns

Short Calibrati on

Time*14 tZQCS min 6 90 ns

Calbration Reset

Time*14 tZQRESET min 3 50 ns

Read Parameters*11

DQS output acces s

time from CK_t/CK_c tDQSCK min 2500 ps

max 5500

DQSCK Delta

Short*15 tDQSCKDS max 330 380 450 540 670 900 1080 ps

DQSCK Delta

Medium*16 tDQSCKDM max 680 780 900 1050 1350 1800 1900 ps

DQSCK Delta

Long*17 tDQSCKDL max 920 1050 1200 1400 1800 2400 - ps

DQS - DQ skew tDQSQ max 200 220 240 280 340 400 500 ps

Data hold skew fact or tQHS max 230 260 280 340 400 480 600 ps

DQS Output High

Pulse Width tQSH min tCH(abs) - 0.05 tCK(avg)

DQS Output Low

Pulse Width tQSL min tCL(abs) - 0.05 tCK(avg)

Data Half Period tQHP min min(tQSH, tQSL) tCK(avg)

DQ / DQS output hol d

time from DQS tQH min tQHP - tQHS ps

Read preamble*11,*12 tRPRE min 0.9 tCK(avg)

Read

postamble*11,*13 tRPST min tCL(abs) - 0.05 tCK(avg)

DQS low-Z from

clock*11 tLZ(DQS) min tDQSCK(MIN) - 300 ps

DQ low-Z from

clock*11 tLZ(DQ) min tDQSCK(MIN) - (1.4 * tQHS(MAX)) ps

DQS high-Z from

clock*11 tHZ(DQS) max tDQSCK(MAX) - 100 ps

DQ high-Z from

clock*11 tHZ(DQ) max tDQSCK(MAX) + (1.4 * tDQSQ(MAX)) ps

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 109 - Revision : P01-004A

Parameter Symbol min /

max min

tCK Unit

1066 933 800 667 533 400 333

Write Parameters*11

DQ and DM input hold time

(Vref based) tDH min 210 235 270 350 430 480 600 ps

DQ and DM input setup time

(Vref based) tDS min 210 235 270 350 430 480 600 ps

DQ and DM input pulse

width tDIPW min 0.35 tCK(avg)

Write command to 1st DQS

latching trans ition tDQSS min 0.75 tCK(avg)

max 1.25

DQS input high-level width tDQSH min 0.4 tCK(avg)

DQS input low-level width tDQSL min 0.4 tCK(avg)

DQS falling edge to CK

setup time tDSS min 0.2 tCK(avg)

DQS falling edge hold time

from CK tDSH min 0.2 tCK(avg)

Write postamble tWPST min 0.4 tCK(avg)

Write preamble tWPRE min 0.35 tCK(avg)

CKE Input Parameters

CKE min. pulse width (high

and low pulse widt h) tCKE min 3 3 tCK(avg)

CKE input setup t i m e tISCKE*2 min 0.25 tCK(avg)

CKE input hold t i m e tIHCKE*3 min 0.25 tCK(avg)

Command Address Input P aram eter s*11

Address and contr ol i nput

setup time (Vref based) tIS*1 min 220 250 290 370 460 600 740 ps

Address and contr ol i nput

hold time (Vref based) tIH*1 min 220 250 290 370 460 600 740 ps

Address and contr ol i nput

pulse width tIPW min 0.40 tCK(avg)

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 110 - Revision : P01-004A

Parameter Symbol min /

max min

tCK LPDDR2 Unit

1066 933 800 667 533 400 333

Boot Parameters (10 MHz - 55 MHz) *5,7

Clock Cycle Time tCKb max 100 ns

min 18

CKE Input Setup Time tISCKEb min 2.5 ns

CKE Input Hold Time tIHCKEb min 2.5 ns

Address & Control Input

Setup Time tISb min 1150 ps

Address & Control Input Hold

Time tIHb min 1150 ps

DQS Output Data Access

Time

from CK_t/CK_c tDQSCKb min 2.0 ns

max 10.0

Data Strobe Edge t o

Ouput Data Edge tDQSQb -

1.2 tDQSQb max 1.2 ns

Data Hold Skew Fact or tQHSb max 1.2 ns

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 111 - Revision : P01-004A

Parameter Symbol min

max

min

tCK

LPDDR2 Unit

1066 933 800 667 533 400 333

Mode Register Parameters ns

MODE REGISTER Write

command period tMRW min 5 5 tCK(avg)

Mode Register Read c ommand

period tMRR min 2 2 tCK(avg)

LPDDR2 SDRAM Core Parameters*9

Read Latency RL min 3 8 7 6 5 4 3 3 tCK(avg)

Write Latency WL min 1 4 4 3 2 2 1 1 tCK(avg)

ACTIVE to ACTIVE command

period tRC min tRAS + tRPab (with all-bank Precharge)

tRAS + tRPpb (with per-bank Precharge) ns

CKE min. pulse width during

Self-Refresh

(low pulse width during Self-

Refresh)

tCKESR min 3 15 ns

Self refresh ex i t to next valid

command delay tXSR min 2 tRFCab + 10 ns

Exit power down to next valid

command delay tXP min 2 7.5 ns

LPDDR2-S4 CAS to CAS delay tCCD min 2 2 tCK(avg)

Internal Read to P recharge

command delay tRTP min 2 7.5 ns

RAS to CAS Delay

tRCD Fast 3 15 ns

Row Prechar ge Ti m e

(single bank) tRPpb Fast 3 15 ns

Row Precharge Time

(all banks) tRPab

8-bank Fast 3 18 ns

Row Active Time tRAS min 3 42 ns

max 70 us

Write Recove ry Time tWR min 3 15 ns

Internal Write to Read

Command Delay tWTR min 2 7.5 10 ns

Active bank A t o Active bank B tRRD min 2 10 ns

Four Bank Activ ate Window tFAW min 8 50 60 ns

Minimum Deep P ower Down

Time tDPD min 500 us

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 112 - Revision : P01-004A

Parameter Symbol min /

max min

tCK LPDDR2 Unit

1066 933 800 667 533 400 333

LPDDR2 Temperature De-Rating

tDQSCK De-Rating tDQSCK

(Derated) max 5620 6000 ps

Core Timings Temperature

De-Rating

tRCD

(Derated) min tRCD + 1.875 ns

tRC (Derated) min tRC + 1.875 ns

tRAS

(Derated) min tRAS + 1.875 ns

tRP (Derated) min tRP + 1.875 ns

tRRD

(Derated) min tRRD + 1.875 ns

Note :1. Input set-up/hold time for signal(CA[0:n], CS_n)

2. CKE input setup time is measured from CKE reaching high/low voltage level to CK_t/CK_c crossing.

3. CKE input hold time is measured from CK_t/CK_c crossing to CKE reaching high/low voltage level

4. Frequency values are for reference only. Clock cycle time (tCK) shall be used to determine device capabilities.

5. To guarantee device operation before the LPDDR2 dev ice is configured a number of AC boot timing parameters are defined in this

Table. Boot parameter symbols have the letter b appended, e.g. tCK during boot is tCKb.

6. Frequency values are for reference only. Clock cycle time (tCK or tCKb) shall be used to determine device capabilities.

7. The SDRAM will set some Mode register default values upon receiving a RESET (MRW) command as specified in “Mode Register

Definition”.

8. The output skew parameters are measured with Ron default settings into the reference load.

9. The min tCK column applies only when tCK is greater than 6ns for LPDDR2-S4 devices .

10. All AC timings assume an input slew rate of 1V/ns.

11. Read, Write, and Input Setup and Hold values are referenced to Vref.

12. For low-to-high and high-to-low transitions, the timing reference will be at the point when the signal crosses VTT. tHZ and tLZ

transitions occur in the same access tim e (with respect to clock) as valid data transitions. Thes e parameters are not referenced to a

specific voltage level but to the time when the device output is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ) ), or begins

driving (for tRPRE, tLZ(DQS), tLZ(DQ) ). Figure below shows a method to calculate the point when device is no longer driving

tHZ(DQS) and tHZ(DQ), or begi ns driving tLZ(DQS), tLZ(DQ) by measuring the s ignal at two different voltages. The actual v oltage

measurement points are not critical as long as the calculation is consistent.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 113 - Revision : P01-004A

Figure of HSUL_12 Driver Output Reference Load for Ti m i ng and Slew Rate

VTT + 2x Y mV

VTT + Y mV

VTT - Y mV

VTT - 2x Y mV

VTT

Actual waveform

tLZ(DQS), tLZ(DQ)

tHZ(DQS), tHZ(DQ)

VOH - X mV

VOH - 2x X mV

VOL + 2x X mV

VOL + X mV

VTT

VOH

VOL

2x Y

2x X X

T1T2

Stop driving point = 2 x T1 – T2

begin driving point = 2 x T1 – T2

The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters tRPRE and tRPST are

determined from the differential signal DQS_t-DQS_c.

13. Measured from the start driving of DQS_t - DQS_c to the start driving the first rising strobe edge.

14. Measured from the from start driving the last falling strobe edge to the stop driving DQS_t , DQS_c.

15. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous

sequence of bursts within a 160ns rolling window. tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is

< 10C/s. Values do not include clock jitter.

16. tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a 1.6us rolling

window. tDQSCK DM is not tested and is guaranteed by design. Temperature drift in the s ystem is < 10C/s. Values do not inc lude clock

jitter.

17. tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a 32ms rolling

window. tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is < 10C/s. Values do not include clock

jitter.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 114 - Revision : P01-004A

7.6.2 CA and CS_n Setup, Hold and Derating

For all input signals (CA and CS_n) the total tIS (setup time) and tIH (hold time) required is calculated by adding the

data sheet tIS(base) and tIH(base) value to the ΔtIS and ΔtIH derating value respectively. Example: tIS (total

setup time) = tIS(base) + ΔtIS.

Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc)

and the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate

between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than

the nominal slew rate line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value. If the

actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew

rate of a tangent li ne to the actual signal f rom the ac level to dc level i s use d for derating value.

Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max

and the first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate

between the last crossing of Vih(dc)min and the first crossing of VREF(dc). If the actual signal is always later than

the nominal slew rate line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value. If the

actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew

rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value.

For a valid transition the input signal has t o remain above/below V IH/IL(ac) for some t i m e tVAC.

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached

VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and

reach VIH/IL(ac).

For slew rates in between the values listed in Tablebelow, the derating values may obtained by linear interpolation.

These values are t ypically not subject to production test. They are verified by design and characterization.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 115 - Revision : P01-004A

7.6.2.1 Table of CA and CS_n Setup and Hold Base-Values for 1V/ns

unit [ps] LPDDR2 reference

1066 933 800 667 533

tIS(base) 0 30 70 150 240 V

IH/L(ac)=VREF(dc)+-220mV

tIH(base) 90 120 160 240 330 V

IH/L(dc)=VREF(dc)+-130mV

unit [ps] LPDDR2 reference

400 333

tIS(base) 300 440 V

IH/L(ac)=VREF(dc)+-300mV

tIH(base) 400 540 VIH/L(dc)VREF(dc)+-200mV

Note : ac/dc referenced for 1V/ns CA and CS_n slew rate and 2V/ns differential CK_t-CK_c slew rate.

7.6.2.2 Table of Derating values LPDDR2 tIS/tIH - ac/dc based AC220

ΔtIS, ΔtIH derating in [ps] AC/DC based

AC220 Threshold -> VIH(ac)=VREF(dc)+220mV, VIL(ac)=VREF(dc)-220mV

DC100 Threshold -> VIH(dc)=VREF(dc)+130mV, VIL(dc)=VREF(dc)-130mV

CK_t,CK_c Differential Slew Ratee

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns

ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH

ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH

CA ,

CS_n

Slew

Rate

V/ns

2.0 110 65 110 65 110 65

1.5 74 43 73 43 73 43 89 59

1.0 0 0 0 0 0 0 16 16 32 32

0.9 -3 -5 -3 -5 13 11 29 27 45 43

0.8 -8 -13 8 3 24 19 40 35 56 55

0.7 2 -6 18 10 34 26 50 46 66 78

0.6 10 -3 26 13 42 33 58 65

0.5 4 -4 20 16 36 48

0.4 -7 2 17 34

Note: Cell contents shaded in red are defined as ‘not supported’.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 116 - Revision : P01-004A

7.6.2.3 Table of Derating values LPDDR2 tIS/tIH - ac/dc based AC3 00

ΔtIS, ΔtIH derating in [ps] AC/DC based

AC300 Threshold -> VIH(ac)=VREF(dc)+300mV, VIL(ac)=VREF(dc)-300mV

DC200 Threshold -> VIH(dc)=VREF(dc)+200mV, VIL(dc)=VREF(dc)-200mV

CK_t,CK_c Differential Slew Rate

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns

ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH

ΔtIS ΔtIH

CA,

CS_n

Slew

Rate

V/ns

2.0 150 100 150 100 150 100

1.5 100 67 100 67 100 67 116 83

1.0 0 0 0 0 0 0 16 16 32 32

0.9 -4 -8 -4 -8 12 8 28 24 44 40

0.8 -12 -20 4 -4 20 12 36 28 52 48

0.7 -3 -18 13 -2 29 14 45 34 61 66

0.6 2 -21 18 -5 34 15 50 47

0.5 -12 -32 4 -12 20 20

0.4 -35 -40 -11 -8

Note: Cell contents shaded in red are defined as ‘not supported’.

7.6.2.4 Table of Required ti m e tVAC above VIH(ac ) { below VIL(ac)} for valid transition

Slew Rate [V/ns] tVAC @ 300 mV [ps] tVAC @ 220mV [ps]

min max min max

> 2.0 75 - 175 -

2.0 57 - 170 -

1.5 50 - 167 -

1.0 38 - 163 -

0.9 34 - 162 -

0.8 29 - 161 -

0.7 22 - 159 -

0.6 13 - 155 -

0.5 0 - 150 -

<0.5 0 - 150 -

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 117 - Revision : P01-004A

7.6.2.5 Figure of nominal slew rate and tVAC for tIS for CA and CS_n with respect to clock.

CK_c

CK_t

DDCA

VIH(ac) min

VIH(dc) min

VREF(dc)

VIL(dc) max

VIL(ac) max

VREF to ac

region

nominal

Slew rate

nominal

Slew rate

REF to ac

region

IHtIH

tIS tIS

tVAC

VssCA

Setup Slew Rate = VREF(dc) - VIL(ac)max

Falling Signal Δ TF Setup Slew Rate = V

IH(ac) min - VREF(dc)

Rising Signal Δ TR

Δ TF Δ TR

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 118 - Revision : P01-004A

7.6.2.6 Figure of nomin al slew rate for hold ti m e tIH for CA and CS_n with respect to clock

CK_t

CK_c

VDDCA

VIH(AC) min

VIH(DC) min

VREF(DC)

VIL(DC) max

VIL(AC) max

DC to VREF

region

nominal

Slew rate

nominal

Slew rate

DC to VREF

region

tIH

tIS tIS

Hold Slew Rate = VREF(DC) - VIL(DC)max

Rising Signal Δ TR

Hold Slew Rate = VIH(DC) min - VREF(DC)

Falling Signal Δ TF

Δ TF

Δ TR

VSSCA

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 119 - Revision : P01-004A

7.6.2.7 Figure of tange nt line for setup time t IS for CA and CS_n wit h r espect to clock

CK_c

CK_t

DDCA

IH(AC)

min

IH(DC)

min

REF(DC)

IL(DC)

max

IL(AC)

max

nominal

line

tangent

line

tangent

line

nominal

line

REF to AC

region

REF to AC

region

Δ TR

Δ TF

VAC

Setup Slew Rate = tangent line[V

REF(DC) - VIL(AC)max]

Falling Signal Δ TF

Setup Slew Rate = tangent line[V

IH(AC)

min - V

REF(DC)

]

Rising Signal Δ TR

VSSCA

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 120 - Revision : P01-004A

7.6.2.8 Figure of tange nt line for for hold time tIH for CA and CS_n with respect to clock

CK_t

CK_c

DDCA

IH(AC)

min

IH(DC)

min

REF(DC)

IL(DC)

max

IL(AC)

max

DC to V

REF

region

DC to V

REF

region nominal

line

nominal

line

tangent

line

tangent

line

Δ TR Δ TF

Hold Slew Rate = tangent line [V

REF(DC)

- V

IL(DC)

max

Rising Signal Δ TR

Hold Slew Rate = tangent line [V

IH(DC)

min - V

REF(DC)

]

Falling Signal Δ TF

VSSCA

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 121 - Revision : P01-004A

7.6.3 Data Setup, Hold and Slew Rate Derating

For all input signals (DQ, DM) the total tDS (setup time) and tDH (hold time) required is calculated by adding the

data sheet tDS(base) and tDH(base) value to the ΔtDS and ΔtDH derating value respectively. Example: tDS

(total setup tim e) = tDS(base) + ΔtDS.

Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc)

and the first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate

between the last crossing of VREF(dc) and the f i rst crossing of VIL(ac)max. If the actual signal is always earlier than

the nominal slew rate line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value. If the

actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew

rate of a tangent li ne to the actual signal f rom the ac level to dc level is used for d erat i ng value.

Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max

and the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling sig5nal is defined as the slew rate

between the last crossing of VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than

the nominal slew rate line between shaded ‘dc level to VREF(dc) region’, use nominal slew rate for derating value. If

the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the

slew rate of a t angent line to the actual si gnal from the dc level to VRE F(dc) level is used f or derating value.

For a valid transition the input signal has t o remain above/below V IH/IL(ac) for some t i m e tVAC.

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached

VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and

reach VIH/IL(ac).

For slew rates in bet ween the values listed i n the tables the derating values may obtained by linear interpolation.

These values are t ypically not subject to production test. They are verified by design and characterization

7.6.3.1 Table of Data Setup and Hold Base-Values

[ps]

LPDDR2

reference

1066

933

800

667

533

tDS(base) -10 15 50 130 210 V

IH/L(ac)=VREF(dc)+-220mV

tDH(base)

80 105 140 220 300

IH/L(dc)=VREF(dc)+-130mV

unit [ps]

LPDDR2

reference

400 333

tDS(base) 180 300 V

IH/L(ac)=VREF(dc)+-300mV

tDH(base) 280 400 V

IH/L(dc)VREF(dc)+-200mV

Note : ac/dc referenced for 1V/ns DQ,DM slew rate and 2V/ns differential DQS_t-DQS_c slew rate

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 122 - Revision : P01-004A

7.6.3.2 Table of Derating values LPDDR2 tDS /tDH - ac/dc based AC220

ΔtDS, ΔDH derating in [ps] AC/DC based a

AC220 Threshold -> VIH(ac)=VREF(dc)+220mV, VIL(ac)=VREF(dc)-220mV

DC130 Threshold -> VIH(dc)=VREF(dc)+130mV, VIL(dc)=VREF(dc)-130mV

DQS_t, DQS_c Differential Slew Rate

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns

ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH

DQ, DM

Slew

Rate

V/ns

2.0 110 65 110 65 110 65 - - - - - - - - - -

1.5 74 43 73 43 73 43 89 59 - - - - - - - -

1.0 0 0 0 0 0 0 16 16 32 32 - - - - - -

0.9 - - -3 -5 -3 -5 13 11 29 27 45 43 - - - -

0.8 - - - - -8 -13 8 3 24 19 40 35 56 55 - -

0.7 - - - - - - 2 -6 18 10 34 26 50 46 66 78

0.6 - - - - - - - - 10 -3 26 13 42 33 58 65

0.5 - - - - - - - - - - 4 -4 20 16 36 48

0.4 - - - - - - - - - - - - -7 2 17 34

Note: Cell contents shaded in red are defined as ‘not supported’.

7.6.3.3 Table of Derating values LPDDR2 tDS /tDH - ac/dc based AC300

ΔtDS, ΔDH derating in [ps] AC/DC based a

AC300 Threshold -> VIH(ac)=VREF(dc)+300mV, VIL(ac)=VREF(dc)-300mV

DC200 Threshold -> VIH(dc)=VREF(dc)+200mV, VIL(dc)=VREF(dc)-200mV

DQS_t, DQS_c Differential Slew Rate

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns

ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH

DQ, DM

Slew

Rate

V/ns

2.0 150 100 150 100 150 100 - - - - - - - - - -

1.5 100 67 100 67 100 67 116 83 - - - - - - - -

1.0 0 0 0 0 0 0 16 16 32 32 - - - - - -

0.9 - - -4 -8 -4 -8 12 8 28 24 44 40 - - - -

0.8 - - - - -12 -20 4 -4 20 12 36 28 52 48 - -

0.7 - - - - - - -3 -18 13 -2 29 14 45 34 61 66

0.6 - - - - - - - - 2 -21 18 -5 34 15 50 47

0.5 - - - - - - - - - - -12 -32 4 -12 20 20

0.4 - - - - - - - - - - - - -35 -40 -11 -8

Note: Cell contents shaded in red are defined as ‘not supported’.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 123 - Revision : P01-004A

7.6.3.4 Table of Required ti m e tVAC above VIH(ac ) { below VIL(ac)} for valid transition

Slew Rate [V/ns] t

VAC

@ 300mV [ps] t

VAC

@ 220mV [ps]

min max min max

> 2.0 75 - 175 -

2.0 57 - 170 -

1.5 50 - 167 -

1.0 38 - 163 -

0.9 34 - 162 -

0.8 29 - 161 -

0.7 22 - 159 -

0.6 13 - 155 -

0.5 0 - 150 -

< 0.5 0 - 150 -

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 124 - Revision : P01-004A

7.6.3.5 Figure of nomin al slew rate and tVAC f or setup time tDS for DQ with respect to strobe

DQS_t

DQS_c

tDH

tDS tDS

VDDQ

nominal

Slew rate

VIH(AC) min

VIH(DC) min

VREF(DC)

VIL(DC) max

VIL(AC) max

VssQ

nominal

Slew rate

VREF to AC

region

VREF to AC

region

tVAC

Δ TR

Δ TF

Setup Slew Rate = VREF(DC) - VIL(AC)max

Falling Signal Δ TF Setup Slew Rate = VIH(AC)min - VREF(DC)

Rising Signal Δ TR

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 125 - Revision : P01-004A

7.6.3.6 Figure of nomin al slew rate for hold ti m e tDH for DQ with respec t to strobe

DQS_t

DQS_c

IH(AC)

min

IH(DC)

min

REF(DC)

IL(DC)

max

IL(AC)

max

VssQ

DDQ

Hold Slew Rate = [VREF(DC) - VIL(DC)max

Rising Signal Δ TR

DC to V

REF

region

nominal

Slew rate

nominal

Slew rate

DC to V

REF

region

Hold Slew Rate = [V

IH(DC)

min - V

REF(DC)

Falling Signal Δ TF

Δ TFΔ TR

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 126 - Revision : P01-004A

7.6.3.7 Figure of tange nt line for setup time t D S for DQ with respect to strobe

DQS_c

DQS_t t

IH(ac)

min

DDQ

Setup Slew Rate = tangent line[VIH(ac)min - VREF(dc)

Rising Signal Δ TR

VAC Δ TR

tangent

line

REF to ac

region

nominal

line

IH(dc)

min

REF(dc)

IL(dc)

max

IL(ac)

max

VssQ

tangent

line

nominal

line

REF to ac

region

Δ TF

VAC

Setup Slew Rate = tangent line[VREF(dc) - VIL(ac)max]

Falling Signal Δ TF

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 127 - Revision : P01-004A

7.6.3.8 Figure of tange nt line for for hold time tDH for DQ with respect to strobe

DQS_c

DQS_t t

DDQ

IH(AC)

min

IH(DC)

min

REF(DC)

IL(DC)

max

IL(AC)

max

VssQ

tangent

line

nominal

line

DC to V

REF

region

Δ TR Δ TF

Hold Slew Rate = tangent line [VREF(DC) - VIL(DC)max

Rising Signal Δ TR

DC to V

REF

region

tangent

line

nominal

line

Hold Slew Rate = tangent line [VIH(DC)min - VREF(DC)]

Falling Signal Δ TF

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 128 - Revision : P01-004A

8. REVISION HISTO RY

Version Date Page Description

P01-001

05/18/2012

All New create document .

P01-002

06/14/2013

1,9,78,99

1,45~48,78,106

100

Update Temp.

Add ordering Info & update part#.

Add tZQINIT(8.2.2)

Add 6.4.7.2 note 2.

Update 6.4.2 2.2 bank MRR:Idle to A ct i ve.

Remove "option" text.

Update Tc to Tj.

Add DQ text.

Remove IDD4RQ.

P01-003

10/24/2013

99~101 Add IDDx v al ue (400 MHz).

P01-004

11/15/2013

99~101 Update typical IDDx value for 400MHz.

P01-004A 7/15/2014 N/A Document modified f or MCP implement ation.

PRELIMINARY W97AH2KK

LPDDR2 S-4B 1Gb

Publication Release : July 15, 2014

- 129 - Revision : P01-004A

[DISCLAIMER]

This specification and all associated documentation, comments or other information (collectively “SPECIFICATION”)

is provided “AS IS” without warranty of any kind. Winbond Electronics Corporation (“WEC”) hereby disclaims all wa

rranties express or implied, including but not limited to, noninfringement of third party rights, and any implied

warranties of merchantability or fitness for any particular purpose. Wec does not warrant that the specification will

meet your requirements. Furthermore, wec does not make any pepresentations regarding the use or the results of

the use of the specification in terms of its correctness, accuracy, reliability, or otherwise. The entire risk arising out

of use or performance of the specification shall remain with you. In no event shall wec, its affiliated companies or

their suppliers be liable for any direct, indirect, consequential, incidental, or special damages (including, without

limitation, damages for loss of profits, business interruption, or loss of information) arising out of your use of or

inability to us e the specification, ev en i f wec has been advised of the possibility of such damages.

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components in systems or

equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments,

transportation instruments, traffic signal instruments, combustion control instruments, or for other applications

intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or severe property or

environmental damage could occur. Winbond customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or

sales.

-------------------------------------------------------------------------------------------------------------------------------------------------

Please note th at all data and specifi cat ions are subject t o change without not ice.

All the tradem ar ks of products and co mpanies mentioned in the datasheet belong to their respective owners.