© Semiconductor Components Industries, LLC, 2007
September, 2007 - Rev. 3
1Publication Order Number:
NB4N507A/D
NB4N507A
3.3V/5V, 50 MHz to 200 MHz
PECL Clock Synthesizer
Description
The NB4N507A is a precision clock synthesizer which generates a
very low jitter differential PECL output clock. It produces a clock
output based on an integer multiple of an input reference frequency.
The NB4N507A accepts a standard fundamental mode crystal,
using Phase-Locked-Loop (PLL) techniques, will produce output
clocks up to 200 MHz. In addition, the PLL circuitry will produce a
50% duty cycle square-wave clock output (see Figure 7).
The NB4N507A can be programmed to generate a selection of input
reference frequency multiples. An exact 155.52 MHz output clock can
be generated from a 19.44 MHz crystal and the x8 multiplier selection.
The NB4N507A is intended for low output jitter clock generation.
The PECL outputs are 15 mA open collector and must be DC loaded
and AC terminated. See Figures 4 and 6.
Features
•Input Crystal Frequency of 10 - 27 MHz
•Enable Usage of Common Low-Cost Crystal
•Differential PECL Output Clock Frequencies up to 200 MHz
•Duty Cycle of 48%/52%
•Operating Range: VCC = 3.0 V to 5.5 V
•Ideal for SONET Applications and Oscillator Manufacturers
•Available in Die Form
•Packaged in 16-Pin Narrow SOIC
•Pb-Free Packages are Available*
Figure 1. Simplified Logic Block Diagram
Osc PD CP VCO PECL
Mult
S1S0
CLKOUT
CLKOUT
OE
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
SOIC-16
D SUFFIX
CASE 751B
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
MARKING DIAGRAM
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NB4N507AG
AWLYWW
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb-Free Package
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Figure 2. NB4N507A Logic Diagram
Crystal
VDD
Feedback
Oscillator
Buffer
X1/CLK
X2
Phase
Detector
GND
Charge
Pump VCO
PECL
Output
Multiplier
Select
S1S0
CLKOUT
CLKOUT
OE
X2
NC
S0
OE
NC
NC
NCNC
GND
GND
S1
VDD
VDD
X1/CLK
Figure 3. 16-Pin SOIC (Top View)
16
15
14
13
12
11
10
CLKOUTCLKOUT 9
1
2
3
4
5
6
7
8
Table 1. CLOCK MULTIPLIER SELECT TABLE
S1 S0 Multiplier
L L 9.72X*
L M 10X
L H 12X
M L 6.25X
M M 8X
M H 5X
H L NA
H M 3X
H H 4X
*Example Crystal = 16 MHz, fCLKOUT = 155.52 MHz
L = GND
H = VDD
M = OPEN
Table 2. OE, OUTPUT ENABLE FUNCTION
OE Function
0 Disable
1 Enable
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Table 3. PIN DESCRIPTION
Pin #
SOIC-16 Name I/O Description
1 X1/CLK Crystal Input Crystal or Clock Input
2,3 VDD Power Supply Positive Supply Voltage (3.0 V to 5.5 V)
4 S1 Tri-Level Input Multiplier Select Pin; When Left Open, Defaults to VDD B 2
5,6 GND Power Supply Negative Supply Voltage
7,10,11,12,
15
NC No Connect Pin 10 does not require an external resistor. The NB4N507A will function with or
without a resistor on Pin 10.
8 CLKOUT PECL Output* Non-inverted differential PECL clock output.
9 CLKOUT PECL Output* Inverted differential PECL clock output.
13 OE (LV)CMOS/(LV)TTL
Input
Output Enable for the CLKOUT/CLKOUT Outputs. Outputs are
enabled when HIGH or when left open; OE pin has internal pullup resistor. Disables
both outputs when LOW. CLKOUT goes LOW, CLKOUT goes HIGH.
14 S0 Tri-Level Input Multiplier Select Pin; When Left Open, Defaults to VDD B 2
16 X2 Crystal Input Crystal Input
*The PECL Outputs are 15 mA open collector and must be DC loaded and AC terminated. See Figures 4, 5 and 6.
Table 4. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 1 kV
> 150 V
> 1 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in
Transistor Count 1145 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC Positive Power Supply GND = 0 V 6 V
VIInput Voltage GND - 0.5 ≤ VI ≤ VDD + 0.5 V
TAOperating Temperature Range -40 to +85 °C
Tstg Storage Temperature Range -65 to +150 °C
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC-16 100
60
°C/W
°C/W
qJC Thermal Resistance (Junction-to-Case) (Note 2) SOIC-16 33 to 36 °C/W
Tsol Wave Solder Pb
Pb-Free
< 3 sec @ 248°C
< 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board - 2S2P (2 signal, 2 power).
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Table 6. DC CHARACTERISTICS (VDD = 3.0 V to 5.5 V, GND = 0 V, TA = -40°C to +85°C (Note 3))
Symbol Characteristic Min Typ Max Unit
IDD Power Supply Current VDD = 5 V
(does not include output load resistor current) VDD = 3.3 V
15
10
27
23
35
30
mA
mA
VOH Output HIGH Voltage (Notes 5 & 6) VDD = 5 V
VDD = 3.3 V
3.95
2.57
4.05
2.67
4.15
2.77
V
VOL Output LOW Voltage (Notes 5 & 6) VDD = 5 V
VDD = 3.3 V
3.12
1.90
3.20
2.00
3.30
2.10
V
VIH Input HIGH Voltage (Note 4) S0, S1, X1/CLK
OE
VDD – 0.5
2.0
VDD V
VIL Input LOW Voltage,(Note 4) S0, S1, X1/CLK
OE
0 0.5
0.8
V
CxInternal Crystal Capacitance, X1 & X2 0 pF
Cin Input Capacitance, S0, S1, OE 5.0 pF
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. PECL output parameters vary 1:1 with VDD.
4. S0 and S1 default to VDD B 2 when left open.
Table 7. AC CHARACTERISTICS (VDD = 3.0 V to 5.5 V, GND = 0 V, TA = -40°C to +85°C (Note 5))
Symbol Characteristic Min Typ Max Unit
fXtal Crystal Input Frequency (Note 7) 10 27 MHz
fCLK Input Clock Frequency (Note 8) 5 52 MHz
fOUT Output Frequency Range 50 200 MHz
Vout pk-pk Output Amplitude 550 680 mV
DC Clock Output Duty Cycle (Note 8) 48 52 %
PLLBW PLL Bandwidth (Note 8) 10 kHz
tjitter (pd) Period Jitter (RMS, 1s, 10,000 Cycles) 10 ps
tjitter (pd) Period Jitter (Peak-to-Peak, 10,000 Cycles) $20 ps
tr/tf Output Rise and Fall Times (Note 8) 50 270 500 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. PECL outputs loaded with external resistors for proper operation (see Figures 4, 5 and 6).
6. VOH and VOL can be set by the external resistors, which can be modified.
7. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors
should be connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by the following equation, where CL
is the specified crystal load capacitance: Crystal caps (pF) = (CL-5) x 2. So, for a crystal with 16 pF load capacitance, use two 22 pF caps,
including board trace capacitance (see Figure 7).
8. Guaranteed by design and characterization.
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Figure 4. Output Structure
GND
15 mA
Current Source
Q
Q
NB4N507
PECL
Driver
PECL
Receiver
D
GND
GND
Figure 5. Evaluation Test Load for the NB4N507A
GND
GND
VDD
VDD
VDD
D
z = 50 W
270 W
62 W
62 W
z = 50 W
z = 50 W
z = 50 W
270 W
Receiver
A
Figure 6. Alternate Termination for Output Driver and Device Evaluation
VDD
50 W50 W
Z = 50 W
Z = 50 W
NB4N507A
VDD
VDD
GND = 0 V
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APPLICATIONS INFORMATION
High Frequency Differential PECL Oscillators: The
NB4N507A, along with a low frequency fundamental mode
crystal, can build a high frequency differential PECL output
oscillator. For example, a 10 MHz crystal connected to the
NB4N507A with the 12X output selected (S1 = 0, S0 = 1)
produces a 120 MHz PECL output clock.
Crystal Oscillator Input Interface
The NB4N507A features an integrated crystal oscillator
to minimize system implementation costs. The oscillator
circuit is a parallel resonant circuit and thus, for optimum
performance, a parallel resonant crystal should be used.
As the oscillator is somewhat sensitive to loading on its
inputs, the user is advised to mount the crystal as close to the
NB4N507A as possible to avoid any board level parasitics.
Surface mount crystals are recommended, but not required.
Figure 7. Crystal Input Interface
C1
33 pF
X1
18 pF
C2
27 pF
Parallel Crystal
X1/CLK
X2
High Frequency VCXO: The bandwidth of the PLL is
guaranteed to be greater than 10 kHz. This means that the
PLL will track any modulation on the input with a frequency
of less than 10 kHz. By using this property, a low frequency
VCXO can be built. The output can then be multiplied by the
NB4N507A, thereby producing a high frequency VCXO.
High Frequency TCXO: Extending the previous
application, an inexpensive, low frequency TCXO can be
built and the output frequency can be multiplied using the
NB4N507A. Since the output of the chip is phase-locked to
the input, the NB4N507A has no temperature dependence,
and the temperature coefficient of the combined system is
the same as that of the low frequency TCXO.
Decoupling and External Components
The NB4N507A requires a 0.01 mF decoupling capacitor
to be connected between VDD and GND on pins 2 and 5. It
must be connected close to the NB4N507A. Other VDD and
GND connections should be connected to those pins, or to the
VDD and GND planes on the board. Another four resistors are
needed for the PECL outputs as shown in Figure 4. Suggested
values of these resistors are shown, but they can be varied to
change the differential pair output swing, and the DC level.
ORDERING INFORMATION
Device Package Shipping†
NB4N507AD SOIC-16 48 Units / Rail
NB4N507ADG SOIC-16
(Pb-Free)
48 Units / Rail
NB4N507ADR2 SOIC-16 2500 / Tape & Reel
NB4N507ADR2G SOIC-16
(Pb-Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D - ECL Clock Distribution Techniques
AN1406/D - Designing with PECL (ECL at +5.0 V)
AN1503/D -ECLinPSt I/O SPiCE Modeling Kit
AN1504/D - Metastability and the ECLinPS Family
AN1568/D - Interfacing Between LVDS and ECL
AN1672/D - The ECL Translator Guide
AND8090/D AC Characteristics of ECL Devices-
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Resource Reference of Application Notes
AND8001/D - Odd Number Counters Design
AND8002/D - Marking and Date Codes
AND8020/D - Termination of ECL Logic Devices
AND8066/D - Interfacing with ECLinPS
AND8090/D - AC Characteristics of ECL Devices
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PACKAGE DIMENSIONS
SOIC-16
D SUFFIX
CASE 751B-05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
-B-
-A-
M
0.25 (0.010) B S
-T-
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
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Phone: 81-3-5773-3850
NB4N507A/D
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
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