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SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
22.4.3 DDR2-SDRAM Initialization
The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized by the following
sequence:
1. Program the memory device type into the Memory Device Register (see Section 22.8.8 on page 265).
2. Program the features of DDR2-SDRAM device into the Timing Register (asynchronous timing (trc, tras,
etc.)), and into the Configuration Register (number of columns, rows, cas latency and output drive
strength) (see Section 22.8.3 on page 256, Section 22.8.4 on page 259 and Section 22.8.5 on page 261).
3. An NOP command is issued to the DDR2-SDRAM. Program the NOP command into the Mode Register,
the application must set Mode to 1 in the Mode Register (see Section 22.8.1 on page 254). Perform a
write access to any DDR2-SDRAM address to acknowledge this command. Now clocks which drive
DDR2-SDRAM device are enabled.
A minimum pause of 200 μs is provided to precede any signal toggle.
4. An NOP command is issued to the DDR2-SDRAM. Program the NOP command into the Mode Register,
the application must set Mode to 1 in the Mode Register (see Section 22.8.1 on page 254). Perform a
write access to any DDR2-SDRAM address to acknowledge this command. Now CKE is driven high.
5. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks precharge command
into the Mode Register, the application must set Mode to 2 in the Mode Register (See Section 22.8.1 on
page 254). Perform a write access to any DDR2-SDRAM address to acknowledge this command
6. An Extended Mode Register set (EMRS2) cycle is issued to chose between commercial or high tempera-
ture operations. The application must set Mode to 5 in the Mode Register (see Section 22.8.1 on page
254) and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address
must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. For example, with a 16-bit 128 MB DDR2-
SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at
the address 0x20800000.
Note: This address is for example purposes only. The real address is dependent on implementation in the product.
7. An Extended Mode Register set (EMRS3) cycle is issued to set the Extended Mode Register to “0”. The
application must set Mode to 5 in the Mode Register (see Section 22.8.1 on page 254) and perform a
write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so
that BA[1] is set to 1 and BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9
columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at the address
0x20C00000.
8. An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. The application must set Mode
to 5 in the Mode Register (see Section 22.8.1 on page 254) and perform a write access to the DDR2-
SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 0 and
BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank
address, the DDR2-SDRAM write access should be done at the address 0x20400000.
An additional 200 cycles of clock are required for locking DLL
9. Program DLL field into the Configuration Register (see Section 22.8.3 on page 256) to high (Enable DLL
reset).
10. A Mode Register set (MRS) cycle is issued to reset DLL. The application must set Mode to 3 in the Mode
Register (see Section 22.8.1 on page 254) and perform a write access to the DDR2-SDRAM to acknowl-
edge this command. The write address must be chosen so that BA[1:0] bits are set to 0. For example, with
a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access
should be done at the address 0x20000000.
11. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks precharge command
into the Mode Register, the application must set Mode to 2 in the Mode Register (See Section 22.8.1 on
page 254). Perform a write access to any DDR2-SDRAM address to acknowledge this command
12. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode
Register, the application must set Mode to 4 in the Mode Register (see Section 22.8.1 on page 254). Per-
forms a write access to any DDR2-SDRAM location twice to acknowledge these commands.