ADS7808 ADS 7808 SBAS018A - JANUARY 1992 - REVISED SEPTEMBER 2003 12-Bit 10s Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTER FEATURES DESCRIPTION The ADS7808 is a complete 12-bit sampling analog-to-digital using state-of-the-art CMOS structures. It contains a 12-bit capacitor-based SAR A/D with S/H, reference, clock, and a serial data interface. Data can be output using the internal clock, or can be synchronized to an external data clock. The ADS7808 also provides an output synchronization pulse for ease of use with standard DSP processors. 100kHz SAMPLING RATE 72dB SINAD WITH 45kHz INPUT 1/2 LSB INL AND DNL SIX SPECIFIED INPUT RANGES SERIAL OUTPUT SINGLE +5V SUPPLY OPERATION PIN-COMPATIBLE WITH 16-BIT ADS7809 USES INTERNAL OR EXTERNAL REFERENCE 100mW MAX POWER DISSIPATION 0.3" SO-20 SIMPLE DSP INTERFACE The ADS7808 is specified at a 100kHz sampling rate, and specified over the full temperature range. Laser-trimmed scaling resistors provide various input ranges including 10V and 0V to 5V, while an innovative design operates from a single +5V supply, with power dissipation under 100mW. The ADS7808 is available in a 0.3" SO-20, fully specified for operation over the industrial -40C to +85C range. CS R/C Power Down Successive Approximation Register and Control Logic Clock 20k CDAC R1IN 10k BUSY R2IN Serial 20k 5k Data Comparator R3IN Data Clock Out Serial Data CAP Buffer Internal +2.5V Ref 4k REF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright (c) 1992-2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY Analog Inputs: R1IN .......................................................................... 25V R2IN .......................................................................... 25V R3IN .......................................................................... 25V CAP ..................................... VANA+0.3V to AGND2 -0.3V REF ....................................... Indefinite Short to AGND2, Momentary Short to VANA Ground Voltage Differences: DGND, AGND2 ................................. 0.3V VANA ...................................................................................................... 7V VDIG to VANA ....................................................................................... +0.3 VDIG ....................................................................................................... 7V Digital Inputs ............................................................. -0.3V to VDIG +0.3V Maximum Junction Temperature .................................................. +165C Internal Power Dissipation ............................................................ 700mW Lead Temperature (soldering, 10s) .............................................. +300C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. PACKAGE/ORDERING INFORMATION PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) MINIMUM SIGNAL-TOSPECIFIED (NOISE + DISTORTION) PACKAGE TEMPERATURE RATIO (DB) PACKAGE-LEAD DESIGNATOR(1) RANGE ADS7808U " 0.9 " 70 " SO-20 " DW " -40C to +85C " ADS7808UB " 0.45 " 72 " " " " " " " PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS7808U " ADS7808U ADS7808U/1K Tube, 38 Tape and Reel, 1000 ADS7808UB ADS7808UB " ADS7808UB/1K Tube, 38 Tape and Reel, 1000 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. ELECTRICAL CHARACTERISTICS At TA = -40C to +85C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors as shown in Figure 4, unless otherwise specified. ADS7808U PARAMETER CONDITIONS MIN TYP RESOLUTION DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise(2) Full Scale Error(3,4) Full Scale Error Drift Full Scale Error(3,4) Full Scale Error Drift Bipolar Zero Error(3) Bipolar Zero Error Drift Unipolar Zero Error(3) Unipolar Zero Error Drift Recovery to Rated Accuracy after Power Down Power Supply Sensitivity (VDIG = VANA = VD) AC ACCURACY Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) Signal-to-Noise Full-Power Bandwidth(6) 2 MIN TYP 12 ANALOG INPUT Voltage Ranges Impedance Capacitance THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate ADS7808UB MAX MAX UNITS Bits 10V, 0V to 5V, etc. (See Table I) See Table I 35 5.7 Acquire and Convert 8 10 0.9 0.9 7 2 2 2 1 0.5 5 0.5 80 70 70 0.45 0.45 LSB(1) LSB 90 -90 73 73 250 0.25 0.25 10 2 5 3 3 0.5 +4.75V < VD < +5.25V 45kHz 45kHz 45kHz 45kHz s s kHz Specified 0.1 fIN = fIN = fIN = fIN = 100 Ext. 2.5000V Ref Ext. 2.5000V Ref Bipolar Ranges Bipolar Ranges 0V to 10V Range 0V to 4V Range 0V to 5V Range Unipolar Ranges 1F Capacitor to CAP pF -80 72 72 LSB % ppm/C % ppm/C mV ppm/C mV mV mV ppm/C ms LSB dB(5) dB dB dB kHz ADS7808 www.ti.com SBAS018A ELECTRICAL CHARACTERISTICS (Cont.) At TA = -40C to +85C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 4, unless otherwise specified. ADS7808U PARAMETER SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response Overvoltage Recovery(7) REFERENCE Internal Reference Voltage Internal Reference Source Current (Must use external buffer) External Reference Voltage Range for Specified Linearity External Reference Current Drain DIGITAL INPUTS Logic Levels VIL VIH(8) IIL IIH DIGITAL OUTPUTS Data Format Data Coding Pipeline Delay Data Clock Internal (Output Only When Transmitting Data) External (Can Run Continually) VOL VOH Leakage Current Output Capacitance POWER SUPPLIES Specified Performance VDIG VANA IDIG IANA Power Dissipation: PWRD LOW PWRD HIGH TEMPERATURE RANGE Specified Performance Derated Performance Storage Thermal Resistance (JA) SO CONDITIONS MIN TYP ADS7808UB MAX MIN No Load MAX 40 Sufficient to meet AC specs 2 150 FS Step TYP 2.5 1 2.52 V A 2.3 2.5 2.7 V A V V A A 100 -0.3 +2.0 +0.8 VD +0.3V 10 10 VIL = 0V VIH = 5V Serial 12 bits Binary Two's Complement or Straight Binary Conversion results only available after completed conversion. Selectable for internal or external data clock 2.3 EXT/INT HIGH 0.1 ISINK = 1.6mA ISOURCE = 500A High-Z State, VOUT = 0V to VDIG High-Z State 10 +0.4 +4.75 +5 0.3 16 +5 +5.25 VDIG = VANA = 5V, fS = 100kHz 5 15 15 pF V mA mA V +5.25 100 75 MHz V V A 50 -40 -55 -65 MHz +4 Must be VANA +4.75 ns ns s ns 2.48 Ext. 2.5000V Ref EXT/INT LOW UNITS +85 +125 +150 CW mW W C C C Specifications same as ADS7808U. NOTES: (1) LSB means Least Significant Bit. For the 10V input range, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and temperatures. (3) As measured with fixed resistors in Figure 4. Adjustable to zero with external potentiometer. (4) For bipolar input ranges, full scale error is the worst case of -Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset error. (5) All specifications in dB are referred to a full-scale 10V input. (6) Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-to (Noise + Distortion) degrades to 60dB. (7) Recovers to specified performance after 2 x FS input overvoltage. (8) The minimum VIH level for the DATACLK signal is 3V. ADS7808 SBAS018A www.ti.com 3 PIN ASSIGNMENTS PIN # NAME 1 R1IN 2 AGND1 3 R2IN DESCRIPTION Analog Input. See Table I and Figure 4 for input range connections. Analog Ground. Used internally as ground reference point. Minimal current flow. Analog Input. See Table I and Figure 4 for input range connections. 4 R3IN Analog Input. See Table I and Figure 4 for input range connections. 5 CAP Reference Buffer Capacitor. 2.2F Tantalum to ground. 6 REF Reference Input/Output. Outputs internal 2.5V reference. Can also be driven by external system reference. In both cases, bypass to ground with a 2.2F Tantalum capacitor. 7 AGND2 Analog Ground. 8 SB/BTC Select Straight Binary or Binary Two's Complement data output format. If HIGH, data will be output in a Straight Binary format. If LOW, data will be output in a Binary Two's complement format. 9 EXT/INT Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized to the clock input on DATACLK. If LOW, a convert command will initiate the transmission of the data from the previous conversion, along with 12 clock pulses output on DATACLK. 10 DGND Digital Ground. 11 SYNC Synch Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on CS with R/C HIGH will output a pulse on SYNC synchronized to the external DATACLK. 12 DATACLK 13 DATA 14 TAG Tag Input for use in external clock mode. If EXT/INT is HIGH, digital data input on TAG will be output on DATA with a delay of 12 DATACLK pulses as long as CS is LOW and R/C is HIGH. See Figure 3. 15 R/C Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion. When EXT/INT is LOW, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is HIGH, a rising edge on R/C with CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the transmission of data from the previous conversion. Either an input or an output depending on the EXT/INT level. Output data will be synchronized to this clock. If EXT/INT is LOW, DATACLK will transmit 12 pulses after each conversion, and then remain LOW between conversions. Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the level of SB/BTC. In the external clock mode, after 12-bits of data, the ADS7808 will output the level input on TAG as long as CS is LOW and R/C is HIGH (see Figure 3.) If EXT/INT is LOW, data will be valid on both the rising and falling edges of DATACLK, and between conversions DATA will stay at the level of the TAG input when the conversion was started. 16 CS 17 BUSY Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the output shift register. CS or R/C must be HIGH when BUSY rises, or another conversion will start without time for signal acquisition. Chip Select. Internally OR'ed with R/C. 18 PWRD Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the previous conversion are maintained in the output shift register. 19 VANA Analog Supply Input. Nominally +5V. Connect directly to pin 20, and decouple to ground with 0.1F ceramic and 10F Tantalum capacitors. 20 VDIG Digital Supply Input. Nominally +5V. Connect directly to pin 19. Must be VANA. PIN CONFIGURATION R1IN 1 AGND1 2 19 VANA R2IN 3 18 PWRD R3IN 4 17 BUSY CAP 5 REF 6 15 R/C AGND2 7 14 TAG SB/BTC 8 13 DATA EXT/INT 9 12 DATACLK DGND 10 4 20 VDIG ADS7808 ANALOG INPUT RANGE CONNECT R1IN VIA 200 TO 10V 5V 3.33 0V to 10V 0V to 5V 0V to 4V VIN AGND VIN AGND AGND VIN CONNECT R2IN VIA 100 CONNECT R3IN TO TO AGND VIN VIN VIN AGND AGND CAP CAP CAP AGND VIN VIN IMPEDANCE 22.9k 13.3k 10.7k 13.3k 10.0k 10.7k 16 CS TABLE I. Input Range Connections. See Figure 4 for complete information. 11 SYNC ADS7808 www.ti.com SBAS018A SYMBOL DESCRIPTION MIN TYP MAX UNITS t1 Convert Pulse Width t2 BUSY Delay 65 ns t3 BUSY LOW 8 s t4 BUSY Delay after End of Conversion 220 ns t5 Aperture Delay 40 ns t6 Conversion Time 5.7 t7 Acquisition Time t6 + t7 Throughput Time 40 4500 t1 CS, R/C ns t3 BUSY t2 t4 t5 MODE Acquire 9 8 s 2 s 10 s t8 R/C LOW to DATACLK Delay 450 ns t9 DATACLK Period 440 ns t10 Data Valid to DATACLK HIGH Delay 20 75 ns t11 Data Valid after DATACLK LOW Delay 100 125 ns t12 External DATACLK Period 100 t13 External DATACLK HIGH 20 ns t14 External DATACLK LOW 30 ns t15 DATACLK HIGH Setup Time 20 t16 R/C to CS Setup Time 10 t17 SYNC Delay After DATACLK HIGH 15 35 55 Convert Acquire t6 t7 FIGURE 1. Basic Conversion Timing. ns t12 + 5 ns ns ns t18 Data Valid Delay 25 t19 CS to Rising Edge Delay 25 ns t20 Data Available after CS LOW 4.5 s ns TABLE II. Conversion and Data Timing TA = -40C to +85C. t8 R/C t9 1 DATACLK 2 3 11 12 Bit 9 Valid Bit 1 Valid LSB Valid t11 t10 SDATA MSB Valid Bit 10 Valid t2 t3 BUSY FIGURE 2. Serial Data Timing Using Internal Clock. (CS, EXT/INT and TAG Tied LOW.) ADS7808 SBAS018A www.ti.com 5 SPECIFIC FUNCTION CS R/C Initiate Conversion and Output Data Using Internal Clock 1>0 0 1 0 Output 0 x Initiates conversion "n". Data from conversion "n-1" clocked out on DATA synchronized to 12 clock pulses output on DATACLK. 0 1>0 1 0 Output 0 x Initiates conversion "n". Data from conversion "n-1" clocked out on DATA synchronized to 12 clock pulses output on DATACLK. 1>0 0 1 1 Input 0 x Initiates conversion "n". 0 1>0 1 1 Input 0 x Initiates conversion "n". 1>0 1 1 1 Input x x Outputs a pulse on SYNC followed by data from conversion "n" clocked out synchronized to external DATACLK. 1>0 1 0 1 Input 0 x Outputs a pulse on SYNC followed by data from conversion "n-1" clocked out synchronized to external DATACLK.(1) Conversion "n" in process. 0 0>1 0 1 Input 0 x Outputs a pulse on SYNC followed by data from conversion "n-1" clocked out synchronized to external DATACLK .(1) Conversion "n" in process. Incorrect Conversions 0 0 0>1 x x 0 x CS or R/C must be HIGH or a new conversion will be initiated without time for acquisition. Power Down x x x x x 0 x Analog circuitry powered. Conversion can proceed. x x x x x 1 x Analog circuitry disabled. Data from previous conversion maintained in output registers. x x x x x x 0 Serial data is output in Binary Two's Complement format. x x x x x x 1 Serial data is output in Straight Binary format. Initiate Conversion and Output Data Using External Clock BUSY EXT/INT DATACLK PWRD SB/BTC Selecting Output Format OPERATION NOTE: (1) See Figure 3b for constraints on previous data valid during conversion. Table III. Control Truth Table. DIGITAL OUTPUT BINARY TWO'S COMPLEMENT (SB/BTC LOW) DESCRIPTION Full-Scale Range Least Significant Bit (LSB) +Full Scale (FS - 1LSB) Midscale One LSB Below Midscale -Full Scale HEX BINARY CODE CODE HEX BINARY CODE 3.99902V 0111 1111 1111 7FF 1111 1111 1111 FFF 2V 0000 0000 0000 000 1000 0000 0000 800 1.99902V 1111 1111 1111 FFF 0111 1111 1111 7FF 0V 1000 0000 0000 800 0000 0000 0000 000 ANALOG INPUT 10 5 3.33V 4.88mV 2.44mV 1.63mV 9.99512V 4.99756V 3.33171V 0V 0V 0V -4.88mV -2.44mV -1.63mV -10V -5V -3.333333V 0V to 5V 0V to 10V 1.22mV 2.44mV 4.99878V 9.99756V 2.5V 5V 2.49878V 4.99756V 0V 0V STRAIGHT BINARY (SB/BTC HIGH) CODE 0V to 4V 0.98mV Table IV. Output Codes and Ideal Input Voltages. 6 ADS7808 www.ti.com SBAS018A FIGURE 3a. Conversion and Read Timing with External Clock. (EXT/INT Tied HIGH). Read After Conversion. ADS7808 SBAS018A www.ti.com 7 TAG DATA SYNC BUSY R/C CS EXTERNAL DATACLK t16 t2 t1 0 t13 t16 t12 t14 t17 t15 1 t12 Tag 0 t18 2 Tag 1 Bit 11 (MSB) 3 Tag 2 Bit 10 4 Tag 11 Bit 1 13 Tag 12 Bit 0 (LSB) 14 Tag 13 Tag 0 Tag 1 Tag 14 t19 Tag 15 Tag 15 Tag 14 Tag 13 Tag 1 Tag 1 t15 t17 Tag 0 t12 t18 t20 Bit 11 (MSB) Tag 12 Bit 0 (LSB) Tag 0 t19 t1 t14 t12 TAG DATA SYNC BUSY R/C CS EXTERNAL DATACLK t16 t2 t13 FIGURE 3b. Conversion and Read Timing with External Clock. (EXT/INT Tied HIGH.) Read During Conversion (Previous Conversion Results). 8 ADS7808 www.ti.com SBAS018A Input Range With Trim (Adjust offset first at 0V, then adjust gain) Without Trim 200 200 R1IN R1IN AGND1 AGND1 100 100 VIN R2IN 33.2k R3IN 0V - 10V R2IN VIN 33.2k R3IN +5V 2.2F CAP + CAP 50k 2.2F 576k REF 2.2F + +5V REF 50k + + 2.2F AGND2 AGND2 200 200 R1IN R1IN AGND1 AGND1 100 100 R2IN 33.2k 0V - 5V R3IN VIN R2IN 33.2k R3IN VIN +5V CAP CAP + +5V 2.2F REF 2.2F 576k + 50k 2.2F REF 50k + 2.2F AGND2 AGND2 200 200 VIN VIN R1IN R1IN AGND1 AGND1 100 100 0V - 4V R2IN R2IN R3IN R3IN 33.2k 2.2F + +5V CAP + 33.2k +5V 2.2F REF + 2.2F 576k 50k CAP REF 50k 2.2F AGND2 + + AGND2 FIGURE 4a. Offset/Gain Circuits for Unipolar Input Ranges. ADS7808 SBAS018A www.ti.com 9 Input Range With Trim (Adjust offset first at 0V, then adjust gain) Without Trim 200 200 VIN VIN R1IN R1IN AGND1 AGND1 100 100 R2IN 10V R2IN +5V 33.2k R3IN 33.2k R3IN 50k +5V CAP + 2.2F 576k 2.2F REF 2.2F CAP + REF 50k + 2.2F + AGND2 AGND2 200 200 R1IN R1IN AGND1 AGND1 100 100 R2IN VIN 33.2k R2IN VIN 33.2k 5V R3IN 2.2F +5V CAP + REF 2.2F CAP +5V 50k 2.2F R3IN + 576k REF 50k + + 2.2F AGND2 AGND2 200 200 VIN VIN R1IN 100 R1IN AGND1 100 AGND1 R2IN R2IN 3.33V R3IN 33.2k R3IN 33.2k 2.2F +5V CAP + CAP +5V 50k + 576k REF 2.2F + REF 50k + 2.2F AGND2 2.2F AGND2 FIGURE 4b. Offset/Gain Circuits for Bipolar Input Ranges. 10 ADS7808 www.ti.com SBAS018A PACKAGE OPTION ADDENDUM www.ti.com 26-Mar-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) ADS7808P OBSOLETE PDIP N 20 TBD Call TI Call TI ADS7808PB OBSOLETE PDIP N 20 TBD Call TI Call TI ADS7808U ACTIVE SOIC DW 20 38 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7808U/1K ACTIVE SOIC DW 20 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR ADS7808U/1KE4 ACTIVE SOIC DW 20 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR ADS7808UB ACTIVE SOIC DW 20 38 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7808UB/1KE4 ACTIVE SOIC DW 20 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR ADS7808UBE4 ACTIVE SOIC DW 20 38 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR ADS7808UBG4 ACTIVE SOIC DW 20 38 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS7808UE4 ACTIVE SOIC DW 20 38 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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