32K x 8 Reprogrammable Registered PROM
CY7C277
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-04006 Rev. ** Revised March 4, 2002
77
Features
• Window ed for reprogramm abi lity
• CMOS for optimum speed/power
• High speed
—30-ns address set-up
—15-ns clock to output
• Low power
—60 mW (commercial)
—715 mW (military)
• Programmable address latch enable input
• Programmable synchronous or asynchronous output
enable
• On-chip edge-triggered output registers
• EPROM technology, 100% programmable
• Slim 300-mil, 28-pin plastic or hermetic DIP
•5V ±10% VCC, commercial and military
•TTL-compatible I/O
•Direct replacement for bipolar PROMs
•Capable of with standing greater than 2001V sta tic dis-
charge
PROGRAMMABLE
MULTIPLEXER
PROGRAMMABLE
CP/ALEOPTIONS
Logic Block Diagram Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12 16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
A10
A11
A12
A13
A14
ALE
CP
E/ES
O7
O6
O4
O5
O3
12
O0
31
4
5
6
7
8
9
10
32130
1314151617
26
25
24
23
22
21
11
A7
V
CC
A6
A5
A4
A3
A2
A1
A0
A13
A14
NC
CP
O7
O6
O5
GND
LCC/PLCC ( Opa que Only)
A12
ALE
A8
O4
O2
O1
181920
27
28
29
32
15
O3
A9
A10
A11
E/ES
NC NC
A14
A13
A12
A11
A10
A9
A8
8-BIT
1 OF 128
MUX
A7
A6
A5
A4
A3
A2
A1
A0
E/ES
CP
15-BIT
ADDRESS
TRANSPARENT/
LATCH
256 x 1024
PROGRAMMABLE
ARRAY
8-BIT
EDGE-
TRIGGERED
REGISTER
ROW
DECODER
1OF256
ALE
COLUMN
DECODER
1OF32
ALE
CP
D
C
Q
NC
Top View
DIP/Flatpack
Top View
Y
ADDRESS
X
ADDRESS
O7
O6
O5
O4
O3
O2
O1
O0
Selection Guide
7C277-30 7C277-40 7C277-50
Minimum Address Set-Up Time (ns) 30 40 50
Maximum Clock to Output (ns) 15 20 25
Maxi mu m Op er at ing
Current (mA) Com’l120 120 120
Mil 130 130
CY7C277
Document #: 38-04006 Rev. ** Page 2 of 13
Functional Description
The CY7C277 is a high-performance 32K word by 8-bit CMOS
PROMs. It is packaged in the slim 28-pin 300-mil package.
The ceramic package may be equipped with an erasure win-
dow; when expos ed to UV l igh t, the PROM is e ras ed an d ca n
then be reprogrammed. The memory cells utilize proven
EPROM floating-gate technology and byte-wide algorithms.
The CY7C277 offers the advantages of low power, superior
performance, and high programming yield. The EPROM cell
requires only 12.5V for the supervoltage and low current re-
quirements allow for gang programming. The EPROM cells
allow for each memory location to be 100% tested, as each
locatio n is writ ten into, era sed, and repea tedly ex ercis ed prior
to encapsulation. Each PROM is also tested for AC perfor-
mance to guarantee that the product will meet DC and AC
specification limits after customer programming.
On the 7C277, the outputs are pipelined through a mas-
ter-slav e register. On the risi ng edge of CP, data is loade d into
the 8-bit edge triggered output register. The E/ES input pro-
vides a programmable bit to select between asynchronous
and synchronous operation. The default condition is asynchro-
nous. Wh en the async hronou s mod e is s elect ed, the E/ES pi n
operates as an asynchronous output enable. If the synchro-
nous mode is selected, the E/ES pin is sampled on the rising
edge of CP to enable and disa ble the outpu ts. The 7C2 77 also
provides a programmable bit to enable the Address Latch in-
put. If this bit is not programmed, the device will ignore the ALE
pin and the address will enter the device asynchronously . If the
ALE function is selected, the address enters the PROM while
the ALE pin is active, and is captured when ALE is deasserted.
The user may define the polarity of the ALE signal, with the
default being acti ve HIGH.
Maximum Ratings
(Above whi ch the use ful life ma y be impa ired. For us er guide-
lines, not tes ted .)
Storage Temperature ....................................−65°C to +150°C
Ambient Temperature wi th
Power Applied.................................................−55°C to +125°C
Supply Voltage to Ground Potential.................−0. 5V to +7.0V
(Pin 24 to Pin 12)
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
DC Input Voltage.................................................−3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20)...........................13.0V
UV Erasure...................................................7258 Wsec/cm2
Static Discharge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 5V ±10%
Industrial[1] −40°C to +85°C 5V ±10%
Military[2] −55°C to +125°C 5V ±10%
Electrical Characteristics Over the Operating Range[3, 4]
Parameter
7C277-30 7C277-40 , 50
Description Test Conditions Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min ., IOH = − 2.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min ., IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Level Guaranteed Input Logical HIGH
Voltage for All Inputs 2.0 VCC 2.0 VCC V
VIL Input LOW Level Guaranteed Input Logical LOW
Voltage for All Inputs 0.8 0.8 V
IIX Input Leakage Current GND < VIN < VCC −10 +10 −10 +10 µA
VCD Input Clamp Di ode Voltage Note 4
IOZ Output Leakage Current 0 < VOUT < VCC, Output Disabled[5] −40 +40 −40 +40 µA
IOS Output Short Circuit Current VCC = Max ., VOUT = 0.0V[6] −20 −90 −20 −90 mA
ICC Power Supply Current VCC = Max., CS > VIH
IOUT = 0 mA Commercial 120 120 mA
Military 130
VPP Programming Supply Voltage 12 13 12 13 V
IPP Programmi ng Supply Current 50 50 mA
VIHP Input HIGH Programm ing Voltage 3.0 3.0 V
VILP Input LOW Programmi ng Voltage 0.4 0.4 V
Notes:
1. Contact a Cypress representative for industrial temperature range specifications.
2. TA is the “instant on ” case temper ature.
3. See the last page of this specifi cat io n for Gro up A subgro up test in g infor ma ti on .
4. See “Introduction to CMOS PROMs” in this Book for general information on testing.
5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
CY7C277
Document #: 38-04006 Rev. ** Page 3 of 13
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0 V 10 pF
COUT Output Capacitance 10 pF
AC Test Loads and W aveforms[4]
3.0V
5V
OUTPUT
R1 500Ω
R2
333Ω
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
<5ns <5ns
5V
OUTPUT
R1 500Ω
R2
333Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) NormalLoad (b) HighZ Load
OUTPUT 2.0V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
(658Ω MIL)
(403Ω MIL ) (403Ω MIL)
OUTPUT 1.9V
Commercial Military
(658Ω MIL)
200Ω250Ω
CY7C277 Switching Characteristics Over the Operating Range[3, 4]
7C277-30 7C277-40 7C277-50
Parameter Description Min. Max. Min. Max. Min. Max. Unit
tAL Address Set-Up to ALE Inactive 510 10 ns
tLA Address Hold from ALE Inactive 10 10 15 ns
tLL ALE Pulse Width 10 10 15 ns
tSA Address Set-Up to Clock HIGH 30 40 50 ns
tHA Address Hold from Clock HIGH 0 0 0 ns
tSES ES Set-Up to Clock HIGH 12 15 15 ns
tHES ES Hold from Clock HIGH 510 10 ns
tCO Clock HIGH to Output Valid 15 20 25 ns
tPWC Clock Pulse Width 15 20 20 ns
tLZC[7] Output Valid from Clock HIGH 15 20 30 ns
tHZC Output High Z from Clock HIGH 15 20 30 ns
tLZE[8] Output Valid from E LOW 15 20 30 ns
tHZE[8] Output High Z from E HIGH 15 20 30 ns
Notes:
7. Applies only when the synchronous (ES) function is used .
8. Applies only when the asynchronous (E) funct ion i s used.
CY7C277
Document #: 38-04006 Rev. ** Page 4 of 13
Architecture By te (8000)
D7 D0
C7C6C5C4 C3 C2 C1 C0
Architecture Configurat ion Bits
Architecture Bit Architecture Verify D7 - D0Function
ALE D10 = DEFAULT Input Transparent
1 = PGMED Input Latched
ALEP D20 = DEFAULT ALE = Active HIGH
1 = PGMED ALE = Active LOW
E/ESD00 = DEFAULT Asynchronous Output Enable (E)
1 = PGMED Synchronous Output Enable (ES)
Bit Map
Programme r Addres s
(Hex.) RAM Data
0000
.
.
.
7FFF
8000
Data
.
.
.
Data
Control Byte
Note:
9. ALE is shown with positive polarity.
tHZE tLZE
tSES
tSES
tLZC
tHZC
tCO
tHES tHES
HIGHZHIGHZ
tAL tLA
tLL
tSA tHA
A0-A
14
ALE
ES
(SYNCH)
CP
O0-O
7
ES
(ASYNCH)
tPWC
tPWC
Timing Diagram (Input Latched)[9]
tLZE
tHZE
tSES
tHZC
Timing Diagram (Input Transparent)
tSES
tLZC
tCO
tHES tHES
HIGHZ HIGHZ
tSA tHA
A0-A
14
ES
(SYNCH)
CP
O0-O
7
ES
(ASYNCH)
tPWC
tPWC
CY7C277
Document #: 38-04006 Rev. ** Page 5 of 13
Programming Informati on
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
progra mming inf ormatio n, in cludi ng a list ing of sof tware pack-
ages, please see the PROM Programming Information located
at the end of t his sect ion . Program ming algorit hms can be ob-
tained from any Cypress representative.
Table 1. Mode Selection
Pin Function[10]
Read or Output Disable A14–A0E, ESCP ALE O7–O0
Mode Other A14–A0VFY PGM VPP D7–D0
Read A14–A0VIL VIH VIL O7–O0
Output Disable A14–A0VIH X X High Z
Program A14–A0VIHP VILP VPP D7–D0
Program Verify A14–A0VILP VIHP/VILP VPP O7–O0
Pro gram Inhibi t A14–A0VIHP VIHP VPP High Z
Blank Check A14–A0VILP VIHP/VILP VPP O7–O0
Note:
10. X = “don’t care” but not to exceed VCC ±5%.
Figure 1. Programming Pinouts
1
2
3
4
5
6
7
8
9
10
11
12 16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
VCC
A10
A11
A12
A13
A14
VPP
PGM
VFY
D7
D6
D4
D5
D3
12
D0
31
4
5
6
7
8
9
10
32130
1314151617
26
25
24
23
22
21
11
A7
VCC
A6
A5
A4
A3
A2
A1
A0PGM
NC
D7
D6
D4
VFY
D3
D2
D1
181920
27
28
29
32
NC
NC
D5
NC
15
VPP
DIP LCC/PLCC (Opaque Only)
Top View Top View
GND
A12
A13
A14
A8
A9
A10
A11
CY7C277
Document #: 38-04006 Rev. ** Page 6 of 13
Typical DC and AC Characteristics
1.4
1.6
1.0
0.8
4.0 4.5 5.0 5.5 6.0 −55 25 125
1.2
1.1
SUPP LYVOLTAG E (V )
NORMALIZED SUPPLY CURRENT
vs. SUP PLY VOLTA GE NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENTTEMPERATURE (°C)
0.6
1.2
NORMALIZED ACCESS TIME
150
175
125
75
50
25
0.0 1.0 2.0 3.0
OUTPUT SINK CURRENT (mA)
0
100
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.0
0.9
0.8
NORMALIZED I
CC
NORMALIZED I
CC
VCC =5.0V
TA=25°C
60
50
40
30
20
10
0 1.0 2.0 3.0
OUTPUT SOURCE CURRENT (mA)
OUTPUT VOLTAGE (V)
30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELTA t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
4.0 0.0 1000
TA=25°C
VCC =4.5V
TA=25°C
f= f
MAX
0
OUTPUT SOURCE CURRENT
vs. VOLTAGE
4.0
1.6
1.4
1.2
1.0
0.8
−55 125
NORMALIZED SET-UP TIME
0.6 25
AMBIENT TEMPERATURE (°C)
NORMALIZED SET-UP TIME
vs. TEMPERATURE
1.2
4.0 4.5 5.0 5.5 6.0
0.4
SUPPLYVOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SU PPLY VOLTAGE
TA=25°C
1.0
0.8
0.6
C277-12
CY7C277
Document #: 38-04006 Rev. ** Page 7 of 13
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Ordering Information[11]
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
30 CY7C277-30JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C277-30PC P21 28-Lead (300-Mil) Molded DIP
CY7C277-30WC W22 28-Lead (300-Mil) Windowed CerDIP
40 CY7C277-40JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C277-40PC P21 28-Lead (300-Mil) Molded DIP
CY7C277-40WC W22 28-Lead (300-Mil) Windowed CerDIP
CY7C277-40DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C277-40KMB K74 28-Lead Rectangular Cerpack
CY7C277-40LMB L55 32-Pin Rectangular Leadless Chip Carrier
CY7C277-40QMB Q55 32-Pin Windowed Rectangular Leadl ess Chip Carrier
CY7C277-40TMB T74 28-Lead Windowed Cerpack
CY7C277-40WMB W22 28-Lead (300-Mil) Windowed CerDIP
50 CY7C277-50JC J65 32-Lead Plastic Leaded Chip Carrier Commercial
CY7C277-50PC P21 28-Lead (300-Mil) Molded DIP
CY7C277-50WC W22 28-Lead (300-Mil) Windowed CerDIP
CY7C277-50DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C277-50KMB K74 28-Lead Rectangular Cerpack
CY7C277-50LMB L55 32-Pin Rectangular Leadless Chip Carrier
CY7C277-50QMB Q55 32-Pin Windowed Rectangular Leadl ess Chip Carrier
CY7C277-50TMB T74 28-Lead Windowed Cerpack
CY7C277-50WMB W22 28-Lead (300-Mil) Windowed CerDIP
Note:
11. Most of the above products are available in industrial temperature range. Contact a Cypress representative for specifications and product
availability.
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameter Subgroups
tSA 7, 8, 9, 10, 11
tHA 7, 8, 9, 10, 11
tCO 7, 8, 9, 10, 11
CY7C277
Document #: 38-04006 Rev. ** Page 8 of 13
Package Diagrams
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config. A
51-80032
32-Lead Plastic Leaded Chip Carrier J65
51-85002-B
CY7C277
Document #: 38-04006 Rev. ** Page 9 of 13
Package Diagrams (continued)
28-Lead Rectangular Cerpack K74
MIL-STD-1835 F-11 Config. A
51-80061
CY7C277
Document #: 38-04006 Rev. ** Page 10 of 13
Package Diagrams (continued)
32-Pin Rectangular Leadless Chip Carrier L55
MIL-STD-1835 C-12
51-80068
51-85014-B
28-Lead (300-Mil) Molded DIP P21
CY7C277
Document #: 38-04006 Rev. ** Page 11 of 13
Package Diagrams (continued)
MIL-STD-1835 C-12
51-80103-*A
32-Pin Windowed Rectangular Leadless Chip Carrier Q 55
CY7C277
Document #: 38-04006 Rev. ** Page 12 of 13
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
28-Lead Windowed Cerpack T74
28-Lead
(300-Mil)
Windowed CerDIP W22
MIL-STD-1835 D-15 Config. A
51-80087
CY7C277
Document #: 38-04006 Rev. ** Page 13 of 13
Document Title: CY7C277 32K x 8 Programmable Registered PROM
Document Number: 38-04006
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 113862 3/8/02 DSG Change from Spec number: 38-00085 to 38-04006
