74LCXH16244MTDX_NL - Fairchild Semiconductor

September 2000

Revised June 2005

74LCXH16244 Low Voltage 16-Bit Buffer /Line Driver with Bushold

74LCXH16244

Low Voltage 16-Bit Buffer/Line Driver with Bushold

General Descript ion

The LCXH16244 contains sixteen non-inverting buffers

with 3-STATE outputs designed to be employed as a mem-

ory and addre ss driver, clock driver, or bu s o riented trans-

mitter/receiver . The device is nibble controlled. Each nibble

has separate 3- S TAT E con tro l inpu ts which can be sh ort ed

together for full 16-bit operation.

The LCXH16244 data inputs include active bushold cir-

cuitry, eliminating the need for external pull-up resistors to

hold unused or floating data inputs at a valid logic level.

The LCXH16244 is designed for low voltage (2.5V or 3.3V)

VCC applications with capability of interfacing to a 5V signal

environment.

The LCXH16244 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

Features

■5V tolerant control inputs and outputs

■2.3V–3.6V VCC specifications provided

■4.5 ns tPD max (VCC

3.0V), 20

A ICC max

■Bushold on inputs eliminates the need for external

pull-up/pull-down resistors

■Power down high impedance inputs and outputs

■

24 mA output drive (VCC

3.0V)

■Latch-up per for man c e exce eds 500 mA

■ESD performa nce :

Human body model

2000V

Machine model

200V

■Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Ordering Code:

Note 1: Ordering code “G” indicates Trays.

Note 2: Devices al so av ailable in Tape and Reel. Specify by appending t he suffix lette r “X” to th e ordering code.

Logic Symbol

Order Number Package Number Package Description

74LCXH16244G

(Note 1)(Note 2) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

74LCXH16244MEA

(Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LCXH16244MTD

(Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

■Implements proprietary noise/EMI reduction circuitry

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74LCXH16244

Connection Diagrams

Pin Assignment for SSOP and TSSOP

Pin Assignment for FBGA

(Top Thru View)

Pin Descriptions

FBGA Pin Assignments

Truth Tables

HIGH Volt age Level X

Immaterial

LOW Voltage Le ve l Z

High Impedance

Pin Names Description

OEnOutput Enable Input (Active LOW)

I0–I15 Inputs

O0–O15 Outputs

NC No Connect

123456

AO0NC OE1OE2NC I0

BO2O1NC NC I1I2

CO4O3VCC VCC I3I4

DO6O5GND GND I5I6

EO8O7GND GND I7I8

FO10 O9GND GND I9I10

GO12 O11 VCC VCC I11 I12

HO14 O13 NC NC I13 I14

JO15 NC OE4OE3NC I15

Inputs Outputs

OE1I0–I3O0–O3

LL L

LH H

HX Z

Inputs Outputs

OE2I4–I7O4–O7

LL L

LH H

HX Z

Inputs Outputs

OE3I8–I11 O8–O11

LL L

LH H

HX Z

Inputs Outputs

OE4I12–I15 O12–O15

LL L

LH H

HX Z

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74LCXH16244

Functional Description

The LCXH16244 contains sixteen non-inverting buffers

with 3-STATE standard outputs. The device is nibble

(4 bits) controlled with each nibble functioning identically,

but independent of the other. The control pins can be

shorted together to obtain full 16-bit operation. The

3-STATE outputs are controlled by an Output Enable (OEn)

input for each nibble. When OEn is LOW , the outputs are in

2-state mode. When OEn is HIGH, the outputs are in the

high impedance mode, but this does not interfere with

enteri ng new data into t he inpu ts.

Logic Diagram

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74LCXH16244

Absolute Maximum Ratings(Note 3)

Recommended Operating Conditions (Note 5)

Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be opera t ed

at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-

mend ed Operating Co nditions ” tab le w ill define th e c onditions fo r ac t ual devi c e operation.

Note 4: IO Absolute Maximum Rating must be observed.

Note 5: Fl oating or unus ed contro l inputs mus t be held H I GH or LOW.

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

VCC Supply Voltage



0.5 to



7.0 V

VIDC Input Voltage OE



0.5 to



7.0 V

I0 - I15



0.5 to VCC



0.5

VODC Output Voltage



0.5 to



7.0 Output in 3-STAT E V



0.5 to VCC



0.5 Output in HIGH or LOW State (Note 4)

IIK DC In put Diode Current



50 VI



GND mA

IOK DC Output Diode Current



50 VO



GND mA



50 VO

VCC

IODC Output Source/Sink Current

50 mA

ICC DC Supply Current per Supply Pin

100 mA

IGND DC Ground Current per Ground Pin

100 mA

TSTG Storage Temperature



65 to



150

Symbol Parameter Min Max Units

VCC Supply Voltage Operating 2.0 3.6 V

Data Retention 1.5 3.6

VIInput Voltage 0V

CC V

VOOutput Voltage HIGH or LOW State 0 VCC V

3-STATE 0 5.5

IOH/IOL Output Current VCC

3.0V



3.6V

24 mAVCC

2.7V



3.0V

VCC

2.3V



2.7V

TAFree-Air Operating Temp erature



40 85

V Input Edge Rate, VIN

0.8V–2.0V, VCC

3.0V 0 10 ns/V

Symbol Parameter Conditions VCC TA



C to



CUnits

(V) Min Max

VIH HIGH Level Input Voltage 2.3



2.7 1.7 V

2.7



3.6 2.0

VIL LOW Level Input Voltage 2.3



2.7 0.7 V

2.7



3.6 0.8

VOH HIGH Level Output Voltage IOH



100

A2.3



3.6 VCC



0.2

IOH



8 mA 2.3 1.8

IOH



12 mA 2.7 2.2

IOH



18 mA 3.0 2.4

IOH



24 mA 3.0 2.2

VOL LOW Level Output Voltage IOL

100

A2.3



3.6 0.2

IOL

8 mA 2.3 0.6

IOL

12 mA 2.7 0.4

IOL

16 mA 3.0 0.4

IOL

24 mA 3.0 0.5 5

IIInput Leakage Current Data VI

VCC or GND 2.3



3.6

5.0

Control 0

5.5 2.3



3.6

5.0

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74LCXH16244

DC Electrical Characteristics (Continued)

Note 6: An exte rnal driver must source at least the specified curren t to switch from LOW-to-HIGH.

Note 7: An external driver mus t s ink at least the s pec if ied current to switc h f rom HIG H -t o-LOW.

AC Electrical Characteristics

Note 8: S k ew is def i ned as t he absolute valu e of the differen c e betwee n t he actu al propagation delay fo r any two separ at e outputs of the same d evice. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (t OSLH). Parameter gu arantee d by design.

Dynamic Switching Characteristics

Capacitance

Symbol Parameter Conditions VCC TA



C to



CUnits

(V) Min Max

II(HOLD) Bushold Input Minimum VIN

0.7V 2.3 45

Drive Hold Current VIN

1.7V



VIN

0.8V 3.0 75

VIN

2.0V



II(OD) Bushold Input Over-Drive (Note 6) 2.7 300

Current to Change State (Note 7)



300

(Note 6) 3.6 450

(Note 7)



450

IOZ 3-STATE Output Leakage 0

5.5V 2.3



3.6

5.0

VIH or VIL

IOFF Power-Off Leakage Current VO

5.5V 0 10

ICC Quiescent Supply Current VI

VCC or GND 2.3



3.6 20

ICC Increase in ICC per Input VIH

VCC



0.6V 2.3



3.6 500

Symbol Parameter



C to



C, RL

500

Units

VCC

3.3V

0.3V VCC

2.7V VCC

2.5V

0.2V

50 pF CL

30 pF

Min Max Min Max Min Max

tPHL Propagation Delay 1.0 4.5 1.0 5.2 1.0 5.4 ns

tPLH Data to Output 1.0 4.5 1.0 5.2 1.0 5.4

tPZL Output Enable Time 1.0 5.5 1.0 6.3 1.0 7.2 ns

tPZH 1.0 5.5 1.0 6.3 1.0 7.2

tPLZ Output Disable Time 1.0 5.4 1.0 5.7 1.0 6.5 ns

tPHZ 1.0 5.4 1.0 5.7 1.0 6.5

tOSHL Output to Output Skew (Note 8) 1.0 ns

tOSLH 1.0

Symbol Parameter Conditions VCC TA

CUnits

(V) Typical

VOLP Quiet Output Dynamic Peak VOL CL

50 pF, VIH

3.3V, VIL

0V 3.3 0.8 V

30 pF, VIH

2.5V, VIL

0V 2.5 0.6

VOLV Quiet Output Dynamic Valley VOL CL

50 pF, VIH

3.3V, VIL

0V 3.3



0.8 V

30 pF, VIH

2.5V, VIL

0V 2.5



0.6

Symbol Parameter Conditions Typical Units

CIN Input Capacit ance VCC

Open, VI

0V or VCC 7pF

COUT Output Capacitance VCC

3.3V, VI

0V or VCC 8pF

CPD Power Dissipation Capacitance VCC

3.3V, VI

0V or VCC, f

10 M Hz 20 pF

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74LCXH16244

AC LOADING and WAVEFORMS Generic for LCX Family

FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Delay. Pulse Width and trec Waveforms

3-STA TE Output Low Enable and

Disable Times for Logic

3-STATE Output High Enable and

Disable Times for Logic

Setup Time, Hold Time and Recovery Time for Logic

trise and tfall

FIGURE 2. Waveforms

(Input Charac teristics; f =1MHz, tr = t f = 3ns)

VICL

6V for VCC

3.3V, 2.7V 50 pF

VCC * 2 for VCC

2.5V 30 pF

Symbol VCC

3.3V

0.3V 2.7V 2.5V

0.2V

Vmi 1.5V 1.5V VCC/2

Vmo 1.5V 1.5V VCC/2

VxVOL



0.3V VOL



0.3V VOL



0.15V

VyVOH



0.3V VOH



0.3V VOH



0.15V

7 www.fairchildsemi.com

74LCXH16244

Schematic Diagram Generic for LCXH Family

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74LCXH16244

Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Packag e Num b er BGA5 4A

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74LCXH16244

Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

Package Number MS48A

www.fairchildsemi.com 10

74LCXH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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user.

2. A critical compon ent i n any compon ent of a lif e supp ort

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device or system, or to affect its safety or effectiveness.