74AC174FCQR - National Semiconductor

TL/F/9935

54AC/74AC174 #54ACT/74ACT174 Hex D Flip-Flop with Master Reset

March 1993

54AC/74AC174 #54ACT/74ACT174

Hex D Flip-Flop with Master Reset

General Description

The ’AC/’ACT174 is a high-speed hex D flip-flop. The de-

vice is used primarily as a 6-bit edge-triggered storage regis-

ter. The information on the D inputs is transferred to storage

during the LOW-to-HIGH clock transition. The device has a

Master Reset to simultaneously clear all flip-flops.

Features

YICC reduced by 50%

YOutputs source/sink 24 mA

Y’ACT174 has TTL-compatible inputs

YStandard Military Drawing (SMD)

Ð ’AC174: 5962-87626

Ð ’ACT174: 5962-87757

Logic Symbols

TL/F/9935–1

IEEE/IEC

TL/F/9935–2

Connection Diagrams

Pin Assignment

for DIP, Flatpak and SOIC

TL/F/9935–3

Pin Assignment

for LCC

TL/F/9935–4

Pin Names Description

D0–D5Data Inputs

CP Clock Pulse Input

MR Master Reset Input

Q0–Q5Outputs

FACTTM is a trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

Functional Description

The ’AC/’ACT174 consists of six edge-triggered D flip-flops

with individual D inputs and Q outputs. The Clock (CP) and

Master Reset (MR) are common to all flip-flops. Each D

input’s state is transferred to the corresponding flip-flop’s

output following the LOW-to-HIGH Clock (CP) transition. A

LOW input to the Master Reset (MR) will force all outputs

LOW independent of Clock or Data inputs. The ’AC/

’ACT174 is useful for applications where the true output

only is required and the Clock and Master Reset are com-

mon to all storage elements.

Truth Table

Inputs Output

MR CP D Q

LXX L

HLHH

HLLL

HLX Q

HIGH Voltage Level

LeLOW Voltage Level

XeImmaterial

LeLOW-to-HIGH Transition

Logic Diagram

TL/F/9935–5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage (VCC)b0.5V to a7.0V

DC Input Diode Current (IIK)

VIeb

0.5V b20 mA

VIeVCC a0.5V a20 mA

DC Input Voltage (VI)b0.5V to VCC a0.5V

DC Output Diode Current (IOK)

VOeb

0.5V b20 mA

VOeVCC a0.5V a20 mA

DC Output Voltage (VO)b0.5V to VCC a0.5V

DC Output Source

or Sink Current (IO)g50 mA

DC VCC or Ground Current

per Output Pin (ICC or IGND)g50 mA

Storage Temperature (TSTG)b65§Ctoa

150§C

Junction Temperature (TJ)

CDIP 175§C

PDIP 140§C

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, without

exception, to ensure that the system design is reliable over its power supply,

temperature, and output/input loading variables. National does not recom-

mend operation of FACTTM circuits outside databook specifications.

Recommended Operating

Conditions

Supply Voltage (VCC)

’AC 2.0V to 6.0V

’ACT 4.5V to 5.5V

Input Voltage (VI) 0VtoV

Output Voltage (VO) 0VtoV

Operating Temperature (TA)

74AC/ACT b40§Ctoa

85§C

54AC/ACT b55§Ctoa

125§C

Minimum Input Edge Rate (DV/Dt)

’AC Devices

VIN from 30% to 70% of VCC

VCC @3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (DV/Dt)

’ACT Devices

VIN from 0.8V to 2.0V

VCC @4.5V, 5.5V 125 mV/ns

DC Characteristics for ’AC Family Devices

74AC 54AC 74AC

Symbol Parameter VCC TAea

25§CTAeTAeUnits Conditions

(V) b55§Ctoa

125§Cb40§Ctoa

85§C

Typ Guaranteed Limits

VIH Minimum High Level 3.0 1.5 2.1 2.1 2.1 VOUT e0.1V

Input Voltage 4.5 2.25 3.15 3.15 3.15 V or VCC b0.1V

5.5 2.75 3.85 3.85 3.85

VIL Maximum Low Level 3.0 1.5 0.9 0.9 0.9 VOUT e0.1V

Input Voltage 4.5 2.25 1.35 1.35 1.35 V or VCC b0.1V

5.5 2.75 1.65 1.65 1.65

VOH Minimum High Level 3.0 2.99 2.9 2.9 2.9 IOUT eb

50 mA

Output Voltage 4.5 4.49 4.4 4.4 4.4 V

5.5 5.49 5.4 5.4 5.4

*VIN eVIL or VIH

3.0 2.56 2.4 2.46 b12 mA

4.5 3.86 3.7 3.76 V IOH b24 mA

5.5 4.86 4.7 4.76 b24 mA

VOL Maximum Low Level 3.0 0.002 0.1 0.1 0.1 IOUT e50 mA

Output Voltage 4.5 0.001 0.1 0.1 0.1 V

5.5 0.001 0.1 0.1 0.1

*VIN eVIL or VIH

3.0 0.36 0.50 0.44 12 mA

4.5 0.36 0.50 0.44 V IOL 24 mA

5.5 0.36 0.50 0.44 24 mA

IIN Maximum Input 5.5 g0.1 g1.0 g1.0 mAVIeVCC, GND

Leakage Current

*All outputs loaded; thresholds on input associated with output under test.

DC Characteristics for ’AC Family Devices (Continued)

74AC 54AC 74AC

Symbol Parameter VCC TAea

25§CTAeTAeUnits Conditions

(V) b55§Ctoa

125§Cb40§Ctoa

85§C

Typ Guaranteed Limits

IOLD ²Minimum Dynamic 5.5 50 75 mA VOLD e1.65V Max

IOHD Output Current 5.5 b50 b75 mA VOHD e3.85V Min

ICC Maximum Quiescent 5.5 4.0 80.0 40.0 mAVIN eVCC

Supply Current or GND

*All outputs loaded; thresholds on input associated with output under test.

²Maximum test duration 2.0 ms, one output loaded at a time.

Note: IIN and ICC @3.0V are guaranteed to be less than or equal to the respective limit @5.5V VCC.

ICC for 54AC @25§C is identical to 74AC @25§C.

DC Characteristics for ’ACT Family Devices

74ACT 54ACT 74ACT

Symbol Parameter VCC TAea

25§CTAeTAeUnits Conditions

(V) b55§Ctoa

125§Cb40§Ctoa

85§C

Typ Guaranteed Limits

VIH Minimum High Level 4.5 1.5 2.0 2.0 2.0 VVOUT e0.1V

Input Voltage 5.5 1.5 2.0 2.0 2.0 or VCC b0.1V

VIL Maximum Low Level 4.5 1.5 0.8 0.8 0.8 VVOUT e0.1V

Input Voltage 5.5 1.5 0.8 0.8 0.8 or VCC b0.1V

VOH Minimum High Level 4.5 4.49 4.4 4.4 4.4 VIOUT eb

50 mA

Output Voltage 5.5 5.49 5.4 5.4 5.4

*VIN eVIL or VIH

4.5 3.86 3.70 3.76 VI

b24 mA

5.5 4.86 4.70 4.76 b24 mA

VOL Maximum Low Level 4.5 0.001 0.1 0.1 0.1 VIOUT e50 mA

Output Voltage 5.5 0.001 0.1 0.1 0.1

*VIN eVIL or VIH

4.5 0.36 0.50 0.44 VI

24 mA

5.5 0.36 0.50 0.44 24 mA

IIN Maximum Input 5.5 g0.1 g1.0 g1.0 mAVIeVCC, GND

Leakage Current

ICCT Maximum 5.5 0.6 1.6 1.5 mA VIeVCC b2.1V

ICC/Input

IOLD ²Minimum Dynamic 5.5 50 75 mA VOLD e1.65V Max

IOHD Output Current 5.5 b50 b75 mA VOHD e3.85V Min

ICC Maximum Quiescent 5.5 4.0 80.0 40.0 mAVIN eVCC

Supply Current or GND

*All outputs loaded; thresholds on input associated with output under test.

²Maximum test duration 2.0 ms, one output loaded at a time.

Note: ICC for 54ACT @25§C is identical to 74ACT @25§C.

AC Electrical Characteristics

74AC 54AC 74AC

VCC*TAea

25§CTAeb

55§CT

40§C

Symbol Parameter (V) CLe50 pF to a125§Cto

85§C Units

CLe50 pF CLe50 pF

Min Typ Max Min Max Min Max

fmax Maximum Clock 3.3 90 100 65 70 MHz

Frequency 5.0 100 125 90 100

tPLH Propagation Delay 3.3 2.0 9.0 11.5 1.0 14.0 1.5 12.5 ns

CP to Qn5.0 1.5 6.0 8.5 1.5 10.5 1.0 9.5

tPHL Propagation Delay 3.3 2.0 8.5 11.0 1.0 13.0 1.5 12.0 ns

CP to Qn5.0 1.5 6.0 8.0 1.5 10.0 1.0 9.0

tPHL Propagation Delay 3.3 2.5 9.0 11.5 1.0 13.5 2.0 12.5 ns

MR to Qn5.0 1.5 7.0 9.0 1.5 11.0 1.5 10.5

*Voltage Range 3.3 is 3.3V g0.3V

Voltage Range 5.0 is 5.0V g0.5V

AC Operating Requirements

74AC 54AC 74AC

VCC*TAea

25§CTAeb

55§CT

40§C

Symbol Parameter (V) CLe50 pF to a125§Cto

85§C Units

CLe50 pF CLe50 pF

Typ Guaranteed Minimum

tsSetup Time, HIGH or LOW 3.3 2.5 6.5 7.5 7.0 ns

Dnto CP 5.0 2.0 5.0 5.5 5.5

thHold Time, HIGH or LOW 3.3 1.0 3.0 3.0 3.0 ns

Dnto CP 5.0 0.5 3.0 3.0 3.0

twMR Pulse Width, LOW 3.3 1.0 5.5 7.0 7.0 ns

5.0 1.0 5.0 5.0 5.0

twCP Pulse Width 3.3 1.0 5.5 7.0 7.0 ns

5.0 1.0 5.0 5.0 5.0

trec Recovery Time 3.3 0 2.5 3.0 2.5 ns

MR to CP 5.0 0 2.0 2.0 2.0

*Voltage Range 3.3 is 3.3V g0.3V

Voltage Range 5.0 is 5.0V g0.5V

AC Electrical Characteristics

74ACT 54ACT 74ACT

VCC*TAea

25§CTAeb

55§CT

40§C

Symbol Parameter (V) CLe50 pF to a125§Cto

85§C Units

CLe50 pF CLe50 pF

Min Typ Max Min Max Min Max

fmax Maximum Clock 5.0 165 200 95 140 MHz

Frequency

tPLH Propagation Delay 5.0 1.5 7.0 10.5 1.5 12.5 1.5 11.5 ns

CP to Qn

tPHL Propagation Delay 5.0 1.5 7.0 10.5 1.5 13.0 1.5 11.5 ns

CP to Qn

tPHL Propagation Delay 5.0 1.5 6.5 9.5 1.5 12.0 1.5 11.0 ns

MR to Qn

*Voltage Range 5.0 is 5.0V g0.5V

AC Operating Requirements

74ACT 54ACT 74ACT

VCC*TAea

25§CTAeb

55§CT

40§C

Symbol Parameter (V) CLe50 pF to a125§Cto

85§C Units

CLe50 pF CLe50 pF

Typ Guaranteed Minimum

tsSetup Time, HIGH or LOW 5.0 0.5 1.5 3.0 1.5 ns

Dnto CP

thHold Time, HIGH or LOW 5.0 1.0 2.0 2.0 2.0 ns

Dnto CP

twMR Pulse Width, LOW 5.0 1.5 3.0 5.0 3.5 ns

twCP Pulse Width, HIGH OR LOW 5.0 1.5 3.0 5.0 3.5 ns

trec Recovery Time 5.0 b1.0 0.5 1.0 0.5 ns

MR to CP

*Voltage Range 5.0 is 5.0V g0.5V

Capacitance

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC eOPEN

CPD Power Dissipation 85.0 pF VCC e5.0V

Capacitance

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

74ACT 174 P C QR

Temperature Range Family Special Variations

74AC eCommercial XeDevices shipped in 13×reels

54AC eMilitary QR eCommercial grade device with

74ACT eCommercial TTL-Compatible burn-in

54ACT eMilitary TTL-Compatible QB eMilitary grade device with

environmental and burn-in

Device Type processing shipped in tubes

Package Code Temperature Range

PePlastic DIP CeCommercial (b40§Ctoa

85§C)

DeCeramic DIP MeMilitary (b55§Ctoa

125§C)

FeFlatpak

LeLeadless Ceramic Chip Carrier (LCC)

SeSmall Outline (SOIC)

Physical Dimensions inches (millimeters)

20-Terminal Ceramic Leadless Chip Carrier (L)

NS Package Number E20A

16-Lead Ceramic Dual-In-Line Package (D)

NS Package Number J16A

Physical Dimensions inches (millimeters) (Continued)

16-Lead Small Outline Integrated Circuit (S)

NS Package Number M16A

16-Lead Plastic Dual-In-Line Package (P)

NS Package Number N16E

54AC/74AC174 #54ACT/74ACT174 Hex D Flip-Flop with Master Reset

Physical Dimensions inches (millimeters) (Continued)

16-Lead Ceramic Flatpak (F)

NS Package Number W16A

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failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

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