54AC/74AC174 # 54ACT/74ACT174 Hex D Flip-Flop with Master Reset General Description Features The 'AC/'ACT174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops. Y Y Y Y ICC reduced by 50% Outputs source/sink 24 mA 'ACT174 has TTL-compatible inputs Standard Military Drawing (SMD) 'AC174: 5962-87626 'ACT174: 5962-87757 Logic Symbols Connection Diagrams Pin Assignment for DIP, Flatpak and SOIC IEEE/IEC TL/F/9935-1 TL/F/9935 - 3 Pin Names D0 - D5 CP MR Q0 - Q5 Description Data Inputs Clock Pulse Input Master Reset Input Outputs TL/F/9935 - 2 Pin Assignment for LCC TL/F/9935 - 4 FACTTM is a trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9935 RRD-B30M75/Printed in U. S. A. 54AC/74AC174 # 54ACT/74ACT174 Hex D Flip-Flop with Master Reset March 1993 Functional Description Truth Table The 'AC/'ACT174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input's state is transferred to the corresponding flip-flop's output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The 'AC/ 'ACT174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Inputs Output MR CP D Q L H H H X L L L X H L X L H L Q H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Transition Logic Diagram TL/F/9935 - 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI e b0.5V VI e VCC a 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO e b0.5V VO e VCC a 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP PDIP Supply Voltage (VCC) 'AC 'ACT Input Voltage (VI) b 0.5V to a 7.0V b 20 mA a 20 mA 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC Output Voltage (VO) Operating Temperature (TA) 74AC/ACT 54AC/ACT b 0.5V to VCC a 0.5V b 20 mA a 20 mA b 40 C to a 85 C b 55 C to a 125 C Minimum Input Edge Rate (DV/Dt) 'AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (DV/Dt) 'ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V b 0.5V to VCC a 0.5V g 50 mA g 50 mA b 65 C to a 150 C 125 mV/ns 125 mV/ns 175 C 140 C Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT TM circuits outside databook specifications. DC Characteristics for 'AC Family Devices Symbol Parameter VCC (V) 74AC 54AC 74AC TA e a 25 C TA e b 55 C to a 125 C TA e b 40 C to a 85 C Typ VIH VIL VOH IIN Conditions Guaranteed Limits Minimum High Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT e 0.1V or VCC b 0.1V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT e 0.1V or VCC b 0.1V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 2.9 4.4 5.4 V 2.56 3.86 4.86 2.4 3.7 4.7 2.46 3.76 4.76 V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V 3.0 4.5 5.5 0.36 0.36 0.36 0.50 0.50 0.50 0.44 0.44 0.44 V 5.5 g 0.1 g 1.0 g 1.0 mA 3.0 4.5 5.5 VOL Units Maximum Low Level Output Voltage Maximum Input Leakage Current 3.0 4.5 5.5 0.002 0.001 0.001 *All outputs loaded; thresholds on input associated with output under test. 3 IOUT e b50 mA *VIN e VIL or VIH b 12 mA b 24 mA IOH b 24 mA IOUT e 50 mA *VIN e VIL or VIH 12 mA IOL 24 mA 24 mA VI e VCC, GND DC Characteristics for 'AC Family Devices (Continued) Symbol Parameter VCC (V) 74AC 54AC 74AC TA e a 25 C TA e b 55 C to a 125 C TA e b 40 C to a 85 C Typ IOLD IOHD ICC Minimum Dynamic Output Current Maximum Quiescent Supply Current Units Conditions Guaranteed Limits 5.5 50 75 mA VOLD e 1.65V Max 5.5 b 50 b 75 mA VOHD e 3.85V Min 80.0 40.0 mA VIN e VCC or GND 5.5 4.0 *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit ICC for 54AC @ 25 C is identical to 74AC @ 25 C. @ 5.5V VCC. DC Characteristics for 'ACT Family Devices 74ACT 54ACT 74ACT TA e a 25 C TA e b 55 C to a 125 C TA e b 40 C to a 85 C Parameter VCC (V) VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 V VOUT e 0.1V or VCC b 0.1V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOUT e 0.1V or VCC b 0.1V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 4.4 5.4 V 3.86 4.86 3.70 4.70 3.76 4.76 V 0.1 0.1 0.1 0.1 0.1 0.1 V 4.5 5.5 0.36 0.36 0.50 0.50 0.44 0.44 V g 0.1 g 1.0 g 1.0 mA VI e VCC, GND 1.6 1.5 mA VI e VCC b 2.1V Symbol Typ 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 IIN Maximum Input Leakage Current 5.5 ICCT Maximum ICC/Input 5.5 IOLD Minimum Dynamic Output Current IOHD ICC Maximum Quiescent Supply Current 0.001 0.001 0.6 IOUT e b50 mA *VIN e VIL or VIH b 24 mA IOH b 24 mA IOUT e 50 mA *VIN e VIL or VIH 24 mA IOL 24 mA 5.5 50 75 mA VOLD e 1.65V Max 5.5 b 50 b 75 mA VOHD e 3.85V Min 80.0 40.0 mA VIN e VCC or GND 5.5 4.0 Maximum test duration 2.0 ms, one output loaded at a time. @ Conditions Guaranteed Limits *All outputs loaded; thresholds on input associated with output under test. Note: ICC for 54ACT Units 25 C is identical to 74ACT @ 25 C. 4 AC Electrical Characteristics Symbol Parameter VCC* (V) 74AC 54AC 74AC TA e a 25 C CL e 50 pF TA e b55 C to a 125 C CL e 50 pF TA e b40 C to a 85 C CL e 50 pF Max Min Max Min Typ fmax Maximum Clock Frequency 3.3 5.0 90 100 100 125 tPLH Propagation Delay CP to Qn 3.3 5.0 2.0 1.5 9.0 6.0 11.5 8.5 1.0 1.5 14.0 10.5 1.5 1.0 12.5 9.5 ns tPHL Propagation Delay CP to Qn 3.3 5.0 2.0 1.5 8.5 6.0 11.0 8.0 1.0 1.5 13.0 10.0 1.5 1.0 12.0 9.0 ns tPHL Propagation Delay MR to Qn 3.3 5.0 2.5 1.5 9.0 7.0 11.5 9.0 1.0 1.5 13.5 11.0 2.0 1.5 12.5 10.5 ns 65 90 Min Units Max 70 100 MHz *Voltage Range 3.3 is 3.3V g 0.3V Voltage Range 5.0 is 5.0V g 0.5V AC Operating Requirements 74AC 54AC 74AC TA e a 25 C CL e 50 pF TA e b55 C to a 125 C CL e 50 pF TA e b40 C to a 85 C CL e 50 pF Parameter VCC* (V) ts Setup Time, HIGH or LOW Dn to CP 3.3 5.0 2.5 2.0 6.5 5.0 7.5 5.5 7.0 5.5 ns th Hold Time, HIGH or LOW Dn to CP 3.3 5.0 1.0 0.5 3.0 3.0 3.0 3.0 3.0 3.0 ns tw MR Pulse Width, LOW 3.3 5.0 1.0 1.0 5.5 5.0 7.0 5.0 7.0 5.0 ns tw CP Pulse Width 3.3 5.0 1.0 1.0 5.5 5.0 7.0 5.0 7.0 5.0 ns trec Recovery Time MR to CP 3.3 5.0 0 0 2.5 2.0 3.0 2.0 2.5 2.0 ns Symbol Typ Units Guaranteed Minimum *Voltage Range 3.3 is 3.3V g 0.3V Voltage Range 5.0 is 5.0V g 0.5V AC Electrical Characteristics Symbol Parameter VCC* (V) 74ACT 54ACT 74ACT TA e a 25 C CL e 50 pF TA e b55 C to a 125 C CL e 50 pF TA e b40 C to a 85 C CL e 50 pF Min Typ 5.0 165 200 Propagation Delay CP to Qn 5.0 1.5 7.0 10.5 1.5 12.5 1.5 11.5 ns tPHL Propagation Delay CP to Qn 5.0 1.5 7.0 10.5 1.5 13.0 1.5 11.5 ns tPHL Propagation Delay MR to Qn 5.0 1.5 6.5 9.5 1.5 12.0 1.5 11.0 ns fmax Maximum Clock Frequency tPLH Max Min Max 95 *Voltage Range 5.0 is 5.0V g 0.5V 5 Min Units Max 140 MHz AC Operating Requirements Symbol Parameter VCC* (V) 74ACT 54ACT 74ACT TA e a 25 C CL e 50 pF TA e b55 C to a 125 C CL e 50 pF TA e b40 C to a 85 C CL e 50 pF Typ Units Guaranteed Minimum ts Setup Time, HIGH or LOW Dn to CP 5.0 0.5 1.5 3.0 1.5 ns th Hold Time, HIGH or LOW Dn to CP 5.0 1.0 2.0 2.0 2.0 ns tw MR Pulse Width, LOW 5.0 1.5 3.0 5.0 3.5 ns tw CP Pulse Width, HIGH OR LOW 5.0 1.5 3.0 5.0 3.5 ns trec Recovery Time MR to CP 5.0 b 1.0 0.5 1.0 0.5 ns *Voltage Range 5.0 is 5.0V g 0.5V Capacitance Symbol Parameter Typ Units Conditions CIN Input Capacitance 4.5 pF VCC e OPEN CPD Power Dissipation Capacitance 85.0 pF VCC e 5.0V Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74ACT 174 P Temperature Range Family 74AC e Commercial 54AC e Military 74ACT e Commercial TTL-Compatible 54ACT e Military TTL-Compatible C QR Special Variations X e Devices shipped in 13x reels QR e Commercial grade device with burn-in QB e Military grade device with environmental and burn-in processing shipped in tubes Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Ceramic Chip Carrier (LCC) S e Small Outline (SOIC) Temperature Range C e Commercial (b40 C to a 85 C) M e Military (b55 C to a 125 C) 6 7 Physical Dimensions inches (millimeters) 20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 8 Physical Dimensions inches (millimeters) (Continued) 16-Lead Small Outline Integrated Circuit (S) NS Package Number M16A 16-Lead Plastic Dual-In-Line Package (P) NS Package Number N16E 9 54AC/74AC174 # 54ACT/74ACT174 Hex D Flip-Flop with Master Reset Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 Tel: 1(800) 272-9959 TWX: (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str. 10 D-82256 F4urstenfeldbruck Germany Tel: (81-41) 35-0 Telex: 527649 Fax: (81-41) 35-1 National Semiconductor Japan Ltd. Sumitomo Chemical Engineering Center Bldg. 7F 1-7-1, Nakase, Mihama-Ku Chiba-City, Ciba Prefecture 261 Tel: (043) 299-2300 Fax: (043) 299-2500 2. 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