DATA SH EET
Product specification
Supersedes data of 2004 Oct 07 2004 Dec 22
INTEGRATED CIRCUITS
PCF8576D
Universal LCD driver for low
multiplex rates
2004 Dec 22 2
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
CONTENTS
1 FEATURES
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 BLOCK DIAGRAM
5 PINNING
6 FUNCTIONAL DESCRIPTION
6.1 Power-on reset
6.2 LCD bias generator
6.3 LCD voltage selector
6.3.1 LCD bias formulae
6.4 LCD drive mode waveforms
6.4.1 Static drive mode
6.4.2 1 : 2 multiplex drive mode
6.4.3 1 : 3 multiplex drive mode
6.4.4 1 : 4 multiplex drive mode
6.5 Oscillator
6.5.1 Internal clock
6.5.2 External clock
6.6 Timing
6.7 Display register
6.8 Segment outputs
6.9 Backplane outputs
6.10 Display RAM
6.11 Data pointer
6.12 Subaddress counter
6.13 Output bank selector
6.14 Input bank selector
6.15 Blinker
7 CHARACTERISTICS OF THE I2C-BUS
7.1 Bit transfer
7.2 Start and stop conditions
7.3 System configuration
7.4 Acknowledge
7.5 PCF8576D I2C-bus controller
7.6 Input filters
7.7 I2C-bus protocol
7.8 Command decoder
7.9 Display controller
7.10 Cascaded operation
8 LIMITING VALUES
9 HANDLING
10 DC CHARACTERISTICS
11 AC CHARACTERISTICS
12 BONDING PAD INFORMATION
13 DEVICE PROTECTION
14 TRAY INFORMATION
15 PACKAGE OUTLINE
16 SOLDERING
16.1 Introduction to soldering surface mount
packages
16.2 Reflow soldering
16.3 Wave soldering
16.4 Manual soldering
16.5 Suitability of surface mount IC packages for
wave and reflow soldering methods
17 DATA SHEET STATUS
18 DEFINITIONS
19 DISCLAIMERS
20 PURCHASE OF PHILIPS I2C COMPONENTS
2004 Dec 22 3
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
1 FEATURES
•Single-chip LCD controller/driver
•Selectable backplane drive configuration: static or 2/3/4
backplane multiplexing
•Selectable display bias configuration: static, 1/2and 1/3
•Internal LCD bias generation with voltage-follower
buffers
•40 segment drives: up to twenty 8-segment numeric
characters; up to ten 15-segment alphanumeric
characters; or any graphics of up to 160 elements
•40 ×4-bit RAM for display data storage
•Auto-incremental display data loading across device
subaddress boundaries
•Display memory bank switching in static and duplex
drive modes
•Versatile blinking modes
•Independent supplies possible for LCD and logic
voltages
•Wide power supply range: from 1.8 to 5.5 V
•Wide logic LCD supply range: from 2.5 V for
low-thresholdLCDsandupto6.5 Vforguest-hostLCDs
and high-threshold (automobile) twisted nematic LCDs
•Low power consumption
•400 kHz I2C-bus interface
•TTL/CMOS compatible
•Compatible with 4, 8 or 16-bit microprocessors or
microcontrollers
•May be cascaded for large LCD applications (up to
2560 elements possible)
•No external components
•Compatible with chip-on-glass technology
•Manufactured in silicon gate CMOS process.
2 GENERAL DESCRIPTION
The PCF8576D is a peripheral device which interfaces to
almost any Liquid Crystal Display (LCD) with low multiplex
rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up
to40 segmentsandcaneasilybecascaded for larger LCD
applications. The PCF8576D is compatible with most
microprocessors/microcontrollersandcommunicatesviaa
two-line bidirectional I2C-bus. Communication overheads
are minimized by a display RAM with auto-incremental
addressing, by hardware subaddressing and by display
memory switching (static and duplex drive modes).
3 ORDERING INFORMATION
Note
1. These types have improved EMC immunity.
TYPE NUMBER PACKAGE
NAME DESCRIPTION VERSION
PCF8576DH TQFP64 plastic thin quad flat package; 64 leads; body 10 ×10 ×1.0 mm SOT357-1
PCF8576DT TSSOP56 plastic thin shrink small outline package; 56 leads; body width
6.1 mm SOT364-1
PCF8576DU/DA −chips in tray −
PCF8576DH/2(1) TQFP64 plastic thin quad flat package; 64 leads; body 10 ×10 ×1.0 mm SOT357-1
PCF8576DT/2(1) TSSOP56 plastic thin shrink small outline package; 56 leads; body width
6.1 mm SOT364-1
PCF8576DU/DA/2(1) −chips in tray −
PCF8576DU/2DA/2(1) −chip with bumps in tray −
2004 Dec 22 4
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
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4 BLOCK DIAGRAM
handbook, full pagewidth
MDB075
LCD
VOLTAGE
SELECTOR
CLOCK SELECT
AND TIMING BLINKER
TIMEBASE
OSCILLATOR
INPUT
FILTERS I
2
C-BUS
CONTROLLER
POWER-ON
RESET
CLK
SYNC
OSC
SCL
SDA
SA0
BACKPLANE
OUTPUTS
DISPLAY
CONTROLLER
BP0
25
21
20
13
12
15
VDD 14
11
10
19 16
1, 8, 9, 22 to 24, 33, 48 17 18
26 27 28
BP2 BP1 BP3
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
OUTPUT BANK SELECT
AND BLINK CONTROL
29 to 32, 34 to 47,
49 to 64, 2 to 7
S0 to S39
n.c. A0 A1 A2
PCF8576DH
LCD BIAS
GENERATOR
VSS
VLCD
COMMAND
DECODER WRITE DATA
CONTROL
DISPLAY
RAM
40 × 4 BIT
DATA POINTER AND
AUTO INCREMENT
SUB-ADDRESS
COUNTER
Fig.1 Block diagram for version PCF8576DH.
2004 Dec 22 5
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
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001aab131
LCD
VOLTAGE
SELECTOR
CLOCK SELECT
AND TIMING BLINKER
TIMEBASE
OSCILLATOR
INPUT
FILTERS I2C-BUS
CONTROLLER
POWER-ON
RESET
CLK
SYNC
OSC
SCL
SDA
SA0
BACKPLANE
OUTPUTS
DISPLAY
CONTROLLER
BP0
56
55
54
47
46
49
VDD 48
45
44
53 50 51 52
123
BP2 BP1 BP3
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
OUTPUT BANK SELECT
AND BLINK CONTROL
4 to 43
S0 to S39
A0 A1 A2
PCF8576DT
LCD BIAS
GENERATOR
VSS
VLCD
COMMAND
DECODER WRITE DATA
CONTROL
DISPLAY
RAM
40 × 4 BIT
DATA POINTER AND
AUTO INCREMENT
SUB-ADDRESS
COUNTER
Fig.2 Block diagram for version PCF8576DT.
2004 Dec 22 6
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
5 PINNING
SYMBOL PIN PAD DESCRIPTION
PCF8576DH PCF8576DT PCF8576DU
SDA 10 44 1, 58 and 59 I2C-bus serial data input/output
SCL 11 45 2 and 3 I2C-bus serial clock input
CLK 13 47 5 external clock input/output
VDD 14 48 6 supply voltage
SYNC 12 46 4 cascade synchronization
input/output
OSC 15 49 7 internal oscillator enable input
A0 to A2 16 to 18 50 to 52 8 to 10 subaddress inputs
SA0 19 53 11 I2C-bus slave address input; bit 0
VSS 20 54 12 logic ground
VLCD 21 55 13 LCD supply voltage
BP0, BP2, BP1, BP3 25 to 28 56, 1, 2, 3 14 to 17 LCD backplane outputs
S0 to S39 29 to 32, 34 to 47,
49 to 64, 2 to 7 4 to 43 18 to 57 LCD segment outputs
n.c. 1, 8, 9, 22 to 24,
33 and 48 −−not connected
2004 Dec 22 7
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
handbook, full pagewidth
PCF8576DH
MDB073
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
n.c.
S34
S35
S36
S37
S38
S39
n.c.
n.c.
SDA
SCL
SYNC
CLK
V
OSC
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
n.c.
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
n.c.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A1
A2
SA0
V
V
n.c.
n.c.
n.c.
BP0
BP2
BP1
BP3
S0
S1
S2
S3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
DD
SS
LCD
Fig.3 Pin configuration (TQFP64).
2004 Dec 22 8
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
PCF8576DT
BP2 BP0
BP1 VLCD
BP3 VSS
S0 SA0
S1 A2
S2 A1
S3 A0
S4 OSC
S5 VDD
S6 CLK
S7 SYNC
S8 SCL
S9 SDA
S10 S39
S11 S38
S12 S37
S13 S36
S14 S35
S15 S34
S16 S33
S17 S32
S18 S31
S19 S30
S20 S29
S21 S28
S22 S27
S23 S26
S24 S25
001aab132
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Fig.4 Pin configuration (TSSOP56).
2004 Dec 22 9
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
6 FUNCTIONAL DESCRIPTION
The PCF8576D is a versatile peripheral device designed
to interface any microprocessor/microcontroller with a
wide variety of LCDs. It can directly drive any static or
multiplexed LCD containing up to four backplanes and up
to 40 segments.
The display configurations possible with the PCF8576D
depend on the number of active backplane outputs
required. A selection of display configurations is shown in
Table 1; all of these configurations can be implemented in
the typical system shown in Fig.5.
The host microprocessor/microcontroller maintains the
2-line I2C-bus communication channel with the
PCF8576D. The internal oscillator is enabled by
connecting pin OSC to pin VSS. The appropriate biasing
voltages for the multiplexed LCD waveforms are
generated internally. The only other connections required
to complete the system are to the power supplies (VDD,
VSS and VLCD) and the LCD panel chosen for the
application.
Table 1 Selection of display configurations
NUMBER OF 7-SEGMENTS NUMERIC 14-SEGMENTS
ALPHANUMERIC DOT MATRIX
BACKPLANES SEGMENTS DIGITS INDICATOR
SYMBOLS CHARACTERS INDICATOR
SYMBOLS
4 160 20 20 10 20 160 dots (4 ×40)
3 120 15 15 8 8 120 dots (3 ×40)
2 80 10 10 5 10 80 dots (2 ×40)
1 40 5 5 2 12 40 dots (1 ×40)
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
tr
2CB
SDA
SCL
OSC
40 segment drives
4 backplanes
LCD PANEL
(up to 160
elements)
PCF8576DU
A0
8
7
2, 3
1, 58, 59
613
9 101112
A1 A2 SA0
VDD
VSS
VSS
VDD VLCD
mdb079
R ≤
Fig.5 Typical system configuration.
The resistance of the power supply lines must be kept to a minimum.
For chip-on-glass applications, due to Indium Tin Oxide (ITO) track resistance, each supply line must be routed separately
between the chip and the connector.
2004 Dec 22 10
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
6.1 Power-on reset
At power-on the PCF8576D resets to the following starting
conditions:
•All backplane outputs are set to VLCD
•All segment outputs are set to VLCD
•Drive mode ‘1 : 4 multiplex with 1⁄3bias’ is selected
•Blinking is switched off
•Input and output bank selectors are reset (as defined in
Table 4)
•The I2C-bus interface is initialized
•The data pointer and the subaddress counter are
cleared
•Display is disabled.
Data transfers on the I2C-bus should be avoided for 1 ms
following power-on to allow completion of the reset action.
6.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an
internal voltage divider comprising three resistors
connected in series between VLCD and VSS. The middle
resistor can be bypassed to provide a 1⁄2bias voltage level
for the 1 : 2 multiplex configuration. The LCD voltage can
be temperature compensated externally via the supply to
pin VLCD.
6.3 LCD voltage selector
The LCD voltage selector co-ordinates the multiplexing of
the LCD in accordance with the selected LCD drive
configuration. The operation of the voltage selector is
controlled by MODE SET commands from the command
decoder. The biasing configurations that apply to the
preferred modes of operation, together with the biasing
characteristics as functions of VLCD and the resulting
Discrimination ratios (D), are given in Table 2.
A practical value for VLCD is determined by equating
Voff(rms) with a defined LCD threshold voltage (Vth),
typically when the LCD exhibits approximately 10%
contrast. In the static drive mode a suitable choice is
VLCD >3V
th.
Multiplex drive modes of 1 : 3 and 1 : 4 with 1⁄2bias are
possible but the discrimination and hence the contrast
ratios are smaller.
6.3.1 LCD BIAS FORMULAE
Bias is calculated by the formula
For 1⁄2bias, a = 1; for 1⁄3bias, a = 2.
The LCD on voltage (Von) is calculated by the formula
The LCD off voltage (Voff) is calculated by the formula
where Vop is the resultant voltage at the LCD segment; N
is the LCD drive mode: 1 = static, 2 = 1 : 2, 3 = 1 : 3,
4=1:4.
Discrimination is the ratio of Von to Voff, and is determined
by the formula
Using the above formula, the discrimination for an LCD
drive mode of 1 : 3 with 1⁄2bias is = 1.732, and the
discrimination for an LCD drive mode of 1 : 4 with 1⁄2bias
is = 1.528.
The advantage of these LCD drive modes is a reduction of
the LCD full-scale voltage VLCD as follows:
1 : 3 multiplex (1⁄2bias):
VLCD = = 2.449 Voff(rms)
1 : 4 multiplex (1⁄2bias):
VLCD = = 2.309 Voff(rms)
These compare with VLCD =3V
off(rms) when 1⁄3bias is
used.
1
1a+
-------------
1
N
----N1–()
1
1a+
-------------
⋅2
+
N
------------------------------------------------------------
Vop
a22a N+()–
N1a+()
2
⋅
----------------------------------
Vop
Von
Voff
--------- a1+()
2N1–()+
a1–()
2N1–()+
---------------------------------------------=
3
21
3
----------
6V
off(rms)
×
43×()
3
----------------------
2004 Dec 22 11
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
Table 2 Discrimination ratios
6.4 LCD drive mode waveforms
6.4.1 STATIC DRIVE MODE
The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment
drive (Sn) waveforms for this mode are shown in Fig.4.
LCD DRIVE MODE NUMBER OF LCD BIAS
CONFIGURATION
BACKPLANES LEVELS
static 1 2 static 0 1 ∞
1 : 2 multiplex 2 3 1⁄20.354 0.791 2.236
1 : 2 multiplex 2 4 1⁄30.333 0.745 2.236
1 : 3 multiplex 3 4 1⁄30.333 0.638 1.915
1 : 4 multiplex 4 4 1⁄30.333 0.577 1.732
Voff(rms)
Vlcd
---------------------Von(rms)
Vlcd
---------------------DVon(rms)
Voff(rms)
---------------------
=
handbook, full pagewidth
MGL745
VSS
VLCD
VSS
VLCD
VSS
VLCD
VLCD
−VLCD
−VLCD
VLCD
state 1 0 V
BP0
Sn
Sn + 1
state 2 0 V
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 1
(on) state 2
(off)
Tframe
Fig.6 Static drive mode waveforms.
Von(rms) VLCD
=
Vstate2 t() V
Sn1+t() V
BP0 t()–=
Voff(rms) 0V=
2004 Dec 22 12
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
6.4.2 1 : 2 MULTIPLEX DRIVE MODE
The 1 : 2 multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD
bias voltages of 1⁄2bias or 1⁄3bias as shown in Figs 7 and 8.
handbook, full pagewidth
MGL746
state 1
BP0
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 2
state 1
VSS
VLCD
VLCD/2
VSS
VSS
VLCD
VLCD
VSS
VLCD
VLCD
VLCD
0 V
0 V
VLCD/2
VLCD/2
VLCD/2
−VLCD
−VLCD
−VLCD/2
−VLCD/2
Sn
Sn + 1
Tframe
Fig.7 Waveforms for the 1 : 2 multiplex drive mode with 1⁄2bias.
Vstate1 t() V
Snt() V
BP0 t()–=
Von(rms) 0.791VLCD
=
Vstate2 t() V
Snt() V
BP1 t()–=
Voff(rms) 0.354VLCD
=
2004 Dec 22 13
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
handbook, full pagewidth
MGL747
state 1
BP0
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
0 V
VLCD
2VLCD/3
−2VLCD/3
VLCD/3
−VLCD/3
−VLCD
0 V
VLCD
2VLCD/3
−2VLCD/3
VLCD/3
−VLCD/3
−VLCD
Sn
Sn + 1
Tframe
VSS
VLCD
2VLCD/3
VLCD/3
Fig.8 Waveforms for the 1 : 2 multiplex drive mode with 1⁄3bias.
Vstate1 t() V
Snt() V
BP0 t()–=
Von(rms) 0.745VLCD
=
Vstate2 t() V
Snt() V
BP1 t()–=
Voff(rms) 0.333VLCD
=
2004 Dec 22 14
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
6.4.3 1 : 3 MULTIPLEX DRIVE MODE
When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies (see Fig.9).
handbook, full pagewidth
MGL748
state 1
BP0
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
(a) Waveforms at driver.
BP2
Sn
Sn + 1
Sn + 2
Tframe
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
0 V
VLCD
2VLCD/3
−2VLCD/3
VLCD/3
−VLCD/3
−VLCD
0 V
VLCD
2VLCD/3
−2VLCD/3
VLCD/3
−VLCD/3
−VLCD
VSS
VLCD
2VLCD/3
VLCD/3
Fig.9 Waveforms for the 1 : 3 multiplex drive mode.
Vstate1 t() V
Snt() V
BP0 t()–=
Von(rms) 0.638VLCD
=
Vstate2 t() V
Snt() V
BP1 t()–=
Voff(rms) 0.333VLCD
=
2004 Dec 22 15
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
6.4.4 1 : 4 MULTIPLEX DRIVE MODE
When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies (see Fig.10).
handbook, full pagewidth
MGL749
state 1
BP0
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
BP2
(a) Waveforms at driver.
BP3
Sn
Sn + 1
Sn + 2
Sn + 3
Tframe
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
0 V
VLCD
2VLCD/3
−2VLCD/3
VLCD/3
−VLCD/3
−VLCD
0 V
VLCD
2VLCD/3
−2VLCD/3
VLCD/3
−VLCD/3
−VLCD
VSS
VLCD
2VLCD/3
VLCD/3
Fig.10 Waveforms for the 1 : 4 multiplex drive mode.
Vstate1 t() V
Snt() V
BP0 t()–=
Von(rms) 0.577VLCD
=
Vstate2 t() V
Snt() V
BP1 t()–=
Voff(rms) 0.333VLCD
=
2004 Dec 22 16
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
6.5 Oscillator
6.5.1 INTERNAL CLOCK
The internal logic of the PCF8576D and its LCD drive
signals are timed either by its internal oscillator or by an
external clock. The internal oscillator is enabled by
connecting pin OSC to pin VSS. If the internal oscillator is
used, the output from pin CLK can be used as the clock
signal for several PCF8576Ds in the system that are
connected in cascade. After power-up, pin SDA must be
HIGH to guarantee that the clock starts.
6.5.2 EXTERNAL CLOCK
Pin CLK is enabled as an external clock input by
connecting pin OSC to VDD.
The LCD frame signal frequency is determined by the
clock frequency (fCLK).
A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.
6.6 Timing
ThePCF8576D timing controls theinternal data flow ofthe
device. This includes the transfer of display data from the
display RAM to the display segment outputs. In cascaded
applications, the correct timing relationship between each
PCF8576D in the system is maintained by the
synchronization signal at pin SYNC. The timing also
generates the LCD frame signal whose frequency is
derived from the clock frequency. The frame signal
frequency is a fixed division of the clock frequency from
either the internal or an external clock.
Frame frequency =
6.7 Display register
The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and each column of the
display RAM.
6.8 Segment outputs
The LCD drive section includes 40 segment outputs
S0 to S39 which should be connected directly to the LCD.
The segment output signals are generated in accordance
with the multiplexed backplane signals and with data
residing in the display latch. When less than 40 segment
outputs are required, the unused segment outputs should
be left open-circuit.
6.9 Backplane outputs
The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required, the unused outputs
can be left open-circuit. In the 1 : 3 multiplex drive mode,
BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced
drive capabilities. In the 1 : 2 multiplex drive mode, BP0
and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.
6.10 Display RAM
The display RAM is a static 40 ×4-bit RAM which stores
LCD data. A logic 1 in the RAM bit-map indicates the
on-state of the corresponding LCD segment; similarly, a
logic 0 indicates the off-state. There is a one-to-one
correspondence between the RAM addresses and the
segmentoutputs,andbetweenthe individual bits ofaRAM
word and the backplane outputs. The first RAM column
corresponds to the 40 segments operated with respect to
backplane BP0 (see Fig.11). In multiplexed LCD
applications the segment data of the second, third and
fourth column of the display RAM are time-multiplexed
with BP1, BP2 and BP3 respectively.
When display data is transmitted to the PCF8576D, the
display bytes received are stored in the display RAM in
accordancewith theselected LCD drive mode. Thedata is
stored as it arrives and does not wait for an acknowledge
cycle as with the commands. Depending on the current
multiplex drive mode, data is stored singularly, in pairs,
triplets or quadruplets. For example, in the 1 : 2 mode, the
RAMdata is storedevery second bit.To illustrate the filling
order, an example of a 7-segment numeric display
showing all drive modes is given in Fig.12; the RAM filling
organization depicted applies equally to other LCD types.
With reference to Fig.12, in the static drive mode, the eight
transmitteddata bits are placed in bit 0 ofeight successive
display RAM addresses. In the 1 : 2 mode, the eight
transmitted data bits are placed in bits 0 and 1 of four
successive display RAM addresses. In the 1 : 3 mode,
these bits are placed in bits 0, 1 and 2 of three successive
addresses, with bit 2 of the third address left unchanged.
This last bit may, if necessary, be controlled by an
additionaltransfer to this addressbutcare should betaken
to avoid overriding adjacent data because full bytes are
always transmitted.
fCLK
24
----------
2004 Dec 22 17
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
In the 1 : 4 mode, the eight transmitted data bits are
placed in bits 0, 1, 2 and 3 of two successive display RAM
addresses.
6.11 Data pointer
The addressing mechanism for the display RAM is
realized using the data pointer. This allows the loading of
an individual display data byte, or a series of display data
bytes, into any location of the display RAM. The sequence
commenceswith the initialization of the data pointerby the
LOAD DATA POINTER command. Following this, an
arriving data byte is stored at the display RAM address
indicated by the data pointer in accordance with the filling
order shown in Fig.12. After each byte is stored, the
contents of the data pointer are automatically incremented
by a value dependent on the selected LCD drive mode:
eight (static drive mode), four (1 : 2 mode), three
(1 : 3 mode) or two (1 : 4 mode). If an I2C-bus data access
is terminated early then the state of the data pointer will be
unknown. The data pointer should be re-written prior to
further RAM accesses.
0
0
1
2
3
1234 3536373839
display RAM addresses (rows) / segment outputs (S)
display RAM bits
(columns) /
backplane outputs
(BP)
MBE525
Fig.11 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs,
and between bits in a RAM word and backplane outputs.
6.12 Subaddress counter
The storage of display data is determined by the contents
of the subaddress counter. Storage is allowed to take
place only when the contents of the subaddress counter
agree with the hardware subaddress applied to A0, A1
and A2. The subaddress counter value is defined by the
DEVICE SELECT command. If the contents of the
subaddress counter and the hardware subaddress do not
agree then data storage is inhibited but the data pointer is
incremented as if data storage had taken place. The
subaddress counter is also incremented when the data
pointer overflows.
The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a
series of display bytes are sent to the display RAM,
automatic wrap-over to the next PCF8576D occurs when
the last RAM address is exceeded. Subaddressing across
device boundaries is successful even if the change to the
next device in the cascade occurs within a transmitted
character (such as during the 14th display data byte
transmitted in 1 : 3 mode).
The hardware subaddress should not be changed whilst
the device is being accessed on the I2C-bus interface.
6.13 Output bank selector
The output bank selector selects one of the four bits per
display RAM address for transfer to the display latch. The
actual bit chosen depends on the selected LCD drive
modeandonthe instantinthemultiplexsequence.In 1 : 4
mode, all RAM addresses of bit 0 are selected, these are
followed by the contents of bit 1, bit 2 and then bit 3.
Similarly in 1 : 3 mode, bits 0, 1 and 2 are selected
sequentially. In 1 : 2 mode, bits 0 and 1 are selected and,
in static mode, bit 0 is selected. Signal SYNC will reset
these sequences to the following starting points; bit 3 for
1 : 4 mode, bit 2 for 1 : 3 mode, bit 1 for 1 : 2 mode and
bit 0 for static mode.
The PCF8576D includes a RAM bank switching feature in
the static and 1 : 2 drive modes. In the static drive mode,
theBANK SELECT command may requestthe contents of
bit 2 to be selected for display instead of the contents of
bit 0. In 1 : 2 mode, the contents of bits 2 and 3 may be
selected instead of bits 0 and 1. This allows display
information to be prepared in an alternative bank and then
selected for display when it is assembled.
2004 Dec 22 18
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
6.14 Input bank selector
The input bank selector loads display data into the display
RAM in accordance with the selected LCD drive
configuration. The BANK SELECT command can be used
to load display data in bit 2 in static drive mode or in
bits 2 and 3 in 1 : 2 mode. The input bank selector
functions are independent of the output bank selector.
6.15 Blinker
The PCF8576D has a very versatile display blinking
capability. The whole display can blink at a frequency
selected by the BLINK command. Each blink frequency is
a multiple integer value of the clock frequency; the ratio
between the clock frequency and blink frequency depends
on the blink mode selected, as shown in Table 3.
An additional feature allows an arbitrary selection of LCD
segmentstobeblinked in the static and1 : 2 drivemodes.
This is implemented without any communication
overheads by the output bank selector which alternates
the displayed data between the data in the display RAM
bank and the data in an alternative RAM bank at the blink
frequency. This mode can also be implemented by the
BLINK command.
In the 1 : 3 and 1 : 4 drive modes, where no alternative
RAM bank is available, groups of LCD segments can be
blinked by selectively changing the display RAM data at
fixed time intervals.
Theentire display canbe blinked at afrequency other than
the nominal blink frequency by sequentially resetting and
setting the display enable bit E at the required rate using
the MODE SET command.
Table 3 Blinking frequencies
Note
1. Blink modes 0.5, 1 and 2 Hz, and nominal blink frequencies 0.5, 1 and 2 Hz correspond to an oscillator frequency
(fCLK) of 1536 Hz at pin CLK. The oscillator frequency range is given in Chapter 11.
BLINK MODE NORMAL OPERATING MODE
RATIO NOMINAL BLINK FREQUENCY
Off −blinking off
2Hz 2Hz
1Hz 1Hz
0.5 Hz 0.5 Hz
fCLK
768
-----------
fCLK
1536
-------------
fCLK
3072
-------------
2004 Dec 22 19
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
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handbook, full pagewidth
MGL751
S2
n
S1
n
S7
n
Sn
Sn
S3
n
S5
n
S2
n
S3
n
S1
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S1
n
S2
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S6
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BP1
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BP0
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1
2
3
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x
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n1 n2 n3 n4 n5 n6 n7
bit/
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cbaf gedDP
abf gecdDP
bDPcadgf e
acbDPf egd
MSB LSB
MSB LSB
MSB LSB
MSB LSB
drive mode
static
1 : 2
multiplex
1 : 3
multiplex
1 : 4
multiplex
LCD segments LCD backplanes display RAM filling order transmitted display byte
Fig.12 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus.
x = data bit unchanged.
2004 Dec 22 20
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
7 CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not
busy.
In chip-on-glass applications where the track resistance
from the SDA pad to the system SDA line can be
significant, a potential divider is generated by the bus
pull-up resistor and the Indium Tin Oxide (ITO) track
resistance. It is therefore necessary to minimize the track
resistance from the SDA pad to the system SDA line to
guarantee a valid LOW-level during the acknowledge
cycle.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
period of the clock pulse as changes in the data line at this
time will be interpreted as a control signal (see Fig.13).
7.2 Start and stop conditions
Bothdataand clock lines remainHIGHwhen the bus isnot
busy. A HIGH-to-LOW transition of the data line while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
isHIGH is defined as theSTOP condition (P), (see Fig.14).
7.3 System configuration
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controlsthemessageisthe‘master’ and thedeviceswhich
are controlled by the master are the ‘slaves’, (see Fig.15).
7.4 Acknowledge
The number of data bytes that can be transferred from
transmitter to receiver between the START and STOP
conditions is unlimited. Each byte of eight bits is followed
by an acknowledge bit. The acknowledge bit is a
HIGH-level signal on the bus that is asserted by the
transmitter during which time the master generates an
extra acknowledge related clock pulse. An addressed
slave receiver must generate an acknowledge after
receiving each byte. Also a master receiver must generate
an acknowledge after receiving each byte that has been
clocked out of the slave transmitter. The acknowledging
device must pull-down the SDA line during the
acknowledge clock pulse so that the SDA line is stable
LOW during the HIGH period of the acknowledge related
clock pulse (set-up and hold times must be taken into
consideration). A master receiver must signal an end of
data to the transmitter by not generating an acknowledge
on the last byte that has been clocked out of the slave.
In this event the transmitter must leave the data line HIGH
to enable the master to generate a STOP condition (see
Fig.16).
7.5 PCF8576D I2C-bus controller
The PCF8576D acts as an I2C-bus slave receiver. It does
not initiate I2C-bus transfers or transmit data to an I2C-bus
master receiver. The only data output from the PCF8576D
are the acknowledge signals of the selected devices.
Device selection depends on the I2C-bus slave address,
on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress
inputs A0, A1 and A2 are normally tied to VSS which
defines the hardware subaddress 0. In multiple device
applications A0, A1 and A2 are tied to VSS or VDD in
accordance with a binary coding scheme such that no two
devices with a common I2C-bus slave address have the
same hardware subaddress.
7.6 Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.7 I2C-bus protocol
Two I2C-bus slave addresses (01110000 and 01110010)
are reserved for the PCF8576D. The least significant bit of
the slave address that a PCF8576D will respond to is
defined by the level tied to its SA0 input. The PCF8576D
is a write-only device and will not respond to a read
access. Having two reserved slave addresses allows the
following on the same I2C-bus:
•Up to 16 PCF8576Ds for very large LCD applications
•The use of two types of LCD multiplex drive.
The I2C-bus protocol is shown in Fig.17. The sequence is
initiated with a START condition (S) from the I2C-bus
master which is followed by one of two possible
PCF8576D slave addresses available. All PCF8576Ds
whose SA0 inputs correspond to bit 0 of the slave address
respond by asserting an acknowledge in parallel. This
I2C-bus transfer is ignored by all PCF8576Ds whose SA0
inputs are set to the alternative level.
2004 Dec 22 21
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
After an acknowledgement, one or more command bytes
follow that define the status of each addressed
PCF8576D.
The last command byte sent is identified by resetting its
most significant bit, continuation bit C, (see Fig.18). The
command bytes are also acknowledged by all addressed
PCF8576Ds on the bus.
After the last command byte, one or more display data
bytes may follow. Display data bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data directed to the intended PCF8576D device.
An acknowledgement after each byte is asserted only by
the PCF8576Ds that are addressed via address lines A0,
A1 and A2. After the last display byte, the I2C-bus master
asserts a STOP condition (P). Alternately a START may
be asserted to RESTART an I2C-bus access.
7.8 Command decoder
The command decoder identifies command bytes that
arrive on the I2C-bus. All available commands carry a
continuation bit C in their most significant bit position as
shown in Fig.18. When this bit is set, it indicates that the
next byte of the transfer to arrive will also represent a
command. If this bit is reset, it indicates that the command
byte is the last in the transfer. Further bytes will be
regarded as display data.
The five commands available to the PCF8576D are
defined in Table 4.
MBA607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig.13 Bit transfer.
handbook, full pagewidth
MBC622
SDA
SCL P
STOP condition
SDA
SCL
S
START condition
Fig.14 Definition of START and STOP conditions.
2004 Dec 22 22
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
MGA807
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Fig.15 System configuration.
handbook, full pagewidth
MBC602
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
Fig.16 Acknowledgement on the I2C-bus.
k
, full pagewidth
MDB078
S
A
0
S011100 0AC COMMAND A P
ADISPLAY DATA
slave address R/W
acknowledge by
all addressed
PCF8576Ds
acknowledge
by A0, A1 and A2
selected
PCF8576D only
1 byte
update data pointers
and if necessary,
subaddress counter
n ≥ 1 byte(s) n ≥ 0 byte(s)
Fig.17 I2C-bus protocol.
2004 Dec 22 23
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
MSA833
REST OF OPCODE
C
MSB LSB
Fig.18 Format of command byte.
C = 0 = last command.
C = 1 = commands continue.
Table 4 Definition of PCF8576D commands
Note
1. Not used.
COMMAND OPCODE OPTIONS DESCRIPTION
MODE SET C 1 0 (1) E B M1 M0 Table 5 Defines LCD drive mode.
Table 6 Defines LCD bias configuration.
Table 7 Defines display status; the possibility to
disable the display allows implementation
of blinking under external control.
LOADDATA
POINTER C 0 P5 P4 P3 P2 P1 P0 Table 8 Six bits of immediate data, bits P5 to P0,
are transferred to the data pointer to
define one of forty display RAM
addresses.
DEVICE
SELECT C1100A2A1A0Table9 Three bits of immediate data, bits A0 to
A2, are transferred to the subaddress
counter to define one of eight hardware
subaddresses.
BANK
SELECT C11110I OTable10Defines input bank selection (storage of
arriving display data).
Table 11 Defines output bank selection (retrieval of
LCD display data); the BANK SELECT
command has no effect in 1 : 3 and 1 : 4
multiplex drive modes.
BLINK C 1110ABF1BF0Table12Defines the blink frequency.
Table 13 Selects the blink mode; normal operation
with frequency set by BF1, BF0 or blinking
by alternating display RAM banks;
alternating RAM bank blinking does not
apply in 1 : 3 and 1 : 4 multiplex drive
modes.
2004 Dec 22 24
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
Table 5 Mode set option 1
Table 6 Mode set option 2
Table 7 Mode set option 3
Table 8 Load data pointer option 1
Table 9 Device select option 1
Table 10 Bank select option 1 (input)
Table 11 Bank select option 2 (output)
Table 12 Blink option 1
Table 13 Blink option 2
Note
1. Normal blinking is assumed when LCD multiplex drive
modes 1 : 3 or 1 : 4 are selected.
7.9 Display controller
The display controller executes the commands identified
by the command decoder. It contains the device’s status
registers and co-ordinates their effects. The display
controller is also responsible for loading display data into
the display RAM in the correct filling order.
7.10 Cascaded operation
In large display configurations, up to 16 PCF8576Ds can
be differentiated on the same I2C-bus by using the 3-bit
hardware subaddresses (A0, A1 and A2) and the
programmable I2C-bus slave address (SA0). PCF8576Ds
connected in cascade are synchronized to allow the
backplane signals from only one device in the cascade to
beshared. This arrangement is cost-effectivein large LCD
applications since the backplane outputs of only one
device need to be through-plated to the backplane
electrodesofthedisplay.The other cascadedPCF8576Ds
contribute additional segment outputs but their backplane
outputs are left open-circuit (see Fig.19).
LCD DRIVE MODE BITS
DRIVE
MODE BACKPLANE M1 M0
Static BP0 0 1
1 : 2 BP0, BP1 1 0
1 : 3 BP0, BP1, BP2 1 1
1 : 4 BP0, BP1, BP2, BP3 0 0
LCD BIAS BIT B
1⁄3bias 0
1⁄2bias 1
DISPLAY STATUS BIT E
Disabled (blank) 0
Enabled 1
DESCRIPTION BITS
6 bit binary value of 0 to 39 P5 P4 P3 P2 P1 P0
DESCRIPTION BITS
3 bit binary value of 0 to 7 A2 A1 A0
MODE BIT I
STATIC 1 : 2
RAM bit 0 RAM bits 0 and 1 0
RAM bit 2 RAM bits 2 and 3 1
MODE BIT O
STATIC 1 : 2
RAM bit 0 RAM bits 0 and 1 0
RAM bit 2 RAM bits 2 and 3 1
BLINK FREQUENCY BITS
BF1 BF0
Off 0 0
2Hz 0 1
1Hz 1 0
0.5 Hz 1 1
BLINK MODE BITA
Normal blinking 0
Alternate RAM bank blinking 1
2004 Dec 22 25
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
All PCF8576Ds connected in cascade are correctly
synchronized by the SYNC signal. This synchronization is
guaranteed after the Power-on reset. The only time that
SYNC is likely to be needed is if synchronization is lost
accidentally, for example, by noise in adverse electrical
environments, or if the LCD multiplex drive mode is
changed in an application using several cascaded
PCF8576Ds, as the drive mode cannot be changed on all
of the cascaded devices simultaneously. SYNC can be
either an input or an output signal; a SYNC output is
implemented as an open-drain driver with an internal
pull-up resistor. A PCF8576D asserts SYNC at the start of
its last active backplane signal, and monitors the SYNC
line at all other times. If cascade synchronization is lost, it
will be restored by the first PCF8576D to assert SYNC.
Thetiming relationship between thebackplane waveforms
and the SYNC signal for each LCD drive mode is shown in
Fig.20.
Table 14 SYNC contact resistance
The contact resistance between the SYNC input/output on
eachcascadeddevicemustbecontrolled.Iftheresistance
is too high, the device will not be able to synchronize
properly; this is particularly applicable to chip-on-glass
applications. The maximum SYNC contact resistance
allowed for the number of devices in cascade is given in
Table 14.
NUMBER OF DEVICES MAXIMUM CONTACT
RESISTANCE
2 6000 Ω
3 to 5 2200 Ω
6 to 10 1200 Ω
10 to 16 700 Ω
handbook, full pagewidth
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDA
SCL
CLK
OSC
SYNC
1, 58, 59
2, 3
4
5
7
89
6
8 9 10 11 12
13
10 11 12
40 segment drives
4 backplanes
40 segment drives LCD PANEL
(up to 2560
elements)
PCF8576DU
A0 A1 A2 SA0
VDD
VLCD
DD
VLCD
V
MDB077
SDA
SCL
SYNC
CLK
OSC
1, 58, 59
613
2, 3
4
5
7BP0 to BP3
(open-circuit)
A0 A1 A2 SA0 VSS
VSS
VSS
VDD VLCD
PCF8576DU
BP0 to BP3
Rtr
2CB
≤
Fig.19 Cascaded PCF8576D configuration.
2004 Dec 22 26
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
handbook, full pagewidth
T=
frame fframe
1
BP0
SYNC
BP1
(1/2 bias)
SYNC
BP2
(a) static drive mode.
(b) 1 : 2 multiplex drive mode.
(c) 1 : 3 multiplex drive mode.
(d) 1 : 4 multiplex drive mode.
BP3
SYNC
SYNC
BP1
(1/3 bias)
MGL755
Fig.20 Synchronization of the cascade for the various PCF8576D drive modes.
2004 Dec 22 27
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
9 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see
“Handling MOS Devices”
).
SYMBOL PARAMETER MIN. MAX. UNIT
VDD supply voltage −0.5 +6.5 V
VLCD LCD supply voltage VSS −0.5 +7.5 V
Vi1 input voltage CLK, SYNC, SA0, OSC, A0 to A2 VSS −0.5 VDD + 0.5 V
Vi2 input voltage SCL and SDA VSS −0.5 +6.5 V
VOoutput voltage S0 to S39, BP0 to BP3 VSS −0.5 VDD + 0.5 V
IIDC input current −10 +10 mA
IODC output current −10 +10 mA
IDD VDD current −50 +50 mA
ISS VSS current −50 +50 mA
ILCD VLCD current −50 +50 mA
Ptot total power dissipation −400 mW
POpower dissipation per output −100 mW
Tstg storage temperature −65 +150 °C
2004 Dec 22 28
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
10 DC CHARACTERISTICS
VDD = 1.8 to 5.5 V; VSS =0V;V
LCD = 2.5 to 6.5 V; Tamb =−40 to +85 °C; unless otherwise specified.
Notes
1. VLCD > 3 V for 1⁄3bias.
2. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive.
3. When tested, I2C pins SCL and SDA have no diode to VDD and may be driven according to the Vi2 limiting values
given in Chapter 8. Also see Fig.24.
4. Periodically sampled, not 100% tested.
5. Outputs measured one at a time.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VDD supply voltage 1.8 −5.5 V
VLCD LCD supply voltage note 1 2.5 −6.5 V
IDD supply current note 2; fCLK = 1536 Hz −820µA
ILCD LCD supply current note 2; fCLK = 1536 Hz −24 60 µA
Logic
VIL LOW-level input voltage
CLK, SYNC, OSC, A0 to A2 and SA0 VSS −0.3VDD V
VIH HIGH-level input voltage
CLK, SYNC, OSC, A0 to A2 and SA0 0.7VDD −VDD V
VIL2 LOW-level input voltage SCL, SDA VSS −0.3VDD V
VIH2 HIGH-level input voltage SCL, SDA note 3 0.7VDD −VDD V
IOL1 LOW-level output current CLK, SYNC VOL = 0.4 V; VDD =5V 1 −−mA
IOH1 HIGH-level output current CLK VOH = 4.6 V; VDD =5V −1−−mA
IOL2 LOW-level output current SDA VOL = 0.4 V; VDD =5V 3 −−mA
IL1 leakage current
CLK, SCL, SDA, A0 to A2 and SA0 VI=V
DD or VSS −1−+1 µA
IL2 leakage current OSC VI=V
DD −1−+1 µA
VPOR power-on reset voltage level 1.0 1.3 1.6 V
CIinput capacitance note 4 −−7pF
LCD outputs
VBP DC voltage tolerance BP0 to BP3 −100 −+100 mV
VSDC voltage tolerance S0 to S39 −100 −+100 mV
RBP output resistance BP0 to BP3 note 5; VLCD =5V −1.5 −kΩ
RSoutput resistance S0 to S39 note 5; VLCD =5V −6.0 −kΩ
2004 Dec 22 29
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
11 AC CHARACTERISTICS
VDD = 1.8 to 5.5 V; VSS =0V; V
LCD = 2.5 to 6.5 V; Tamb =−40 to +85 °C; unless otherwise specified.
Notes
1. Typical output duty factor: 50% measured at the CLK output pin.
2. Not tested in production.
3. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
fCLK oscillator frequency note 1 960 1890 2640 Hz
tCLKH input CLK HIGH time 60 −−µs
tCLKL input CLK LOW time 60 −−µs
tPD(SYNC) SYNC propagation delay −30 −ns
tSYNCL SYNC LOW time 1 −−µs
tPD(LCD) driver delays with test loads VLCD = 5 V; note 2 −−30 µs
Timing characteristics: I2C-bus; note 3
fSCL SCL clock frequency −−400 kHz
tBUF bus free time between a STOP and START 1.3 −−µs
tHD;STA START condition hold time 0.6 −−µs
tSU;STA set-up time for a repeated START condition 0.6 −−µs
tLOW SCL LOW time 1.3 −−µs
tHIGH SCL HIGH time 0.6 −−µs
trSCL and SDA rise time fSCL = 400 kHz −−0.3 µs
fSCL < 125 kHz −−1.0 µs
tfSCL and SDA fall time −−0.3 µs
CBcapacitive bus line load −−400 pF
tSU;DAT data set-up time 100 −−ns
tHD;DAT data hold time 0 −−ns
tSU;STO set-up time for STOP condition 0.6 −−µs
tSW tolerable spike width on bus −−50 ns
handbook, full pagewidth
MCE439
Ω3.3 k Ω1.5 k
0.5VDD VDD
VSS
SDA,
SCL
CLK
1 nF
BP0 to BP3, and
S0 to S39
(2%)(2%)
Ω6.8 VDD
SYNC (2%)
Fig.21 Test loads.
2004 Dec 22 30
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
handbook, full pagewidth
MCE424
0.7VDD
0.3VDD
0.7VDD
0.3VDD
SYNC
CLK
0.5 V
0.5 V
tPD(LCD)
tPD(SYNC)
BP0 to BP3,
and S0 to S39
tPD(SYNC)
tSYNCL
(VDD = 5 V)
1/fCLK tCLKL
tCLKH
Fig.22 Driver timing waveforms.
handbook, full pagewidth
SDA
MGA728
SDA
SCL
tSU;STA tSU;STO
tHD;STA
tBUF tLOW
tHD;DAT tHIGH
tr
tf
tSU;DAT
Fig.23 I2C-bus timing waveforms.
2004 Dec 22 31
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
12 BONDING PAD INFORMATION
Table 15 Bonding pad locations
All x/y coordinates represent the position of the centre of
each pad (in µm) with respect to the centre (x/y = 0) of the
chip (see Fig.23).
Table 16 Gold bump dimension PCF8576DU/2DA/2
SYMBOL PAD COORDINATES
xy
SDA 1 −34.38 −876.6
SCL 2 +109.53 −876.6
SCL 3 +181.53 −876.6
SYNC 4 +365.58 −876.6
CLK 5 +469.08 −876.6
VDD 6 +577.08 −876.6
OSC 7 +740.88 −876.6
A0 8 +835.83 −876.6
A1 9 +1005.48 −630.9
A2 10 +1005.48 −513.9
SA0 11 +1005.48 −396.9
VSS 12 +1005.48 −221.4
VLCD 13 1005.48 10.71
BP0 14 1005.48 156.51
BP2 15 1005.48 232.74
BP1 16 1005.48 308.97
BP3 17 1005.48 385.2
S0 18 1005.48 493.2
S1 19 1005.48 565.2
S2 20 1005.48 637.2
S3 21 1005.48 709.2
S4 22 347.22 876.6
S5 23 263.97 876.6
S6 24 180.72 876.6
S7 25 97.47 876.6
S8 26 14.22 876.6
S9 27 −69.03 +876.6
S10 28 −152.28 +876.6
S11 29 −235.53 +876.6
S12 30 −318.78 +876.6
S13 31 −402.03 +876.6
S14 32 −485.28 +876.6
S15 33 −568.53 +876.6
S16 34 −651.78 +876.6
S17 35 −735.03 +876.6
S18 36 −1005.5 +625.59
S19 37 −1005.5 +541.62
S20 38 −1005.5 +458.19
S21 39 −1005.5 +374.76
S22 40 −1005.5 +291.33
S23 41 −1005.5 +207.9
S24 42 −1005.5 +124.47
S25 43 −1005.5 +41.04
S26 44 −1005.5 −42.39
S27 45 −1005.5 −125.8
S28 46 −1005.5 −209.3
S29 47 −1005.5 −292.7
S30 48 −1005.5 −376.1
S31 49 −1005.5 −459.5
S32 50 −1005.5 −543
S33 51 −1005.5 −625.6
S34 52 −735.03 −876.6
S35 53 −663.03 −876.6
S36 54 −591.03 −876.6
S37 55 −519.03 −876.6
S38 56 −447.03 −876.6
S39 57 −375.03 −876.6
SDA 58 −196.38 −876.6
SDA 59 −106.38 −876.6
Alignment marks
C1 +930.42 −870.3
C2 −829.98 −870.3
DESCRIPTION DIMENSION
Gold bump dimension 52 µm×80 µm×15 µm
Gold bump tolerance 3 µm
SYMBOL PAD COORDINATES
xy
2004 Dec 22 32
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
handbook, full pagewidth
S25
S26
S27
S28
S29
S30
S31
S32
S33
C2
S4
S6
S5
S7
S9
S10
S8
S11
S12
S13
S15
S14
S16
S17
OSC
A0
SYNC
SCL
CLK
SDA
SDA
SDA
SCL
S39
S38
S36
S37
S35
S34
2.26 mm
A2
A1
C1
SA0
VSS
BP2
BP0
VLCD
BP1
BP3
S0
S2
S1
S3
PCF8576DU
VDD
2.01
mm
MDB074
x
y
0
0
35 34 33 32 31 30 29 28 27 26 25 24 23 22
21
20
19
18
17
16
15
14
13
12
11
10
9
52 53 54 55 56 57 58 59 12
3456 78
43
44
45
46
47
48
49
S18
S19
S20
S21
S22
S23
S24
36
37
38
39
40
41
42
50
51
Fig.23 Bonding pad locations.
Chip dimensions: approximately 2.26 ×2.01 mm.
Bump dimensions (except pad 1): 52 ×80 ×17.5 (height) µm.
Bump dimensions (pad 1): 52 ×76 ×17.5 (height) µm.
Alignment marks: diameter = 72 µm.
2004 Dec 22 33
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
13 DEVICE PROTECTION
handbook, full pagewidth
SA0
VDD VDD
VSS VSS
VLCD
VSS
SDA
MDB076
VSS
SCL
VSS
CLK
VDD
VSS
OSC
VDD
VSS
SYNC
VDD
VSS
A0, A1 A2
VDD
VSS
BP0, BP1,
BP2, BP3
VLCD
VSS
S0 to S39
VLCD
VSS
Fig.24 Device protection diagram.
2004 Dec 22 34
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
14 TRAY INFORMATION
handbook, full pagewidth
x
y
F
H
MCE404
D
E
A
G
1,1 x,12,1
1,2
1,y x,y
C
B
Fig.25 Tray details.
For dimensions, see Table 17.
Table 17 Tray dimensions (see Fig.25)
SYMBOL DESCRIPTION VALUE
A pocket pitch, in x direction 5.59 mm
B pocket pitch, in y direction 6.35 mm
C pocket width, in x direction 3.16 mm
D pocket width, in y direction 3.16 mm
E tray width, in x direction 50.8 mm
F tray width, in y direction 50.8 mm
G cut corner to pocket 1,1 centre 5.83 mm
H cut corner to pocket 1,1 centre 6.35 mm
x number of pockets in x direction 8
y number of pockets in y direction 7
handbook, halfpage
MDB080
PC8576DU
Fig.26 Tray alignment.
The orientation of the IC in a pocket is indicated by the
position of the IC type name on the die surface with
respecttothechamferontheupperleftcornerofthetray.
2004 Dec 22 35
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
15 PACKAGE OUTLINES
UNIT A
max. A
1
A
2
A
3
b
p
cE
(1)
eH
E
LL
p
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.2 0.15
0.05 1.05
0.95 0.25 0.27
0.17 0.18
0.12 10.1
9.9 0.5 12.15
11.85 1.45
1.05 7
0
o
o
0.08 0.11 0.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT357-1 137E10 MS-026 00-01-19
02-03-14
D
(1) (1)(1)
10.1
9.9
H
D
12.15
11.85
E
Z
1.45
1.05
D
b
p
e
θ
EA
1
A
L
p
detail X
L
(A )
3
B
16
c
D
H
b
p
E
HA
2
v
M
B
D
ZD
A
ZE
e
v
M
A
X
1
64
49
48 33
32
17
y
pin 1 index
w
M
w
M
0 2.5 5 mm
scale
TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm SOT357-1
2004 Dec 22 36
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(2)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT364-1 99-12-27
03-02-19
w
M
θ
A
A
1
A
2
D
L
p
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
128
56 29
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 14.1
13.9 6.2
6.0 0.5 1
8.3
7.9 0.50
0.35 0.5
0.1
0.080.25
0.8
0.4
p
Ev
M
A
A
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
2004 Dec 22 37
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
16 SOLDERING
16.1 Introduction to soldering surface mount
packages
Thistextgivesaverybriefinsighttoacomplextechnology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certainsurfacemountICs,butit is notsuitableforfinepitch
SMDs. In these situations reflow soldering is
recommended.
16.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuit board by screenprinting,stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 seconds and 200 seconds
depending on heating method.
Typical reflow peak temperatures range from
215 °C to 270 °Cdepending onsolder paste material. The
top-surface temperature of the packages should
preferably be kept:
•below 225 °C (SnPb process) or below 245 °C (Pb-free
process)
– for all BGA, HTSSON..T and SSOP..T packages
– for packages with a thickness ≥2.5 mm
– for packages with a thickness < 2.5 mm and a
volume ≥350 mm3 so called thick/large packages.
•below 240 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
16.3 Wave soldering
Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackageswithleadsonfour sides, thefootprintmust
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250 °C or 265 °C, depending
on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
16.4 Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 seconds to 5 seconds
between 270 °C and 320 °C.
2004 Dec 22 38
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
16.5 Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. Formoredetailedinformation on the BGA packagesrefertothe
“(LF)BGAApplicationNote”
(AN01026);orderacopy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C±10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.
9. Hot bar soldering or manual soldering is suitable for PMFP packages.
PACKAGE(1) SOLDERING METHOD
WAVE REFLOW(2)
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA,
VFBGA, XSON not suitable suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable(4) suitable
PLCC(5), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(5)(6) suitable
SSOP, TSSOP, VSO, VSSOP not recommended(7) suitable
CWQCCN..L(8), PMFP(9), WQCCN..L(8) not suitable not suitable
2004 Dec 22 39
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
17 DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
18 DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseoratanyotherconditionsabovethosegiveninthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuchapplicationswillbe
suitable for the specified use without further testing or
modification.
19 DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusing orsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no license or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
2004 Dec 22 40
Philips Semiconductors Product specification
Universal LCD driver for low
multiplex rates PCF8576D
Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for
a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be
separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips
Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die.
Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems
after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify
their application in which the die is used.
20 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
© Koninklijke Philips Electronics N.V. 2004 SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a worldwide compan y
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands R15/05/pp41 Date of release: 2004 Dec 22 Document order number: 9397 750 14492
