150 mA, Low Dropout,
CMOS Linear Regulator
ADP1710/ADP1711
Rev. 0
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Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
Maximum output current: 150 mA
Input voltage range: 2.5 V to 5.5 V
Light load efficient
IGND = 35 μA with zero load
IGND = 40 μA with 100 μA load
Low shutdown current: <1 μA
Low dropout voltage: 150 mV @ 150 mA load
Initial accuracy: ±1%
Accuracy over line, load, and temperature: ±2%
Stable with small 1μF ceramic output capacitor
16 fixed output voltage options: 0.75 V to 3.3 V (ADP1710)
Adjustable output voltage option: 0.8 V to 5.0 V
(ADP1710 Adjustable)
16 fixed output voltage options with reference bypass:
0.75 V to 3.3 V (ADP1711)
High PSRR: 69 dB @ 1 kHz
Low noise: 40 μVRMS
Excellent load/line transient response
Current limit and thermal overload protection
Logic controlled enable
5-lead TSOT package
APPLICATIONS
Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
Post dc-dc regulation
TYPICAL APPLICATION CIRCUITS
IN
GND
EN
OUT
NC
1
2
3
5
4
ADP1710
NC = NO CO NNECT
1µF 1µF
V
IN
= 5V V
OUT
= 3.3V
06310-001
Figure 1. ADP1710 with Fixed Output Voltage, 3.3 V
IN
GND
EN
OUT
ADJ
1
2
3
5
4
A
DP1710
ADJUSTABLE
1µF 1µF
V
IN
= 5.5V
R1
R2
V
OUT
= 0.8V(1 + R1/R2)
06310-002
Figure 2. ADP1710 with Adjustable Output Voltage, 0.8 V to 5.0 V
IN
GND
EN
OUT
BYP
1
2
3
5
4
ADP1711
1µF 1µF
10nF
V
IN = 5V VOUT = 3.3V
0
6310-003
Figure 3. ADP1711 with Fixed Output Voltage and Bypass Capacitor, 3.3 V
GENERAL DESCRIPTION
The ADP1710/ADP1711 are low dropout linear regulators
that operate from 2.5 V to 5.5 V and provide up to 150 mA of
output current. Utilizing a novel scaling architecture, ground
current drawn is a very low 40 μA, when driving a 100 μA
load, making the ADP1710/ADP1711 ideal for battery-
operated portable equipment.
The ADP1710 and the ADP1711 are each available in sixteen
fixed output voltage options. The ADP1710 is also available in
an adjustable version, which allows output voltages that range
from 0.8 V to 5 V via an external divider. The ADP1711 allows
for a reference bypass capacitor to be connected, which reduces
output voltage noise and improves power supply rejection.
The ADP1710/ADP1711 are optimized for stable operation with
small 1 μF ceramic output capacitors, allowing for good transient
performance while occupying minimal board space. An enable
pin controls the output voltage on both devices. There is also an
under-voltage lockout circuit on both devices, which disables the
regulator if IN drops below a minimum threshold.
An internal soft start gives a typical start-up time of 80 μs.
Short-circuit protection and thermal overload protection
circuits prevent damage to the devices in adverse conditions.
Both the ADP1710 and the ADP1711 are available in tiny
5lead TSOT packages, for the smallest footprint solution to all
your power needs.
ADP1710/ADP1711
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Typical Application Circuits............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ........................................................................ 8
Adjustable Output Voltage (ADP1710 Adjustable) ................. 8
Bypass Capacitor (ADP1711) ..................................................... 8
Enable Feature ...............................................................................8
Undervoltage Lockout (UVLO) ..................................................9
Application Information................................................................ 10
Capacitor Selection .................................................................... 10
Current Limit and Thermal Overload Protection ................. 10
Thermal Considerations............................................................ 11
Printed Circuit Board Layout Considerations ....................... 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 14
REVISION HISTORY
10/06—Revision 0: Initial Version
ADP1710/ADP1711
Rev. 0 | Page 3 of 16
SPECIFICATIONS
VIN = (VOUT + 0.5 V) or 2.5 V (whichever is greater), IOUT = 1 mA, CIN = COUT = 1 μF, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT VOLTAGE RANGE VIN TJ = –40°C to +125°C 2.5 5.5 V
OPERATING SUPPLY CURRENT IGND IOUT = 0 μA 35 μA
I
OUT = 0 μA, TJ = –40°C to +125°C 50 μA
I
OUT = 100 μA 40 μA
I
OUT = 100 μA, TJ = –40°C to +125°C 80 μA
I
OUT = 100 mA 665 μA
I
OUT = 100 mA, TJ = –40°C to +125°C 860 μA
I
OUT = 150 mA 1 mA
I
OUT = 150 mA, TJ = –40°C to +125°C 1.3 mA
SHUTDOWN CURRENT IGND-SD EN = GND 0.1 μA
EN = GND, TJ = –40°C to +125°C 1.0 μA
FIXED OUTPUT VOLTAGE ACCURACY VOUT IOUT = 1 mA –1 +1 %
(ADP1710 AND ADP1711) 100 μA < IOUT < 150 mA, TJ = –40°C to +125°C –2 +2 %
ADJUSTABLE OUTPUT VOLTAGE VOUT IOUT = 1 mA 0.792 0.8 0.808 V
ACCURACY (ADP1710 ADJUSTABLE)1 100 μA < IOUT < 150 mA, TJ = –40°C to +125°C 0.784 0.816 V
LINE REGULATION ∆VOUT/∆VIN VIN = (VOUT + 0.5 V) to 5.5 V, TJ = –40°C to +125°C –0.1 +0.1 %/ V
LOAD REGULATION2∆VOUT/∆IOUT IOUT = 10 mA to 150 mA 0.002 %/mA
I
OUT = 10 mA to 150 mA, TJ = –40°C to +125°C 0.004 %/mA
DROPOUT VOLTAGE3VDROPOUT IOUT = 100 mA, VOUT ≥ 3.0 V 100 mV
I
OUT = 100 mA, VOUT ≥ 3.0 V, TJ = –40°C to +125°C 175 mV
I
OUT = 150 mA, VOUT ≥ 3.0 V 150 mV
I
OUT = 150 mA, VOUT ≥ 3.0 V, TJ = –40°C to +125°C 250 mV
I
OUT = 100 mA, 2.5 V ≤ VOUT < 3.0 V 120 mV
I
OUT = 100 mA, 2.5 V ≤ VOUT < 3.0 V, TJ = –40°C to +125°C 200 mV
I
OUT = 150 mA, 2.5 V ≤ VOUT < 3.0 V 180 mV
I
OUT = 150 mA, 2.5 V ≤ VOUT < 3.0 V, TJ = –40°C to +125°C 300 mV
START-UP TIME4TSTART-UP
ADP1710 80 μs
ADP1711 With 10 nF bypass capacitor 100 μs
CURRENT LIMIT THRESHOLD5ILIMIT 180 270 360 mA
THERMAL SHUTDOWN THRESHOLD TSSD TJ rising 150 °C
THERMAL SHUTDOWN HYSTERESIS TSSD-HYS 15
°C
UVLO ACTIVE THRESHOLD UVLOACTIVE VIN falling 1.95 V
UVLO INACTIVE THRESHOLD UVLOINACTIVE VIN rising 2.45 V
UVLO HYSTERESIS UVLOHYS 250 mV
EN INPUT LOGIC HIGH VIH 2.5 V ≤ VIN ≤ 5.5 V 1.8 V
EN INPUT LOGIC LOW VIL 2.5 V ≤ VIN ≤ 5.5 V 0.4 V
EN INPUT LEAKAGE CURRENT VI-LEAKAGE EN = IN or GND 0.1 1 μA
ADJ INPUT BIAS CURRENT
(ADP1710 ADJUSTABLE) ADJI-BIAS 30 100 nA
OUTPUT NOISE OUTNOISE
ADP1710 10 Hz to 100 kHz, VOUT = 3.3 V 330 μVrms
ADP1711 10 Hz to 100 kHz, VOUT = 0.75 V, with 10 nF bypass capacitor 40 μVrms
POWER SUPPLY REJECTION RATIO PSRR
ADP1710 1 kHz, VOUT = 3.3 V 58 dB
ADP1711 1 kHz, VOUT = 0.75 V, with 10 nF bypass capacitor 69 dB
1 Accuracy when OUT is connected directly to ADJ. When OUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances
of resistors used.
2 Based on an end-point calculation using 10 mA and 150 mA loads. See Figure 8 for typical load regulation performance for loads less than 10 mA.
3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.5 V.
4 Start-up time is defined as the time between the rising edge of EN to OUT being at 90% of its nominal value.
5 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.
ADP1710/ADP1711
Rev. 0 | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
IN to GND –0.3 V to +6 V
OUT to GND –0.3 V to IN
EN to GND –0.3 V to +6 V
ADJ/BYP to GND –0.3 V to +6 V
Storage Temperature Range –65°C to +150°C
Operating Junction Temperature Range –40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA Unit
5-Lead TSOT 170 °C/W
ESD CAUTION
ADP1710/ADP1711
Rev. 0 | Page 5 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN
G
ND
EN
OUT
NC
1
2
3
5
4
NC = NO CONNECT
ADP1710
FIXED
TOP VIEW
(Not to Scale)
06310-004
IN
G
ND
EN
OUT
ADJ
1
2
3
5
4
ADP1710
ADJUSTABLE
TOP VIEW
(No t to Scale)
06310-005
IN
GND
EN
OUT
BYP
1
2
3
5
4
ADP1711
TO P VI EW
(No t to S cal e)
06310-006
Figure 4. 5-Lead TSOT (UJ-Suffix) Figure 5. 5-Lead TSOT (UJ-Suffix) Figure 6. 5-Lead TSOT (UJ-Suffix)
Table 4. Pin Function Descriptions
ADP1710
Fixed
Pin No.
ADP1710
Adjustable
Pin No.
ADP1711
Pin No. Mnemonic Description
1 1 1 IN Regulator Input Supply. Bypass IN to GND with a 1 μF or greater capacitor.
2 2 2 GND Ground.
3 3 3 EN Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the
regulator. For automatic startup, connect EN to IN.
4 NC No Connect.
4 ADJ Adjust. A resistor divider from OUT to ADJ sets the output voltage.
4 BYP
Connect a 1 nF or greater capacitor (10 nF is recommended) between BYP and GND
to reduce the internal reference noise for low noise applications.
5 5 5 OUT Regulated Output Voltage. Bypass OUT to GND with a 1 μF or greater capacitor.
ADP1710/ADP1711
Rev. 0 | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.8 V, IOUT = 1 mA, CIN = COUT = 1 μF, TA = 25°C, unless otherwise noted.
3.34
3.23 –40
TJ (°C)
VOUT (V)
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
3.24
–5 25 85 125
I
LOAD
= 150mA
I
LOAD
= 100mA
I
LOAD
= 50mA
I
LOAD
= 100µ A
I
LOAD
= 1mA
I
LOAD
= 10mA
06310-007
Figure 7. Output Voltage vs. Junction Temperature
3.32
3.26
0.1 1000
I
LOAD
(mA)
VOUT (V)
1 10 100
3.31
3.30
3.29
3.28
3.27
06310-008
Figure 8. Output Voltage vs. Load Current
3.32
3.26
3.3 3.8 4.3 4.8 5.3
V
IN
(V)
V
OUT
(V)
3.31
3.30
3.29
3.28
3.27
I
LOAD
= 150mA
I
LOAD
= 100mA
I
LOAD
= 50mA
I
LOAD
= 10mAI
LOAD
= 1mAI
LOAD
= 100µA
06310-009
Figure 9. Output Voltage vs. Input Voltage
1100
0–40
T
J
(°C)
I
GND
(µA)
1000
900
800
700
600
500
400
300
200
100
–5 25 85 125
I
LOAD
= 100µ A
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
06310-010
Figure 10. Ground Current vs. Junction Temperature
1100
0
0.1
I
LOAD
(mA)
I
GND
(µA)
1000
900
800
700
600
500
400
300
200
100
1000
110100
06310-011
Figure 11. Ground Current vs. Load Current
1500
0
3.3 3.8 4.3 4.8 5.3
V
IN
(V)
I
GND
(µA)
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
I
LOAD
= 150mA
I
LOAD
= 100mA
I
LOAD
= 50mA
I
LOAD
= 10mA I
LOAD
= 1mA I
LOAD
= 100µ A
06310-012
Figure 12. Ground Current vs. Input Voltage
ADP1710/ADP1711
Rev. 0 | Page 7 of 16
180
0
0.1 1000
I
LOAD
(mA)
V
DROPOUT
(mV)
1 10 100
160
140
120
100
80
60
40
20
06310-013
Figure 13. Dropout Voltage vs. Load Current
3.35
2.95
3.2 3.6
V
IN
(V)
V
OUT
(V)
3.30
3.25
3.20
3.15
3.10
3.05
3.00
3.3 3.4 3.5
I
LOAD
= 100µ A
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
06310-014
Figure 14. Output Voltage vs. Input Voltage (in Dropout)
7
0
3.20 3.60
V
IN
(V)
I
GND
(mA)
6
5
4
3
2
1
3.25 3.30 3.35 3.40 3.45 3.50 3.55
I
LOAD
=
100µA
I
LOAD
=
1mA
I
LOAD
=
10mA
I
LOAD
= 150mA
I
LOAD
= 100mA
I
LOAD
=
50mA
06310-015
Figure 15. Ground Current vs. Input Voltage (In Dropout)
0
10 10M
FREQUENCY (Hz)
PSRR (d B)
100 1k 10k 100k 1M
–10
–20
–30
–40
–50
–60
–70
–80
–90
V
RIPPLE
= 50mV
V
IN
= 5V
V
OUT
= 0. 75V
C
OUT
= 1µF
I
LOAD
= 50mA
I
LOAD
=
10mA
I
LOAD
= 100µ A
06310-016
Figure 16. ADP1711 Power Supply Rejection Ratio vs. Frequency
(10 nF Bypass Capacitor)
0
10 10M
FREQUENCY (Hz)
PSRR (dB)
100 1k 10k 100k 1M
–10
–20
–30
–40
–50
–60
–70
–80
–90
V
RIPPLE
= 50mV
V
IN
= 5V
V
OUT
= 3. 3V
C
OUT
= 1µF
I
LOAD
= 100µ A
I
LOAD
= 50mA
I
LOAD
= 10mA
06310-017
Figure 17. ADP1710 Power Supply Rejection Ratio vs. Frequency
ADP1710/ADP1711
Rev. 0 | Page 8 of 16
THEORY OF OPERATION
The ADP1710/ADP1711 are low dropout, CMOS linear
regulators that use an advanced, proprietary architecture to
provide high power supply rejection ratio (PSRR) and excellent
line and load transient response with just a small 1 μF ceramic
output capacitor. Both devices operate from a 2.5 V to 5.5 V
input rail and provide up to 150 mA of output current.
Incorporating a novel scaling architecture, ground current is
very low when driving light loads. Ground current in shutdown
mode is typically 100 nA.
REFERENCE
CURRENT L IMI T
THERMAL PROTECT
SHUTDOWN
AND UVLO
GND
OUT
NC/
A
DJ/
BYP
NC = NO CONNECT
IN
EN
06310-018
+
Figure 18. Internal Block Diagram
Internally, the ADP1710/ADP1711 each consist of a reference,
an error amplifier, a feedback voltage divider, and a PMOS pass
transistor. Output current is delivered via the PMOS pass
device, which is controlled by the error amplifier. The error
amplifier compares the reference voltage with the feedback
voltage from the output and amplifies the difference. If the
feedback voltage is lower than the reference voltage, the gate of
the PMOS device is pulled lower, allowing more current to pass
and increasing the output voltage. If the feedback voltage is
higher than the reference voltage, the gate of the PMOS device
is pulled higher, allowing less current to pass and decreasing the
output voltage.
The ADP1710 is available in two versions, one with fixed output
voltage options and one with an adjustable output voltage. The
fixed output voltage option is set internally to one of sixteen
values between 0.75 V and 3.3 V, using an internal feedback
network. The adjustable output voltage can be set to between 0.8
V and 5.0 V by an external voltage divider connected from OUT
to ADJ. The ADP1711 is available with fixed output voltage
options and features a bypass pin, which allows an external
capacitor to be connected, which reduces internal reference
noise. All devices are controlled by an enable pin (EN).
ADJUSTABLE OUTPUT VOLTAGE
(ADP1710 ADJUSTABLE)
The ADP1710 adjustable version can have its output voltage
set over a 0.8 V to 5.0 V range. The output voltage is set by
connecting a resistive voltage divider from OUT to ADJ. The
output voltage is calculated using the equation
VOUT = 0.8 V (1 + R1/R2) (1)
where:
R1 is the resistor from OUT to ADJ.
R2 is the resistor from ADJ to GND.
The maximum bias current into ADJ is 100 nA, so for less
than 0.5% error due to the bias current, use values less than
60 kΩ for R2.
BYPASS CAPACITOR (ADP1711)
The ADP1711 allows for an external bypass capacitor to be
connected to the internal reference, which reduces output
voltage noise and improves power supply rejection. A low
leakage capacitor of 1 nF or greater (10 nF is recommended)
must be connected between the BYP and GND pins.
ENABLE FEATURE
The ADP1710/ADP1711 use the EN pin to enable and disable
the OUT pin under normal operating conditions. As shown in
Figure 19, when a rising voltage on EN crosses the active
threshold, OUT turns on. When a falling voltage on EN crosses
the inactive threshold, OUT turns off.
2
EN
OUT V
IN
= 5V
V
OUT
= 1. 6V
C
IN
= 1µF
C
OUT
= 1µF
I
LOAD
= 10mA
TIME (1ms/DIV)
CH1, CH2 (5 00mV /DIV )
06310-019
Figure 19. ADP1710 Adjustable Typical EN Pin Operation
ADP1710/ADP1711
Rev. 0 | Page 9 of 16
As can be seen, the EN pin has hysteresis built in. This prevents
on/off oscillations that can occur due to noise on the EN pin as
it passes through the threshold points.
The EN pin active/inactive thresholds are derived from the IN
voltage. Therefore, these thresholds vary with changing input
voltage. Figure 20 shows typical EN active/inactive thresholds
when the input voltage varies from 2.5 V to 5.5 V.
1.4
0.5
2.50 5.50
V
IN
(V)
TYP ICAL E N THRESHOL DS ( V )
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
EN INACT IVE
EN ACTIVE
HYSTERESIS
06310-020
Figure 20. Typical EN Pin Thresholds vs. Input Voltage
UNDERVOLTAGE LOCKOUT (UVLO)
The ADP1710/ADP1711 have an undervoltage lockout circuit,
which monitors the voltage on the IN pin. When the voltage on
IN drops below 1.95 V (minimum), the circuit activates, disabling
the OUT pin.
ADP1710/ADP1711
Rev. 0 | Page 10 of 16
APPLICATION INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP1710/ADP1711 are designed for operation with small,
space-saving ceramic capacitors, but they will function with most
commonly used capacitors as long as care is taken about the
effective series resistance (ESR) value. The ESR of the output
capacitor affects stability of the LDO control loop. A minimum of
1 μF capacitance with an ESR of 500 mΩ or less is recommended
to ensure stability of the ADP1710/ADP1711. Transient response
to changes in load current is also affected by output capacitance.
Using a larger value of output capacitance improves the transient
response of the ADP1710/ADP1711 to large changes in load
current. Figure 21 and Figure 22 show the transient responses for
output capacitance values of 1 μF and 22 μF, respectively.
VIN = 5V
VOUT = 3.3V
CIN = 1µF
COUT = 1µF
TIME (4µs/DIV)
1
10mV/DI
V
VOUT RESPONSE TO LOAD STEP
FROM 7. 5 mA TO 14 2.5mA
06310-021
Figure 21. Output Transient Response, COUT = 1 μF
VIN = 5V
VOUT = 3.3V
CIN = 22µF
COUT = 22µF
TIME (4µs/DIV)
1
10mV/DI
V
VOUT RESPONSE TO LOAD STEP
FROM 7. 5 mA TO 14 2.5mA
06310-022
Figure 22. Output Transient Response, COUT = 22 μF
Input Bypass Capacitor
Connecting a 1 μF capacitor from IN to GND reduces the
circuit sensitivity to printed circuit board (PCB) layout,
especially when long input traces or high source impedance are
encountered. If greater than 1 μF of output capacitance is
required, the input capacitor should be increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADP1710/ADP1711, as long as they meet the minimum
capacitance and maximum ESR requirements. Ceramic
capacitors are manufactured with a variety of dielectrics, each
with different behavior over temperature and applied voltage.
Capacitors must have a dielectric adequate to ensure the
minimum capacitance over the necessary temperature range
and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended. Y5V and Z5U
dielectrics are not recommended, due to their poor temperature
and dc bias characteristics.
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP1710/ADP1711 are protected against damage due to
excessive power dissipation by current and thermal overload
protection circuits. The ADP1710/ADP1711 are designed to
current limit when the output load reaches 270 mA (typical).
When the output load exceeds 270 mA, the output voltage is
reduced to maintain a constant current limit.
Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation) when the junction temperature starts to rise
above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
135°C, the output is turned on again and output current is
restored to its nominal value.
Consider the case where a hard short from OUT to ground
occurs. At first the ADP1710/ADP1711 current limits, so that
only 270 mA is conducted into the short. If self heating of the
junction is great enough to cause its temperature to rise above
150°C, thermal shutdown activates, turning off the output and
reducing the output current to zero. As the junction
temperature cools and drops below 135°C, the output turns on
and conducts 270 mA into the short, again causing the
junction temperature to rise above 150°C. This thermal
oscillation between 135°C and 150°C causes a current
oscillation between 270 mA and 0 mA, which continues as
long as the short remains at the output.
ADP1710/ADP1711
Rev. 0 | Page 11 of 16
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation must be externally limited
so junction temperatures do not exceed 125°C.
THERMAL CONSIDERATIONS
To guarantee reliable operation, the junction temperature of the
ADP1710/ADP1711 must not exceed 125°C. To ensure the
junction temperature stays below this maximum value, the user
needs to be aware of the parameters that contribute to junction
temperature changes. These parameters include ambient
temperature, power dissipation in the power device, and thermal
resistances between the junction and ambient air (θJA). The θJA
number is dependent on the package assembly compounds used
and the amount of copper to which the GND pins of the package
are soldered on the PCB. Table 5 shows typical θJA values of the
5lead TSOT package for various PCB copper sizes.
Table 5.
Copper Size (mm2) θJA (°C/W)
01 170
50 152
100 146
300 134
500 131
1 Device soldered to minimum size pin traces.
The junction temperature of the ADP1710/ADP1711 can be
calculated from the following equation:
TJ = TA + (PD × θJA) (2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN – VOUT) × ILOAD] + (VIN × IGND) (3)
where:
ILOAD is the load current.
IGND is the ground current.
VIN and VOUT are the input voltage and output voltage,
respectively.
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation
simplifies to the following:
TJ = TA + {[(VIN – VOUT) × ILOAD] × θJA} (4)
As shown in Equation 4, for a given ambient temperature, input
to output voltage differential, and continuous load current,
there exists a minimum copper size requirement for the PCB to
ensure the junction temperature does not rise above 125°C. The
following figures show junction temperature calculations for
different ambient temperatures, load currents, VIN to VOUT
differentials, and areas of PCB copper.
140
0
0.5 5.0
V
IN
– V
OUT
(V)
T
J
(°C)
120
100
80
60
40
20
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
1mA
10mA 30mA
80mA 100mA
125mA 150mA
(LOAD CURRENT)
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
06310-023
Figure 23. 500 mm2 of PCB Copper, TA = 25°C
140
0
0.5 5.0
V
IN
– V
OUT
(V)
T
J
(°C)
120
100
80
60
40
20
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
1mA
10mA 30mA
80mA 100mA
125mA 150mA
(LOAD CURRENT)
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
06310-024
Figure 24. 100 mm2 of PCB Copper, TA = 25°C
140
0
0.5 5.0
V
IN
– V
OUT
(V)
T
J
(°C)
120
100
80
60
40
20
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
1mA
10mA 30mA
80mA 100mA
125mA 150mA
(LOAD CURRENT)
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
06310-025
Figure 25. 0 mm2 of PCB Copper, TA = 25°C
ADP1710/ADP1711
Rev. 0 | Page 12 of 16
140
0
0.5 5.0
V
IN
– V
OUT
(V)
T
J
(°C)
120
100
80
60
40
20
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
1mA
10mA 30mA
80mA 100mA
125mA 150mA
(LOAD CURRENT )
MAX T
J
(DO NOT OPERATE ABOVE THIS POINT)
06310-026
Figure 26. 500 mm2 of PCB Copper, TA = 50°C
140
0
0.5 5.0
V
IN
– V
OUT
(V)
T
J
(°C)
120
100
80
60
40
20
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
1mA
10mA 30mA
80mA 100mA
125mA 150mA
(LOAD CURRENT )
MAX T
J
(DO NOT OPERATE ABOVE THIS POINT)
06310-027
Figure 27. 100 mm2 of PCB Copper, TA = 50°C
140
0
0.5 5.0
V
IN
– V
OUT
(V)
T
J
(°C)
120
100
80
60
40
20
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
1mA
10mA 30mA
80mA 100mA
125mA 150mA
(LOAD CURRENT )
MAX T
J
(DO NOT OPERATE ABOVE THIS POINT)
06310-028
Figure 28. 0 mm2 of PCB Copper, TA = 50°C
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP1710/
ADP1711. However, as can be seen from Table 5, a point of
diminishing returns eventually is reached, beyond which an
increase in the copper size does not yield significant heat
dissipation benefits.
Place the input capacitor as close as possible to the IN and GND
pins. Place the output capacitor as close as possible to the OUT
and GND pins. For ADP1711, place the internal reference
bypass capacitor as close as possible to the BYP pin. Use of 0402
or 0603 size capacitors and resistors achieves the smallest
possible footprint solution on boards where area is limited.
GND (BOTTOM)
GND (TOP)
ADP1710/
ADP1711
IN
EN
R2
R1
C3
OUT
C2C1
06310-029
Figure 29. Example PCB Layout
ADP1710/ADP1711
Rev. 0 | Page 13 of 16
OUTLINE DIMENSIONS
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
PIN 1
1.60 BSC 2.80 BSC
1.90
BSC
0.95 BSC
0.20
0.08
0.60
0.45
0.30
8°
4°
0°
0.50
0.30
0.10 MAX SEATING
PLANE
*1.00 MAX
*0.90
0.87
0.84
2.90 BS C
54
123
Figure 30. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions show in millimeters
ADP1710/ADP1711
Rev. 0 | Page 14 of 16
ORDERING GUIDE
Model
Temperature
Range
Output
Voltage (V)
Package
Description
Package
Option Branding
ADP1710AUJZ-0.75R71–40°C to +125°C 0.75 5-Lead TSOT UJ-5 L4S
ADP1710AUJZ-0.8-R71–40°C to +125°C 0.80 5-Lead TSOT UJ-5 L0D
ADP1710AUJZ-0.85R71–40°C to +125°C 0.85 5-Lead TSOT UJ-5 L40
ADP1710AUJZ-0.9-R71–40°C to +125°C 0.90 5-Lead TSOT UJ-5 L41
ADP1710AUJZ-0.95R71–40°C to +125°C 0.95 5-Lead TSOT UJ-5 L42
ADP1710AUJZ-1.0-R71–40°C to +125°C 1.00 5-Lead TSOT UJ-5 L0E
ADP1710AUJZ-1.05R71–40°C to +125°C 1.05 5-Lead TSOT UJ-5 L43
ADP1710AUJZ-1.10R71–40°C to +125°C 1.10 5-Lead TSOT UJ-5 L47
ADP1710AUJZ-1.15R71–40°C to +125°C 1.15 5-Lead TSOT UJ-5 L44
ADP1710AUJZ-1.2-R71–40°C to +125°C 1.20 5-Lead TSOT UJ-5 L45
ADP1710AUJZ-1.3-R71–40°C to +125°C 1.30 5-Lead TSOT UJ-5 L46
ADP1710AUJZ-1.5-R71–40°C to +125°C 1.50 5-Lead TSOT UJ-5 L0F
ADP1710AUJZ-1.8-R71–40°C to +125°C 1.80 5-Lead TSOT UJ-5 L0G
ADP1710AUJZ-2.5-R71–40°C to +125°C 2.50 5-Lead TSOT UJ-5 L0H
ADP1710AUJZ-3.0-R71–40°C to +125°C 3.00 5-Lead TSOT UJ-5 L0J
ADP1710AUJZ-3.3-R71–40°C to +125°C 3.30 5-Lead TSOT UJ-5 L0K
ADP1710AUJZ-R71–40°C to +125°C 0.8 to 5.0 5-Lead TSOT UJ-5 L0L
ADP1711AUJZ-0.75R71–40°C to +125°C 0.75 5-Lead TSOT UJ-5 L4T
ADP1711AUJZ-0.8-R71–40°C to +125°C 0.80 5-Lead TSOT UJ-5 L0M
ADP1711AUJZ-0.85R71–40°C to +125°C 0.85 5-Lead TSOT UJ-5 L48
ADP1711AUJZ-0.9-R71–40°C to +125°C 0.90 5-Lead TSOT UJ-5 L49
ADP1711AUJZ-0.95R71–40°C to +125°C 0.95 5-Lead TSOT UJ-5 L4A
ADP1711AUJZ-1.0-R71–40°C to +125°C 1.00 5-Lead TSOT UJ-5 L0N
ADP1711AUJZ-1.05R71–40°C to +125°C 1.05 5-Lead TSOT UJ-5 L4C
ADP1711AUJZ-1.10R71–40°C to +125°C 1.10 5-Lead TSOT UJ-5 L4G
ADP1711AUJZ-1.15R71–40°C to +125°C 1.15 5-Lead TSOT UJ-5 L4D
ADP1711AUJZ-1.2-R71–40°C to +125°C 1.20 5-Lead TSOT UJ-5 L4E
ADP1711AUJZ-1.3-R71–40°C to +125°C 1.30 5-Lead TSOT UJ-5 L4F
ADP1711AUJZ-1.5-R71–40°C to +125°C 1.50 5-Lead TSOT UJ-5 L0P
ADP1711AUJZ-1.8-R71–40°C to +125°C 1.80 5-Lead TSOT UJ-5 L0Q
ADP1711AUJZ-2.5-R71–40°C to +125°C 2.50 5-Lead TSOT UJ-5 L0R
ADP1711AUJZ-3.0-R71–40°C to +125°C 3.00 5-Lead TSOT UJ-5 L0S
ADP1711AUJZ-3.3-R71–40°C to +125°C 3.30 5-Lead TSOT UJ-5 L0U
1 Z = Pb-free part.
ADP1710/ADP1711
Rev. 0 | Page 15 of 16
NOTES
ADP1710/ADP1711
Rev. 0 | Page 16 of 16
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06310-0-10/06(0)
NOTES
