NCV1060, NCV1063 Automotive High-Voltage Switcher for Low Power Offline SMPS The NCV106X products integrate a fixed frequency current mode controller with a 670 V MOSFET. Available in a SOIC-10 or SOIC-16 package, the NCV106X offer a high level of integration, including soft-start, frequency-jittering, short-circuit protection, skip-cycle, adjustable peak current set point, ramp compensation, and a Dynamic Self-Supply (eliminating the need for an auxiliary winding). Unlike other monolithic solutions, the NCV106X is quiet by nature: during nominal load operation, the part switches at one of the available frequencies (60 kHz or 100 kHz). When the output power demand diminishes, the IC automatically enters frequency foldback mode and provides excellent efficiency at light loads. When the power demand reduces further, it enters into a skip mode to reduce the standby consumption down to a no load condition. Protection features include: a timer to detect an overload or a short-circuit event, Overvoltage Protection with auto-recovery and AC input line voltage detection (A version). The ON proprietary integrated Over Power Protection (OPP) lets you harness the maximum delivered power without affecting your standby performance simply via external resistors. For improved standby performance, the connection of an auxiliary winding stops the DSS operation and helps to reduce input power consumption below 50 mW at high line. NCV106x can be seamlessly used both in non-isolated and in isolated topologies. www.onsemi.com MARKING DIAGRAMS 16 1 10 1 * * * (c) Semiconductor Components Industries, LLC, 2018 May, 2018 - Rev. 0 1 SOIC-10 CASE 751BQ AD or BD SUFFIX 1 V1060fyyy ALYWX G x = Power Switch Circuit On-state Resistance (0 = 34 W, 3 = 11.4 W) f = Brown In (A = Yes, B = No) yyy = Oscillator Frequency (060 = 60 kHz, 100 = 100 kHz) A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb-Free Package * Built-in 670 V MOSFET with RDS(on) of 34 W (NCV1060) and * * * * * * * * * * NCV1063fyyyG AWLYWW 10 Features 11.4 W (NCV1063) Large Creepage Distance Between High-voltage Pins Current-Mode Fixed Frequency Operation - 60 kHz or 100 kHz Adjustable Peak Current: see below table Fixed Ramp Compensation Direct Feedback Connection for Non-isolated Converter Internal and Adjustable Over Power Protection (OPP) Circuit Skip-Cycle Operation at Low Peak Currents Only Dynamic Self-Supply: No Need for an Auxiliary Winding Internal 4 ms Soft-Start Auto-Recovery Output Short Circuit Protection with Timer-Based Detection Auto-Recovery Overvoltage Protection with Auxiliary Winding Operation Frequency Jittering for Better EMI Signature No Load Input Consumption < 50 mW 16 SOIC-16 CASE 751B-05 D SUFFIX 1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 28 of this data sheet. * Frequency Foldback to Improve Efficiency * * at Light Load NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable These Devices are Pb-Free and are RoHS Compliant Typical Applications * Auxiliary & Standby Isolated Power Supplies for HEV/EV Publication Order Number: NCV1060/D NCV1060, NCV1063 Table 1. PRODUCT INFORMATION & INDICATIVE MAXIMUM OUTPUT POWER 230 Vac + 15% 85 - 265 Vac Product RDS(on) IIPK(0) Adapter Open Frame Adapter Open Frame NCV1060 60 kHz 34 W 300 mA 2.9 W 7.2 W 1.7 W 4.1 W NCV1063 100 kHz 11.4 W 780 mA 6.9 W 17.1 W 3.7 W 8.6 W NOTE: Informative values only, with Tamb = 25C, Tcase = 100C, SOIC-10 package for NCV1060 and SOIC-16 package for NCV1063, Self supply via Auxiliary winding and circuit mounted on minimum copper area as recommended. GND DRAIN DRAIN GND GND GND VCC LIM/OPP DRAIN DRAIN N.C. N.C. N.C. N.C. FB COMP GND VCC LIM/OPP FB COMP DRAIN DRAIN DRAIN DRAIN DRAIN SOIC-10 SOIC-16 Figure 1. Pin Connections Table 2. PIN FUNCTION DESCRIPTION Pin No SOIC 10 SOIC 16 Pin Name Function 1 1-4 GND The IC Ground 2 5 VCC Powers the Internal Circuitry This pin is connected to an external capacitor. The VDD includes an auto-recovery over voltage protection 3 6 LIM/OPP Ipeak Set / Over Power Limitation The current drown from the pin decreases Ipeak of the primary winding. If resistive divider from the auxiliary winding is connected to this pin it sets the OPP compensation level (it diminishes the peak current.) 4 7 FB Feedback Signal Input This is the inverting input of the trans conductance error amplifier. It is normally connected to the switching power supply output through a resistor divider 5 8 Comp Compensation The error amplifier output is available on this pin. The network connected between this pin and ground adjusts the regulation loop bandwidth. Also, by connecting an opto-coupler to this pin, the peak current set point is adjusted accordingly to the output power demand 9-12 6-10 13-16 Pin Description This un-connected pin ensures adequate creepage distance Drain Drain Connection The internal drain MOSFET connection www.onsemi.com 2 NCV1060, NCV1063 Table 3. TYPICAL APPLICATIONS * If the output voltage is above 9.0 V typ. (between VCC(on) level and VOVP level) VCC is supplied from output via D2 * If the output voltage is below 9.0 V, D2 is redundant, the IC is supplied from DSS * R2 limits maximum output power (can be omitted if not required) * Direct feedback, resistive divider formed by R3, R4 sets output voltage * If the output voltage is above 9.0 V typ. (between VCC(on) level and VOVP level) VCC is supplied from output via D3 * If the output voltage is below 9.0 V, D3 and C5 are redundant, the IC is supplied from DSS * R2 limits maximum output power (can be omitted if not required) * Optocoupler feedback Typical Non-isolated Application - Buck Converter * If the output voltage is above 9.0 V typ. between VCC(ON) level and VOVP level - VCC supplied from output via D2 * R2 limits maximal output power * Direct feedback, resistive divider formed by R3, R4 sets output voltage * VCC supplied from DSS * Output voltage is below 9.0 V typ. * LIM/OPP pin floating - no limit output power * Direct feedback, resistive divider formed by R2, R3 sets output voltage Typical Non-isolated Application - Buck-Boost Converter www.onsemi.com 3 NCV1060, NCV1063 Table 3. TYPICAL APPLICATIONS (continued) * VCC supplied from DSS * Output voltage is below 9.0 V typ. * LIM/OPP pin floating - no limit output power * Resistive divider formed by R2, R3 sets output voltage * If the output voltage is above 9.0 V typ. between VCC(ON) level and VOVP level - VCC supplied from output via D4 * LIM/OPP pin floating - no limit output power * Resistive divider formed by R2, R3 sets output voltage Typical Non-isolated Application - Flyback Converter * VCC supplied from auxiliary winding * Resistive divider formed by R2, R3 sets output power limit and over power protection * Optocoupler feedback, resistive divider formed by R6, R7 sets output voltage Typical Isolated Application - Flyback Converter www.onsemi.com 4 NCV1060, NCV1063 DRAIN VCC 80-ms Filter SCP VOVP I pflag S OFF UVLO Q t SCP R trecovery VCOMP(REF ) OSC LineOK Line Detection UVLO OFF LineOK Jittering UVLO Reset Vdd VCC Management VCC OVP TSD VCC Sawtooth R COMP(up) S Foldback Q Sawtooth R ICOMPskip SKIP Ramp compensation SKIP = "1" e Shut down some blocks to reduce consumption COMP FB/COMP Processing GND LEB Ipflag ICOMPfault ICOMP to CS setpoint Reset I Freeze I LMDEC IFB Soft-Start Ipk(0) Reset SS as recoving from SCP, TSD, VCC OVP or UVLO FB 0 ILMOP (min) ILMDEC ILMOP (max ) ILMOP I LMOP IPKL VLMOP LIM/OPP Figure 2. Simplified Internal Circuit Architecture www.onsemi.com 5 NCV1060, NCV1063 Table 4. MAXIMUM RATING TABLE (All voltages related to GND terminal) Symbol Value Unit VCC -0.3 to 20 V Voltage on all pins, except Drain and VCC pin Vinmax -0.3 to 10 V Drain voltage BVdss -0.3 to 670 V ICC 10 mA Rating Power supply voltage, VCC pin, continuous voltage Maximum Current into VCC pin Drain Current Peak during Transformer Saturation (TJ = 150C, Note 2): NCV1060 NCV1063 Drain Current Peak during Transformer Saturation (TJ = 125C, Note 2): NCV1060 NCV1063 Drain Current Peak during Transformer Saturation (TJ = 25C, Note 2): NCV1060 NCV1063 IDS(PK) mA 300 850 335 950 520 1500 Thermal Resistance Junction-to-Air - SOIC10 with 200 mm@ of 35-m copper area RJA Thermal Resistance Junction-to-Air - SOIC16 with 200 mm@ of 35-m copper area 132 C/W RJA 104 C/W Junction Temperature Range TJ -40 to +150 C Storage Temperature Range Tstg -60 to +150 C Human Body Model ESD Capability (All pins except HV pin) per AEC-Q100-002 (JESD22-A114F) HBM 2 kV Charged-Device Model ESD Capability per AEC-Q100-11(JESD22-C101E) CDM 1 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78. 2. Maximum drain current IDS(PK) is obtained when the transformer saturates. It should not be mixed with short pulses that can be seen at turn on. Figure 3 below provides spike limits the device can tolerate. Figure 3. Spike Limits www.onsemi.com 6 NCV1060, NCV1063 Table 5. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25C, for min/max values TJ = -40C to +125C, VCC = 14 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit SUPPLY SECTION AND VCC MANAGEMENT VCC(on) VCC increasing level at which the switcher starts operation 2 (5) 8.4 9.0 9.5 V VCC(min) VCC decreasing level at which the HV current source restarts 2 (5) 7.0 7.5 7.8 V VCC(off) VCC decreasing level at which the switcher stops operation (UVLO) 2 (5) 6.7 7.0 7.2 V Internal IC consumption, NCV1060 switching at 60 kHz, LIM/OPP = 0 A Internal IC consumption, NCV1060 switching at 100 kHz, LIM/OPP = 0 A Internal IC consumption, NCV1063 switching at 60 kHz, LIM/OPP = 0 A Internal IC consumption, NCV1063 switching at 100 kHz, LIM/OPP = 0 A 2 (5) - - - - 0.92 0.97 0.99 1.07 - - - - mA Internal IC consumption, COMP is 0 V (No switching on MOSFET) 2 (5) - 340 - mA ICC1 ICCskip POWER SWITCH CIRCUIT Power Switch Circuit on-state resistance NCV1060 (Id = 50 mA) Tj = 25C Tj = 125C NCV1063 (Id = 50 mA) Tj = 25C Tj = 125C 7, 8 (6-10) (13-16) BVDSS Power Switch Circuit & Startup breakdown voltage (ID(off) = 120 mA, Tj = 25C) IDSS(off) RDS(on) tr tf ton(min) W - - 34 65 41 72 - - 11.4 22 14.0 24 7, 8 (6-10) (13-16) 670 - - V Power Switch & Startup breakdown voltage off-state leakage current Tj = 125C (Vds = 670 V) 7, 8 (6-10) (13-16) - 84 - mA Switching characteristics (RL = 50 W, VDS set for Idrain = 0.7 x Ilim) Turn-on time (90% - 10%) Turn-off time (10% - 90%) 7, 8 (6-10) (13-16) - - 20 10 - - Minimum on time NCV1060 NCV1063 7, 8 (6-10) (13-16) - - 200 230 - - ns ns INTERNAL START-UP CURRENT SOURCE Istart1 High-voltage current source, VCC = VCC(on) - 200 mV 7, 8 (6-10) (13-16) 5 8 12 mA Istart2 High-voltage current source, VCC = 0 V 7, 8 (6-10) (13-16) - 0.5 - mA 2 (5) - 1.4 - V 21 V VCCTH Vstart(min) VCC Transient level for Istart1 to Istart2 toggling point Minimum startup voltage, VCC = 0 V 7, 8 (6-10) (13-16) CURRENT COMPARATOR IIPK IIPK(0) Maximum internal current setpoint at 50% duty cycle FB = 2 V, LIM/OPP = 0 mA, Tj = 25C NCV1060 NCV1063 mA - - Maximum internal current setpoint at beginning of switching cycle FB = 2 V, LIM/OPP pin open Tj = 25C NCV1060 NCV1063 - - 250 650 - - mA - - 268 702 300 780 332 858 3. The final switch current is: IIPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built-in slope compensation, Vin the input voltage, LP the primary inductor in a flyback, and tprop the propagation delay. 4. Oscillator frequency is measured with disabled jittering. www.onsemi.com 7 NCV1060, NCV1063 Table 5. ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25C, for min/max values TJ = -40C to +125C, VCC = 14 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit CURRENT COMPARATOR IIPKSW IIPKSW ILMDEC Final switch current with a primary slope of 200 mA/ms, FSW = 60 kHz (Note 3), LIM/OPP pin open NCV1060 NCV1063 Final switch current with a primary slope of 200 mA/ms, FSW = 100 kHz (Note 3), LIM/OPP pin open NCV1060 NCV1063 mA - - - - 330 740 - - mA - - - - 320 710 - - Maximum internal current setpoint at beginning of switching cycle FB = 2 V, LIM/OPP = -285 mA, Tj = 25C NCV1060 NCV1063 mA - - - - 128 312 - - tSS Soft-start duration (guaranteed by design) - - 4 - ms tprop Propagation delay from current detection to drain OFF state - - 70 - ns tLEB Leading Edge Blanking Duration NCV1060 NCV1063 - - - - 130 160 - - ns INTERNAL OSCILLATOR fOSC Oscillation frequency, 60 kHz version, Tj = 25C (Note 4) - 54 60 66 kHz fOSC Oscillation frequency, 100 kHz version, Tj = 25C (Note 4) - 90 100 110 kHz fjitter Frequency jittering in percentage of fOSC - - 6 - % fswing Jittering swing frequency - - 300 - Hz Dmax Maximum duty-cycle - 62 66 72 % Voltage Feedback Input (VCOMP = 2.5 V) 4 (7) 3.2 3.3 3.4 V IFB Input Bias Current (VFB = 3.3 V) 4 (7) - 1 - mA GM ERROR AMPLIFIER SECTION VREF Transconductance 5 (8) 2 mS IOTAlim OTA maximum current capability (VFB > VOTAen) 5 (8) 150 mA VOTAen FB voltage to disable OTA 4 (7) 0.7 1.3 1.7 V COMPENSATION SECTION ICOMPfault COMP current for which Fault is detected 5 (8) - -40 - mA ICOMP100% COMP current for which internal current set-point is 100% (IIPK(0)) 5 (8) - -44 - mA ICOMPfreeze COMP current for which internal current setpoint is: IFreeze1 or 2 (NCV1060/3) 5 (8) - -80 - mA VCOMP(REF) Equivalent pull-up voltage in linear regulation range (Guaranteed by design) 5 (8) - 2.7 - V Equivalent feedback resistor in linear regulation range (Guaranteed by design) 5 (8) - 17.7 - k VLMOP Voltage on LIM/OPP pin @ ILMOP = -35 mA Voltage on LIM/OPP pin @ ILMOP = -250 mA, Tj = 25C 3 (6) 1.40 1.28 1.50 1.35 1.60 1.42 V ILMOP -330 -420 mA -26 -32 mA RCOMP(up) Maximum current from LIM/OPP pin 3 (6) ILMOP(min) Current at which LIM/OPP starts to decrease IPEAK 3 (6) ILMOP(max) Current at which LIM/OPP stops to decrease IPEAK 3 (6) -285 mA ILMOP(neg) Negative Active Clamp Voltage (ILMOP = -2.5 mA) 3 (6) -0.7 V -20 3. The final switch current is: IIPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built-in slope compensation, Vin the input voltage, LP the primary inductor in a flyback, and tprop the propagation delay. 4. Oscillator frequency is measured with disabled jittering. www.onsemi.com 8 NCV1060, NCV1063 Table 5. ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25C, for min/max values TJ = -40C to +125C, VCC = 14 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit COMPENSATION SECTION ILMOP(pos) Positive Active Clamp (Guaranteed by design) 3 (6) 2.5 mA FREQUENCY FOLDBACK & SKIP ICOMPfold Start of frequency foldback COMP pin current level ICOMPfold(end) End of frequency foldback COMP pin current level, fsw = fmin 5 (8) - -68 - mA 5 (8) - -100 - mA kHz fmin The frequency below which skip-cycle occurs - 21 25 29 ICOMPskip The COMP pin current level to enter skip mode 5 (8) - -120 - mA IFreeze1 Internal minimum current setpoint (ICOMP = ICOMPFreeze) in NCV1060 - 110 - mA IFreeze2 Internal minimum current setpoint (ICOMP = ICOMPFreeze) in NCV1063 - 270 - mA RAMP COMPENSATION Sa(60) The internal ramp compensation @ 60 kHz: NCV1060 NCV1063 - - - - 8.4 15.6 - - Sa(100) The internal ramp compensation @ 100 kHz: NCV1060 NCV1063 - - - - 14 26 - - Fault validation further to error flag assertion - 35 48 - ms OFF phase in fault mode - - 400 - ms 2 (5) 17.0 18.0 18.8 V - - 80 - ms 7,8 (6-10) (13-16) 67 87 110 V mA/ms mA/ms PROTECTIONS tSCP trecovery VOVP VCC voltage at which the switcher stops pulsing tOVP The filter of VCC OVP comparator VHV(EN) The drain pin voltage above which allows MOSFET operate, which is detected after TSD, UVLO, SCP, or VCC OVP mode. (A version only) TEMPERATURE MANAGEMENT TSD Temperature shutdown (Guaranteed by design) - 150 163 - C TSDhyst Hysteresis in shutdown (Guaranteed by design) - - 20 - C 3. The final switch current is: IIPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built-in slope compensation, Vin the input voltage, LP the primary inductor in a flyback, and tprop the propagation delay. 4. Oscillator frequency is measured with disabled jittering. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 9 NCV1060, NCV1063 TYPICAL CHARACTERISTICS 9.15 7.52 7.50 7.48 9.05 VOLTAGE (V) VOLTAGE (V) 9.10 9.00 8.95 7.46 7.44 7.42 7.40 7.38 7.36 8.90 7.34 8.85 -40 -20 0 20 40 60 80 100 7.32 -40 120 -20 0 20 40 60 80 100 TEMPERATURE (C) TEMPERATURE (C) Figure 4. VCC(on) vs. Temperature Figure 5. VCC(min) vs. Temperature 120 800 7.00 700 6.98 CURRENT (mA) VOLTAGE (V) 600 6.96 6.94 6.92 500 400 300 200 6.90 -20 0 20 40 60 80 100 0 -40 120 0 20 40 60 80 100 TEMPERATURE (C) Figure 6. VCC(off) vs. Temperature Figure 7. IDSS(off) vs. Temperature 0.95 0.99 0.94 0.98 0.93 0.97 0.92 0.91 0.90 120 0.96 0.95 0.94 0.93 0.89 0.88 -40 -20 TEMPERATURE (C) CURRENT (mA) CURRENT (mA) 6.88 -40 100 -20 0 20 40 60 80 100 0.92 -40 120 -20 0 20 40 60 80 100 TEMPERATURE (C) TEMPERATURE (C) Figure 8. ICC1 60 kHz vs. Temperature Figure 9. ICC1 100 kHz vs. Temperature www.onsemi.com 10 120 NCV1060, NCV1063 310 770 308 765 306 760 CURRENT (mA) 304 302 300 298 296 294 750 745 740 735 292 290 288 -40 -20 725 720 -40 0 20 40 60 80 100 120 0 20 40 60 80 100 TEMPERATURE (C) Figure 10. IIPK(0)1060 vs. Temperature Figure 11. IIPK(0)1063 vs. Temperature 12 0.6 10 0.5 8 6 4 120 0.4 0.3 0.2 0.1 0 -40 -20 0 20 40 60 80 100 0 -40 120 -20 0 20 40 60 80 100 TEMPERATURE (C) TEMPERATURE (C) Figure 12. Istart1 vs. Temperature Figure 13. Istart2 vs. Temperature 70 120 25 60 20 RESISTIVITY (W) 50 40 30 20 15 10 5 10 0 -40 -20 TEMPERATURE (C) 2 RESISTIVITY (W) 755 730 CURRENT (mA) CURRENT (mA) CURRENT (mA) TYPICAL CHARACTERISTICS -20 0 20 40 60 80 100 0 -40 120 -20 0 20 40 60 80 100 TEMPERATURE (C) TEMPERATURE (C) Figure 14. RDS(on)1060 vs. Temperature Figure 15. RDS(on)1063 vs. Temperature www.onsemi.com 11 120 NCV1060, NCV1063 60.0 100 59.5 99 59.0 98 FREQUENCY (kHz) FREQUENCY (kHz) TYPICAL CHARACTERISTICS 58.5 58.0 57.5 57.0 56.5 -20 0 20 40 60 80 100 94 92 -40 120 20 40 60 80 100 Figure 16. fOSC60 vs. Temperature Figure 17. fOSC100 vs. Temperature 108 272 107 270 106 105 104 103 266 264 262 260 101 258 0 20 40 60 80 100 256 -40 120 120 268 102 -20 0 20 40 60 80 100 TEMPERATURE (C) TEMPERATURE (C) Figure 18. Ifreeze1060 vs. Temperature Figure 19. Ifreeze1063 vs. Temperature 120 25.8 66.2 25.6 FREQUENCY (kHz) 66.1 66.0 65.9 65.8 65.7 65.6 -40 0 TEMPERATURE (C) 274 -20 -20 TEMPERATURE (C) CURRENT (mA) CURRENT (mA) 95 109 100 -40 DUTY CYCLE (%) 96 93 56.0 55.5 -40 97 25.4 25.2 25.0 24.8 24.6 -20 0 20 40 60 80 100 24.4 -40 -20 120 0 20 40 60 80 TEMPERATURE (C) TEMPERATURE (C) Figure 20. D(max) vs. Temperature Figure 21. fmin vs. Temperature www.onsemi.com 12 100 120 NCV1060, NCV1063 TYPICAL CHARACTERISTICS 53 430 425 52 420 51 TIME (ms) TIME (ms) 415 410 405 400 47 390 0 20 40 60 80 100 46 -40 120 0 20 40 60 80 100 TEMPERATURE (C) Figure 22. trecovery vs. Temperature Figure 23. tSCP vs. Temperature 92 18.1 91 18.0 90 17.9 17.8 17.7 88 87 86 17.5 85 -20 0 20 40 60 80 100 84 -40 120 -20 0 20 40 60 80 100 TEMPERATURE (C) TEMPERATURE (C) Figure 24. VOVP vs. Temperature Figure 25. VHV(EN) vs. Temperature 3.34 1.6 3.33 1.4 3.32 120 89 17.6 120 1.2 VOLTAGE (V) 3.31 3.30 3.29 3.28 3.27 1.0 0.8 0.6 0.4 3.26 3.25 3.24 -40 -20 TEMPERATURE (C) VOLTAGE (V) VOLTAGE (V) -20 18.2 17.4 -40 VOLTAGE (V) 49 48 395 385 -40 50 0.2 -20 0 20 40 60 80 100 0 -40 120 -20 0 20 40 60 80 100 TEMPERATURE (C) TEMPERATURE (C) Figure 26. VREF vs. Temperature Figure 27. VOTAen vs. Temperature www.onsemi.com 13 120 NCV1060, NCV1063 TYPICAL CHARACTERISTICS 1.100 2.5 NCV1063 1.075 BVDSS/BVDSS (25C)(-) IDS(PK) (A) 2.0 1.5 1.0 NCV1060 0.5 1.050 1.025 1.000 0.975 0.950 0 -50 -25 0 25 50 75 100 125 0.925 -40 150 -20 0 20 40 60 80 100 125 TJ, JUNCTION TEMPERATURE (C) TEMPERATURE (C) Figure 28. Drain Current Peak during Transformer Saturation vs. Junction Temperature Figure 29. Breakdown Voltage vs. Temperature www.onsemi.com 14 NCV1060, NCV1063 APPLICATION INFORMATION * If the drain voltage is lower than the internal threshold Introduction The NCV106X offers a complete current-mode control solution. The component integrates everything needed to build a rugged and cost effective Switch-Mode Power Supply (SMPS) featuring low standby power. The Quick Selection Table, Table 6, details the differences between references, mainly peak current setpoints, RDS(on) value and operating frequency. * Current-mode Operation: the controller uses current-mode control architecture. * 670 V -_ Power MOSFET: Due to ON Semiconductor Very High Voltage Integrated Circuit technology, the circuit hosts a high-voltage power MOSFET featuring a 34 W or 11.4 W RDS(on) - Tj = 25C. This value lets the designer build a power supply up to 8.6 W or 17.1 W operated on universal mains. An internal current source delivers the startup current, necessary to crank the power supply. * Dynamic Self-supply: Due to the internal high voltage current source, this device could be used in the application without the auxiliary winding to provide supply voltage. * Short Circuit Protection: by permanently monitoring the COMP line activity, the IC is able to detect the presence of a short-circuit, immediately reducing the output power for a total system protection. A tSCP timer is started as soon as the COMP current is below threshold, ICOMPfault, which indicates the maximum peak current. If at the end of this timer the fault is still present, then the device enters a safe, auto-recovery burst mode, affected by a fixed timer recurrence, trecovery. Once the short has disappeared, the controller resumes and goes back to normal operation. * Built-in VCC Over Voltage Protection: when the auxiliary winding is used to bias the VCC pin (no DSS), an internal comparator is connected to VCC pin. In case the voltage on the pin exceeds a level of VOVP (18 V typically), the controller immediately stops switching and waits a full timer period (trecovery) before attempting to restart. If the fault is gone, the controller resumes operation. If the fault is still there, e.g. a broken opto-coupler, the controller protects the load through a safe burst mode. * Line Detection: An internal comparator monitors the drain voltage as recovering from one of the following situations: Short Circuit Protection, VCC OVP is confirmed, UVLO, TSD * * * * * (VHV(EN)), the internal power switch is inhibited. This avoids operating at too low ac input. This is also called brown-in function in some fields. For applications not using standard AC mains (24 Vdc industrial bus for instance), the B version doesn't incorporate this line detection and let the device start as soon as voltage supply reaches Vstart(min). Frequency Jittering: an internal low-frequency modulation signal varies the pace at which the oscillator frequency is modulated. This helps spreading out energy in conducted noise analysis. To improve the EMI signature at low power levels, the jittering remains active in frequency foldback mode. Soft-start: a 4 ms soft-start ensures a smooth startup sequence, reducing output overshoots. Frequency Foldback Capability: a continuous flow of pulses is not compatible with no-load/light-load standby power requirements. To excel in this domain, the controller observes the COMP pin current information and when it reaches a level of ICOMPfold, the oscillator then starts to reduce its switching frequency as the feedback current continues to increase (the power demand continues to reduce). It can go down to 25 kHz (typical) reached for a feedback level of ICOMPfold(end) (100 mA roughly). At this point, if the power continues to drop, the controller enters classical skip-cycle mode. Skip: if SMPS naturally exhibits a good efficiency at nominal load, it begins to be less efficient when the output power demand diminishes. By skipping un-needed switching cycles, the NCV106X drastically reduces the power wasted during light load conditions. Ipeak Set: If current in range 26 mA and 285 mA is drawn from the pin, the peak current is proportionally reduced down to 40% of its original value. This feature enables to designer to set up the peak current to the value which is ideal for the application. By routing a portion of the negative voltage present during the on-time on the auxiliary winding to the LIM/OPP pin, the user has a simple and non-dissipative means to alter the maximum peak current setpoint as the bulk voltage increases. www.onsemi.com 15 NCV1060, NCV1063 Startup Sequence above VHV(EN) level (87 V typically) for A version and if bulk voltage is above Vstart(min) (21 V dc) for B version. There is no disable level for drain pin voltage, the device will stop switching when the input voltage is removed and sub-sequentially the VCC reaches the VCC(OFF) level, or tSCP timer elapses. Figure 30 details the simplified internal circuitry. When the power supply is first powered from the mains outlet, the internal current source (typically 8.0 mA) is biased and charges up the VCC capacitor from the drain pin. Once the voltage on this VCC capacitor reaches the VCC(on) level (typically 9.0 V), the current source turns off and pulses are delivered by the output stage: the circuit is awake and activates the power MOSFET if the bulk voltage is Vbulk I1 Rlimit I start1 ICC1 1 Drain 5 I2 - + CVCC VCC(on) VCC(min) + - VOVP VCC > 18 V ? aOVP fault 8 Figure 30. The Internal Arrangement of the Start-up Circuitry Being loaded by the circuit consumption, the voltage on the VCC capacitor goes down. When VCC is below VCC(min) level (7.5 V typically), it activates the internal current source to bring VCC toward VCC(on) level and stops again: a cycle takes place whose low frequency depends on the VCC capacitor and the IC consumption. A 1.5 V ripple takes place on the VCC pin whose average value equals (VCC(on) + VCC(min))/2. Figure 31 portrays a typical operation of the DSS. www.onsemi.com 16 NCV1060, NCV1063 10 9 9.0 V 8 7 V (V) 7.5 V VCC 6 5 Device Internal Pulses 4 3 VCCTH 2 1 0 0 1 2 3 Startup Duration 4 5 TIME (ms) 6 7 8 9 10 Figure 31. The Charge/Discharge Cycle over a 1 mF VCC Capacitor trecovery duration (400 ms typically). Then a new start-up attempt takes place to check whether the fault has disappeared or not. The OVP paragraph gives more design details on this particular section. As one can see, even if there is auxiliary winding to provide energy for VCC, it happens that the device is still biased by DSS during start-up time or some fault mode when the voltage on auxiliary winding is not ready yet. The VCC capacitor shall be dimensioned to avoid VCC crosses VCC(off) level, which stops operation. The V between VCC(min) and VCC(off) is 0.5 V. There is no current source to charge VCC capacitor when driver is on, i.e. drain voltage is close to zero. Hence the VCC capacitor can be calculated using C VCC w I CC1 @ D max f OSC @ DV Fault Condition - Short-circuit on VCC In some fault situations, a short-circuit can purposely occur between VCC and GND. In high line conditions (VHV = 370 VDC) the current delivered by the startup device will seriously increase the junction temperature. For instance, since Istart1 equals 5 mA (the min corresponds to the highest Tj), the device would dissipate 370 x 5 m = 1.85 W. To avoid this situation, the controller includes a novel circuitry made of two startup levels, Istart1 and Istart2. At power-up, as long as VCC is below a 1.4 V level, the source delivers Istart2 (around 500 mA typical), then, when VCC reaches 1.4 V, the source smoothly transitions to Istart1 and delivers its nominal value. As a result, in case of short-circuit between VCC and GND, the power dissipation will drop to 370 x 500 m = 185 mW. Figure 31 portrays this particular behavior. The first startup period is calculated by the formula C x V = I x t, which implies a 1 m x 1.4 / 500 m = 2.8 ms startup time for the first sequence. The second sequence is obtained by toggling the source to 8 mA with a delta V of VCC(on) - VCCTH = 9.0 - 1.4 = 7.6 V, which finally leads to a second startup time of 1 m x 7.6 / 8 m = 0.95 ms. The total startup time becomes 2.8 m + 0.95 m = 3.75 ms. Please note that this calculation is approximated by the presence of the knee in the vicinity of the transition. (eq. 1) Take the 60 kHz device as an example. CVCC should be above 0.8 m @ 72% + 21 nF. 54 kHz @ 0.5 A margin that covers the temperature drift and the voltage drop due to switching inside FET should be considered, and thus a capacitor above 0.1 mF is appropriate. The VCC capacitor has only a supply role and its value does not impact other parameters such as fault duration or the frequency sweep period for instance. As one can see on Figure 30, an internal OVP comparator, protects the switcher against lethal VCC runaways. This situation can occur if the feedback loop optocoupler fails, for instance, and you would like to protect the converter against an over voltage event. In that case, the over voltage protection (OVP) circuit and immediately stops the output pulses for www.onsemi.com 17 NCV1060, NCV1063 Fault Condition - Output Short-circuit asserted, Ipflag, indicating that the system has reached its maximum current limit set point. The assertion of this flag triggers a fault counter tSCP (48 ms typically). If at counter completion, Ipflag remains asserted, all driving pulses are stopped and the part stays off in trecovery duration (about 400 ms). A new attempt to re-start occurs and will last 48 ms providing the fault is still present. If the fault still affects the output, a safe burst mode is entered, affected by a low duty-cycle operation (11%). When the fault disappears, the power supply quickly resumes operation. Figure 32 depicts this particular mode: As soon as VCC reaches VCC(on), drive pulses are internally enabled. If everything is correct, the auxiliary winding increases the voltage on the VCC pin as the output voltage rises. During the start-sequence, the controller smoothly ramps up the peak drain current to maximum setting, i.e. IIPK, which is reached after a typical period of 4 ms. When the output voltage is not regulated, the current coming through COMP pin is below ICOMPfault level (40 mA typically), which is not only during the startup period but also anytime an overload occurs, an internal error flag is VCC VCC(on) VCC(min) IpFlag Open loop FB VCOMP Fault 48 ms typ. Timer 400 ms typ. DRV internal Figure 32. In Case of Short-circuit or Overload, the NCV106X Protects itself and the Power Supply via a Low Frequency Burst Mode. The VCC is Maintained by the Current Source and Self-supplies the Controller Auto-recovery Over Voltage Protection IC against high voltage spikes, which can damage the IC, and to filter out the Vcc line to avoid undesired OVP activation. Rlimit should be carefully selected to avoid triggering the OVP as we discussed, but also to avoid disturbing the VCC in low / light load conditions. Self-supplying controllers in extremely low standby applications often puzzles the designer. Actually, if a SMPS operated at nominal load can deliver an auxiliary voltage of an arbitrary 16 V (Vnom), this voltage can drop below 10 V (Vstby) when entering standby. This is because the recurrence of the switching pulses expands so much that the low frequency re-fueling rate of the VCC capacitor is not enough to keep a proper auxiliary voltage. The particular NCV106X arrangement offers a simple way to prevent output voltage runaway when the optocoupler fails. As Figure 33 shows, a comparator monitors the VCC pin. If the auxiliary pushes too much voltage into the CVCC capacitor, then the controller considers an OVP situation and stops the internal drivers. When an OVP occurs, all switching pulses are permanently disabled. After trecovery delay, it resumes the internal drivers. If the failure symptom still exists, e.g. feedback opto-coupler fails, the device keeps the auto-recovery OVP mode. It is recommended insertion of a resistor (Rlimit) between the auxiliary dc level and the VCC pin to protect the www.onsemi.com 18 NCV1060, NCV1063 Drain VCC (on ) = 9.0 V VCC (min ) = 7. 5 V Istart 1 VCC Shut down Internal DRV C VCC 80 ms filter VOVP D1 R limit C AUX N AUX GND Figure 33. A More Detailed View of the NCV106X Offers Better Insight on how to Properly Wire an Auxiliary Winding V OVP V CC(on) V CC(min) VCC I COMP 48 ms typ. Fault level TIMER 400 ms typ. DRV internal Figure 34. Describes the Main Signal Variations when the Part Operates in Auto-recovery OVP Soft-start The NCV106X features a 4 ms soft-start which reduces the power-on stress but also contributes to lower the output overshoot. Figure 35 shows a typical operating waveform. The NCV106X features a novel patented structure which offers a better soft-start ramp, almost ignoring the start-up pedestal inherent to traditional current-mode supplies. www.onsemi.com 19 NCV1060, NCV1063 VCC VCCON 0V (fresh PON) Max Ip Drain current 4 ms Figure 35. The 4 ms Soft-start Sequence Jittering sawtooth is internally generated and modulates the clock up and down with a fixed frequency of 300 Hz. Figure 36 shows the relationship between the jitter ramp and the frequency deviation. It is not possible to externally disable the jitter. Frequency jittering is a method used to soften the EMI signature by spreading the energy in the vicinity of the main switching component. The NCV106X offers a 6% deviation of the nominal switching frequency. The sweep Jitter ramp 63.6 kHz 60 kHz Internal sawtooth 56.4 kHz adjustable Figure 36. Modulation Effects on the Clock Signal by the Jittering Sawtooth * UVLO * TSD Line Detection (for A version only) An internal comparator monitors the drain voltage as recovering from one of the following situations: * Short Circuit Protection, * VCC OVP is confirmed, If the drain voltage is lower than the internal threshold VHV(EN) (87 Vdc typically), the internal power switch is inhibited. This avoids operating at too low ac input. www.onsemi.com 20 NCV1060, NCV1063 Frequency Foldback Frequency [kHz] The reduction of no-load standby power associated with the need for improving the efficiency, requires to change the traditional fixed-frequency type of operation. This device implements a switching frequency foldback when the COMP current passes above a certain level, ICOMPfold, set around 68 mA. At this point, the oscillator enters frequency foldback and reduces its switching frequency. The internal peak current set-point is following the COMP current information until its level reaches IFreeze. 110 100 90 80 70 60 50 40 30 20 10 0 Below this value, the peak current setpoint is frozen to 30% of the IPK(0). The only way to further reduce the transmitted power is to diminish the operating frequency down to Fmin (25 kHz typically). This value is reached at a COMP current level of ICOMPfold(end) (100 mA typically). Below this point, if the output power continues to decrease, the part enters skip cycle for the best noise-free performance in no-load conditions. Figure 37 and Figure 38 depict the adopted scheme for the part. NCV1060 NCV1063 50 60 70 80 90 100 ICOMP [mA] Figure 37. By Observing the Current on the COMP Pin, the Controller Reduces its Switching Frequency for an Improved Performance at Light Load 900 NCV1060 Current set point [mA] 800 NCV1063 700 600 500 400 300 200 100 0 40 50 60 70 80 90 100 ICOMP [mA] Figure 38. Ipk Set-point is Frozen at Lower Power Demand www.onsemi.com 21 110 NCV1060, NCV1063 350 NCV1060 Current set point [mA] 300 NCV1063 250 200 150 100 50 0 40 50 60 70 80 90 100 110 ICOMP [mA] Figure 39. Ipk Set-point is Frozen at Lower Power Demand (ILMOP 285 mA) Feedback and Skip this linear operating range, the dynamic resistance is 17.7 kW typically (RCOMP(up)) and the effective pull up voltage is 2.7 V typically (VCOMP(REF)). When ICOMP is decreases, the COMP voltage will increase to 3.2 V. Figure 40 depicts the relationship between COMP pin voltage and current. The COMP pin operates linearly as the absolute value of COMP current (ICOMP) is above 40 mA. In 3.5 3.0 VCOMP [V] 2.5 2.0 1.5 1.0 0.5 0.0 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 ICOMP [A] Figure 40. COMP Pin Voltage vs. Current Figure 41 depicts the skip mode block diagram. When the COMP current information reaches ICOMPskip, the internal clock setting the flip-flop is blanked and the internal consumption of the controller is decreased. The hysteresis of internal skip comparator is minimized to lower the ripple of the auxiliary voltage for VCC pin and VOUT of power supply during skip mode. It easies the design of VCC over load range. www.onsemi.com 22 NCV1060, NCV1063 Jittering OSC S Foldback R VCOMP(REF) DRV stage Q Q ICOMPskip RCOMP(UP) SKIP CS comparator COMP Figure 41. Skip Cycle Schematic Ilimit and OPP Function The function makes the integrated circuit more flexible. The current drawn out of LIM/OPP pin defines the current set point. 900 NCV1060 Current set point [mA] 800 NCV1063 700 600 500 400 300 200 100 0 0 50 100 150 200 250 300 350 ILMOP [mA] Figure 42. Ipk Set-point Dependence on ILMOP Current ROPPU and ROPPL (Figure 43) define current drawn from LIM/OPP and the negative voltage on auxiliary winding. The negative voltage is tied up with bulk voltage, so the higher the bulk voltage is, the deeper is the negative voltage on auxiliary winding, the higher current is drawn from LIM/OPP pin and the lower the peak current is. During the internal MOSFET off period, voltage on auxiliary winding is positive, but the IC ignores the LIM/OPP current. The positive LIM/OPP current has no influence on proper IC function. There are several known ways to implement Over Power Protection (OPP), all suffering from particular problems. These problems range from the added consumption burden on the converter or the skip-cycle disturbance brought by the current-sense offset. A way to reduce the power capability at high line is to capitalize on the negative voltage swing present on the auxiliary diode anode. During the power switch on-time, this point dips to -NVin , N being the turns ratio between the primary winding and the auxiliary winding. The negative plateau on auxiliary winding will have an amplitude dependant on the input voltage. Resistors www.onsemi.com 23 NCV1060, NCV1063 D4 VCC OSC Aux winding C2 S Q MOSFET R Vramp + Vsense ICOMP ICOMP to CS setpoint R OPPU ILMDEC LIM/ OPP 0 25 mA I Freeze 250 mA Ipk(0 ) ILMOP ILMOP IPKL ILMDEC R OPPL Figure 43. The OPP Circuitry Affects the Maximum Peak Current Set Point Ramp Compensation and Ipk Set-point NCV1060 In order to allow the NCV106X to operate in CCM with a duty cycle above 50%, a fixed slope compensation is internally applied to the current-mode control. Here we got a table of the ramp compensation, the initial current set point, and the final current set-point of different versions of switcher. NCV1063 fsw 60 kHz 100 kHz 60 kHz 100 kHz Sa 8.4 mA/ms 14 mA/ms 15.6 mA/ms 26 mA/ms Ipk(Duty 250 mA 650 mA 300 mA 780 mA =50%) Ipk(0) Figure 44 depicts the variation of IPK set-point vs. the power switcher duty ratio, which is caused by the internal ramp compensation. 900 NCV1060 800 NCV1063 Ipk set-point [mA] 700 600 500 400 300 200 100 0 0% 10% 20% 30% 40% 50% 60% 70% Dutty Ratio [%] Figure 44. IPK Set-point Varies with Power Switch on Time, which is Caused by the Ramp Compensation FB Pin Function positive current is defined by internal RCOMP(up) resistor and VCOMP(ref) voltage. If FB path loop is broken (i.e. the FB pin is disconnected), an internal current IFB (1 mA typ.) will pull up the FB pin and the IC stops switching to avoid uncontrolled output voltage increasing. In isolated topology, the FB pin should be connected to GND pin. In this configuration no current flows from OTA to COMP pin (OTA is disabled) so the OTA has no influence on regulation at all. The FB pin is used in non isolated SMPS application only. Portion of the output voltage is connected into the pin. The voltage is compared with internal VREF (3.3 V) using Operation Transconductance Amplifier (Figure 45). The OTAs output is connected to COMP pin. The OTA output is accessible through the COMP pin and is used for the loop compensation, usually an RC network. The current capability of OTA is limited to -150 mA typically. The www.onsemi.com 24 NCV1060, NCV1063 Vin max = 265 Vac or 375 Vdc Vout = 12 V Pout = 5 W Operating mode is CCM = 0.8 1. The lateral MOSFET body-diode shall never be forward biased, either during start-up (because of a large leakage inductance) or in normal operation as shown in Figure 46. This condition sets the maximum voltage that can be reflected during toff. As a result, the Flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. When selecting components, you thus must adopt a turn ratio which adheres to the following equation: VCOMP (REF ) RCOMP (up ) I COMP COMP I FB IOTAlim OTA out = 0 A if FB = 0 V FB OTA VREF N @ V out ) V f t V in,min Figure 45. FB Pin Connection 2. In our case, since we operate from a 127 V DC rail while delivering 12 V, we can select a reflected voltage of 120 V dc maximum. Therefore, the turn ratio Np:Ns must be smaller than Design Procedure The design of an SMPS around a monolithic device does not differ from that of a standard circuit using a controller and a MOSFET. However, one needs to be aware of certain characteristics specific of monolithic devices. Let us follow the steps: Vin min = 90 Vac or 127 Vdc once rectified, assuming a low bulk ripple V reflect + 120 + 9.6 or Np : Ns t 9.6. 12 ) 0.5 V out ) V f Here we choose N = 8 in this case. We will see later on how it affects the calculation. 350 250 150 50.0 > 0 !! -50.0 1.004M 1.011M (eq. 2) 1.018M 1.025M 1.032M Figure 46. The Drain-source Wave Shall always be Positive www.onsemi.com 25 NCV1060, NCV1063 where K + DI L I Lavg and defines the amount of ripple we want in CCM (see Figure 47). * Small K: deep CCM, implying a large primary inductance, a low bandwidth and a large leakage inductance. * Large K: approaching DCM where the RMS losses are worse, but smaller inductance, leading to a better leakage inductance. From Equation 6, a K factor of 1 (50% ripple), gives an inductance of: 2 (127 @ 0.44) + 10.04 mH 60k @ 1 @ 5 V @d DI L + in + 127 @ 0.44 + 92.8 mA peak to peak L @ f sw 10.04m @ 60k L+ Figure 47. Primary Inductance Current Evolution in CCM The peak current can be evaluated to be: 3. Lateral MOSFETs have a poorly doped body-diode which naturally limits their ability to sustain the avalanche. A traditional RCD clamping network shall thus be installed to protect the MOSFET. In some low power applications, a simple capacitor can also be used since V drain,max + V in ) N @ V out ) V f ) I peak @ I peak + On IL, ILavg can also be calculated: I Lavg + I peak * I d,rms + + + 1) 1 Vin,min L+ DI L 2 3 0.44 @ 0.158 2 * 0.158 @ 0.0928 ) 0.0928 3 2 P cond + I d,rms 2 @ R DS(on) + 110 mW 7. Off-time and on-time switching losses can be estimated based on the following calculations: P off + + (eq. 4) I peak @ V bulk ) V clamp @ t off (eq. 6) 2T SW 0.158 @ (127 ) 100 @ 2) @ 10n 2 @ 16.7 m + 15.5 mW + 0.44 Where, assume the Vclamp is equal to 2 times of reflected voltage. N@(Vout@Vf) 2 f sw @ K @ P in d @ I peak 2 * I peak @ DI L ) If we take the maximum RDS(on) for a 125C junction temperature, i.e. 34 W, then conduction losses worse case are: 5. To obtain the primary inductance, we have the choice between two equations: V in @ d + 57 mA N @ V out @ V f N @ V out @ V f ) V in,min DI L + 158m * 92.8m + 111.6 mA 2 2 6. Based on the above numbers, we can now evaluate the conduction losses: Lf (eq. 3) C tot where Lf is the leakage inductance, Ctot the total capacitance at the drain node (which is increased by the capacitor you will wire between drain and source), N the NP:NS turn ratio, Vout the output voltage, Vf the secondary diode forward drop and finally, Ipeak the maximum peak current. Worse case occurs when the SMPS is very close to regulation, e.g. the Vout target is almost reached and Ipeak is still pushed to the maximum. For this design, we have selected our maximum voltage around 650 V (at Vin = 375 Vdc). This voltage is given by the RCD clamp installed from the drain to the bulk voltage. We will see how to calculate it later on. 4. Calculate the maximum operating duty-cycle for this flyback converter operated in CCM: d max + I avg DI L 49.2 m 92.8 m ) + ) + 158 mA 0.44 2 2 d (eq. 5) www.onsemi.com 26 NCV1060, NCV1063 P on + I valley @ V bulk ) N @ (V out ) V f) @ t on (eq. 7) 6 @ T SW 9. If the NCV106X operates at DSS mode, then the losses caused by DSS mode should be counted as losses of this device on the following calculation: 0.0464 @ (127 ) 100) @ 10 n 6 @ 16.7 m + 2.1 mW P DSS + I CC1 @ V in.max + 0.8m @ 375 + 300 mW (eq. 8) + MOSFET Protection It is noted that the overlap of voltage and current seen on MOSFET during turning on and off duration is dependent on the snubber and parasitic capacitance seen from drain pin. Therefore the toff and ton in Equation 7 and Equation 8 have to be modified after measuring on the bench. 8. The theoretical total power is then 117 + 15.5 + 2.1 = 127.6 mW As in any Flyback design, it is important to limit the drain excursion to a safe value, e.g. below the MOSFET BVdss which is 670 V. Figure 48 a-b-c present possible implementations: Figure 48. a, b, c: Different Options to Clamp the Leakage Spike Figure 48a: the simple capacitor limits the voltage according to the lateral MOSFET body-diode shall never be forward biased, either during start-up (because of a large leakage inductance) or in normal operation as shown by Figure 46. This condition sets the maximum voltage that can be reflected during toff. As a result, the flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. When selecting components, you must adopt a turn ratio which adheres to the following Equation 3. This option is only valid for low power applications, e.g. below 5 W, otherwise chances exist to destroy the MOSFET. After evaluating the leakage inductance, you can compute C with (Equation 4). Typical values are between 100 pF and up to 470 pF. Large capacitors increase capacitive losses... Figure 48b: the most standard circuitry is called the RCD network. You calculate Rclamp and Cclamp using the following formulae: R clamp + C clamp + 2 @ V clamp @ V clamp ) N @ (V out ) V f) L leak @ I leak 2 @ f sw a MUR160 represents a good choice. One major drawback of the RCD network lies in its dependency upon the peak current. Worse case occurs when Ipeak and Vin are maximum and Vout is close to reach the steady-state value. Figure 48c: this option is probably the most expensive of all three but it offers the best protection degree. If you need a very precise clamping level, you must implement a zener diode or a TVS. There are little technology differences behind a standard zener diode and a TVS. However, the die area is far bigger for a transient suppressor than that of zener. A 5 W zener diode like the 1N5388B will accept 180 W peak power if it lasts less than 8.3 ms. If the peak current in the worse case (e.g. when the PWM circuit maximum current limit works) multiplied by the nominal zener voltage exceeds these 180 W, then the diode will be destroyed when the supply experiences overloads. A transient suppressor like the P6KE200 still dissipates 5 W of continuous power but is able to accept surges up to 600 W @ 1 ms. Select the zener or TVS clamping level between 40 to 80 volts above the reflected output voltage when the supply is heavily loaded. As a good design practice, it is recommended to implement one of this protection to make sure Drain pin voltage doesn't go above 650 V (to have some margin between Drain pin voltage and BVdss) during most stringent operating conditions (high Vin and peak power). (eq. 9) V clamp V ripple @ f sw @ R clamp Vclamp is usually selected 50-80 V above the reflected value N x (Vout + Vf). The diode needs to be a fast one and www.onsemi.com 27 NCV1060, NCV1063 Power Dissipation and Heatsinking The NCV106X welcomes two dissipating terms, the DSS current-source (when active) and the MOSFET. Thus, Ptot = PDSS + PMOSFET. It is mandatory to properly manage the heat generated by losses. If no precaution is taken, risks exist to trigger the internal thermal shutdown (TSD). To help dissipating the heat, the PCB designer must foresee large copper areas around the package. Take the SOIC-10 package as an example, when surrounded by a surface approximately 200 mm2 of 35 mm copper, the maximum power the device can thus evacuate is: P max + T Jmax * T ambmax R qJA (eq. 10) which gives around 760 mW for an ambient of 50C and a maximum junction of 150C. If the surface is not large enough, the RJA is growing and the maximum power the device can evacuate decreases. Figure 49 gives a possible layout to help drop the thermal resistance. Figure 49. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction-to-Ambient Bill of material: C1 C2, R1, D1 C3 OK1 R2 Bulk capacitor, input DC voltage is connected to the capacitor Clamping elements Vcc capacitor Optocoupler Resistor to setting IPEAK current Table 6. ORDERING INFORMATION Package Type Shipping Device Frequency RDS(on) Brown In NCV1060BD060R2G* 60 kHz 34 No NCV1060BD100R2G* 100 kHz 34 No SOIC-10 (Pb-Free) 2500 / Tape & Reel NCV1063AD060R2G* 60 kHz 11.4 Yes SOIC-16 (Pb-Free) 2500 / Tape & Reel NCV1063AD100R2G* 100 kHz 11.4 Yes SOIC-16 (Pb-Free) 2500 / Tape & Reel 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable. www.onsemi.com 28 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC-16 CASE 751B-05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 16 9 -B- 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C -T- SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N-CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P-CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P-CH SOURCE P-CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N-CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N-CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: STATUS: 98ASB42566B ON SEMICONDUCTOR STANDARD NEW STANDARD: (c) Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 - Rev. 0 SOIC-16 http://onsemi.com 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. Case Outline Number: PAGE 1 OFXXX 2 DOCUMENT NUMBER: 98ASB42566B PAGE 2 OF 2 ISSUE K REVISION ADDED SOLDERING FOOTPRINT. REQ. BY L. MORAN. DATE 29 DEC 2006 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. (c) Semiconductor Components Industries, LLC, 2006 December, 2006 - Rev. 05K Case Outline Number: 751B MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC-10 NB CASE 751BQ ISSUE B 10 1 SCALE 1:1 DATE 26 NOV 2013 2X 0.10 C A-B D D A 2X F 0.10 C A-B 10 6 H E 1 5 0.20 C 10X B 2X 5 TIPS L2 b 0.25 A3 L C DETAIL A M SEATING PLANE C A-B D TOP VIEW 10X h 0.10 C 0.10 C X 45 _ M A e A1 C SIDE VIEW SEATING PLANE DETAIL A END VIEW DIM A A1 A3 b D E e H h L L2 M 10 1.00 PITCH 1 1 DIMENSION: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: STATUS: 98AON52341E ON SEMICONDUCTOR STANDARD NEW STANDARD: (c) Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 - Rev. 0 SOIC-10 NB XXXXX ALYWX G XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G", may or not be present. 6.50 10X 1.18 MILLIMETERS MIN MAX 1.25 1.75 0.10 0.25 0.17 0.25 0.31 0.51 4.80 5.00 3.80 4.00 1.00 BSC 5.80 6.20 0.37 REF 0.40 0.80 0.25 BSC 0_ 8_ GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 10X 0.58 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.10mm TOTAL IN EXCESS OF 'b' AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15mm PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F. 5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F. 6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. http://onsemi.com 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. Case Outline Number: PAGE 1 OFXXX 2 DOCUMENT NUMBER: 98AON52341E PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION. REQ. BY M. RAMOS. 06 JUL 2010 A CHANGED DIMENSION A MIN FROM 1.35 TO 1.25. REQ. BY HB TAN. 25 APR 2011 B CHANGED DIMENSION L MAX FROM 1.27 TO 0.80 MM. REQ. BY C. TAN. 26 NOV 2013 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. (c) Semiconductor Components Industries, LLC, 2013 November, 2013 - Rev. B Case Outline Number: 751BQ ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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