ADC12020CIVYX/NOPB - TEXAS INSTRUMENTS

May, 2018 − Rev. 0

1Publication Order Number:

NCV1060/D

NCV1060, NCV1063

Automotive High-Voltage

Switcher for Low Power

Offline SMPS

The NCV106X products integrate a fixed frequency current mode

controller with a 670 V MOSFET. Available in a SOIC−10 or

SOIC−16 package, the NCV106X offer a high level of integration,

including soft−start, frequency−jittering, short−circuit protection,

skip−cycle, adjustable peak current set point, ramp compensation, and a

Dynamic Self−Supply (eliminating the need for an auxiliary winding).

Unlike other monolithic solutions, the NCV106X is quiet by nature:

during nominal load operation, the part switches at one of the available

frequencies (60 kHz or 100 kHz). When the output power demand

diminishes, the IC automatically enters frequency foldback mode and

provides excellent efficiency at light loads. When the power demand

reduces further, it enters into a skip mode to reduce the standby

consumption down to a no load condition.

Protection features include: a timer to detect an overload or a

short−circuit event, Overvoltage Protection with auto−recovery and

AC input line voltage detection (A version).

The ON proprietary integrated Over Power Protection (OPP) lets

you harness the maximum delivered power without affecting your

standby performance simply via external resistors.

For improved standby performance, the connection of an auxiliary

winding stops the DSS operation and helps to reduce input power

consumption below 50 mW at high line.

NCV106x can be seamlessly used both in non−isolated and in

isolated topologies.

Features

•Built−in 670 V MOSFET with RDS(on) of 34 W (NCV1060) and

11.4 W (NCV1063)

•Large Creepage Distance Between High−voltage Pins

•Current−Mode Fixed Frequency Operation – 60 kHz or 100 kHz

•Adjustable Peak Current: see below table

•Fixed Ramp Compensation

•Direct Feedback Connection for Non−isolated Converter

•Internal and Adjustable Over Power Protection (OPP) Circuit

•Skip−Cycle Operation at Low Peak Currents Only

•Dynamic Self−Supply: No Need for an Auxiliary Winding

•Internal 4 ms Soft−Start

•Auto−Recovery Output Short Circuit Protection with Timer−Based

Detection

•Auto−Recovery Overvoltage Protection with Auxiliary Winding

Operation

•Frequency Jittering for Better EMI Signature

•No Load Input Consumption < 50 mW

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MARKING DIAGRAMS

See detailed ordering and shipping information in the package

dimensions section on page 28 of this data sheet.

ORDERING INFORMATION

SOIC−10

CASE 751BQ

AD or BD SUFFIX

SOIC−16

CASE 751B−05

D SUFFIX

x = Power Switch Circuit

On−state Resistance

(0 = 34 W, 3 = 11.4 W)

f = Brown In (A = Yes, B = No)

yyy = Oscillator Frequency

(060 = 60 kHz, 100 = 100 kHz)

A = Assembly Location

L, WL = Wafer Lot

Y, YY = Year

W, WW = Work Week

G or G= Pb−Free Package

V1060fyyy

ALYWX

NCV1063fyyyG

AWLYWW

•Frequency Foldback to Improve Efficiency

at Light Load

•NCV Prefix for Automotive and Other

Applications Requiring Unique Site and

Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

•These Devices are Pb−Free and are RoHS

Compliant

Typical Applications

•Auxiliary & Standby Isolated Power Sup-

plies for HEV/EV

NCV1060, NCV1063

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Table 1. PRODUCT INFORMATION & INDICATIVE MAXIMUM OUTPUT POWER

Product RDS(on) IIPK(0)

230 Vac + 15% 85 − 265 Vac

Adapter Open Frame Adapter Open Frame

NCV1060 60 kHz 34 W300 mA 2.9 W 7.2 W 1.7 W 4.1 W

NCV1063 100 kHz 11.4 W780 mA 6.9 W 17.1 W 3.7 W 8.6 W

NOTE: Informative values only, with Tamb = 25°C, Tcase = 100°C, SOIC−10 package for NCV1060 and SOIC−16 package for NCV1063,

Self supply via Auxiliary winding and circuit mounted on minimum copper area as recommended.

SOIC−16

DRAIN

N.C.

GND

VCC

LIM/OPP

COMP

SOIC−10

DRAIN

GND

VCC

LIM/OPP

COMP DRAIN

Figure 1. Pin Connections

Table 2. PIN FUNCTION DESCRIPTION

Pin No

Pin Name Function Pin Description

SOIC 10 SOIC 16

1 1−4 GND The IC Ground

2 5 VCC Powers the Internal

Circuitry

This pin is connected to an external capacitor. The VDD includes an

auto−recovery over voltage protection

3 6 LIM/OPP Ipeak Set / Over

Power Limitation

The current drown from the pin decreases Ipeak of the primary

winding. If resistive divider from the auxiliary winding is connected to

this pin it sets the OPP compensation level (it diminishes the peak

current.)

4 7 FB Feedback Signal

Input

This is the inverting input of the trans conductance error amplifier. It

is normally connected to the switching power supply output through

a resistor divider

5 8 Comp Compensation The error amplifier output is available on this pin. The network

connected between this pin and ground adjusts the regulation loop

bandwidth. Also, by connecting an opto−coupler to this pin, the peak

current set point is adjusted accordingly to the output power demand

9−12 This un−connected pin ensures adequate creepage distance

6−10 13−16 Drain Drain Connection The internal drain MOSFET connection

NCV1060, NCV1063

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Table 3. TYPICAL APPLICATIONS

•If the output voltage is above

9.0 V typ. (between VCC(on)

level and VOVP level) VCC is

supplied from output via D2

•If the output voltage is below

9.0 V, D2 is redundant, the IC

is supplied from DSS

•R2 limits maximum output

power (can be omitted if not

required)

•Direct feedback, resistive

divider formed by R3, R4 sets

output voltage

•If the output voltage is above

9.0 V typ. (between VCC(on)

level and VOVP level) VCC is

supplied from output via D3

•If the output voltage is below

9.0 V, D3 and C5 are

redundant, the IC is supplied

from DSS

•R2 limits maximum output

power (can be omitted if not

required)

•Optocoupler feedback

Typical Non−isolated Application – Buck Converter

•If the output voltage is above

9.0 V typ. between VCC(ON)

level and VOVP level − VCC

supplied from output via D2

•R2 limits maximal output

power

•Direct feedback, resistive

divider formed by R3, R4 sets

output voltage

•VCC supplied from DSS

•Output voltage is below 9.0 V

typ.

•LIM/OPP pin floating − no limit

output power

•Direct feedback, resistive

divider formed by R2, R3 sets

output voltage

Typical Non−isolated Application – Buck−Boost Converter

NCV1060, NCV1063

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Table 3. TYPICAL APPLICATIONS (continued)

•VCC supplied from DSS

•Output voltage is below 9.0 V

typ.

•LIM/OPP pin floating − no limit

output power

•Resistive divider formed by R2,

R3 sets output voltage

•If the output voltage is above

9.0 V typ. between VCC(ON)

level and VOVP level − VCC

supplied from output via D4

•LIM/OPP pin floating − no limit

output power

•Resistive divider formed by R2,

R3 sets output voltage

Typical Non−isolated Application – Flyback Converter

•VCC supplied from auxiliary

winding

•Resistive divider formed by R2,

R3 sets output power limit and

over power protection

•Optocoupler feedback, resis-

tive divider formed by R6, R7

sets output voltage

Typical Isolated Application – Flyback Converter

NCV1060, NCV1063

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LIM/OPP

COMP

GND

DRAIN

VCC

Management Reset

UVLO

Vdd

tSCP

Ipflag

SCP

trecovery

80−

ms Filter

Line

Detection

OFF UVLO

RCOMP(up)

UVLO

TSD

LEB

Soft−Start

Reset

Reset SS as recoving from

SCP, TSD, VCC OVP or UVLO

ICOMP to CS setpoint

IFreeze Ipk (0)

VCC

OSC Sawtooth

Foldback

LineOK

Sawtooth

Ipflag

Ramp

compensation

OFF

VCC

OVP

SKIP = ”1” èShut down some

blocks to reduce consumption

SKIP

ILMOP

VLMOP

ILMDEC

ILMOP

PKL

IFB

VCOMP (REF )

ICOMPskip

ICOMPfault

ILMOP (min) ILMOP (max )

Jittering

VOVP

FB/COMP

Processing

Figure 2. Simplified Internal Circuit Architecture

NCV1060, NCV1063

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Table 4. MAXIMUM RATING TABLE (All voltages related to GND terminal)

Rating Symbol Value Unit

Power supply voltage, VCC pin, continuous voltage VCC −0.3 to 20 V

Voltage on all pins, except Drain and VCC pin Vinmax −0.3 to 10 V

Drain voltage BVdss −0.3 to 670 V

Maximum Current into VCC pin ICC 10 mA

Drain Current Peak during Transformer Saturation (TJ = 150°C, Note 2):

NCV1060

NCV1063

Drain Current Peak during Transformer Saturation (TJ = 125°C, Note 2):

NCV1060

NCV1063

Drain Current Peak during Transformer Saturation (TJ = 25°C, Note 2):

NCV1060

NCV1063

IDS(PK)

300

850

335

950

520

1500

Thermal Resistance Junction−to−Air – SOIC10 with 200 mm@ of 35−m copper area RθJA 132 °C/W

Thermal Resistance Junction−to−Air – SOIC16 with 200 mm@ of 35−m copper area RθJA 104 °C/W

Junction Temperature Range TJ−40 to +150 °C

Storage Temperature Range Tstg −60 to +150 °C

Human Body Model ESD Capability (All pins except HV pin) per AEC−Q100−002

(JESD22−A114F)

HBM 2 kV

Charged−Device Model ESD Capability per AEC−Q100−11(JESD22−C101E) CDM 1 kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

2. Maximum drain current IDS(PK) is obtained when the transformer saturates. It should not be mixed with short pulses that can be seen at turn

on. Figure 3 below provides spike limits the device can tolerate.

Figure 3. Spike Limits

NCV1060, NCV1063

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Table 5. ELECTRICAL CHARACTERISTICS

(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 14 V unless otherwise noted)

Symbol Rating Pin Min Typ Max Unit

SUPPLY SECTION AND VCC MANAGEMENT

VCC(on) VCC increasing level at which the switcher starts operation 2 (5) 8.4 9.0 9.5 V

VCC(min) VCC decreasing level at which the HV current source restarts 2 (5) 7.0 7.5 7.8 V

VCC(off) VCC decreasing level at which the switcher stops operation (UVLO) 2 (5) 6.7 7.0 7.2 V

ICC1 Internal IC consumption, NCV1060 switching at 60 kHz, LIM/OPP = 0 A

Internal IC consumption, NCV1060 switching at 100 kHz, LIM/OPP = 0 A

Internal IC consumption, NCV1063 switching at 60 kHz, LIM/OPP = 0 A

Internal IC consumption, NCV1063 switching at 100 kHz, LIM/OPP = 0 A

2 (5) −

−

0.92

0.97

0.99

1.07

−

ICCskip Internal IC consumption, COMP is 0 V (No switching on MOSFET) 2 (5) −340 −mA

POWER SWITCH CIRCUIT

RDS(on) Power Switch Circuit on−state resistance

NCV1060 (Id = 50 mA)

Tj = 25°C

Tj = 125°C

NCV1063 (Id = 50 mA)

Tj = 25°C

Tj = 125°C

7, 8

(6−10)

(13−16) −

−

11.4

14.0

BVDSS Power Switch Circuit & Startup breakdown voltage

(ID(off) = 120 mA, Tj = 25°C)

7, 8

(6−10)

(13−16)

670 − − V

IDSS(off) Power Switch & Startup breakdown voltage off−state leakage current

Tj = 125°C (Vds = 670 V)

7, 8

(6−10)

(13−16)

−84 −mA

Switching characteristics (RL = 50 W, VDS set for Idrain = 0.7 x Ilim)

Turn−on time (90% − 10%)

Turn−off time (10% − 90%)

7, 8

(6−10)

(13−16)

−

ton(min) Minimum on time

NCV1060

NCV1063

7, 8

(6−10)

(13−16)

−

200

230

−

INTERNAL START−UP CURRENT SOURCE

Istart1 High−voltage current source, VCC = VCC(on) – 200 mV 7, 8

(6−10)

(13−16)

5 8 12 mA

Istart2 High−voltage current source, VCC = 0 V 7, 8

(6−10)

(13−16)

−0.5 −mA

VCCTH VCC Transient level for Istart1 to Istart2 toggling point 2 (5) −1.4 −V

Vstart(min) Minimum startup voltage, VCC = 0 V 7, 8

(6−10)

(13−16)

21 V

CURRENT COMPARATOR

IIPK Maximum internal current setpoint at 50% duty cycle

FB = 2 V, LIM/OPP = 0 mA, Tj = 25°C

NCV1060

NCV1063

−

250

650

−

IIPK(0) Maximum internal current setpoint at beginning of switching cycle

FB = 2 V, LIM/OPP pin open Tj = 25°C

NCV1060

NCV1063

−

268

702

300

780

332

858

3. The final switch current is: IIPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage,

LP the primary inductor in a flyback, and tprop the propagation delay.

4. Oscillator frequency is measured with disabled jittering.

NCV1060, NCV1063

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Table 5. ELECTRICAL CHARACTERISTICS (continued)

(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 14 V unless otherwise noted)

Symbol UnitMaxTypMinPinRating

CURRENT COMPARATOR

IIPKSW Final switch current with a primary slope of 200 mA/ms,

FSW = 60 kHz (Note 3), LIM/OPP pin open

NCV1060

NCV1063

−

330

740

−

IIPKSW Final switch current with a primary slope of 200 mA/ms,

FSW = 100 kHz (Note 3), LIM/OPP pin open

NCV1060

NCV1063

−

320

710

−

ILMDEC Maximum internal current setpoint at beginning of switching cycle

FB = 2 V, LIM/OPP = −285 mA, Tj = 25°C

NCV1060

NCV1063

−

128

312

−

tSS Soft−start duration (guaranteed by design) − − 4−ms

tprop Propagation delay from current detection to drain OFF state − − 70 −ns

tLEB Leading Edge Blanking Duration

NCV1060

NCV1063

−

130

160

−

INTERNAL OSCILLATOR

fOSC Oscillation frequency, 60 kHz version, Tj = 25°C (Note 4) −54 60 66 kHz

fOSC Oscillation frequency, 100 kHz version, Tj = 25°C (Note 4) −90 100 110 kHz

fjitter Frequency jittering in percentage of fOSC − − ±6−%

fswing Jittering swing frequency − − 300 −Hz

Dmax Maximum duty−cycle −62 66 72 %

ERROR AMPLIFIER SECTION

VREF Voltage Feedback Input (VCOMP = 2.5 V) 4 (7) 3.2 3.3 3.4 V

IFB Input Bias Current (VFB = 3.3 V) 4 (7) −1−mA

GMTransconductance 5 (8) 2 mS

IOTAlim OTA maximum current capability (VFB > VOTAen)5 (8) ±150 mA

VOTAen FB voltage to disable OTA 4 (7) 0.7 1.3 1.7 V

COMPENSATION SECTION

ICOMPfault COMP current for which Fault is detected 5 (8) − −40 −mA

ICOMP100% COMP current for which internal current set−point is 100% (IIPK(0))5 (8) − −44 −mA

ICOMPfreeze COMP current for which internal current setpoint is:

IFreeze1 or 2 (NCV1060/3)

5 (8) − −80 −mA

VCOMP(REF) Equivalent pull−up voltage in linear regulation range

(Guaranteed by design)

5 (8) −2.7 −V

RCOMP(up) Equivalent feedback resistor in linear regulation range

(Guaranteed by design)

5 (8) −17.7 −kΩ

VLMOP Voltage on LIM/OPP pin @ ILMOP = −35 mA

Voltage on LIM/OPP pin @ ILMOP = −250 mA, Tj = 25°C

3 (6) 1.40

1.28

1.50

1.35

1.60

1.42

ILMOP Maximum current from LIM/OPP pin 3 (6) −330 −420 mA

ILMOP(min) Current at which LIM/OPP starts to decrease IPEAK 3 (6) −20 −26 −32 mA

ILMOP(max) Current at which LIM/OPP stops to decrease IPEAK 3 (6) −285 mA

ILMOP(neg) Negative Active Clamp Voltage (ILMOP = −2.5 mA) 3 (6) −0.7 V

3. The final switch current is: IIPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage,

LP the primary inductor in a flyback, and tprop the propagation delay.

4. Oscillator frequency is measured with disabled jittering.

NCV1060, NCV1063

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Table 5. ELECTRICAL CHARACTERISTICS (continued)

(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 14 V unless otherwise noted)

Symbol UnitMaxTypMinPinRating

COMPENSATION SECTION

ILMOP(pos) Positive Active Clamp (Guaranteed by design) 3 (6) 2.5 mA

FREQUENCY FOLDBACK & SKIP

ICOMPfold Start of frequency foldback COMP pin current level 5 (8) − −68 −mA

ICOMPfold(end) End of frequency foldback COMP pin current level, fsw = fmin 5 (8) − −100 −mA

fmin The frequency below which skip−cycle occurs −21 25 29 kHz

ICOMPskip The COMP pin current level to enter skip mode 5 (8) − −120 −mA

IFreeze1 Internal minimum current setpoint (ICOMP = ICOMPFreeze) in NCV1060 −110 −mA

IFreeze2 Internal minimum current setpoint (ICOMP = ICOMPFreeze) in NCV1063 −270 −mA

RAMP COMPENSATION

Sa(60) The internal ramp compensation @ 60 kHz:

NCV1060

NCV1063

−

8.4

15.6

−

mA/ms

Sa(100) The internal ramp compensation @ 100 kHz:

NCV1060

NCV1063

−

mA/ms

PROTECTIONS

tSCP Fault validation further to error flag assertion −35 48 −ms

trecovery OFF phase in fault mode − − 400 −ms

VOVP VCC voltage at which the switcher stops pulsing 2 (5) 17.0 18.0 18.8 V

tOVP The filter of VCC OVP comparator − − 80 −ms

VHV(EN) The drain pin voltage above which allows MOSFET operate, which is

detected after TSD, UVLO, SCP, or VCC OVP mode. (A version only)

7,8

(6−10)

(13−16)

67 87 110 V

TEMPERATURE MANAGEMENT

TSD Temperature shutdown (Guaranteed by design) −150 163 −°C

TSDhyst Hysteresis in shutdown (Guaranteed by design) − − 20 −°C

3. The final switch current is: IIPK(0) / (Vin/LP + Sa) x Vin/LP + Vin/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage,

LP the primary inductor in a flyback, and tprop the propagation delay.

4. Oscillator frequency is measured with disabled jittering.

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

NCV1060, NCV1063

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TYPICAL CHARACTERISTICS

Figure 4. VCC(on) vs. Temperature Figure 5. VCC(min) vs. Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

100806040200−20−40

8.85

8.90

8.95

9.00

9.05

9.10

9.15

100806040200−20−40

7.32

7.34

7.38

7.42

7.46

7.48

7.52

Figure 6. VCC(off) vs. Temperature Figure 7. IDSS(off) vs. Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

100806040200−20−40

6.88

6.90

6.92

6.94

6.96

6.98

7.00

100806040200−20−40

100

200

300

400

600

700

800

Figure 8. ICC1 60 kHz vs. Temperature Figure 9. ICC1 100 kHz vs. Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

100806040200−20−40

0.88

0.89

0.90

0.91

0.92

0.93

0.94

0.95

100806040200−20−40

0.92

0.93

0.94

0.95

0.96

0.97

0.98

0.99

VOLTAGE (V)

CURRENT (mA)

120 120

120

7.36

7.40

7.44

7.50

120

500

120 120

NCV1060, NCV1063

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TYPICAL CHARACTERISTICS

Figure 10. IIPK(0)1060 vs. Temperature Figure 11. IIPK(0)1063 vs. Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

100806040200−20−40

288

292

294

296

300

304

306

310

100806040200−20−40

720

725

735

740

750

755

765

770

Figure 12. Istart1 vs. Temperature Figure 13. Istart2 vs. Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

100806040200−20−40

0.1

0.2

0.3

0.4

0.5

0.6

Figure 14. RDS(on)1060 vs. Temperature Figure 15. RDS(on)1063 vs. Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

100806040200−20−40

CURRENT (mA)

RESISTIVITY (W)

120

290

298

302

308

120

730

745

760

120

120120

NCV1060, NCV1063

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TYPICAL CHARACTERISTICS

Figure 16. fOSC60 vs. Temperature Figure 17. fOSC100 vs. Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

100806040200−20−40

55.5

56.0

57.0

57.5

58.0

58.5

59.5

60.0

100806040200−20−40

100

Figure 18. Ifreeze1060 vs. Temperature Figure 19. Ifreeze1063 vs. Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

100806040200−20−40

100

101

103

104

105

106

108

109

100806040200−20−40

256

258

262

264

266

268

272

274

Figure 20. D(max) vs. Temperature Figure 21. fmin vs. Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

100806040200−20−40

65.6

65.7

65.8

65.9

66.0

66.1

66.2

100806040200−20−40

24.4

24.6

24.8

25.0

25.2

25.4

25.6

25.8

FREQUENCY (kHz)

CURRENT (mA)

DUTY CYCLE (%)

FREQUENCY (kHz)

120

56.5

59.0

120

102

107

120

260

270

120 120

NCV1060, NCV1063

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TYPICAL CHARACTERISTICS

Figure 22. trecovery vs. Temperature Figure 23. tSCP vs. Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

100806040200−20−40

385

390

400

405

410

415

425

430

100806040200−20−40

Figure 24. VOVP vs. Temperature Figure 25. VHV(EN) vs. Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

100806040200−20−40

17.4

17.5

17.6

17.8

17.9

18.0

18.1

18.2

100806040200−20−40

Figure 26. VREF vs. Temperature Figure 27. VOTAen vs. Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

100806040200−20−40

3.24

3.26

3.27

3.28

3.30

3.31

3.33

3.34

100806040200−20−40

0.2

0.4

0.6

0.8

1.2

1.4

1.6

TIME (ms)

VOLTAGE (V)

120

395

420

120

17.7

120

3.25

3.29

3.32

120

1.0

NCV1060, NCV1063

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TYPICAL CHARACTERISTICS

Figure 28. Drain Current Peak during Transformer

Saturation vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−50

1.0

1.5

2.5

IDS(PK) (A)

150

0.5

2.0

NCV1063

NCV1060

Figure 29. Breakdown Voltage vs. Temperature

TEMPERATURE (°C)

1006040200−20−40

0.925

0.950

0.975

1.025

1.050

1.100

BVDSS/BVDSS (25°C)(−)

125

1.000

1.075

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APPLICATION INFORMATION

Introduction

The NCV106X offers a complete current−mode control

solution. The component integrates everything needed to

build a rugged and cost effective Switch−Mode Power

Supply (SMPS) featuring low standby power. The Quick

Selection Table, Table 6, details the differences between

references, mainly peak current setpoints, RDS(on) value and

operating frequency.

•Current−mode Operation: the controller uses

current−mode control architecture.

•670 V –_ Power MOSFET: Due to ON Semiconductor

Very High Voltage Integrated Circuit technology, the

circuit hosts a high−voltage power MOSFET featuring

a 34 W or 11.4 W RDS(on) – Tj = 25°C. This value lets

the designer build a power supply up to 8.6 W or

17.1 W operated on universal mains. An internal

current source delivers the startup current, necessary to

crank the power supply.

•Dynamic Self−supply: Due to the internal high voltage

current source, this device could be used in the

application without the auxiliary winding to provide

supply voltage.

•Short Circuit Protection: by permanently monitoring

the COMP line activity, the IC is able to detect the

presence of a short−circuit, immediately reducing the

output power for a total system protection. A tSCP timer

is started as soon as the COMP current is below

threshold, ICOMPfault, which indicates the maximum

peak current. If at the end of this timer the fault is still

present, then the device enters a safe, auto−recovery

burst mode, affected by a fixed timer recurrence,

trecovery. Once the short has disappeared, the controller

resumes and goes back to normal operation.

•Built−in VCC Over Voltage Protection: when the

auxiliary winding is used to bias the VCC pin (no DSS),

an internal comparator is connected to VCC pin. In case

the voltage on the pin exceeds a level of VOVP (18 V

typically), the controller immediately stops switching

and waits a full timer period (trecovery) before

attempting to restart. If the fault is gone, the controller

resumes operation. If the fault is still there, e.g. a

broken opto−coupler, the controller protects the load

through a safe burst mode.

•Line Detection: An internal comparator monitors the

drain voltage as recovering from one of the following

situations:

♦Short Circuit Protection,

♦VCC OVP is confirmed,

♦UVLO,

♦TSD

•If the drain voltage is lower than the internal threshold

(VHV(EN)), the internal power switch is inhibited. This

avoids operating at too low ac input. This is also called

brown−in function in some fields. For applications not

using standard AC mains (24 Vdc industrial bus for

instance), the B version doesn’t incorporate this line

detection and let the device start as soon as voltage

supply reaches Vstart(min).

•Frequency Jittering: an internal low−frequency

modulation signal varies the pace at which the

oscillator frequency is modulated. This helps spreading

out energy in conducted noise analysis. To improve the

EMI signature at low power levels, the jittering remains

active in frequency foldback mode.

•Soft−start: a 4 ms soft−start ensures a smooth startup

sequence, reducing output overshoots.

•Frequency Foldback Capability: a continuous flow of

pulses is not compatible with no−load/light−load

standby power requirements. To excel in this domain,

the controller observes the COMP pin current

information and when it reaches a level of ICOMPfold,

the oscillator then starts to reduce its switching

frequency as the feedback current continues to increase

(the power demand continues to reduce). It can go

down to 25 kHz (typical) reached for a feedback level

of ICOMPfold(end) (100 mA roughly). At this point, if the

power continues to drop, the controller enters classical

skip−cycle mode.

•Skip: if SMPS naturally exhibits a good efficiency at

nominal load, it begins to be less efficient when the

output power demand diminishes. By skipping

un−needed switching cycles, the NCV106X drastically

reduces the power wasted during light load conditions.

•Ipeak Set: If current in range 26 mA and 285 mA is

drawn from the pin, the peak current is proportionally

reduced down to 40% of its original value. This feature

enables to designer to set up the peak current to the

value which is ideal for the application.

By routing a portion of the negative voltage present during

the on−time on the auxiliary winding to the LIM/OPP pin,

the user has a simple and non−dissipative means to alter the

maximum peak current setpoint as the bulk voltage

increases.

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Startup Sequence

When the power supply is first powered from the mains

outlet, the internal current source (typically 8.0 mA) is

biased and charges up the VCC capacitor from the drain pin.

Once the voltage on this VCC capacitor reaches the VCC(on)

level (typically 9.0 V), the current source turns off and

pulses are delivered by the output stage: the circuit is awake

and activates the power MOSFET if the bulk voltage is

above VHV(EN) level (87 V typically) for A version and if

bulk voltage is above Vstart(min) (21 V dc) for B version.

There is no disable level for drain pin voltage, the device will

stop switching when the input voltage is removed and

sub−sequentially the VCC reaches the VCC(OFF) level, or

tSCP timer elapses. Figure 30 details the simplified internal

circuitry.

+−

VCC(on)

VCC(min)

Istart1

Vbulk

CVCC

Rlimit

ICC1

VCC > 18 V ?

OVP fault

Drain

+−

VOVP

Figure 30. The Internal Arrangement of the Start−up Circuitry

Being loaded by the circuit consumption, the voltage on

the VCC capacitor goes down. When VCC is below VCC(min)

level (7.5 V typically), it activates the internal current source

to bring VCC toward VCC(on) level and stops again: a cycle

takes place whose low frequency depends on the VCC

capacitor and the IC consumption. A 1.5 V ripple takes place

on the VCC pin whose average value equals (VCC(on) +

VCC(min))/2. Figure 31 portrays a typical operation of the

DSS.

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012345678910

VCC

9.0 V

VCCTH

Startup Duration

Figure 31. The Charge/Discharge Cycle over a 1 mF VCC Capacitor

Device

Internal

Pulses

7.5 V

TIME (ms)

V (V)

As one can see, even if there is auxiliary winding to provide

energy for VCC, it happens that the device is still biased by

DSS during start−up time or some fault mode when the

voltage on auxiliary winding is not ready yet. The VCC

capacitor shall be dimensioned to avoid VCC crosses VCC(off)

level, which stops operation. The ΔV between VCC(min) and

VCC(off) is 0.5 V. There is no current source to charge VCC

capacitor when driver is on, i.e. drain voltage is close to zero.

Hence the VCC capacitor can be calculated using

CVCC wICC1 @Dmax

fOSC @DV(eq. 1)

Take the 60 kHz device as an example. CVCC should be

above

0.8 m @72%

54 kHz @0.5 +21 nF.

A margin that covers the temperature drift and the voltage

drop due to switching inside FET should be considered, and

thus a capacitor above 0.1 mF is appropriate.

The VCC capacitor has only a supply role and its value

does not impact other parameters such as fault duration or

the frequency sweep period for instance. As one can see on

Figure 30, an internal OVP comparator, protects the

switcher against lethal VCC runaways. This situation can

occur if the feedback loop optocoupler fails, for instance,

and you would like to protect the converter against an over

voltage event. In that case, the over voltage protection

(OVP) circuit and immediately stops the output pulses for

trecovery duration (400 ms typically). Then a new start−up

attempt takes place to check whether the fault has

disappeared or not. The OVP paragraph gives more design

details on this particular section.

Fault Condition – Short−circuit on VCC

In some fault situations, a short−circuit can purposely

occur between VCC and GND. In high line conditions (VHV

= 370 VDC) the current delivered by the startup device will

seriously increase the junction temperature. For instance,

since Istart1 equals 5 mA (the min corresponds to the highest

Tj), the device would dissipate 370 x 5 m = 1.85 W. To avoid

this situation, the controller includes a novel circuitry made

of two startup levels, Istart1 and Istart2. At power−up, as long

as VCC is below a 1.4 V level, the source delivers Istart2

(around 500 mA typical), then, when VCC reaches 1.4 V, the

source smoothly transitions to Istart1 and delivers its nominal

value. As a result, in case of short−circuit between VCC and

GND, the power dissipation will drop to 370 x 500 m =

185 mW. Figure 31 portrays this particular behavior.

The first startup period is calculated by the formula C x V

= I x t, which implies a 1 m x 1.4 / 500 m = 2.8 ms startup time

for the first sequence. The second sequence is obtained by

toggling the source to 8 mA with a delta V of VCC(on) –

VCCTH = 9.0 – 1.4 = 7.6 V, which finally leads to a second

startup time of 1 m x 7.6 / 8 m = 0.95 ms. The total startup

time becomes 2.8 m + 0.95 m = 3.75 ms. Please note that this

calculation is approximated by the presence of the knee in

the vicinity of the transition.

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Fault Condition – Output Short−circuit

As soon as VCC reaches VCC(on), drive pulses are

internally enabled. If everything is correct, the auxiliary

winding increases the voltage on the VCC pin as the output

voltage rises. During the start−sequence, the controller

smoothly ramps up the peak drain current to maximum

setting, i.e. IIPK, which is reached after a typical period of

4 ms. When the output voltage is not regulated, the current

coming through COMP pin is below ICOMPfault level (40 mA

typically), which is not only during the startup period but

also anytime an overload occurs, an internal error flag is

asserted, Ipflag, indicating that the system has reached its

maximum current limit set point. The assertion of this flag

triggers a fault counter tSCP (48 ms typically). If at counter

completion, Ipflag remains asserted, all driving pulses are

stopped and the part stays off in trecovery duration (about

400 ms). A new attempt to re−start occurs and will last

48 ms providing the fault is still present. If the fault still

affects the output, a safe burst mode is entered, affected by

a low duty−cycle operation (11%). When the fault

disappears, the power supply quickly resumes operation.

Figure 32 depicts this particular mode:

Figure 32. In Case of Short−circuit or Overload, the NCV106X Protects itself and the Power Supply via a Low

Frequency Burst Mode. The VCC is Maintained by the Current Source and Self−supplies the Controller

IpFlag

Timer

DRV

internal

48 ms typ.

400 ms typ.

Fault

Open loop FB

VCC(on)

VCC(min)

VCC

VCOMP

Auto−recovery Over Voltage Protection

The particular NCV106X arrangement offers a simple

way to prevent output voltage runaway when the

optocoupler fails. As Figure 33 shows, a comparator

monitors the VCC pin. If the auxiliary pushes too much

voltage into the CVCC capacitor, then the controller

considers an OVP situation and stops the internal drivers.

When an OVP occurs, all switching pulses are permanently

disabled. After trecovery delay, it resumes the internal drivers.

If the failure symptom still exists, e.g. feedback

opto−coupler fails, the device keeps the auto−recovery OVP

mode. It is recommended insertion of a resistor (Rlimit)

between the auxiliary dc level and the VCC pin to protect the

IC against high voltage spikes, which can damage the IC,

and to filter out the Vcc line to avoid undesired OVP

activation. Rlimit should be carefully selected to avoid

triggering the OVP as we discussed, but also to avoid

disturbing the VCC in low / light load conditions.

Self−supplying controllers in extremely low standby

applications often puzzles the designer. Actually, if a SMPS

operated at nominal load can deliver an auxiliary voltage of

an arbitrary 16 V (Vnom), this voltage can drop below 10 V

(Vstby) when entering standby. This is because the

recurrence of the switching pulses expands so much that the

low frequency re−fueling rate of the VCC capacitor is not

enough to keep a proper auxiliary voltage.

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VOVP GND

VCC

Drain

Shut down

Internal DRV

80 ms

filter

VCC ( on )

=9.0V

VCC (min ) =7.5V

Istart 1

Rlimit

CVCC CAUX NAUX

Figure 33. A More Detailed View of the NCV106X Offers Better Insight on how to Properly Wire

an Auxiliary Winding

VCC

ICOMP

TIMER

DRV

internal

VCC(min)

VCC(on)

VOVP

Fault level

48 ms typ.

400 ms typ.

Figure 34. Describes the Main Signal Variations when the Part Operates in Auto−recovery OVP

Soft−start

The NCV106X features a 4 ms soft−start which reduces

the power−on stress but also contributes to lower the output

overshoot. Figure 35 shows a typical operating waveform.

The NCV106X features a novel patented structure which

offers a better soft−start ramp, almost ignoring the start−up

pedestal inherent to traditional current−mode supplies.

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Drain current

VCC VCCON

Max Ip

4ms

0V (fresh PON)

Figure 35. The 4 ms Soft−start Sequence

Jittering

Frequency jittering is a method used to soften the EMI

signature by spreading the energy in the vicinity of the main

switching component. The NCV106X offers a ±6%

deviation of the nominal switching frequency. The sweep

sawtooth is internally generated and modulates the clock up

and down with a fixed frequency of 300 Hz. Figure 36 shows

the relationship between the jitter ramp and the frequency

deviation. It is not possible to externally disable the jitter.

60 kHz

63.6 kHz

56.4 kHz

Jitter ramp

Internal

sawtooth

adjustable

Figure 36. Modulation Effects on the Clock Signal by the Jittering Sawtooth

Line Detection (for A version only)

An internal comparator monitors the drain voltage as

recovering from one of the following situations:

•Short Circuit Protection,

•VCC OVP is confirmed,

•UVLO

•TSD

If the drain voltage is lower than the internal threshold

VHV(EN) (87 Vdc typically), the internal power switch is

inhibited. This avoids operating at too low ac input.

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Frequency Foldback

The reduction of no−load standby power associated with

the need for improving the efficiency, requires to change the

traditional fixed−frequency type of operation. This device

implements a switching frequency foldback when the

COMP current passes above a certain level, ICOMPfold, set

around 68 mA. At this point, the oscillator enters frequency

foldback and reduces its switching frequency.

The internal peak current set−point is following the

COMP current information until its level reaches IFreeze.

Below this value, the peak current setpoint is frozen to 30%

of the IPK(0). The only way to further reduce the transmitted

power is to diminish the operating frequency down to Fmin

(25 kHz typically). This value is reached at a COMP current

level of ICOMPfold(end) (100 mA typically). Below this point,

if the output power continues to decrease, the part enters skip

cycle for the best noise−free performance in no−load

conditions. Figure 37 and Figure 38 depict the adopted

scheme for the part.

Figure 37. By Observing the Current on the COMP Pin, the Controller Reduces

its Switching Frequency for an Improved Performance at Light Load

100

110

50 60 70 80 90 100

Frequency [kHz]

ICOMP [mA]

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Figure 38. Ipk Set−point is Frozen at Lower Power Demand

100

200

300

400

500

600

700

800

900

40 50 60 70 80 90 100 110

Current set point [mA]

ICOMP [mA]

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Figure 39. Ipk Set−point is Frozen at Lower Power Demand (ILMOP ≥ 285 mA)

100

150

200

250

300

350

40 50 60 70 80 90 100 110

Current set point [mA]

ICOMP [mA]

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Feedback and Skip

Figure 40 depicts the relationship between COMP pin

voltage and current. The COMP pin operates linearly as the

absolute value of COMP current (ICOMP) is above 40 mA. In

this linear operating range, the dynamic resistance is

17.7 kW typically (RCOMP(up)) and the effective pull up

voltage is 2.7 V typically (VCOMP(REF)). When ICOMP is

decreases, the COMP voltage will increase to 3.2 V.

Figure 40. COMP Pin Voltage vs. Current

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-180 -160 -140 -120 -100 -80 -60 -40 -20 0

VCOMP [V]

ICOMP [μA]

Figure 41 depicts the skip mode block diagram. When the

COMP current information reaches ICOMPskip, the internal

clock setting the flip−flop is blanked and the internal

consumption of the controller is decreased. The hysteresis of

internal skip comparator is minimized to lower the ripple of

the auxiliary voltage for VCC pin and VOUT of power supply

during skip mode. It easies the design of VCC over load

range.

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Jittering

OSC

Foldback

SKIP CS comparator

DRV stage

COMP

VCOMP(REF)

RCOMP(UP)

ICOMPskip

Figure 41. Skip Cycle Schematic

Ilimit and OPP Function

The function makes the integrated circuit more flexible. The current drawn out of LIM/OPP pin defines the current set point.

Figure 42. Ipk Set−point Dependence on ILMOP Current

100

200

300

400

500

600

700

800

900

0 50 100 150 200 250 300 350

Current set point [mA]

ILMOP [mA]

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There are several known ways to implement Over Power

Protection (OPP), all suffering from particular problems.

These problems range from the added consumption burden

on the converter or the skip−cycle disturbance brought by

the current−sense offset. A way to reduce the power

capability at high line is to capitalize on the negative voltage

swing present on the auxiliary diode anode. During the

power switch on−time, this point dips to –NVin , N being the

turns ratio between the primary winding and the auxiliary

winding. The negative plateau on auxiliary winding will

have an amplitude dependant on the input voltage. Resistors

ROPPU and ROPPL (Figure 43) define current drawn from

LIM/OPP and the negative voltage on auxiliary winding.

The negative voltage is tied up with bulk voltage, so the

higher the bulk voltage is, the deeper is the negative voltage

on auxiliary winding, the higher current is drawn from

LIM/OPP pin and the lower the peak current is. During the

internal MOSFET off period, voltage on auxiliary winding

is positive, but the IC ignores the LIM/OPP current. The

positive LIM/OPP current has no influence on proper IC

function.

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ICOMP to CS setpoint

IFreeze Ipk(0 )

Vramp + Vsense

OSC

ILMOP

ILMDEC

ILMOP

025 mA250 mA

IPKL

ICOMP

MOSFET

LIM/ OPP

VCC

ROPPU

ROPPL

Aux

winding

Figure 43. The OPP Circuitry Affects the Maximum Peak Current Set Point

Ramp Compensation and Ipk Set−point

In order to allow the NCV106X to operate in CCM with

a duty cycle above 50%, a fixed slope compensation is

internally applied to the current−mode control.

Here we got a table of the ramp compensation, the initial

current set point, and the final current set−point of different

versions of switcher.

NCV1060 NCV1063

fsw 60 kHz 100 kHz 60 kHz 100 kHz

Sa8.4 mA/ms14 mA/ms15.6 mA/ms26 mA/ms

Ipk(Duty

=50%)

250 mA 650 mA

Ipk(0) 300 mA 780 mA

Figure 44 depicts the variation of IPK set−point vs. the

power switcher duty ratio, which is caused by the internal

ramp compensation.

Figure 44. IPK Set−point Varies with Power Switch on Time, which is Caused by the Ramp Compensation

100

200

300

400

500

600

700

800

900

0% 10% 20% 30% 40% 50% 60% 70%

Ipk set-point [mA]

Dutty Ratio [%]

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FB Pin Function

The FB pin is used in non isolated SMPS application only.

Portion of the output voltage is connected into the pin. The

voltage is compared with internal VREF (3.3 V) using

Operation Transconductance Amplifier (Figure 45). The

OTAs output is connected to COMP pin. The OTA output is

accessible through the COMP pin and is used for the loop

compensation, usually an RC network. The current

capability of OTA is limited to −150 mA typically. The

positive current is defined by internal RCOMP(up) resistor

and VCOMP(ref) voltage. If FB path loop is broken (i.e. the FB

pin is disconnected), an internal current IFB (1 mA typ.) will

pull up the FB pin and the IC stops switching to avoid

uncontrolled output voltage increasing.

In isolated topology, the FB pin should be connected to

GND pin. In this configuration no current flows from OTA

to COMP pin (OTA is disabled) so the OTA has no influence

on regulation at all.

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COMP

RCOMP (up )

OTA

IFB

VCOMP ( REF )

VREF

IOTAlim

ICOMP

OTA out = 0 A

if FB = 0 V

Figure 45. FB Pin Connection

Design Procedure

The design of an SMPS around a monolithic device does

not differ from that of a standard circuit using a controller

and a MOSFET. However, one needs to be aware of certain

characteristics specific of monolithic devices. Let us follow

the steps:

Vin min = 90 Vac or 127 Vdc once rectified, assuming a low

bulk ripple

Vin max = 265 Vac or 375 Vdc

Vout = 12 V

Pout = 5 W

Operating mode is CCM

η = 0.8

1. The lateral MOSFET body−diode shall never be

forward biased, either during start−up (because of

a large leakage inductance) or in normal operation

as shown in Figure 46. This condition sets the

maximum voltage that can be reflected during toff.

As a result, the Flyback voltage which is reflected

on the drain at the switch opening cannot be larger

than the input voltage. When selecting

components, you thus must adopt a turn ratio

which adheres to the following equation:

N@ǒVout )VfǓtVin,min (eq. 2)

2. In our case, since we operate from a 127 V DC rail

while delivering 12 V, we can select a reflected

voltage of 120 V dc maximum. Therefore, the turn

ratio Np:Ns must be smaller than

Vreflect

Vout )Vf+120

12 )0.5 +9.6orNp:Nst9.6.

Here we choose N = 8 in this case. We will see later

on how it affects the calculation.

1.004M 1.011M 1.018M 1.025M 1.032M

−50.0

50.0

150

250

350

> 0 !!

Figure 46. The Drain−source Wave Shall always be Positive

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Figure 47. Primary Inductance Current

Evolution in CCM

3. Lateral MOSFETs have a poorly doped

body−diode which naturally limits their ability to

sustain the avalanche. A traditional RCD clamping

network shall thus be installed to protect the

MOSFET. In some low power applications, a

simple capacitor can also be used since

Vdrain,max +Vin )N@ǒVout )VfǓ)Ipeak @Lf

Ctot

Ǹ(eq. 3)

where Lf is the leakage inductance, Ctot the total

capacitance at the drain node (which is increased by

the capacitor you will wire between drain and

source), N the NP:NS turn ratio, Vout the output

voltage, Vf the secondary diode forward drop and

finally, Ipeak the maximum peak current. Worse case

occurs when the SMPS is very close to regulation,

e.g. the Vout target is almost reached and Ipeak is still

pushed to the maximum. For this design, we have

selected our maximum voltage around 650 V (at Vin

= 375 Vdc). This voltage is given by the RCD clamp

installed from the drain to the bulk voltage. We will

see how to calculate it later on.

4. Calculate the maximum operating duty−cycle for

this flyback converter operated in CCM:

dmax +N@ǒVout @VfǓ

N@ǒVout @VfǓ)Vin,min (eq. 4)

Vin,min

N@(Vout@Vf)

+0.44

5. To obtain the primary inductance, we have the

choice between two equations:

L+ǒVin @dǓ2

fsw @K@Pin

(eq. 5)

where K +DIL

ILavg

and defines the amount of ripple we want in CCM (see

Figure 47).

•Small K: deep CCM, implying a large primary

inductance, a low bandwidth and a large leakage

inductance.

•Large K: approaching DCM where the RMS losses are

worse, but smaller inductance, leading to a better

leakage inductance.

From Equation 6, a K factor of 1 (50% ripple), gives an

inductance of:

L+(127 @0.44)2

60k @1@5+10.04 mH

DIL+Vin @d

L@fsw +127 @0.44

10.04m @60k +92.8 mA peak to peak

The peak current can be evaluated to be:

Ipeak +Iavg

d)DIL

2+49.2 m

0.44 )92.8 m

2+158 mA

On IL, ILavg can also be calculated:

ILavg +Ipeak *DIL

2+158m *92.8m

2+111.6 mA

6. Based on the above numbers, we can now evaluate

the conduction losses:

Id,rms +d@ǒIpeak 2*Ipeak @DIL)DIL2

3Ǔ

+0.44 @ǒ0.1582*0.158 @0.0928 )0.09282

3Ǔ

+57 mA

If we take the maximum RDS(on) for a 125°C

junction temperature, i.e. 34 W, then conduction

losses worse case are:

Pcond +Id,rms 2@RDS(on) +110 mW

7. Off−time and on−time switching losses can be

estimated based on the following calculations:

Poff +

Ipeak @ǒVbulk )VclampǓ@toff

2TSW

+0.158 @(127 )100 @2)@10n

2@16.7 m

+15.5 mW

(eq. 6)

Where, assume the Vclamp is equal to 2 times of reflected

voltage.

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Pon +

Ivalley @ǒVbulk )N@(Vout )Vf)Ǔ@ton

6@TSW

+0.0464 @(127 )100) @10 n

6@16.7 m

+2.1 mW

(eq. 7)

It is noted that the overlap of voltage and current seen on

MOSFET during turning on and off duration is dependent on

the snubber and parasitic capacitance seen from drain pin.

Therefore the toff and ton in Equation 7 and Equation 8 have

to be modified after measuring on the bench.

8. The theoretical total power is then

117 + 15.5 + 2.1 = 127.6 mW

9. If the NCV106X operates at DSS mode, then the

losses caused by DSS mode should be counted as

losses of this device on the following calculation:

PDSS +ICC1 @Vin.max +0.8m @375 +300 mW (eq. 8)

MOSFET Protection

As in any Flyback design, it is important to limit the drain

excursion to a safe value, e.g. below the MOSFET BVdss

which is 670 V. Figure 48 a−b−c present possible

implementations:

Figure 48. a, b, c: Different Options to Clamp the Leakage Spike

Figure 48a: the simple capacitor limits the voltage

according to the lateral MOSFET body−diode shall never be

forward biased, either during start−up (because of a large

leakage inductance) or in normal operation as shown by

Figure 46. This condition sets the maximum voltage that can

be reflected during toff. As a result, the flyback voltage

which is reflected on the drain at the switch opening cannot

be larger than the input voltage. When selecting

components, you must adopt a turn ratio which adheres to

the following Equation 3. This option is only valid for low

power applications, e.g. below 5 W, otherwise chances exist

to destroy the MOSFET. After evaluating the leakage

inductance, you can compute C with (Equation 4). Typical

values are between 100 pF and up to 470 pF. Large

capacitors increase capacitive losses...

Figure 48b: the most standard circuitry is called the RCD

network. You calculate Rclamp and Cclamp using the

following formulae:

Rclamp +

2@Vclamp @ǒVclamp )N@(Vout )Vf)Ǔ

Lleak @Ileak 2@fsw (eq. 9)

Cclamp +

Vclamp

Vripple @fsw @Rclamp

Vclamp is usually selected 50−80 V above the reflected

value N x (Vout + Vf). The diode needs to be a fast one and

a MUR160 represents a good choice. One major drawback

of the RCD network lies in its dependency upon the peak

current. Worse case occurs when Ipeak and Vin are maximum

and Vout is close to reach the steady−state value.

Figure 48c: this option is probably the most expensive of

all three but it offers the best protection degree. If you need

a very precise clamping level, you must implement a zener

diode or a TVS. There are little technology differences

behind a standard zener diode and a TVS. However, the die

area is far bigger for a transient suppressor than that of zener.

A 5 W zener diode like the 1N5388B will accept 180 W peak

power if it lasts less than 8.3 ms. If the peak current in the

worse case (e.g. when the PWM circuit maximum current

limit works) multiplied by the nominal zener voltage

exceeds these 180 W, then the diode will be destroyed when

the supply experiences overloads. A transient suppressor

like the P6KE200 still dissipates 5 W of continuous power

but is able to accept surges up to 600 W @ 1 ms. Select the

zener or TVS clamping level between 40 to 80 volts above the

reflected output voltage when the supply is heavily loaded.

As a good design practice, it is recommended to

implement one of this protection to make sure Drain pin

voltage doesn’t go above 650 V (to have some margin

between Drain pin voltage and BVdss) during most stringent

operating conditions (high Vin and peak power).

NCV1060, NCV1063

www.onsemi.com

Power Dissipation and Heatsinking

The NCV106X welcomes two dissipating terms, the DSS

current−source (when active) and the MOSFET. Thus, Ptot

= PDSS + PMOSFET. It is mandatory to properly manage the

heat generated by losses. If no precaution is taken, risks exist

to trigger the internal thermal shutdown (TSD). To help

dissipating the heat, the PCB designer must foresee large

copper areas around the package. Take the SOIC−10

package as an example, when surrounded by a surface

approximately 200 mm2 of 35 mm copper, the maximum

power the device can thus evacuate is:

Pmax +TJmax *Tambmax

RqJA

(eq. 10)

which gives around 760 mW for an ambient of 50°C and a

maximum junction of 150°C. If the surface is not large

enough, the RθJA is growing and the maximum power the

device can evacuate decreases. Figure 49 gives a possible

layout to help drop the thermal resistance.

Figure 49. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient

Bill of material:

C1 Bulk capacitor, input DC voltage is connected to the capacitor

C2, R1, D1 Clamping elements

C3 Vcc capacitor

OK1 Optocoupler

R2 Resistor to setting IPEAK current

Table 6. ORDERING INFORMATION

Device Frequency RDS(on) Brown In Package Type Shipping†

NCV1060BD060R2G* 60 kHz 34 No 2500 / Tape & Reel

NCV1060BD100R2G* 100 kHz 34 No SOIC−10

(Pb−Free)

2500 / Tape & Reel

NCV1063AD060R2G* 60 kHz 11.4 Yes SOIC−16

(Pb−Free)

2500 / Tape & Reel

NCV1063AD100R2G* 100 kHz 11.4 Yes SOIC−16

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable.

SOIC−16

CASE 751B−05

ISSUE K DATE 29 DEC 2006

SCALE 1:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

16 9

SEATING

PLANE

RX 45_

8 PLP

−B−

−A−

0.25 (0.010) B S

−T−

16 PL

0.25 (0.010) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT

STYLE 1:

PIN 1. COLLECTOR

2. BASE

3. EMITTER

4. NO CONNECTION

5. EMITTER

6. BASE

7. COLLECTOR

8. COLLECTOR

9. BASE

10. EMITTER

11. NO CONNECTION

12. EMITTER

13. BASE

14. COLLECTOR

15. EMITTER

16. COLLECTOR

STYLE 2:

PIN 1. CATHODE

2. ANODE

3. NO CONNECTION

4. CATHODE

5. CATHODE

6. NO CONNECTION

7. ANODE

8. CATHODE

9. CATHODE

10. ANODE

11. NO CONNECTION

12. CATHODE

13. CATHODE

14. NO CONNECTION

15. ANODE

16. CATHODE

STYLE 3:

PIN 1. COLLECTOR, DYE #1

2. BASE, #1

3. EMITTER, #1

4. COLLECTOR, #1

5. COLLECTOR, #2

6. BASE, #2

7. EMITTER, #2

8. COLLECTOR, #2

9. COLLECTOR, #3

10. BASE, #3

11. EMITTER, #3

12. COLLECTOR, #3

13. COLLECTOR, #4

14. BASE, #4

15. EMITTER, #4

16. COLLECTOR, #4

STYLE 4:

PIN 1. COLLECTOR, DYE #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. COLLECTOR, #3

6. COLLECTOR, #3

7. COLLECTOR, #4

8. COLLECTOR, #4

9. BASE, #4

10. EMITTER, #4

11. BASE, #3

12. EMITTER, #3

13. BASE, #2

14. EMITTER, #2

15. BASE, #1

16. EMITTER, #1

STYLE 5:

PIN 1. DRAIN, DYE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. DRAIN, #3

6. DRAIN, #3

7. DRAIN, #4

8. DRAIN, #4

9. GATE, #4

10. SOURCE, #4

11. GATE, #3

12. SOURCE, #3

13. GATE, #2

14. SOURCE, #2

15. GATE, #1

16. SOURCE, #1

STYLE 6:

PIN 1. CATHODE

2. CATHODE

3. CATHODE

4. CATHODE

5. CATHODE

6. CATHODE

7. CATHODE

8. CATHODE

9. ANODE

10. ANODE

11. ANODE

12. ANODE

13. ANODE

14. ANODE

15. ANODE

16. ANODE

STYLE 7:

PIN 1. SOURCE N-CH

2. COMMON DRAIN (OUTPUT)

3. COMMON DRAIN (OUTPUT)

4. GATE P-CH

5. COMMON DRAIN (OUTPUT)

6. COMMON DRAIN (OUTPUT)

7. COMMON DRAIN (OUTPUT)

8. SOURCE P-CH

9. SOURCE P-CH

10. COMMON DRAIN (OUTPUT)

11. COMMON DRAIN (OUTPUT)

12. COMMON DRAIN (OUTPUT)

13. GATE N-CH

14. COMMON DRAIN (OUTPUT)

15. COMMON DRAIN (OUTPUT)

16. SOURCE N-CH

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

http://onsemi.com

October, 2002 − Rev. 0 Case Outline Number:

XXX

DOCUMENT NUMBER:

STATUS:

NEW STANDARD:

DESCRIPTION:

98ASB42566B

ON SEMICONDUCTOR STANDARD

SOIC−16

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

PAGE 1 OF 2

DOCUMENT NUMBER:

98ASB42566B

PAGE 2 OF 2

ISSUE REVISION DATE

KADDED SOLDERING FOOTPRINT. REQ. BY L. MORAN. 29 DEC 2006

December, 2006 − Rev. 05K Case Outline Number:

751B

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its of ficers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

SOIC−10 NB

CASE 751BQ

ISSUE B

DATE 26 NOV 2013

SEATING

PLANE

610

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’

AT MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS. MOLD FLASH, PROTRUSIONS, OR

GATE BURRS SHALL NOT EXCEED 0.15mm

PER SIDE. DIMENSIONS D AND E ARE DE-

TERMINED AT DATUM F.

5. DIMENSIONS A AND B ARE TO BE DETERM-

INED AT DATUM F.

6. A1 IS DEFINED AS THE VERTICAL DISTANCE

FROM THE SEATING PLANE TO THE LOWEST

POINT ON THE PACKAGE BODY.

SCALE 1:1

DIM

MIN MAX

4.80 5.00

MILLIMETERS

E3.80 4.00

A1.25 1.75

b0.31 0.51

e1.00 BSC

A1 0.10 0.25

A3 0.17 0.25

L0.40 0.80

M0 8

H5.80 6.20

0.25

XXXXX = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

GENERIC

MARKING DIAGRAM*

*This information is generic. Please refer

to device data sheet for actual part

marking. Pb−Free indicator, “G”, may

or not be present.

DIMENSION: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

XXXXX

ALYWX

h0.37 REF

L2 0.25 BSC

TOP VIEW

C0.20

2X 5 TIPS A-B D

C0.10 A-B

C0.10

b10X

C0.10

10X

SIDE VIEW END VIEW

DETAIL A

6.50

10X 1.18

10X 0.58 1.00

PITCH

RECOMMENDED

SEATING

PLANE

L2 A3

DETAIL A

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

http://onsemi.com

October, 2002 − Rev. 0

Case Outline Number:

XXX

DOCUMENT NUMBER:

STATUS:

NEW STANDARD:

DESCRIPTION:

98AON52341E

ON SEMICONDUCTOR STANDARD

SOIC−10 NB

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

PAGE 1 OF 2

DOCUMENT NUMBER:

98AON52341E

PAGE 2 OF 2

ISSUE REVISION DATE

ORELEASED FOR PRODUCTION. REQ. BY M. RAMOS. 06 JUL 2010

ACHANGED DIMENSION A MIN FROM 1.35 TO 1.25. REQ. BY HB TAN. 25 APR 2011

BCHANGED DIMENSION L MAX FROM 1.27 TO 0.80 MM. REQ. BY C. TAN. 26 NOV 2013

November, 2013 − Rev. B

Case Outline Number:

751BQ

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor ’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer ’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body . Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

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