SST34HF1641C-70-4E-L1PE - Silicon Storage Technology

S71252-04-EOL 6/07

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

CSF and ComboMemory are trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

EOL Data Sheet

FEATURES:

• Flash Organization: 1M x16 or 2M x8

• Dual-Bank Architecture for Concurrent

Read/Write Operation

– Bottom Sector Protection

– 16 Mbit: 12 Mbit + 4 Mbit

• SRAM Organization:

– 2 Mbit: 128K x16

– 4 Mbit: 256K x16

• Single 2.7-3.3V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Current: 25 mA (typical)

– SRAM Standby Current: 20 µA (typical)

• Hardware Sector Protection (WP#)

– Protects 4 outer most sectors (4 KWord) in the

larger bank by holding WP# low and unprotects

by holding WP# high

• Hardware Reset Pin (RST#)

– Resets the internal state machine to reading

data array

• Byte Selection for Flash (CIOF pin)

– Selects 8-bit or 16-bit mode (56-ball package

only)

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Block-Erase Capability

– Uniform 32 KWord blocks

• Read Access Time

– Flash: 70 ns

–SRAM: 70 ns

• Erase-Suspend / Erase-Resume Capabilities

• Security ID Feature

– SST: 128 bits

– User: 128 bits

• Latched Address and Data

• Fast Erase and Program (typical):

– Sector-Erase Time: 18 ms

– Block-Erase Time: 18 ms

– Chip-Erase Time: 35 ms

– Program Time: 7 µs

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

– Ready/Busy# pin

• CMOS I/O Compatibility

• JEDEC Standard Command Set

• Packages Available

– 56-ball LFBGA (8mm x 10mm)

– 62-ball LFBGA (8mm x 10mm)

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The SST34HF16x1C ComboMemory devices integrate

either a 1M x16 or 2M x8 CMOS flash memory bank with

either a 128K x16 or 256K x16 CMOS SRAM memory

bank in a multi-chip package (MCP). These devices are

fabricated using SST’s proprietary, high-performance

CMOS SuperFlash technology incorporating the split-gate

cell design and thick-oxide tunneling injector to attain better

reliability and manufacturability compared with alternate

approaches. The SST34HF16x1C devices are ideal for

applications such as cellular phones, GPS devices, PDAs,

and other portable electronic devices in a low power and

small form factor system.

The SST34HF16x1C feature dual flash memory bank

architecture allowing for concurrent operations between the

two flash memory banks and the SRAM. The devices can

read data from either bank while an Erase or Program

operation is in progress in the opposite bank. The two flash

memory banks are partitioned into 12 Mbit and 4 Mbit with

bottom sector protection options for storing boot code, pro-

gram code, configuration/parameter data and user data.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore, the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles. The SST34HF16x1C devices offer a guaran-

teed endurance of 10,000 cycles. Data retention is rated at

greater than 100 years. With high-performance Program

operations, the flash memory banks provide a typical Pro-

gram time of 7 µsec. The entire flash memory bank can be

erased and programmed word-by-word in typically 4 sec-

onds for the SST34HF16x1C, when using interface fea-

tures such as Toggle Bit, Data# Polling, or RY/BY# to

indicate the completion of Program operation. To protect

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

SST34HF168116Mb CSF (x8/x16) + 2/4/8 Mb SRAM (x16) MCP ComboMemory

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

against inadvertent flash write, the SST34HF16x1C

devices contain on-chip hardware and software data pro-

tection schemes.

The flash and SRAM operate as two independent memory

banks with respective bank enable signals. The memory

bank selection is done by two bank enable signals. The

SRAM bank enable signals, BES1# and BES2, select the

SRAM bank. The flash memory bank enable signal, BEF#,

has to be used with Software Data Protection (SDP) com-

mand sequence when controlling the Erase and Program

operations in the flash memory bank. The memory banks

are superimposed in the same memory address space

where they share common address lines, data lines, WE#

and OE# which minimize power consumption and area.

Designed, manufactured, and tested for applications requir-

ing low power and small form factor, the SST34HF16x1C

are offered in extended temperatures and a small footprint

package to meet board space constraint requirements. See

Figures 4 and 5 for pin assignments.

Device Operation

The SST34HF16x1C uses BES1#, BES2 and BEF# to

control operation of either the flash or the SRAM memory

bank. When BEF# is low, the flash bank is activated for

Read, Program or Erase operation. When BES1# is low,

and BES2 is high the SRAM is activated for Read and

Write operation. BEF# and BES1# cannot be at low level,

and BES2 cannot be at high level at the same time. If all

bank enable signals are asserted, bus contention will

result and the device may suffer permanent damage.

All address, data, and control lines are shared by flash and

SRAM memory banks which minimizes power consump-

tion and loading. The device goes into standby when BEF#

and BES1# bank enables are raised to VIHC (Logic High) or

when BEF# is high and BES2 is low.

Concurrent Read/Write Operation

Dual bank architecture of SST34HF16x1C devices allows

the Concurrent Read/Write operation whereby the user

can read from one bank while programming or erasing in

the other bank. This operation can be used when the user

needs to read system code in one bank while updating

data in the other bank. See Figures 2 and 3 for dual-bank

memory organization.

Note: For the purposes of this table, Write means to perform

Block-/Sector-Erase or Program operations

as applicable to the appropriate bank.

Flash Read Operation

The Read operation of the SST34HF16x1C is controlled by

BEF# and OE#, both have to be low for the system to

obtain data from the outputs. BEF# is used for device

selection. When BEF# is high, the chip is deselected and

only standby power is consumed. OE# is the output control

and is used to gate data from the output pins. The data bus

is in high impedance state when either BEF# or OE# is

high. Refer to the Read cycle timing diagram for further

details (Figure 9).

Concurrent Read/Write States

Flash

SRAMBank 1 Bank 2

Read Write No Operation

Write Read No Operation

Write No Operation Read

No Operation Write Read

Write No Operation Write

No Operation Write Write

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

Flash Program Operation

These devices are programmed on a word-by-word or

byte-by-byte basis depending on the state of the CIOF pin.

Before programming, one must ensure that the sector

which is being programmed is fully erased.

The Program operation is accomplished in three steps:

1. Software Data Protection is initiated using the

three-byte load sequence.

2. Address and data are loaded.

During the Program operation, the addresses are

latched on the falling edge of either BEF# or WE#,

whichever occurs last. The data is latched on the

rising edge of either BEF# or WE#, whichever

occurs first.

3. The internal Program operation is initiated after

the rising edge of the fourth WE# or BEF#, which-

ever occurs first. The Program operation, once ini-

tiated, will be completed typically within 7 µs.

See Figures 10 and 11 for WE# and BEF# controlled Pro-

gram operation timing diagrams and Figure 24 for flow-

charts. During the Program operation, the only valid reads

are Data# Polling and Toggle Bit. During the internal Pro-

gram operation, the host is free to perform additional tasks.

Any commands issued during an internal Program opera-

tion are ignored.

Flash Sector- /Block-Erase Operation

These devices offer both Sector-Erase and Block-Erase

operations. These operations allow the system to erase the

devices on a sector-by-sector (or block-by-block) basis.

The sector architecture is based on a uniform sector size of

2 KWord. The Block-Erase mode is based on a uniform

block size of 32 KWord. The Sector-Erase operation is initi-

ated by executing a six-byte command sequence with a

Sector-Erase command (30H) and sector address (SA) in

the last bus cycle. The Block-Erase operation is initiated by

executing a six-byte command sequence with Block-Erase

command (50H) and block address (BA) in the last bus

cycle. The sector or block address is latched on the falling

edge of the sixth WE# pulse, while the command (30H or

50H) is latched on the rising edge of the sixth WE# pulse.

The internal Erase operation begins after the sixth WE#

pulse. Any commands issued during the Block- or Sector-

Erase operation are ignored except Erase-Suspend and

Erase-Resume. See Figures 15 and 16 for timing wave-

forms.

Flash Chip-Erase Operation

The SST34HF16x1C provide a Chip-Erase operation,

which allows the user to erase all sectors/blocks to the “1”

state. This is useful when the device must be quickly

erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command (10H)

at address 555H in the last byte sequence. The Erase

operation begins with the rising edge of the sixth WE# or

BEF#, whichever occurs first. During the Erase operation,

the only valid read is Toggle Bits or Data# Polling. See

Table 5 for the command sequence, Figure 14 for timing

diagram, and Figure 28 for the flowchart. Any commands

issued during the Chip-Erase operation are ignored. When

WP# is low, any attempt to Chip-Erase will be ignored.

Flash Erase-Suspend/-Resume Operations

The Erase-Suspend operation temporarily suspends a

Sector- or Block-Erase operation thus allowing data to be

read from any memory location, or program data into any

sector/block that is not suspended for an Erase operation.

The operation is executed by issuing a one-byte command

sequence with Erase-Suspend command (B0H). The

device automatically enters read mode no more than 10 µs

after the Erase-Suspend command had been issued. (TES

maximum latency equals 10 µs.) Valid data can be read

from any sector or block that is not suspended from an

Erase operation. Reading at address location within erase-

suspended sectors/blocks will output DQ2 toggling and

DQ6 at “1”. While in Erase-Suspend mode, a Program

operation is allowed except for the sector or block selected

for Erase-Suspend. To resume Sector-Erase or Block-

Erase operation which has been suspended, the system

must issue an Erase-Resume command. The operation is

executed by issuing a one-byte command sequence with

Erase Resume command (30H) at any address in the one-

byte sequence.

Flash Write Operation Status Detection

The SST34HF16x1C provide one hardware and two soft-

ware means to detect the completion of a Write (Program

or Erase) cycle, in order to optimize the system Write

cycle time. The hardware detection uses the Ready/

Busy# (RY/BY#) pin. The software detection includes two

status bits: Data# Polling (DQ7) and Toggle Bit (DQ6).

The End-of-Write detection mode is enabled after the ris-

ing edge of WE#, which initiates the internal Program or

Erase operation.

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Ready/Busy# (RY/

BY#), Data# Polling (DQ7) or Toggle Bit (DQ6) read may be

simultaneous with the completion of the Write cycle. If this

occurs, the system may possibly get an erroneous result,

i.e., valid data may appear to conflict with either DQ7 or

DQ6. In order to prevent spurious rejection, if an erroneous

result occurs, the software routine should include a loop to

read the accessed location an additional two (2) times. If

both reads are valid, then the device has completed the

Write cycle, otherwise the rejection is valid.

Ready/Busy# (RY/BY#)

The SST34HF16x1C include a Ready/Busy# (RY/BY#)

output signal. RY/BY# is an open drain output pin that indi-

cates whether an Erase or Program operation is in

progress. Since RY/BY# is an open drain output, it allows

several devices to be tied in parallel to VDD via an external

pull-up resistor. After the rising edge of the final WE# pulse

in the command sequence, the RY/BY# status is valid.

When RY/BY# is actively pulled low, it indicates that an

Erase or Program operation is in progress. When RY/BY#

is high (Ready), the devices may be read or left in standby

mode.

Byte/Word (CIOF)

This function, found only on the 56-ball package, includes a

CIOF pin to control whether the device data I/O pins oper-

ate x8 or x16. If the CIOF pin is at logic “1” (VIH) the device

is in x16 data configuration: all data I/0 pins DQ0-DQ15 are

active and controlled by BEF# and OE#.

If the CIOF pin is at logic “0”, the device is in x8 data config-

uration: only data I/O pins DQ0-DQ7 are active and con-

trolled by BEF# and OE#. The remaining data pins DQ8-

DQ14 are at Hi-Z, while pin DQ15 is used as the address

input A-1 for the Least Significant Bit of the address bus.

Flash Data# Polling (DQ7)

When the devices are in an internal Program operation, any

attempt to read DQ7 will produce the complement of the

true data. Once the Program operation is completed, DQ7

will produce true data. During internal Erase operation, any

attempt to read DQ7 will produce a ‘0’. Once the internal

Erase operation is completed, DQ7 will produce a ‘1’. The

Data# Polling is valid after the rising edge of fourth WE# (or

BEF#) pulse for Program operation. For Sector-, Block-, or

Chip-Erase, the Data# Polling is valid after the rising edge

of sixth WE# (or BEF#) pulse. See Figure 12 for Data# Poll-

ing (DQ7) timing diagram and Figure 25 for a flowchart.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating “1”s

and “0”s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the DQ6 bit will

stop toggling. The device is then ready for the next opera-

tion. The toggle bit is valid after the rising edge of the fourth

WE# (or BEF#) pulse for Program operations. For Sector-,

Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the

rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to

“1” if a Read operation is attempted on an Erase-sus-

pended Sector/Block. If Program operation is initiated in a

sector/block not selected in Erase-Suspend mode, DQ6 will

toggle.

An additional Toggle Bit is available on DQ2, which can be

used in conjunction with DQ6 to check whether a particular

sector is being actively erased or erase-suspended. Table 1

shows detailed status bit information. The Toggle Bit (DQ2)

is valid after the rising edge of the last WE# (or BEF#)

pulse of a Write operation. See Figure 13 for Toggle Bit tim-

ing diagram and Figure 25 for a flowchart.

Note: DQ7, DQ6, and DQ2 require a valid address when reading status information. The address must be in the bank where the operation is in

progress in order to read the operation status. If the address is pointing to a different bank (not busy), the device will output array data.

TABLE 1: Write Operation Status

Status DQ7DQ6DQ2RY/BY#

Normal Operation Standard Program DQ7# Toggle No Toggle 0

Standard Erase 0 Toggle Toggle 0

Erase-Suspend Mode Read From Erase Suspended Sector/Block 1 1 Toggle 1

Read From Non-Erase Suspended Sector/Block Data Data Data 1

Program DQ7# Toggle No Toggle 0

T1.2 1252

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

Data Protection

The SST34HF16x1C provide both hardware and software

features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than

5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#

high will inhibit the Write operation. This prevents inadvert-

ent writes during power-up or power-down.

Hardware Block Protection

The SST34HF16x1C provide a hardware block protection

which protects the outermost 8 KWord in Bank 1. The block

is protected when WP# is held low. See Figures 2 and 3 for

Block-Protection location.

A user can disable block protection by driving WP# high

thus allowing erase or program of data into the protected

sectors. WP# must be held high prior to issuing the write

command and remain stable until after the entire Write

operation has completed. If WP# is left floating, it is inter-

nally held high via a pull-up resistor, and the Boot Block is

unprotected, enabling Program and Erase operations on

that block.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the

device to read array data. When the RST# pin is held low

for at least TRP, any in-progress operation will terminate and

return to Read mode, see Figure 21. When no internal Pro-

gram/Erase operation is in progress, a minimum period of

TRHR is required after RST# is driven high before a valid

Read can take place, see Figure 20.

The Erase operation that has been interrupted needs to be

reinitiated after the device resumes normal operation mode

to ensure data integrity. See Figures 20 and 21 for timing

diagrams.

Software Data Protection (SDP)

The SST34HF16x1C provide the JEDEC standard Soft-

ware Data Protection scheme for all data alteration opera-

tions, i.e., Program and Erase. Any Program operation

requires the inclusion of the three-byte sequence. The

three-byte load sequence is used to initiate the Program

operation, providing optimal protection from inadvertent

Write operations, e.g., during the system power-up or

power-down. Any Erase operation requires the inclusion of

six-byte sequence. The SST34HF16x1C are shipped with

the Software Data Protection permanently enabled. See

Table 5 for the specific software command codes. During

SDP command sequence, invalid commands will abort the

device to Read mode within TRC. The contents of DQ15-

DQ8 are “Don’t Care” during any SDP command

sequence.

Common Flash Memory Interface (CFI)

These devices also contain the CFI information to describe

the characteristics of the devices. In order to enter the CFI

Query mode, the system must write the three-byte

sequence same as the Software ID Entry command with

98H (CFI Query command) to address 555H in the last

byte sequence. For CFI Entry and Bead timing diagram,

See Figure 18. Once the device enters the CFI Query

mode, the system can read CFI data a t the addresses

given in Tables 7 and 9. The system must write the CFI Exit

command to return to Bead mode from the CFI Query

mode.

Security ID

The SST34HF16x1C devices offer a 256-bit Security ID

space. The Secure ID space is divided into two 128-bit seg-

ments—one factory programmed segment and one user

programmed segment. The first segment is programmed

and locked at SST with a unique, 128-bit number. The user

segment is left un-programmed for the customer to pro-

gram as desired. To program the user segment of the

Security ID, the user must use the Security ID Program

command. End-of-Write status is checked by reading the

toggle bits. Data# Polling is not used for Security ID End-of-

Write detection. Once programming is complete, the Sec

ID should be locked using the User-Sec-ID-Program-Lock-

Out. This disables any future corruption of this space. Note

that regardless of whether or not the Sec ID is locked, nei-

ther Sec ID segment can be erased. The Secure ID space

can be queried by executing a three-byte command

sequence with Query-Sec-ID command (88H) at address

555H in the last byte sequence. To exit this mode, the Exit-

Sec-ID command should be executed. Refer to Table 5 for

more details.

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

Product Identification

The Product Identification mode identifies the device as the

SST34HF16x1C and manufacturer as SST. This mode

may be accessed by software operations only. The hard-

ware device ID Read operation, which is typically used by

programmers cannot be used on this device because of

the shared lines between flash and SRAM in the multi-chip

package. Therefore, application of high voltage to pin A9

may damage this device. Users may use the software

Product Identification operation to identify the part (i.e.,

using the device ID) when using multiple manufacturers in

the same socket. For details, see Tables 4 and 5 for soft-

ware operation, Figure 17 for the Software ID Entry and

Read timing diagram and Figure 26 for the ID Entry com-

mand sequence flowchart.

Note: BK = Bank Address (A19-A18)

Product Identification Mode Exit

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exit is accom-

plished by issuing the Software ID Exit command

sequence, which returns the device to the Read mode.

This command may also be used to reset the device to the

Read mode after any inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. Note that the Software ID Exit/CFI Exit

command is ignored during an internal Program or Erase

operation. See Table 5 for software command codes, Fig-

ure 19 for timing waveform and Figure 26 for a flowchart.

SRAM Operation

With BES1# low, BES2 and BEF# high, the

SST34HF16x1C operate as either 128K x16, 256K x16, or

512K x16 CMOS SRAM, with fully static operation requir-

ing no external clocks or timing strobes. The

SST34HF16x1C SRAM is mapped into the first 512

KWord address space. When BES1#, BEF# are high and

BES2 is low, all memory banks are deselected and the

device enters standby. Read and Write cycle times are

equal. The control signals UBS# and LBS# provide access

to the upper data byte and lower data byte. For SRAM

Read and Write data byte control modes of operation, see

Table 4.

SRAM Read

The SRAM Read operation of the SST34HF16x1C is con-

trolled by OE# and BES1#, both have to be low with WE#

and BES2 high for the system to obtain data from the out-

puts. BES1# and BES2 are used for SRAM bank selection.

OE# is the output control and is used to gate data from the

output pins. The data bus is in high impedance state when

OE# is high. Refer to the Read cycle timing diagram, Fig-

ure 6, for further details.

SRAM Write

The SRAM Write operation of the SST34HF16x1C is con-

trolled by WE# and BES1#, both have to be low, BES2

must be high for the system to write to the SRAM. During

the Word-Write operation, the addresses and data are ref-

erenced to the rising edge of either BES1#, WE#, or the

falling edge of BES2 whichever occurs first. The write time

is measured from the last falling edge of BES#1 or WE# or

the rising edge of BES2 to the first rising edge of BES1#, or

WE# or the falling edge of BES2. Refer to the Write cycle

timing diagrams, Figures 7 and 8, for further details.

TABLE 2: Product Identification

ADDRESS DATA

Manufacturer’s ID BK0000H 00BFH

Device ID

SST34HF16x1C BK0001H 734BH

T2.1 1252

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 1: Functional Block Diagram

1252 B1.5

SuperFlash Memory

(Bank 1)

I/O Buffers

SuperFlash Memory

(Bank 2)

2 / 4 Mbit

SRAM

AMS1- A0

DQ15/A-1 - DQ0

Notes: 1. AMS = Most significant address

2. For LSE package only: WE# = WEF# and/or WES#

OE# = OEF# and/or OES#

Control

Logic

CIOF

RST#

BEF#

WP#

LBS#

UBS#

WE#2

OE#2

BES1#

BES2

RY/BY#

Address

Buffers

Address

Buffers

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 2: 1M x16 Concurrent SuperFlash Dual-Bank Memory Organization

FFFFFH

F8000H Block 31

F7FFFH

F0000H Block 30

EFFFFH

E8000H Block 29

E7FFFH

E0000H Block 28

DFFFFH

D8000H Block 27

D7FFFH

D0000H Block 26

CFFFFH

C8000H Block 25

C7FFFH

C0000H Block 24

Bank 2

BFFFFH

B8000H Block 23

B7FFFH

B0000H Block 22

AFFFFH

A8000H Block 21

A7FFFH

A0000H Block 20

9FFFFH

98000H Block 19

97FFFH

90000H Block 18

8FFFFH

88000H Block 17

87FFFH

80000H Block 16

7FFFFH

78000H Block 15

77FFFH

70000H Block 14

6FFFFH

68000H Block 13

67FFFH

60000H Block 12

5FFFFH

58000H Block 11

57FFFH

50000H Block 10

4FFFFH

48000H Block 9

47FFFH

40000H Block 8

3FFFFH

38000H Block 7

37FFFH

30000H Block 6

2FFFFH

28000H Block 5

27FFFH

20000H Block 4

1FFFFH

18000H Block 3

17FFFH

10000H Block 2

0FFFFH

08000H Block 1

07FFFH

02000H

01FFFH

00000H

Block 0

Bank 1

Bottom Sector Protection; 32 KWord Blocks; 2 KWord Sectors

8 KWord Sector Protection

(4-2 KWord Sectors)

1252 F01.0

Note: The address input range in x16 mode (COIF=VIH) is A19-A0

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 3: 2M x8 Concurrent SuperFlash Dual-Bank Memory Organization

1FFFFFH

1F0000H Block 31

1EFFFFH

1E0000H Block 30

1DFFFFH

1D0000H Block 29

1CFFFFH

1C0000H Block 28

1BFFFFH

1B0000H Block 27

1AFFFFH

1A0000H Block 26

19FFFFH

190000H Block 25

18FFFFH

180000H Block 24

Bank 2

17FFFFH

170000H Block 23

16FFFFH

160000H Block 22

15FFFFH

150000H Block 21

14FFFFH

140000H Block 20

13FFFFH

130000H Block 19

12FFFFH

120000H Block 18

11FFFFH

110000H Block 17

10FFFFH

100000H Block 16

0FFFFFH

0F0000H Block 15

0EFFFFH

0E0000H Block 14

0DFFFFH

0D0000H Block 13

0CFFFFH

0C0000H Block 12

0BFFFFH

0B0000H Block 11

0AFFFFH

0A0000H Block 10

09FFFFH

090000H Block 9

08FFFFH

080000H Block 8

07FFFFH

070000H Block 7

06FFFFH

060000H Block 6

05FFFFH

050000H Block 5

04FFFFH

040000H Block 4

03FFFFH

030000H Block 3

02FFFFH

020000H Block 2

01FFFFH

010000H Block 1

00FFFFH

004000H

003FFFH

000000H

Block 0

Bank 1

Bottom Sector Protection; 64 KByte Blocks; 4 KByte Sectors

16 KByte Sector Protection

(4-4 KByte Sectors)

1252 F01b.0

Note: The address input range in x8 mode (CIOF=VIL) is A19-A-1

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 4: Pin Assignments for 56-ball LFBGA (8mm x 10mm)

FIGURE 5: Pin Assignments for 62-ball LFBGA (8mm x 10mm)

1252 56-lfbga P1a.0

A11

WE#

WP#

LBS#

A15

A12

A19

BES2

RST#

UBS#

A13

RY/BY#

A18

A14

A10

A17

A16

DQ6

DQ1

VSS

CIOF

NOTE*

DQ13

DQ4

DQ3

DQ9

OE#

BEF#

VSS

DQ7

DQ12

VDDS

VDDF

DQ10

DQ0

BES1#

DQ14

DQ5

DQ11

DQ2

DQ8

A B C D E F G H

TOP VIEW (balls facing down)

Note* = DQ

-1

1252 62-lfbga P2.1

A16

WEF#

VSSS

WP#

LBS#

A18

A11

RY/BY#

RST#

UBS#

A17

A15

A10

A19

OES#

A14

DQ11

A13

DQ15

DQ13

DQ12

DQ9

BEF#

A12

WES#

DQ6

BES2

DQ10

DQ8

VSSF

DQ14

DQ4

VDDS

DQ2

DQ0

OEF#

DQ7

DQ5

VDDF

DQ3

DQ1

BES1#

A B C D E F G H J K

TOP VIEW (balls facing down)

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

TABLE 3: Pin Description

Symbol Pin Name Functions

AMS1 to A0Address Inputs To provide flash address, A19-A0.

To provide SRAM address, AMS-A0

DQ14-DQ0Data Inputs/Outputs To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a flash Erase/Program cycle. The outputs are in

tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.

DQ15/A-1 Data Input/Output

and LBS Address

DQ15 is used as data I/O pin when in x16 mode (CIOF = “1”)

A-1 is used as the LBS address pin when in x8 mode (CIOF = “0”)

BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low

BES1# SRAM Memory Bank Enable To activate the SRAM memory bank when BES1# is low

BES2 SRAM Memory Bank Enable To activate the SRAM memory bank when BES2 is high

OEF#2Output Enable To gate the data output buffers for Flash2 only

OES#2Output Enable To gate the data output buffers for SRAM2 only

WEF#2Write Enable To control the Write operations for Flash2 only

WES#2Write Enable To control the Write operations for SRAM2 only

OE# Output Enable To gate the data output buffers

WE# Write Enable To control the Write operations

CIOF3Byte Selection for Flash When low, select Byte mode. When high, select Word mode.

UBS# Upper Byte Control (SRAM) To enable DQ15-DQ8

LBS# Lower Byte Control (SRAM) To enable DQ7-DQ0

WP# Write Protect To protect and unprotect the bottom 8 KWord (4 sectors) from Erase or Program

operation

RST# Reset To Reset and return the device to Read mode

RY/BY# Ready/Busy# To output the status of a Program or Erase Operation

RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required to

allow RY/BY# to transition high indicating the device is ready to read.

VSSF2Ground Flash2 only

VSSS2Ground SRAM2 only

VSS Ground

VDDFPower Supply (Flash) 2.7-3.3V Power Supply to Flash only

VDDSPower Supply (SRAM) 2.7-3.3V Power Supply to SRAM only

NC No Connection Unconnected pins

T3.1 1252

1. AMS = Most Significant Address

AMS = A16 for SST34HF1621C, A17 for SST34HF1641C

2. LSE package only

3. L1PE package only

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

TABLE 4: Operational Modes Selection

Mode BEF#1BES1#1,2 BES21,2 OE#2,3 WE#2,3 LBS#2UBS#2

DQ15-8

DQ7-0 CIOF = VIH CIOF = VIL

Full Standby VIH VIH X X X X X HIGH-Z HIGH-Z HIGH-Z

IL XXXX

Output Disable VIH VIL VIH VIH VIH X X HIGH-Z HIGH-Z HIGH-Z

VIL VIH XXV

IH VIH

VIL VIH XV

IH VIH X X HIGH-Z HIGH-Z HIGH-Z

Flash Read VIL VIH XV

IL VIH XXD

OUT DOUT DQ14-8 = HIGH-Z

DQ15 = A-1

Flash Write VIL VIH X VIH VIL XXD

IN DIN DQ14-8 = HIGH-Z

DQ15 = A-1

Flash Erase VIL VIH XV

IH VIL XX X X X

SRAM Read VIH V

IL VIH VIL VIH VIL V

IL DOUT DOUT DOUT

VIH VIL HIGH-Z DOUT DOUT

VIL VIH DOUT HIGH-Z HIGH-Z

SRAM Write VIH VIL VIH XV

IL VIL VIL DIN DIN DIN

VIH VIL HIGH-Z DIN DIN

VIL VIH DIN HIGH-Z HIGH-Z

Product

Identification4

VIL VIH V

IL V

IL VIH X X Manufacturer’s ID5

Device ID5

T4.1 1252

1. Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time

2. X can be VIL or VIH, but no other value.

3. OE# = OEF# and OES#

WE# = WEF# and WES# for LSE package only

4. Software mode only

5. With A19-A18 = VIL;SST Manufacturer’s ID = BFH, is read with A0=0,

SST34HF16x1C Device ID = 734BH, is read with A0=1

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

TABLE 5: Software Command Sequence

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Program 555H AAH 2AAH 55H 555H A0H WA3Data

Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX430H

Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX450H

Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Erase-Suspend XXXXH B0H

Erase-Resume XXXXH 30H

Query Sec ID5555H AAH 2AAH 55H 555H 88H

User Security ID

Program

555H AAH 2AAH 55H 555H A5H SIWA6Data

User Security ID

Program Lock-out7

555H AAH 2AAH 55H 555H 85H XXH 0000H

Software ID Entry8555H AAH 2AAH 55H BKX9

555H

90H

CFI Query Entry 555H AAH 2AAH 55H BKX9

555H

98H

Software ID Exit/

CFI Exit

Sec ID Exit10,11

555H AAH 2AAH 55H 555H F0H

Software ID Exit/

CFI Exit

Sec ID Exit10,11

XXH F0H

T5.4 1252

1. Address format A10-A0 (Hex), Addresses A19-A11 can be VIL or VIH, but no other value, for the command sequence when in x16 mode.

When in x8 mode, Addresses A19-A12, Address A-1 and DQ14-DQ8 can be VIL or VIH, but no other value, for the command sequence.

2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence

3. WA = Program word/byte address

4. SAX for Sector-Erase; uses A19-A11 address lines

BAX for Block-Erase; uses A19-A15 address lines

5. For SST34HF16x1C,

SST ID is read with A4 = 0 (Address range = 00000H to 00007H),

User ID is read with A4 = 1 (Address range = 00010H to 00017H).

Lock Status is read with A7-A0 = 000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.

6. SIWA = User Security ID Program word/byte address

For SST34HF16x1C, valid Word-Addresses for User Sec ID are from 00010H-00017H.

All 4 cycles of User Security ID Program and Program Lock-out must be completed before going back to Read-Array mode.

7. The User Security ID Program Lock-out command must be executed in x16 mode (CIOF=VIH).

8. The device does not remain in Software Product Identification mode if powered down.

9. A19 and A18 = VIL

10. Both Software ID Exit operations are equivalent

11. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the

User Sec ID mode again (the programmed “0” bits cannot be reversed to “1”).

For SST34HF16x1C, valid Word-Addresses for User Sec ID are from 00010H-00017H.

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

TABLE 6: CFI QUERY IDENTIFICATION STRING1

Address

x16 Mode

Address

x8 Mode Data2Description

10H

11H

12H

20H

22H

24H

0051H

0052H

0059H

Query Unique ASCII string “QRY”

13H

14H

26H

28H

001H

007H

Primary OEM command set

15H

16H

2AH

2CH

0000H

Address for Primary Extended Table

17H

18H

2EH

30H

0000H

Alternate OEM command set (00H = none exits)

19H

1AH

32H

34H

0000H

Address for Alternate OEM extended Table (00H - none exits)

T6.0 1252

1. Refer to CFI publication 100 for more details.

2. In x8 mode only the lower byte of data is output.

TABLE 7: SYSTEM INTERFACE INFORMATION

Address

x16 Mode

Address

x8 Mode Data1

1. In x8 mode, only the lower byte of data is output.

Description

1BH 36H 0027H VDD Min (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 Millivolts

1CH 38H 0036H VDD Max (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 Millivolts

1DH 3AH 0000H VDD Min (00H = No VDD pin)

1EH 3CH 0000H VDD Max (00H = No VDD pin)

1FH 3EHh 0004H Typical time out for Program 2N µs (24 = 16 µs)

20H 40H 0000H Typical time out for min size buffer program 2N µs (00H = not supported)

21H 42H 0004H Typical time out for individual Sector-/Block-Erase 2N ms (2N = 16 ms)

22H 44H 0006H Typical time out for Chip-Erase 2N ms (26 = 64 ms)

23H 46H 0001H Maximum time out for Program 2N time typical (21 x 24 - 32 µs)

24H 48H 0000H Maximum time out for buffer program 2N time typical

25H 4AH 0001H Maximum time out for individual Sector-Block-Erase 2N time typical (21 x 24 - 32 ms)

26H 4CH 0001H Maximum time out for individual Chip-Erase 2N time typical (21 x 26 - 128 ms)

T7.0 1252

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

TABLE 8: SYSTEM INTERFACE INFORMATION

Address

x16 Mode

Address

x8 Mode Data1Description

27H 4EH 0015H Device size = 2N Bytes (15H = 21; 221 = 2 MByte)

28H

29H

50H

52H

0002H

0000H

Flash Device Interface description; 0002H = x8/x16 asynchronous interface

2AH

2BH

54H

56H

00000H

0000H

Maximum number of bytes in multi-byte write = 2N (00H = not supported)

2CH 58H 0002H Number of Erase Sector/Block sizes supported by device

2DH

2EH

2FH

30H

5AH

5CH

5EH

60H

00FFH

0001H

0010H

0000H

Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

y = 511 + 1 = 512 sectors (01FFH = 512)

z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)

31H

32H

33H

34H

62H

64H

66H

68H

001FH

0000H

0001H

Block Information (y + 1 = Number of blocks; z x 256B = block size)

y = 31 + 1 = 32 blocks (001FH = 31)

z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

T8.0 1252

1. In x8 mode, only the lower byte of data is output.

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

ELECTRICAL SPECIFICATIONS

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V

1. VDD = VDDF and VDDS

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V

Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

Operating Range

Range Ambient Temp VDD

Extended -20°C to +85°C 2.7-3.3V

AC Conditions of Test

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 22 and 23

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

DC Characteristics

TABLE 9: DC Operating Characteristics (VDD = VDDF and VDDS = 2.7-3.3V)

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD1

1. Address input = VILT/VIHT, VDD=VDD Max (See Figure 22)

Active VDD Current Address input = VILT/VIHT, at f=5 MHz,

VDD=VDD Max, all DQs open

Read OE#=VIL, WE#=VIH

Flash 35 mA BEF#=VIL, BES1#=VIH, or BES2=VIL

SRAM 30 mA BEF#=VIH, BES1#=VIL , BES2=VIH

Concurrent Operation 60 mA BEF#=VIH, BES1#=VIL , BES2=VIH

Write2

2. IDD active while Erase or Program is in progress.

WE#=VIL

Flash 40 mA BEF#=VIL, BES1#=VIH, or BES2=VIL, OE#=VIH

SRAM 30 mA BEF#=VIH, BES1#=VIL , BES2=VIH

ISB Standby VDD Current 30 µA VDD = VDD Max, BEF#=BES1#=VIHC, BES2=VILC

IRT Reset VDD Current 30 µA RST#=GND

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILIW Input Leakage Current

on WP# pin and RST# pin

10 µA WP#=GND to VDD, VDD=VDD Max

RST#=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

VIH Input High Voltage 0.7 VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOLF Flash Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOHF Flash Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

VOLS SRAM Output Low Voltage 0.4 V IOL =1 mA, VDD=VDD Min

VOHS SRAM Output High Voltage 2.2 V IOH =-500 µA, VDD=VDD Min

T9.1 1252

TABLE 10: Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Write Operation 100 µs

T10.0 1252

TABLE 11: Capacitance (TA = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 20 pF

CIN1Input Capacitance VIN = 0V 16 pF

T11.0 1252

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

AC CHARACTERISTICS

TABLE 12: Flash Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T12.0 1252

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 13: SRAM Read Cycle Timing Parameters

Min Max Units

TRCS Read Cycle Time 70 ns

TAAS Address Access Time 70 ns

TBES Bank Enable Access Time 70 ns

TOES Output Enable Access Time 35 ns

TBYES UBS#, LBS# Access Time 70 ns

TBLZS1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

BES# to Active Output 0 ns

TOLZS1Output Enable to Active Output 0 ns

TBYLZS1UBS#, LBS# to Active Output 0 ns

TBHZS1BES# to High-Z Output 25 ns

TOHZS1Output Disable to High-Z Output 25 ns

TBYHZS1UBS#, LBS# to High-Z Output 35 ns

TOHS Output Hold from Address Change 10 ns

T13.0 1252

TABLE 14: SRAM Write Cycle Timing Parameters

Symbol Parameter Min Max Units

TWCS Write Cycle Time 70 ns

TBWS Bank Enable to End-of-Write 60 ns

TAWS Address Valid to End-of-Write 60 ns

TASTS Address Set-up Time 0 ns

TWPS Write Pulse Width 60 ns

TWRS Write Recovery Time 0 ns

TBYWS UBS#, LBS# to End-of-Write 50 ns

TODWS Output Disable from WE# Low 30 ns

TOEWS Output Enable from WE# High 0 ns

TDSS Data Set-up Time 30 ns

TDHS Data Hold from Write Time 0 ns

T14.0 1252

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

TABLE 15: Flash Read Cycle Timing Parameters VDD = 2.7-3.3V

Symbol Parameter Min Max Units

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TCLZ1BEF# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1BEF# High to High-Z Output 20 ns

TOHZ1OE# High to High-Z Output 20 ns

TOH1Output Hold from Address Change 0 ns

TRP1RST# Pulse Width 500 ns

TRHR1RST# High Before Read 50 ns

TRY1,2 RST# Pin Low to Read 20 µs

T15.0 1252

1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase.

TABLE 16: Flash Program/Erase Cycle Timing Parameters

Symbol Parameter Min Max Units

TBP Program Time 10 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 40 ns

TCS WE# and BEF# Setup Time 0 ns

TCH WE# and BEF# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP BEF# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1 BEF# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TES Erase-Suspend Latency 10 µs

TBY1,2

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

This parameter does not apply to Chip-Erase operations.

RY/BY# Delay Time 90 ns

TBR1Bus# Recovery Time 1µs

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 50 ms

T16.1 1252

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 6: SRAM Read Cycle Timing Diagram

FIGURE 7: SRAM Write Cycle Timing Diagram (WE# Controlled)1

ADDRESSES

AMSS-0

DQ15-0

UBS#, LBS#

OE#

BES1#

BES2

TRCS

TAAS

TBES

TOES

TBLZS

TOLZS

TBYES

TBYLZS TBYHZS

DATA VALID

TOHZS

TBHZS

TOHS

1252 F04.0

TBES

Note: AMSS = Most Significant Address

AMSS = A16 for SST34HF1621C, A17 for SST34HF1641C

AWS

ADDRESSES AMSS3-0

BES1#

BES2

WE#

UBS#, LBS#

TWPS TWRS

TWCS

TASTS

TBWS

TBYWS

TODWS TOEWS

TDSS TDHS

1252 F05.0

NOTE 2

DQ15-8, DQ7-0 VALID DATA IN

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will remain at high impedance.

If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance.

Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. AMSS = Most Significant SRAM Address

AMSS = A16 for SST34HF1621C and A17 for SST34HF1641C

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 8: SRAM Write Cycle Timing Diagram (UBS#, LBS# Controlled)1 x16 SRAM ONLY

ADDRESSES AMSS3-0

WE#

BES1#

BES2

TBWS

TAWS

TWCS

TWPS TWRS

TASTS TBYWS

DQ15-8, DQ7-0 VALID DATA IN

TDSS TDHS

UBS#, LBS#

1252 F06.0

NOTE 2 NOTE 2

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. AMSS = Most Significant SRAM Address

AMSS = A16 for SST34HF1621C and A17 for SST34HF1641C

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 9: Flash Read Cycle Timing Diagram for Word Mode

(For Byte Mode A-1 = Address Input)

FIGURE 10: Flash WE# Controlled Program Cycle Timing Diagram for Word Mode

(For Byte Mode A-1 = Address Input)

1252 F07.0

ADDRESS A19-0

DQ15-0

WE#

OE#

BEF#

TCE

TRC TAA

TOE

TOLZ

VIH

HIGH-Z TCLZ TOH

TCHZ

HIGH-Z

DATA VALIDDATA VALID

TOHZ

1252 F08.1

ADDRESS A19-0

DQ15-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS?TBY

BEF#

RY/BY#

555 2AA 555 ADDR

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

OE#

WE#

TBR

TBP

Note: X can be VIL or VIH, but no other value.

VALID

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 11: Flash BEF# Controlled Program Cycle Timing Diagram for Word Mode

(For Byte Mode A-1 = Address Input)

FIGURE 12: Flash Data# Polling Timing Diagram for Word Mode

(For Byte Mode A-1 = Address Input)

VALID

1252 F09.1

ADDRESS A19-0

DQ15-0

TDH

CPH

TDS

TCP

TAH

TAS

TCH

TCS?

WE#

555 2AA 555 ADDR

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

OE#

BEF#

TBP

TBY

RY/BY# TBR

Note: X can be VIL or VIH, but no other value.

1252 F10.0

ADDRESS A19-0

DQ7DATA DATA# DATA# DATA

WE#

OE#

BEF#

TOEH

TOE

TCE

TOES

RY/BY#

TBY

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 13: Flash Toggle Bit Timing Diagram for Word Mode

(For Byte Mode A-1 = Don’t Care)

FIGURE 14: Flash WE# Controlled Chip-Erase Timing Diagram for Word Mode

(For Byte Mode A-1 = Don’t Care)

1252 F11.0

ADDRESS A19-0

DQ6

WE#

OE#

BEF#

TOE

TOEH

TCE

TWO READ CYCLES

WITH SAME OUTPUTS

VALID DATA

TBR

VALID

1252 F12.1

ADDRESS A

19-0

15-0

WE#

555 2AA 2AA555 555

XX55 XX10XX55XXAA XX80 XXAA

555

OE#

BEF#

SIX-BYTE CODE FOR CHIP-ERASE

SCE

RY/BY#

Note: This device also supports BEF# controlled Chip-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 16.)

X can be VIL or VIH, but no other value.

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 15: Flash WE# Controlled Block-Erase Timing Diagram for Word Mode

(For Byte Mode A-1 = Don’t Care)

FIGURE 16: Flash WE# Controlled Sector-Erase Timing Diagram for Word Mode

(For Byte Mode A-1 = Don’t Care)

1252 F13.1

ADDRESS

A19-0

DQ15-0

WE#

555 2AA 2AA555 555

XX55 XX50XX55XXAA XX80 XXAA

BAX

OE#

BEF#

SIX-BYTE CODE FOR BLOCK-ERASE

TWP

TBY

RY/BY#

VALID

TBR

TBE

Note: This device also supports BEF# controlled Block-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 16.)

BAX = Block Address

X can be VIL or VIH, but no other value.

1252 F14.1

ADDRESS

19-0

15-0

WE#

555 2AA 2AA555 555

XX55 XX30XX55XXAA XX80 XXAA

OE#

BEF#

SIX-BYTE CODE FOR SECTOR-ERASE

RY/BY#

VALID

Note: This device also supports BEF# controlled Sector-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 16.)

SAX = Sector Address

X can be VIL or VIH, but no other value.

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 17: Flash Software ID Entry and Read for Word Mode

(For Byte Mode A-1 = 0)

FIGURE 18: CEI Entry and Read

1252 F15.1

ADDRESS A14-0

TIDA

DQ15-0

WE#

555 2AA 555 0000 0001

OE#

BEF#

Three-Byte Sequence For Software ID Entry

TWP

TWPH TAA

00BF Device ID

XX55XXAA XX90

Note: X can be VIL or VIH, but no other value.

Device ID - 734BH for SST34HF16x1C

1252 F26.0

ADDRESSES

IDA

15-0

WE#

555 2AA 555

OE#

CE#

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

WPH

XX55XXAA XX98

Note: X can be VIL or VIH, but no other value.

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 19: Flash Software ID Exit/CEI Exit for Word Mode

(For Byte Mode A-1 = 0)

1252 F16.1

ADDRESS A14-0

DQ15-0

TIDA

TWP

TWHP

WE#

555 2AA 555

Three-Byte Sequence for Software ID Exit and Reset

OE#

BEF#

XXAA XX55 XXF0

Note: X can be VIL or VIH, but no other value

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 20: RST Timing (when no internal operations in progress)

FIGURE 21: RST# Timing (during Sector- or Block-Erase operation)

1252 F17.0

RY/BY#

RST#

BEF#/OE#

TRP

RHR

1252 F18.0

RY/BY#

BEF#

OE#

TRP

TRY

TBR

RST#

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 22: AC Input/Output Reference Waveforms

FIGURE 23: A Test Load Example

1252 F19.0

REFERENCE POINTS OUTPUTINPUT? V

IHT

ILT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points

for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Te s t

VOT - VOUTPUT Tes t

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1252 F20.0

TO TESTER

TO DUT

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 24: Program Algorithm

1252 F21.2

Start

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XXA0H

Address: 555H

Load

Address/Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

Note: X can be VIL or VIH, but no other value.

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 25: Wait Options

1252 F22.1

Wait TBP,

TSCE, TSE

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match?

Read same

byte/word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read

byte/word

Is DQ7 =

true data?

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 26: Software Product ID/CFI/Sec ID Command Flowcharts

1252 F23.2

Load data: XXAAH

Address: 555H

Software Product ID Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX90H

Address: 555H

Wait TIDA

Read Software ID

Load data: XXAAH

Address: 555H

CFI Query Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX98H

Address: 555H

Wait TIDA

Read CFI data

Load data: XXAAH

Address: 555H

Sec ID Query Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX88H

Address: 555H

Wait TIDA

Read Sec ID

X can be VIL or VIH, but no other value

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 27: Software Sec ID/CFI/ Exit/Sec ID Exit Command Flowcharts

1252 F24.2

Load data: XXAAH

Address: 555H

Software ID Exit/CFI Exit/Sec ID Exit

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XXF0H

Address: 555H

Load data: XXF0H

Address: XXH

Return to normal

operation

Wait TIDA

Return to normal

operation

X can be VIL or VIH, but no other value

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 28: Erase Command Sequence

1252 F25.1

Load data: XXAAH

Address: 555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX10H

Address: 555H

Load data: XXAAH

Address: 555H

Wait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX30H

Address: SAX

Load data: XXAAH

Address: 555H

Wait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX50H

Address: BAX

Load data: XXAAH

Address: 555H

Wait TBE

Block erased

to FFFFH

Note: X can be VIL or VIH, but no other value.

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

PRODUCT ORDERING INFORMATION

Valid combinations for SST34HF1621C

SST34HF1621C-70-4E-L1PE SST34HF1621C-70-4E-LSE

Valid combinations for SST34HF1641C

SST34HF1641C-70-4E-L1PE SST34HF1641C-70-4E-LSE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Package Attribute

E1 = non-Pb

Package Modifier

P = 56 balls

S = 62 balls

Package Type

L1 = LFBGA (8mm x 10mm x 1.4mm, 0.45mm ball size)

L = LFBGA (8mm x 10mm x 1.4mm, 0.40mm ball size)

Temperature Range

E = Extended = -20°C to +85°C

Minimum Endurance

4 =10,000 cycles

Read Access Speed

70 = 70 ns

Version

C = x16 Mbit SRAM

Boot Block Protection

1 = Bottom Boot Block

SRAM Density

2 = 2 Mbit

4 = 4 Mbit

Flash Density

16 = 16 Mbit

Voltage

H = 2.7-3.3V

Product Series

34 = Concurrent SuperFlash +

SRAM ComboMemory

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

Device Speed Suffix1 Suffix2

SST34HF16x1X- XXX -XX-XXXX

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

PACKAGING DIAGRAMS

FIGURE 29: 56-Ball Low-Profile, Fine-Pitch Ball Grid Array (LFBGA) 8mm x 10mm

SST Package Code: L1PE

H G F E D C B A

A B C D E F G H

SIDE VIEW

SEATING PLANE

0.35 ± 0.05

1.30 ± 0.10

0.12

0.45 ± 0.05

(56X)

0.80

5.60

0.80

5.60

56-lfbga-L1P-8x10-450mic-4

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1mm

A1 CORNER

BOTTOM VIEWTOP VIEW

8.00 ± 0.20

A1 CORNER

10.00 ± 0.20

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

FIGURE 30: 62-Ball Low-Profile, Fine-Pitch Ball Grid Array (LFBGA) 8mm x 10mm

SST Package Code: LSE

A1 CORNER

K J H G F E D C B A

A B C D E F G H J K

BOTTOM VIEWTOP VIEW

8.00 ± 0.20

0.40 ± 0.05

(62X)

A1 CORNER

10.00 ± 0.20

0.80

5.60

0.80

7.20

62-lfbga-LS-8x10-400mic-4

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.32 mm (± 0.05 mm)

1mm

SIDE VIEW

SEATING PLANE 0.32 ± 0.05

1.30 ± 0.10

0.12

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EOL Data Sheet

16 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemory

SST34HF1621C / SST34HF1641C

TABLE 17: Revision History

Number Description Date

00 •Initial Release Mar 2004

01 •Renamed all devices previously released with version “D” to “J”

•Removed 8 Mbit x8 PSRAM organization for SST34HF1681J

•Changed references to Word-Program and Byte-Program to Program

•Updated “Flash Erase-Suspend/-Resume Operations” on page 3

•Added RoHS compliance information on page 1 and in the “Product Ordering Infor-

mation” on page 37

•Removed all references to, and MPNs for, SST34HF1601C to EOL Data Sheet

•Removed all references to, and MPNs for, SST34HF1601S

•Moved all references to, and MPNs for, SST34HF1601S to S71301

•Updated software command sequence addresses in Table 5 on page 13, timing

diagrams, and flowcharts

•Added the solder reflow temperature to the “Absolute Maximum Stress Ratings” on

page 17

•Corrected footnote 5 in Table 6 “Software Command Sequence” on page 14

•Added Table 7, “CFI Query Identification String” on page 15

•Added Table 8, “System Interface Information” on page 15

•Added Table 9, “Device Geometry Information” on page 16

•Changed IDD test condition for frequency specification from 1/TRC Min to 5 MHz

See Table 9 on page 17

•Updated TES parameter from 20 µs to 10 µs in Table 17 on page 21

Nov 2005

02 •Removed all occurrences of 256K x8

•Removed x8 SRAM Read and Write cross reference on page 6

•Removed x8 SRAM from Figure 1 Functional Block Diagram page 7

•Removed SRAM x8 Address from Table 3 on page 11

•Removed Table 5 Operational Modes Selection for x8 SRAM

•Applied new style formats throughout

Feb 2006

03 •Removed PSRAM references, and moved to S71336 Aug 2006

04 •End of Life for all valid combinations in this data sheet.

•Replacement part: SST34HF16x1J in data sheet S71336

Jun 2007

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

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