5V
V+
75:
75:
75:
INPUT
VREF
1k
1k
SD
V-
+
-
SHUTDOWN INPUT
OUT
10n
100n
LMH6639
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SNOS989G –JANUARY 2002–REVISED MARCH 2013
LMH6639 190MHz Rail-to-Rail Output Amplifier with Disable
Check for Samples: LMH6639
1FEATURES DESCRIPTION
The LMH6639 is a voltage feedback operational
2• (VS= 5V, Typical Values Unless Specified) amplifier with a rail-to-rail output drive capability of
• Supply Current (No Load) 3.6mA 110mA. Employing TI’s patented VIP10 process, the
• Supply Current (Off Mode) 400μALMH6639 delivers a bandwidth of 190MHz at a
current consumption of only 3.6mA. An input common
• Output Resistance (Closed Loop 1MHz) 0.186Ωmode voltage range extending to 0.2V below the V−
•−3dB BW (AV= 1) 190MHz and to within 1V of V+, makes the LMH6639 a true
• Settling Time 33nsec single supply op-amp. The output voltage range
extends to within 30mV of either supply rail providing
• Input Common Mode Voltage −0.2V to 4V the user with a dynamic range that is especially
• Output Voltage Swing 40mV from Rails desirable in low voltage applications.
• Linear Output Current 110mA The LMH6639 offers a slew rate of 172V/μs resulting
• Total Harmonic Distortion −60dBc in a full power bandwidth of approximately 28MHz.
• Fully Characterized for 3V, 5V and ±5V The LMH6639 also offers protection for the input
transistors by using two anti-parallel diodes and a
• No Output Phase Reversal with CMVR series resistor connected across the inputs. The TON
Exceeded value of 83nsec combined with a settling time of
• Excellent Overdrive Recovery 33nsec makes this device ideally suited for
• Off Isolation 1MHz −70dB multiplexing applications (see application note for
details). Careful attention has been paid to ensure
• Differential Gain 0.12% device stability under all operating voltages and
• Differential Phase 0.045° modes. The result is a very well behaved frequency
response characteristic for any gain setting including
APPLICATIONS +1, and excellent specifications for driving video
cables including harmonic distortion of −60dBc,
• Active Filters differential gain of 0.12% and differential phase of
• CD/DVD ROM 0.045°
• ADC Buffer Amplifier
• Portable Video
• Current Sense Buffer
Figure 1. Typical Single Supply Schematic
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2002–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMH6639
SNOS989G –JANUARY 2002–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
ESD Tolerance 2KV(3)
200V(4)
VIN Differential ±2.5V
Input Current ±10mA
Supply Voltage (V+– V−) 13.5V
Voltage at Input/Output pins V++0.8V, V−−0.8V
Storage Temperature Range −65°C to +150°C
Junction Temperature(5)(6) +150°C
Soldering Information Infrared or Convection (20 sec) 235°C
Wave Soldering (10 sec) 260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, 1.5kΩin series with 100pF.
(4) Machine Model, 0Ωin series with 200pF.
(5) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
(6) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
Operating Ratings(1)
Supply Voltage (V+to V−) 3V to 12V
Operating Temperature Range(2) −40°C to +85°C
Package Thermal Resistance (θJA)(2) SOT-23-6 265°C/W
SOIC-8 190°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
3V Electrical Characteristics
Unless otherwise specified, all limits ensured for at TJ= 25°C, V+= 3V, V−= 0V, VO= VCM = V+/2, and RL= 2kΩto V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(1) Typ(2) Max(1) Units
BW −3dB BW AV= +1 120 170 MHz
AV=−1 63
BW0.1dB 0.1dB Gain Flatness RF= 2.65kΩ, RL= 1kΩ, 16.4 MHz
FPBW Full Power Bandwidth AV= +1, VOUT = 2VPP,−1dB 21 MHz
V+= 1.8V, V−= 1.2V
GBW Gain Bandwidth product AV= +1 83 MHz
enInput-Referred Voltage Noise RF= 33kΩf = 10kHz 19 nV/√Hz
f = 1MHz 16
inInput-Referred Current Noise RF= 1MΩf = 10kHz 1.30 pA/√Hz
f = 1MHz 0.36
THD Total Harmonic Distortion f = 5MHz, VO= 2VPP, AV= +2, −50 dBc
RL= 1kΩto V+/2
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
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3V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for at TJ= 25°C, V+= 3V, V−= 0V, VO= VCM = V+/2, and RL= 2kΩto V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(1) Typ(2) Max(1) Units
TSSettling Time VO= 2VPP, ±0.1% 37 ns
SR Slew Rate AV=−1(3) 120 167 V/μs
VOS Input Offset Voltage 1.01 5 mV
7
TC VOS Input Offset Average Drift See(4) 8μV/°C
IBInput Bias Current See(5) −1.02 −2.6 μA
−3.5
IOS Input Offset Current 20 800 nA
1000
RIN Common Mode Input Resistance AV= +1, f = 1kHz, RS= 1MΩ6.1 MΩ
CIN Common Mode Input AV= +1, RS= 100kΩ1.35 pF
Capacitance
CMVR Input Common-Mode Voltage CMRR ≥50dB −0.3 −0.2
Range −0.1 V
1.8 2
1.6
CMRR Common Mode Rejection Ratio See(6) 72 93 dB
AVOL Large Signal Voltage Gain VO= 2VPP, RL= 2kΩto V+/2 80 100
76 dB
VO= 2VPP, RL= 150Ωto V+/2 74 78
70
VOOutput Swing RL= 2kΩto V+/2, VID = 200mV 2.90 2.98
High RL= 150Ωto V+/2, VID = 200mV 2.75 2.93 V
RL= 50Ωto V+/2, VID = 200mV 2.6 2.85
Output Swing RL= 2kΩto V+/2, VID =−200mV 25 75
Low RL= 150Ωto V+/2, VID =−200mV 75 200 mV
RL= 50Ωto V+/2, VID =−200mV 130 300
ISC Output Short Circuit Current Sourcing to V+/2(7) 50 120
35 mA
Sinking to V+/2(7) 67 140
40
IOUT Output Current VO= 0.5V from either supply 99 mA
PSRR Power Supply Rejection Ratio See(6) 72 96 dB
ISSupply Current (Enabled) No Load 3.5 5.6
7.5 mA
Supply Current (Disabled) 0.3 0.5
0.7
TH_SD Threshold Voltage for Shutdown V+−1.59 V
Mode
I_SD PIN Shutdown Pin Input Current SD Pin Connect to 0V(8) −13 μA
TON On Time After Shutdown 83 nsec
TOFF Off Time to Shutdown 160 nsec
ROUT Output Resistance Closed Loop RF= 10kΩ, f = 1kHz, AV=−1 27 mΩ
RF= 10kΩ, f = 1MHz, AV=−1 266
(3) Slew rate is the average of the rising and falling slew rates.
(4) Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(5) Positive current corresponds to current flowing into the device.
(6) f ≤1kHz (see typical performance Characteristics)
(7) Short circuit test is a momentary test.
(8) Positive current corresponds to current flowing into the device.
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5V Electrical Characteristics
Unless otherwise specified, all limits ensured for at TJ= 25°C, V+= 5V, V−= 0V, VO= VCM = V+/2, and RL= 2kΩto V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(1) Typ (2) Max(1) Units
BW −3dB BW AV= +1 130 190 MHz
AV=−1 64
BW0.1dB 0.1dB Gain Flatness RF= 2.51kΩ, RL= 1kΩ, 16.4 MHz
FPBW Full Power Bandwidth AV= +1, VOUT = 2VPP,−1dB 28 MHz
GBW Gain Bandwidth Product AV= +1 86 MHz
enInput-Referred Voltage Noise RF= 33kΩf = 10kHz 19 nV/√Hz
f = 1MHz 16
inInput-Referred Current Noise RF= 1MΩf = 10KHz 1.35 pA/√Hz
f = 1MHz 0.35
THD Total Harmonic Distortion f = 5MHz, VO= 2VPP, AV= +2 −60 dBc
RL= 1kΩto V+/2
DG Differential Gain NTSC, AV= +2 0.12 %
RL= 150Ωto V+/2
DP Differential Phase NTSC, AV= +2 0.045 deg
RL= 150Ωto V+/2
TSSettling Time VO= 2VPP, ±0.1% 33 ns
SR Slew Rate AV=−1(3) 130 172 V/µs
VOS Input Offset Voltage 1.02 5 mV
7
TC VOS Input Offset Average Drift See(4) 8 µV/°C
IBInput Bias Current See(5) −1.2 −2.6 µA
−3.25
IOS Input Offset Current 20 800 nA
1000
RIN Common Mode Input Resistance AV= +1, f = 1kHz, RS= 1MΩ6.88 MΩ
CIN Common Mode Input AV= +1, RS= 100kΩ1.32 pF
Capacitance
CMVR Common-Mode Input Voltage CMRR ≥50dB −0.3 −0.2
Range −0.1 V
4 3.8
3.6
CMRR Common Mode Rejection Ratio See(6) 72 95 dB
AVOL Large Signal Voltage Gain VO= 4VPP 86 100
RL= 2kΩto V+/2 82 dB
VO= 3.75VPP 74 77
RL= 150Ωto V+/2 70
VOOutput Swing RL= 2kΩto V+/2, VID = 200mV 4.90 4.97
High RL= 150Ωto V+/2, VID = 200mV 4.65 4.90 V
RL= 50Ωto V+/2, VID = 200mV 4.40 4.77
Output Swing RL= 2kΩto V+/2, VID =−200mV 25 100
Low RL= 150Ωto V+/2, VID =−200mV 85 200 mV
RL= 50Ωto V+/2, VID =−200mV 190 400
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Slew rate is the average of the rising and falling slew rates.
(4) Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(5) Positive current corresponds to current flowing into the device.
(6) f ≤1kHz (see typical performance Characteristics)
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SNOS989G –JANUARY 2002–REVISED MARCH 2013
5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for at TJ= 25°C, V+= 5V, V−= 0V, VO= VCM = V+/2, and RL= 2kΩto V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(1) Typ (2) Max(1) Units
ISC Output Short Circuit Current Sourcing to V+/2(7) 100 160
79 mA
Sinking from V+/2(7) 120 190
85
IOUT Output Current VO= 0.5V from either supply 110 mA
PSRR Power Supply Rejection Ratio See(6) 72 96 dB
ISSupply Current (Enabled) No Load 3.6 5.8
8.0 mA
Supply Current (Disabled) 0.40 0.8
1.0
TH_SD Threshold Voltage for Shutdown V+−1.65 V
Mode
I_SD PIN Shutdown Pin Input Current SD Pin Connected to 0V(5) −30 μA
TON On Time after Shutdown 83 nsec
TOFF Off Time to Shutdown 160 nsec
ROUT Output Resistance Closed Loop RF= 10kΩ, f = 1kHz, AV=−1 29 mΩ
RF= 10kΩ, f = 1MHz, AV=−1 253
(7) Short circuit test is a momentary test.
±5V Electrical Characteristics
Unless otherwise specified, all limits ensured for at TJ= 25°C, VSUPPLY = ±5V, VO= VCM = GND, and RL= 2kΩto V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(1) Typ(2) Max(1) Units
BW −3dB BW AV= +1 150 228 MHz
AV=−1 65
BW0.1dB 0.1dB Gain Flatness RF= 2.26kΩ, RL= 1kΩ18 MHz
FPBW Full Power Bandwidth AV= +1, VOUT = 2VPP,−1dB 29 MHz
GBW Gain Bandwidth Product AV= +1 90 MHz
enInput-Referred Voltage Noise RF= 33kΩf = 10kHz 19 nV/√Hz
f = 1MHz 16
inInput-Referred Current Noise RF= 1MΩf = 10kHz 1.13 pA/√Hz
f = 1MHz 0.34
THD Total Harmonic Distortion f = 5MHz, VO= 2VPP, AV= +2, −71.2 dBc
RL= 1kΩ
DG Differential Gain NTSC, AV= +2 0.11 %
RL= 150Ω
DP Differential Phase NTSC, AV= +2 0.053 deg
RL= 150Ω
TSSettling Time VO= 2VPP, ±0.1% 33 ns
SR Slew Rate AV=−1(3) 140 200 V/µs
VOS Input Offset Voltage 1.03 5 mV
7
TC VOS Input Offset Voltage Drift See(4) 8 µV/°C
IBInput Bias Current See(5) −1.40 −2.6 µA
−3.25
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Slew rate is the average of the rising and falling slew rates.
(4) Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(5) Positive current corresponds to current flowing into the device.
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±5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for at TJ= 25°C, VSUPPLY = ±5V, VO= VCM = GND, and RL= 2kΩto V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(1) Typ(2) Max(1) Units
IOS Input Offset Current 20 800 nA
1000
RIN Common Mode Input Resistance AV+1, f = 1kHz, RS= 1MΩ7.5 MΩ
CIN Common Mode Input AV= +1, RS= 100kΩ1.28 pF
Capacitance
CMVR Common Mode Input Voltage CMRR ≥50dB −5.3 −5.2
Range −5.1 V
3.8 4.0
3.6
CMRR Common Mode Rejection Ratio See(6) 72 95 dB
AVOL Large Signal Voltage Gain VO= 9VPP, RL= 2kΩ88 100
84 dB
VO= 8VPP, RL= 150Ω74 77
70
VOOutput Swing RL= 2kΩ, VID = 200mV 4.85 4.96
High RL= 150Ω, VID = 200mV 4.55 4.80 V
RL= 50Ω, VID = 200mV 3.60 4.55
Output Swing RL= 2kΩ, VID =−200mV −4.97 −4.90
Low RL= 150Ω, VID =−200mV −4.85 −4.55 V
RL= 50Ω, VID =−200mV −4.65 −4.30
ISC Output Short Circuit Current Sourcing to Ground(7) 100 168
80 mA
Sinking to Ground(7) 110 190
85
IOUT Output Current VO= 0.5V from either supply 112 mA
PSRR Power Supply Rejection Ratio See(8) 72 96 dB
ISSupply Current (Enabled) No Load 4.18 6.5
8.5 mA
Supply Current (Disabled) 0.758 1.0
1.3
TH_SD Threshold Voltage for Shutdown V+−1.67 V
Mode
I_SD PIN Shutdown Pin Input Current SD Pin Connected to −5V(9) −84 μA
TON On Time after Shutdown 83 nsec
TOFF Off Time to Shutdown 160 nsec
ROUT Output Resistance Closed Loop RF= 10kΩ, f = 1kHz, AV=−1 32 mΩ
RF= 10kΩ, f = 1MHz, AV=−1 226
(6) f ≤1kHz (see typical performance Characteristics)
(7) Short circuit test is a momentary test.
(8) f ≤1kHz (see typical performance Characteristics)
(9) Positive current corresponds to current flowing into the device.
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V+
1
2
3
45
6
7
8
N/C
-IN
+IN
V-
OUTPUT
N/C
SD
+
-
OUTPUT
V-
+IN
V+
-IN
+-
1
2
3
5
4
6
SD
LMH6639
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SNOS989G –JANUARY 2002–REVISED MARCH 2013
Connection Diagram
Figure 2. SOT-23-6 Figure 3. SOIC-8
Top View Top View
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0.1 110 100 1000
ISOURCE (mA)
0.01
0.1
1
10
VOUT FROM V+ (V)
125°C
85°C
25°C
-40°C
VS=±5V
0.1 110 100 1000
ISINK (mA)
0.01
0.1
1
10
VOUT FROM V-(V)
125°C
85°C
25°C
-40°C
VS=±5V
246 8 10 12
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
SATURATION VOLTAGE FROM V+ (V)
VS (V)
125°C
85°C
-40°C
25°C
RL = 150: TIED TO VS/
2
125°C
25°C -40°C
85°C
RL=150:TIED TO VS/2
2
0
SATURATION VOLTAGE FROM V- (V)
VS (V)
46 8 10 12
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
020 40 60 80 100 120140 160 180 200
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
ISINK (mA)
VOUT FROM V- (V)
-40°C
125°C
85°C
25°C
VS=±2.5V
0 20 40 60 80 100 120 140 160 180 200
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
VOUT FROM V+ (V)
-40°C
125°C
85°C
25°C
VS=±2.5V
ISOURCING (mA)
LMH6639
SNOS989G –JANUARY 2002–REVISED MARCH 2013
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Typical Performance Characteristics
At TJ= 25°C, V+= +2.5, V−=−2.5V, RF= 330Ωfor AV= +2, RF= 1kΩfor AV=−1. Unless otherwise specified.
Output Sinking Saturation Voltage vs. IOUT Output Sourcing Saturation Voltage vs. IOUT
for Various Temperature for Various Temperature
Figure 4. Figure 5.
Positive Output Saturation Voltage vs. VSUPPLY Negative Output Saturation Voltage vs. VSUPPLY
for Various Temperature for Various Temperature
Figure 6. Figure 7.
VOUT from V+vs. VOUT from V−vs.
ISOURCE ISINK
Figure 8. Figure 9.
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VOS (mV)
2345678910
VS (V)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
TJ= -40°C
UNIT 1
UNIT 3
UNIT 2
-1 458910
2
2.5
3.5
4
4.5
5
5.5
6
6.5
7
IS (mA)
VCM (V)
3
1 2 36 7
0
125°C
85°C
VS=10V
-40°C
25°C
2345678910
VS (V)
-1.5
-1
-0.5
0
0.5
1
VOS (mV)
TJ = 85°C
UNIT 1
UNIT 3
UNIT 2
2345678910
VS (V)
-1.2
-1
-0.6
-0.4
-0.2
0
0.4
0.6
VOS (mV)
TJ = 25°C
UNIT 3
-0.8
0.2 UNIT 1
UNIT 2
246810 12
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
IOS (nA)
VS (V)
125°C
85°C
25°C
-40°C
2345678910
VS (V)
-2
-1.5
-1
-0.5
0
1
VOS (mV)
TJ = 125°C
UNIT 3
0.5
UNIT 1
UNIT 2
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SNOS989G –JANUARY 2002–REVISED MARCH 2013
Typical Performance Characteristics (continued)
At TJ= 25°C, V+= +2.5, V−=−2.5V, RF= 330Ωfor AV= +2, RF= 1kΩfor AV=−1. Unless otherwise specified.
IOS vs. VOS vs.
VSfor Various Temperature VSfor 3 Representative Units
Figure 10. Figure 11.
VOS vs. VOS vs.
VSfor 3 Representative Units VSfor 3 Representative Units
Figure 12. Figure 13.
VOS vs. ISUPPLY vs.
VSfor 3 Representative Units VCM for Various Temperature
Figure 14. Figure 15.
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10k 100k 1M 10M 100M 300M
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
dB
FREQUENCY (Hz)
RL = 500:
AV = +10
AV = +5
AV = +2
AV = +1
10k 100k 1M 10M 100M 300M
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
dB
FREQUENCY (Hz)
RL - 500:
AV = -1
AV = -2
AV = -5
AV = -10
1M 10M 100M 300M
-15
-12
-9
-6
-3
0
3
6
dB
FREQUENCY (Hz)
3V
10V
5V
AV = +1
RL = 500:
1M 10M 100M 300M
-36
-30
-24
-18
-12
-6
0
6
dB
FREQUENCY (Hz)
AV = -1
RL = 500:
5V
3V
10V
VS = 10V
VS = 3V
23 4 5 67 8 911
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
IS (mA)
VS (V) 10
125°C
-40°C
85°C
25°C
24681
0
-2.6
-2.4
-2.2
-2
-1.8
-1.6
-1.4
-1.2
-1
IB (µA)
VS (V)
-40°C
85°C
125°C
25°C
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Typical Performance Characteristics (continued)
At TJ= 25°C, V+= +2.5, V−=−2.5V, RF= 330Ωfor AV= +2, RF= 1kΩfor AV=−1. Unless otherwise specified.
ISUPPLY vs. IBvs.
VSfor Various Temperature VSfor Various Temperature
Figure 16. Figure 17.
Bandwidth for Various VSBandwidth for Various VS
Figure 18. Figure 19.
Gain vs. Gain vs.
Frequency Normalized Frequency Normalized
Figure 20. Figure 21.
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-100 -75 -50 -25 025 50 75 100
DIFF GAIN (%)
IRE
DIFF PHASE (°)
-0.1
0.14
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
-0.05
0.07
-0.04
-0.03
-0.02
-0.01
0.00
0.01
0.02
0.03
0.04
0.05
0.06
GAIN
PHASE
VS = 5V
RL = 150:
f = 3.58MHz
80 ns/DIV
-0.2
0.3
0.8
VOLT
0
SHUTDOWN PULSE
SWITCHED DC VOLTAGE
AV = 2
11.5 2 2.5 3 3.5 4 4.5 4.75
OUTPUT VOLTAGE (VPP)
-100
-90
-80
-70
-60
-50
-40
DISTORTION (dBc)
f = 5MHz
A = +2
RL = 1k
VS = 5V
THD
2nd
3rd
4th
3rd
2nd
100k 1M 10
M100M 300M
-25
-20
-15
-10
-5
0
5
10
dB
FREQUENCY (Hz)
85°C
-40°C
25°C
AV = +1
RL = 500:
100k 1
M10M 100M
FREQUENCY (Hz)
-1.00
-0.80
-0.60
-0.40
-0.20
0.00
0.20
dB
RS = 1k
RF = 2.65k VS = 3V
RF = 2.51k VS = 5V
RF = 2.26k VS = 10V
3V
10V
5V
+
-
RF
RS
100k 1M 10M 100M
FREQUENCY (Hz)
-30
-20
-10
0
10
20
30
40
50
60
70
GAIN (dB)
-60
-40
-20
0
20
40
60
80
100
120
140
PHASE (°)
200M
GAIN
85/25/ & -40°C
PHASE
85/25/ & -40°C
LMH6639
www.ti.com
SNOS989G –JANUARY 2002–REVISED MARCH 2013
Typical Performance Characteristics (continued)
At TJ= 25°C, V+= +2.5, V−=−2.5V, RF= 330Ωfor AV= +2, RF= 1kΩfor AV=−1. Unless otherwise specified.
Gain and phase vs.
0.1dB Gain Flatness Frequency for Various Temperature
Figure 22. Figure 23.
Frequency Response vs.
Temperature Harmonic Distortion
Figure 24. Figure 25.
Differential Gain/Phase On-Off Switching DC Voltage
Figure 26. Figure 27.
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LMH6639
OUTPUT
(dBm)
-10 -6 -2 26 8 12 16
INPUT (dBm)
-15
-10
-5
0
5
10
15
20
10 144
0
-4
-8
AV = +1
VS = 5V
1MHz
10MHz
25MHz
100MHz
50MHz
10 1k 100k 10M
FREQUENCY (Hz)
dB
1M
10k
100
120
0
80
100
60
40
20
VS = 10V
VS =
5V VS = 3V
-1.50
-1.00
-0.50
0.00
0.50
1.00
1.50
VOLT
4 ns/DIV
INPUT
OUTPUT
25 ms/DIV
-2.00
-1.00
0.00
1.00
VOLT
SHUTDOWN PULSE
AV = +2
-1.50
-1.00
-0.50
0.00
0.50
1.00
1.50
VOLT
4 ns/DIV
OUTPUT
INPUT
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
VOLT
100 ns/DIV
SHUTDOWN PULSE
SWITCHED 10MHz SIGNAL
AV = 2
LMH6639
SNOS989G –JANUARY 2002–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
At TJ= 25°C, V+= +2.5, V−=−2.5V, RF= 330Ωfor AV= +2, RF= 1kΩfor AV=−1. Unless otherwise specified.
On-Off Switching 10MHz Slew Rate (Positive)
Figure 28. Figure 29.
Slew Rate (Negative) On-Off Switching of Sinewave
Figure 30. Figure 31.
CMRR vs.
Power Sweep Frequency
Figure 32. Figure 33.
12 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: LMH6639
1k 100k 100M
FREQUENCY (Hz)
-80
-60
-40
-10
dB
10M
1M
10k
-20
-50
-70
-30 AV = +1
AV = +2
50 ns/DIV
50 mV/DIV
VS = 3 to 10V
1k 10k 100k 1M 10M
FREQUENCY (Hz)
0
5
10
15
20
25
30
35
40 VS = 3V TO 10V
Hz)
en(nV/
100 10k 10M
FREQUENCY
(Hz)
0
200
1000
m:
1M
100k
1k
900
500
100
800
600
400
300
700
RF = RS = 10k
AV = -1
3V
5V
10V
1k 10k 100k 1M
FREQUENCY (Hz)
0
1
2
3
4
5
6VS = 3V TO 10V
RF = 1M
(pA/ Hz)
INPUT CURRENT NOISE
80
10 1k 100k 10M
FREQUENCY (Hz)
0
20
50
dB
1M
10k
100
70
60
40
30
10 VS = 5V
AV = +1
NEGATIVE PSRR
POSITIVE PSRR
LMH6639
www.ti.com
SNOS989G –JANUARY 2002–REVISED MARCH 2013
Typical Performance Characteristics (continued)
At TJ= 25°C, V+= +2.5, V−=−2.5V, RF= 330Ωfor AV= +2, RF= 1kΩfor AV=−1. Unless otherwise specified.
PSRR vs.
Frequency Current Noise
Figure 34. Figure 35.
Closed Loop Output Resistance vs.
Voltage Noise Frequency
Figure 36. Figure 37.
Off Isolation Small Signal Pulse Response (AV= +1, RL= 2k )
Figure 38. Figure 39.
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMH6639
0.5 V/DIV
50 ns/DIV
VS = 5V
AV = +1
RL = 100:
CL = ~5pF
0.5 V/DIV
50 ns/DIV
VS = 10V
AV = +1
RL = 100:
CL = ~ 5pF
0.5 V/DIV
50 ns/DIV
VS = 3V
AV = +1
RL = 100:
CL = ~ 5pF
50 ns/DIV
50 mV/DIV
VS = 3 to 10V
CL = 10pF
RS = 10:
LMH6639
SNOS989G –JANUARY 2002–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
At TJ= 25°C, V+= +2.5, V−=−2.5V, RF= 330Ωfor AV= +2, RF= 1kΩfor AV=−1. Unless otherwise specified.
Small Signal Pulse Response (AV=−1) Large Signal Pulse Response (RL= 2k)
Figure 40. Figure 41.
Large Signal Pulse Response Large Signal Pulse Response
Figure 42. Figure 43.
14 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: LMH6639
4
2
38
7
5V
6
1k
-
+SD
CIN COUT
IN+ IN-
R R
V-
V+
V+V+
V-
LMH6639
www.ti.com
SNOS989G –JANUARY 2002–REVISED MARCH 2013
APPLICATION NOTES
INPUT AND OUTPUT TOPOLOGY
All input / output pins are protected against excessive voltages by ESD diodes connected to V+ and V- rails (see
Figure 44). These diodes start conducting when the input / output pin voltage approaches 1Vbe beyond V+ or V-
to protect against over voltage. These diodes are normally reverse biased. Further protection of the inputs is
provided by the two resistors (R in Figure 44), in conjunction with the string of anti-parallel diodes connected
between both bases of the input stage. The combination of these resistors and diodes reduces excessive
differential input voltages approaching 2Vbe. The most common situation when this occurs is when the device is
put in shutdown and the LMH6639’s inputs no longer follow each other. In such a case, the diodes may conduct.
As a consequence, input current increases, and a portion of signal may appear at the Hi-Z output. Another
possible situation for the conduction of these diodes is when the LMH6639 is used as a comparator (or with little
or no feedback). In either case, it is important to make sure that the subsequent current flow through the device
input pins does not violate the Absolute Maximum Ratings of the device. To limit the current through the
protection circuit extra series resistors can be placed. Together with the build in series resistors of several
hundred ohms this extra resistors can limit the input current to a safe number depending on the used application.
Be aware of the effect that extra series resistors may impact the switching speed of the device. A special
situation occurs when the part is configured for a gain of +1, which means the output is directly connected to the
inverting input, see Figure 45. When the part is now placed in shutdown mode the output comes in a high
impedance state and is unable to keep the inverting input at the same level as the non-inverting input. In many
applications the output is connected to the ground via a low impedance resistor. When this situation occurs and
there is a DC voltage offset of more than 2 volt between the non-inverting input and the output, current flows
from the non-inverting input through the series resistors R via the bypass diodes to the output. Now the input
current becomes much bigger than expected and in many cases the source at the input cannot deliver this
current and will drop down. Be sure in this situation that no DC current path is available from the non-inverting
input to the output pin, or from the output pin to the load resistor. This DC path is drawn by a curved line and can
be broken by placing one of the capacitors CIN or COUT or both, depending on the used application.
Figure 44.
Figure 45. DC path while in shutdown
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMH6639
-1
-0.5
0
0.5
1
1.5
VOLT
TIME (400 ns/DIV)
SHUTDOWN
330:330:
330:330:
5V
2
3
48
6
7
5V
76
8
4
4
2
38
7
5V
6OUT
2k
1k
1k
VREF
-
+
IC3
IC2
IC1
-
+
+
-
FREQ 2
FREQ 1
SD
SD
50
50
5V
LMH6639
SNOS989G –JANUARY 2002–REVISED MARCH 2013
www.ti.com
MULTIPLEXING 5 AND 10MHz
The LMH6639 may be used to implement a circuit which multiplexes two signals of different frequencies. Three
LMH6639 high speed op-amps are used in the circuit of Figure 46 to accomplish the multiplexing function. Two
LMH6639 are used to provide gain for the input signals, and the third device is used to provide output gain for
the selected signal.
Note: Pin numbers pertain to SOIC-8 package
Figure 46. Multiplexer
Multiplexing signals “FREQ 1” and “FREQ 2” exhibit closed loop non-inverting gain of +2 each based upon
identical 330Ωresistors in the gain setting positions of IC1 and IC2. The two multiplexing signals are combined
at the input of IC3, which is the third LMH6639. This amplifier may be used as a unity gain buffer or may be used
to set a particular gain for the circuit.
Figure 47. Switching between 5 and 10MHz
1k resistors are used to set an inverting gain of −1 for IC3 in the circuit of Figure 46.Figure 47 illustrates the
waveforms produced. The upper trace shows the switching waveform used to switch between the 5MHz and
10MHz multiplex signals. The lower trace shows the output waveform consisting of 5MHz and 10MHz signals
corresponding to the high or low state of the switching signal.
16 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: LMH6639
+
-SD
V+
V-
PUSH-PULL
OUTPUT
LOGIC GATE
V+
V-
V+
V-
LMH6639
+
-SD
V+
V-
PUSH-PULL
OUTPUT
LOGIC GATE
VS
V+
V-
LMH6639
LMH6639
www.ti.com
SNOS989G –JANUARY 2002–REVISED MARCH 2013
In the circuit of Figure 46, the outputs of IC1 and IC2 are tied together such that their output impedances are
placed in parallel at the input of IC3. The output impedance of the disabled amplifier is high compared both to the
output impedance of the active amplifier and the 330Ωgain setting resistors. The closed loop output resistance
for the LMH6639 is around 0.2Ω. Thus the active state amplifier output impedance dominates the input node to
IC3, while the disabled amplifier is assured of a high level of suppression of unwanted signals which might be
present at the output.
SHUTDOWN OPERATION
With SD pin left floating, the device enters normal operation. However, since the SD pin has high input
impedance, it is best tied to V+for normal operation. This will avoid inadvertent shutdown due to capacitive pick-
up from nearby nodes. LMH6639 will typically go into shutdown when SD pin is more than 1.7V below V+,
regardless of operating supplies.
The SD pin can be driven by push-pull or open collector (open drain) output logic. Because the LMH6639's
shutdown is referenced to V+, interfacing to the shutdown logic is rather simple, for both single and dual supply
operation, with either form of logic used. Typical configurations are shown in Figure 48 and Figure 49 below for
push-pull output:
Figure 48. Shutdown Interface (Single Supply)
Figure 49. Shutdown Interface (Dual Supplies)
Common voltages for logic gates are +5V or +3V. To ensure proper power on/off with these supplies, the logic
should be able to swing to 3.4V and 1.4V minimum, respectively.
LMH6639’s shutdown pin can also be easily controlled in applications where the analog and digital sections are
operated at different supplies. Figure 50 shows a configuration where a logic output, SD, can turn the LMH6639
on and off, independent of what supplies are used for the analog and the digital sections:
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LMH6639
+
-+
-SD
V+
V-
V+
LMH6639
SD
LMH6639
SNOS989G –JANUARY 2002–REVISED MARCH 2013
www.ti.com
Figure 50. Shutdown Interface (Single Supply, Open Collector Logic)
The LMH6639 has an internal pull-up resistor on SD such that if left un-connected, the device will be in normal
operation. Therefore, no pull-up resistor is needed on this pin. Another common application is where the
transistor in Figure 50 above, would be internal to an open collector (open drain) logic gate; the basic
connections will remain the same as shown.
PCB LAYOUT CONSIDERATION AND COMPONENTS SELECTION
Care should be taken while placing components on a PCB. All standard rules should be followed especially the
ones for high frequency and/ or high gain designs. Input and output pins should be separated to reduce cross-
talk, especially under high gain conditions. A groundplane will be helpful to avoid oscillations. In addition, a
ground plane can be used to create micro-strip transmission lines for matching purposes. Power supply, as well
as shutdown pin de-coupling will reduce cross-talk and chances of oscillations.
Another important parameter in working with high speed amplifiers is the component values selection. Choosing
high value resistances reduces the cut-off frequency because of the influence of parasitic capacitances. On the
other hand choosing the resistor values too low could "load down" the nodes and will contribute to higher overall
power dissipation. Keeping resistor values at several hundreds of ohms up to several kΩwill offer good
performance.
Texas Instruments suggests the following evaluation boards as a guide for high frequency layout and as an aid in
device testing and characterization:
Device Package Evaluation Board PN
LMH6639MA 8-Pin SOIC CLC730027
LMH6639MF SOT-23-6 CLC730116
18 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: LMH6639
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH6639 MDC ACTIVE DIESALE Y 0 400 RoHS & Green Call TI Level-1-NA-UNLIM -40 to 85
LMH6639MA NRND SOIC D 8 95 Non-RoHS
& Green Call TI Call TI -40 to 85 LMH66
39MA
LMH6639MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH66
39MA
LMH6639MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH66
39MA
LMH6639MF NRND SOT-23 DBV 6 1000 Non-RoHS
& Green Call TI Call TI -40 to 85 A81A
LMH6639MF/NOPB ACTIVE SOT-23 DBV 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A81A
LMH6639MFX/NOPB ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A81A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 2
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH6639MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6639MF SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6639MF/NOPB SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6639MFX/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6639MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6639MF SOT-23 DBV 6 1000 210.0 185.0 35.0
LMH6639MF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0
LMH6639MFX/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.45 MAX
0.15
0.00 TYP
6X 0.50
0.25
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
6
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
6X (1.1)
6X (0.6)
(2.6)
2X (0.95)
(R0.05) TYP
4214840/B 03/2018
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
6
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
2X(0.95)
6X (1.1)
6X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
6
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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