54FCT533 Octal Transparent Latch with TRI-STATE (R) Outputs General Description Features The FCT533 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. n n n n Eight latches in a single package TTL input and output level compatible CMOS power consumption TRI-STATE outputs drive bus lines or buffer memory address registers n Output sink capability of 32mA, source capability of 12 mA n Inverted version of the FCT373 n Standard Microcircuit Drawing (SMD) 5962-8865101 Logic Symbols IEEE/IEC DS100969-1 DS100969-2 Pin Names Description D0-D7 Data Inputs LE Latch Enable Input OE Output Enable Input O0-O7 TRI-STATE Latch Outputs TRI-STATE (R) is a registered trademark of National Semiconductor Corporation. FACTTM is a trademark of Fairchild Semiconductor Corporation. (c) 1998 National Semiconductor Corporation DS100969 www.national.com 54FCT533 Octal Transparent Latch with TRI-STATE Outputs September 1998 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100969-4 DS100969-3 Truth Table Functional Description The FCT533 contains eight D-type latches with TRI-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Inputs Outputs LE OE Dn X H X Z H L L H H L H L L L X O0 On H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH to Low transition of Latch Enable Logic Diagram DS100969-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) DC Latchup Source or Sink Current Junction Temperature (TJ) CDIP If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) -0.5V to +7.0V 300 mA 175C Recommended Operating Conditions -20 mA +20 mA -0.5V to VCC + 0.5V Supply Voltage (VCC) 'FCT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54FCT -20 mA +20 mA -0.5V to VCC + 0.5V 4.5V to 5.5V 0V to VCC 0V to VCC -55C to +125C Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT (R) circuits outside databook specifications. 50 mA 50 mA -65C to +150C DC Characteristics for 'FCT Family Devices Symbol Parameter FCT541 Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current Typ Units VCC Conditions Max 2.0 V 0.8 V -1.2 V Recognized HIGH Signal Min 54FCT 4.3 V Min 54FCT 2.4 V Min V Min 54FCT 0.2 54FCT 0.5 V Min 5 A Max Recognized LOW Signal IIN = -18 mA IOH = -300 A IOH = -12 mA IOL = 300 A IOL = 32 mA VIN = VCC VIN = 0.0V VOUT = 5.5V; OEn = 2.0V VOUT = 0.0V; OEn = 2.0V VOUT = 0.0V IIL Input LOW Current -5 A Max IOZH Output Leakage Current 10 A Max IOZL Output Leakage Current -10 A Max IOS Output Short-Circuit Current -60 mA Max ICCQ Quiescent Power Supply Current 1.5 mA Max ICC Quiescent Power Supply Current 2.0 mA Max ICCD Dynamic ICC 0.4 mA/ MHz Max VCC = 5.5V, Outputs Open, One Bit Toggling, 50% Duty Cycle, OEn = GND ICC Total Power Supply Current 6.0 mA Max VCC = 5.5V, Outputs Open, fI = 10MHz, OEn = GND, One Bit Toggling, 50% Duty Cycle VIN < 0.2V or VIN 5.3V, VCC = 5.5V VI = VCC - 2.1V Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. 3 www.national.com AC Electrical Characteristics 54FCT TA = -55C VCC Symbol Parameter (V) (Note 4) tPHL, tPLH Propagation Delay Fig. to +125C CL = 50 pF Units Min Max 5.0 1.5 12.0 ns 5.0 2.0 14.0 ns No. Dn to On tPHL, tPLH Propagation Delay LE to On tPZL, tPZH Output Enable Time 5.0 1.5 12.5 ns tPHZ, tPLZ Output Disable Time 5.0 1.5 8.5 ns Note 4: Voltage Range 5.0 is 5.0V 0.5V. AC Operating Requirements 54FCT TA = -55C VCC Symbol Parameter (V) to +125C CL = 50 pF (Note 5) Fig. Units Guaranteed Minimum tS Setup Time, HIGH or LOW 5.0 2.0 ns 5.0 3.0 ns 5.0 6.0 ns Dn to LE tH Hold Time, HIGH or LOW Dn to LE tW LE Pulse Width, HIGH Note 5: Voltage Range 5.0 is 5.0V 0.5V. Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 10 pF Power Dissipation 40 pF Capacitance www.national.com 4 Conditions VCC = OPEN VCC = 5.0V No. Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 5 www.national.com 54FCT533 Octal Transparent Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. 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