74HC147D-T - NXP SEMICONDUCTORS - Datasheet.Directory

May, 2013 − Rev. 10

1Publication Order Number:

MC14069UB/D

MC14069UB

Hex Inverter

The MC14069UB hex inverter is constructed with MOS P−channel

and N−channel enhancement mode devices in a single monolithic

structure. These inverters find primary use where low power

dissipation and/or high noise immunity is desired. Each of the six

inverters is a single stage to minimize propagation delays.

Features

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Capable of Driving Two Low−Power TTL Loads or One

Low−Power Schottky TTL Load Over the Rated Temperature

Range

•Triple Diode Protection on All Inputs

•Pin−for−Pin Replacement for CD4069UB

•Meets JEDEC UB Specifications

•These Devices are Pb−Free and are RoHS Compliant

•NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range −0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient)

−0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin

±10 mA

PDPower Dissipation, per Package

(Note 1)

500 mW

TAAmbient Temperature Range −55 to +125 °C

Tstg Storage Temperature Range −65 to +150 °C

TLLead Temperature

(8−Second Soldering)

260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

MARKING

DIAGRAMS

1

14

PDIP−14

P SUFFIX

CASE 646

MC14069UBCP

AWLYYWWG

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14

DT SUFFIX

CASE 948G

1

14

14069UG

AWLYWW

14

069U

ALYWG

G

1

14

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Package

SOEIAJ−14

F SUFFIX

CASE 965

1

14

MC14069UB

ALYWG

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

http://onsemi.com

(Note: Microdot may be in either location)

G

MC14069UB

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2

Figure 1. Pin Assignment

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT 5

IN 5

OUT 6

IN 6

VDD

OUT 4

IN 4

OUT 2

IN 2

OUT 1

IN 1

VSS

OUT 3

IN 3

Figure 2. Circuit SchematicFigure 3. Logic Diagram

13

11

9

5

3

1

12

10

8

6

4

2

VDD = PIN 14

VSS = PIN 7

VDD

VSS

OUTPUT

INPUT*

*Double diode protection on all inputs not shown

Figure 4. Switching Time Test Circuit and Waveforms

PULSE

GENERATOR

VDD

VSS

7

INPUT

OUTPUT

CL

14

20 ns 20 ns

VDD

VSS

VOH

VOL

tTHL tTLH

OUTPUT

INPUT

tPHL tPLH

90%

50%

10%

90%

50%

10%

(1/6 of circuit shown)

ORDERING INFORMATION

Device Package Shipping†

MC14069UBCPG PDIP−14

(Pb−Free) 500 Units / Tape & Ammunition Box

MC14069UBDG SOIC−14

(Pb−Free) 55 Units / Rail

NLV14069UBDG*

MC14069UBDR2G SOIC−14

(Pb−Free) 2500 Units / Tape & Reel

NLV14069UBDR2G*

MC14069UBDTR2G TSSOP−14

(Pb−Free) 2500 Units / Tape & Reel

NLV14069UBDTR2G*

MC14069UBFELG SOEIAJ−14

(Pb−Free) 2000 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

MC14069UB

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎ

Symbo

l

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎ

− 55_C

ÎÎÎÎÎÎÎÎÎ

25_C

ÎÎÎÎÎ

125_C

ÎÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Typ (2)

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎÎ

Output Voltage “0” Level

Vin = VDD

Vin = 0 “1” Level

ÎÎÎ

VOL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎÎ

−

ÎÎÎ

0

ÎÎÎÎ

0.05

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎ

Vdc

ÎÎÎ

VOH

ÎÎÎ

5.0

10

15

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 4.5 Vdc)

(VO = 9.0 Vdc)

(VO = 13.5 Vdc)

“1” Level

(VO = 0.5 Vdc)

(VO = 1.0 Vdc)

(VO = 1.5 Vdc)

ÎÎÎ

VIL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

1.0

2.0

2.5

ÎÎÎÎ

−

ÎÎÎ

2.25

4.50

6.75

ÎÎÎÎ

1.0

2.0

2.5

ÎÎÎ

−

ÎÎÎ

1.0

2.0

2.5

ÎÎÎ

Vdc

ÎÎÎ

VIH

ÎÎÎ

5.0

10

15

ÎÎÎ

4.0

8.0

12.5

ÎÎÎ

−

ÎÎÎÎ

4.0

8.0

12.5

ÎÎÎ

2.75

5.50

8.25

ÎÎÎÎ

−

ÎÎÎ

4.0

8.0

12.5

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎ

IOH

ÎÎÎ

5.0

10

15

ÎÎÎ

– 3.0

– 0.64

– 1.6

– 4.2

ÎÎÎ

−

ÎÎÎÎ

– 2.4

– 0.51

– 1.3

– 3.4

ÎÎÎ

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎÎÎ

−

ÎÎÎ

– 1.7

– 0.36

– 0.9

– 2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎ

IOL

ÎÎÎ

5.0

10

15

ÎÎÎ

0.64

1.6

4.2

ÎÎÎ

−

ÎÎÎÎ

0.51

1.3

3.4

ÎÎÎ

0.88

2.25

8.8

ÎÎÎÎ

−

ÎÎÎ

0.36

0.9

2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎ

Iin

ÎÎÎ

15

ÎÎÎ

−

ÎÎÎ

± 0.1

ÎÎÎÎ

−

ÎÎÎ

±0.00001

ÎÎÎÎ

± 0.1

ÎÎÎ

−

ÎÎÎ

± 1.0

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎ

Cin

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎ

5.0

ÎÎÎÎ

7.5

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎ

IDD

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

0.25

0.5

1.0

ÎÎÎÎ

−

ÎÎÎ

0.0005

0.0010

0.0015

ÎÎÎÎ

0.25

0.5

1.0

ÎÎÎ

−

ÎÎÎ

7.5

15

30

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎ

Total Supply Current (3) (4)

(Dynamic plus Quiescent,

Per Gate) (CL = 50 pF)

ÎÎÎ

IT

ÎÎÎ

5.0

10

15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (0.3 mA/kHz) f + IDD/6

IT = (0.6 mA/kHz) f + IDD/6

IT = (0.9 mA/kHz) f + IDD/6

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎ

Output Rise and Fall Times (3)

(CL = 50 pF)

tTLH, tTHL = (1.35 ns/pF) CL + 33 ns

tTLH, tTHL = (0.60 ns/pF) CL + 20 ns

tTLH, tTHL = (0.40 ns/pF) CL + 20 ns

ÎÎÎ

tTLH,

tTHL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎ

100

50

40

ÎÎÎÎ

200

100

80

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Times (3)

(CL = 50 pF)

tPLH, tPHL = (0.90 ns/pF) CL + 20 ns

tPLH, tPHL = (0.36 ns/pF) CL + 22 ns

tPLH, tPHL = (0.26 ns/pF) CL + 17 ns

ÎÎÎ

tPLH,

tPHL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎ

65

40

30

ÎÎÎÎ

125

75

55

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

ns

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

MC14069UB

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4

PACKAGE DIMENSIONS

PDIP−14

CASE 646−06

ISSUE P

17

14 8

B

ADIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L

M−−− 10 −−− 10

N0.015 0.039 0.38 1.01

__

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

F

HG D

K

C

SEATING

PLANE

N

−T−

14 PL

M

0.13 (0.005)

L

M

J

0.290 0.310 7.37 7.87

MC14069UB

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5

PACKAGE DIMENSIONS

SOIC−14 NB

CASE 751A−03

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF AT

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PER

SIDE.

H

14 8

71

M

0.25 B M

C

h

X 45

SEATING

PLANE

A1

A

M

_

S

A

M

0.25 B S

C

b

13X

B

A

E

D

e

DETAIL A

L

A3

DETAIL A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

D8.55 8.75 0.337 0.344

E3.80 4.00 0.150 0.157

A1.35 1.75 0.054 0.068

b0.35 0.49 0.014 0.019

L0.40 1.25 0.016 0.049

e1.27 BSC 0.050 BSC

A3 0.19 0.25 0.008 0.010

A1 0.10 0.25 0.004 0.010

M0 7 0 7

H5.80 6.20 0.228 0.244

h0.25 0.50 0.010 0.019

__ __

6.50

14X

0.58

14X

1.18

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC14069UB

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6

PACKAGE DIMENSIONS

TSSOP−14

CASE 948G−01

ISSUE B

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V S

T

L−U−

SEATING

PLANE

0.10 (0.004)

−T−

ÇÇÇ

SECTION N−N

DETAIL E

JJ1

K

K1

ÉÉÉ

DETAIL E

F

M

−W−

0.25 (0.010)

8

14

7

1

PIN 1

IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

−V−

14X REFK

N

7.06

14X

0.36 14X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC14069UB

http://onsemi.com

7

PACKAGE DIMENSIONS

SOEIAJ−14

CASE 965−01

ISSUE B

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.004 0.008

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 1.42 --- 0.056

A1

HE

Q1

LE

_10 _0

_10 _

LE

Q1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

0.13 (0.005) M0.10 (0.004)

D

Z

E

1

14 8

7

eA

b

VIEW P

c

L

DETAIL P

M

A

b

c

D

E

e

L

M

Z

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Phone: 81−3−5817−1050

MC14069UB/D

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