PD-9.524D International Rectifier IRFR110 HEXFET Power MOSFET IRFU1 | 0 @ Dynamic dv/dt Rating Repetitive Avalanche Rated D _ Surface Mount (IRFR110) Vpss = 100V Straight Lead (IRFU110) @ Available in Tape & Reel 6 Rps(ony = 0.540 Fast Switching Ease of Paralleling S Ip =4.3A Description Third Generation HEXFETs from International Rectifier provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The D-Pak is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. D-PAK LPAK TO-252AA TO-2510A Absolute Maximum Ratings Parameter Max. Units Ip @ To = 26C Continuous Drain Current, Ves @ 10 V 43 Ip @ Tc = 100C | Continuous Drain Current, Ves @ 10 V 27 A Ibm Pulsed Drain Current 17 Pp @ Tc = 25C | Power Dissipation 25 w Pp @ Ta= 25C | Power Dissipation (PCB Mount)** 2.5 Linear Derating Factor 0.20 wre Linear Derating Factor (PCB Mount)** 0.020 Vas Gate-to-Source Voltage +20 Vv Eas Single Pulse Avalanche Energy 100 mJ lar Avalanche Current 4.3 A Ear Repetitive Avalanche Energy 2.5 md dv/dt Peak Diode Recovery dv/dt @ 5.5 Vins Ts, Tsta Junction and Storage Temperature Range -55 to +150 C Soldering Temperature, for 10 seconds 260 (1.6mm from case) Thermal Resistance Parameter Min. Typ. Max. Units Resc Junction-to-Case = 5.0 Raia Junction-to-Ambient (PCB mount)** = 50 C Reva Junction-to-Ambient _ _ 110 _| ** When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. 1133IRFR110, IRFU110 Electrical Characteristics @ Ty = 25C (unless otherwise specified) Parameter Min. | Typ. | Max. | Units Test Conditions Visripss Drain-to-Source Breakdown Voltage | 100 | | | V_ | Vas=0V, In= 250uA AVeryoss/ATy| Breakdown Voltage Temp. Coefficient |013 | | V/C | Reference to 25C, Ip= mA Rosvon} Static Drain-to-Source On-Resistance _ | 054 | Q | Vas=10V, In=2.6A Vesith Gate Threshold Voltage 2.0 | 40 Vv i Vos=Vas, !p= 250A Dis Forward Transconductance 1.6 _ + _ s | Vos=50V, Ip=2.6A . = 25 Vps=100V, Ves=0V Ipss Drain-to-Source Leakage Current = = | 350 A Vos=80V, Vas-OV, Ti=125C less Gate-to-Source Forward Leakage = _ 100 nA Ves=20V Gate-to-Source Reverse Leakage _ | -100 Ves=-20V Qg Total Gate Charge _ | 83 Ip=5.6A Qgs Gate-to-Source Charge | | 23 | nC | Vps=80v Qo Gate-to-Drain ("Miller") Charge _ _- 3.8 Vas=10V See Fig. 6 and 13 ta(on) Turn-On Delay Time _ 6.9 _ Vpp=50V t Rise Time = 16 =| ns [p=5.6A tacoth Turn-Off Delay Time 15 | Re=24 tf Fall Time _ 9.4 =~ | Ro=8.4Q See Figure 10 Lb Internal Drain Inductance 45 _ | e a pai } : nH_| from package i) Ls Internal Source Inductance | 754 and center of die contact 8 Cisg Input Capacitance _ 180 _~ Vaes=0V Coss Output Capacitance _ 80 _ PF | Vos=25V Crss Reverse Transfer Capacitance _- 15 _ f=1.0MHz See Figure 5 Source-Drain Ratings and Characteristics Parameter Min. | Typ. | Max. | Units Test Conditions Is Continuous Source Current _ _ 43 MOSFET symbol (Body Diode) . A showing the Ism Pulsed Source Current ~|}_ lw integral reverse = @ (Body Diode) p-n junction diode. s Vsp Diode Forward Voltage _ 2.5 Vo | Ty=25C, Is=4.3A, Vag=0V @ ter Reverse Recovery Time | | 100 | 200 | ns [Ty=25C, Ip=5.6A Qn Reverse Recovery Charge [ | 0.44 | 0.88 | pC | di/dt=100A/us @ ton Forward Tum-On Time Intrinsic turn-on time is neglegible (turn-on is dominated by Ls+Lp) Notes: @ Repetitive rating; pulse width limited by isps5.6A, di/dts75A/us, Vop<sV(eR)Dss, max. junction temperature (See Figure 11) Tys150C Vop=25V, starting Tj=25C, L=8.1mMH @ Pulse width < 300 us; duty cycle <2%. Re=25Q, las=4.3A (See Figure 12} 1134104 Ip, Drain Current (Amps) 20us PULSE WIDTH Te = 25C tov! to-t 10! Vos, Drain-to-Source Voltage (volts) 100 Fig 1. Typical Output Characteristics, Tc=25C Ip, Drain Current (Amps) 4 5 6 7 a g Vas, Gate-to-Source Voltage (volts) 40 Fig 3. Typical Transfer Characteristics IRFR110, IRFU110 400 Ip, Drain Current (Amps) 20us PULSE WIDTH Te = 150C tov! tort 400 104 Vps, Drain-to-Source Voltage (volts) Fig 2. Typical Output Characteristics, Tc=150C w ~% uw ~ o on on 10V Rps(on Drain-to-Source On Resistance (Normalized) 0.0 V6s = 60 -40 -20 0 20 40 60 80 100 120 440 160 Ty, Junction Temperature (C) Fig 4. Normalized On-Resistance Vs. Temperature 1135IRFR110, IRFU110 Veg = OV, f = IMHzZ Ciss = fgg + Cgg Cus Crss = Cad + Capacitance (pF) Veg, Gate-to-Source Voltage (volts) FOR TEST CIRCUIT SEE FIGURE 13 Cogs 409 40! 4 8 10 Vos, Drain-to-Source Voltage (volts) Qe, Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs. Drain-to-Source Voltage Gate-to-Source Voltage 10? OPERATION IN THIS AREA LIMITED g BY Aps (oN) E < a = E cS <x 10 a - o oS & = > & 6 Ty=150C c 8 3B 5 T 3=25C 6 1 > = o a & L a T 2 Ty=150C SINGLE 0.4 0.4 0. 0.4 0.8 4.2 1.6 2.0 4. 2 5 49 2 5 492 2 5 403 Vsp, Source-to-Drain Voltage (volts) Vps, Drain-to-Source Voltage (volts) Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area Forward Voltage 1136Ip, Drain Current (Amps) 5.0 B oO us nm o a 0.0 25 Fig 9. 50 75 100 125 150 Tc, Case Temperature (C) Maximum Drain Current Vs. Case Temperature Thermal Response (Zajc) o 10 e an 10 Fig 11. e 1075 SINGLE PULSE (THERMAL RESPONSE) 104 10-3 IRFR110, IRFU110 Vos > WANG D.U.T. x = 1Voo \T10v Pulse Width < 1ps Duty Factor < 0.1% L Fig 10b. Switching Time Waveforms Tt Pow feet tall . DUTY FACTOR, D=t41/t2 2. PEAK Tj=Ppm x Zehjc + Te O.4 t 10 ty, Rectangular Pulse Duration (seconds) Maximum Effective Transient Thermal Impedance, Junction-to-CaseIRFR110, IRFU110 Vary tp to obtain Vps > required las Ip TOP = 4.9A 2.78 BOTTOM 4.38 200 150 Fig 12a. Unclamped Inductive Test Circuit 100 V(BR)DSS 50 Eas, Single Pulse Energy (mJ) Vps 0 25 50 75 100 125 150 Starting Tj, Junction Temperature(C}) lag a Fig 12c. Maximum Avalanche Energy Fig 12b. Unclamped Inductive Waveforms Vs. Drain Current Current Regulator Vos Ves ama ft [ Ie = | Charge Current Sampling heststors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit Appendix A: Figure 14, Peak Diode Recovery dv/dt Test Circuit - See page 1505 Appendix B: Package Outline Mechanical Drawing See pages 1512, 1513 Appendix C: Part Marking Information See page 1518 : n 2 Appendix D: Tape & Reel Information See page 1523 Internatio nal 1138