1/11August 2004
■HIGH SPE ED:
tPD = 4.4ns (TYP.) at VCC = 3.3V
■5V TOLERANT INPUTS
■INPUT VOLTAGE LEVEL:
VIL=0.8V, VIH=2V AT VCC=3V
■LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA=25°C
■LOW NOISE:
VOLP = 0. 3V (TYP.) at VCC = 3.3V
■SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
■BALANCED PRO PAG AT ION DELAYS:
tPLH ≅ tPHL
■OPERATIN G VOLTAGE RANGE:
VCC(O PR) = 2V to 3.6V (1.2V Data Retention)
■PIN AND FUNCTION COMPAT IBLE WITH
74 SERIE S 32
■IMPROVED L ATCH-UP IMMU NI TY
■POWER DOWN PROTEC TION ON INPUTS
DESCRIPTION
The 74LVX32 is a low voltage CMOS QUAD
2-INPUT OR GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
The internal circuit is composed of 2 stages
includin g bu ffer output, which prov id es hig h noise
immunity and stable outpu t.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed pe rformance with
the t rue CMOS l ow power consumption. All inputs
and outputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient exces s voltage.
74LVX32
LOW VOLTAGE C MOS QUAD 2-I NPUT OR GATE
WITH 5V TOLERANT INPUTS
Fi gure 1: Pin C onnec t ion An d I E C Logi c Sy m bols
Table 1: Order Codes
PACKAGE T & R
SOP 74LVX32MTR
TSSOP 74LVX32TTR
TSSOPSOP
Rev. 4