MC1496, MC1496B
Balanced Modulators/
Demodulators
These devices were designed for use where the output voltage is a
product of an input voltage (signal) and a switching function (carrier).
Typical applications include suppressed carrier and amplitude
modulation, synchronous detection, FM detection, phase detection,
and chopper applications. See ON Semiconductor Application Note
AN531 for additional design information.
•Excellent Carrier Suppression –65 dB typ @ 0.5 MHz
–50 dB typ @ 10 MHz
•Adjustable Gain and Signal Handling
•Balanced Inputs and Outputs
•High Common Mode Rejection –85 dB typical
This device contains 8 active transistors.
Semiconductor Components Industries, LLC, 2001
September, 2001 – Rev. 6 1Publication Order Number:
MC1496/D
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SO–14
D SUFFIX
CASE 751A
14 1
14
1
PDIP–14
P SUFFIX
CASE 646
PIN CONNECTIONS
Signal Input 1
2
3
4
5
6
7
10
11
14
13
12
9
N/C
Output
Bias
Signal Input
Gain Adjust
Gain Adjust
Input Carrier
8
VEE
N/C
Output
N/C
Carrier Input
N/C
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
See general marking information in the device marking
section on page 11 of this data sheet.
DEVICE MARKING INFORMATION
IC = 500 kHz, IS = 1.0 kHz
IC = 500 kHz
IS = 1.0 kHz
60
40
20
0
Log Scale Id
499 kHz 500 kHz 501 kHz
IC = 500 kHz
IS = 1.0 kHz
IC = 500 kHz
IS = 1.0 kHz
499 kHz 500 kHz 501 kHz
Linear Scale
10
8.0
6.0
4.0
2.0
0
Figure 1. Suppressed
Carrier Output
Waveform
Figure 1. Suppressed
Carrier Output
Waveform
Figure 2. Suppressed
Carrier Spectrum
Figure 3. Amplitude
Modulation Output
Waveform
Figure 4. Amplitude–Modulation Spectrum
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2
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating Symbol Value Unit
Applied Voltage
(V6–V8, V10–V1, V12–V8, V12–V10, V8–V4, V8–V1, V10–V4, V6–V10, V2–V5, V3–V5) ∆V 30 Vdc
Differential Input Signal V8 – V10
V4 – V1 +5.0
±(5+I5Re)Vdc
Maximum Bias Current I510 mA
Thermal Resistance, Junction–to–Air
Plastic Dual In–Line Package RθJA 100 °C/W
Operating Ambient Temperature Range MC1496
MC1496B TA0 to +70
–40 to +125 °C
Storage Temperature Range Tstg –65 to +150 °C
NOTE: ESD data available upon request.
ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, VEE = –8.0 Vdc, I5 = 1.0 mAdc, RL = 3.9 kΩ, Re = 1.0 kΩ, TA = Tlow to Thigh,
all input and output characteristics are single–ended, unless otherwise noted.) (Note 1)
Characteristic Fig. Note Symbol Min Typ Max Unit
Carrier Feedthrough
VC = 60 mVrms sine wave and
offset adjusted to zero
VC = 300 mVpp square wave:
offset adjusted to zero
offset not adjusted
fC = 1.0 kHz
fC = 10 MHz
fC = 1.0 kHz
fC = 1.0 kHz
5 1 VCFT –
–
–
–
40
140
0.04
20
–
–
0.4
200
µVrms
mVrms
Carrier Suppression
fS = 10 kHz, 300 mVrms
fC = 500 kHz, 60 mVrms sine wave
fC = 10 MHz, 60 mVrms sine wave
5 2 VCS
40
–65
50 –
–
dB
k
Transadmittance Bandwidth (Magnitude) (RL = 50 Ω)
Carrier Input Port, VC = 60 mVrms sine wave
fS = 1.0 kHz, 300 mVrms sine wave
Signal Input Port, VS = 300 mVrms sine wave
|VC| = 0.5 Vdc
8 8 BW3dB –
–
300
80
–
–
MHz
Signal Gain (VS = 100 mVrms, f = 1.0 kHz; |VC|= 0.5 Vdc) 10 3 AVS 2.5 3.5 – V/V
Single–Ended Input Impedance, Signal Port, f = 5.0 MHz
Parallel Input Resistance
Parallel Input Capacitance
6 – rip
cip –
–200
2.0 –
–kΩ
pF
Single–Ended Output Impedance, f = 10 MHz
Parallel Output Resistance
Parallel Output Capacitance
6 – rop
coo –
–40
5.0 –
–kΩ
pF
Input Bias Current 7 –
I
12
30
µA
IbS I1 I4
2;I
bC I8 I10
2IbS
IbC –
–12
12 30
30
µ
Input Offset Current
IioS = I1–I4; IioC = I8–I10 7 – IioS
IioC–
–0.7
0.7 7.0
7.0 µA
Average Temperature Coefficient of Input Offset Current
(TA = –55°C to +125°C) 7 – TCIio– 2.0 – nA/°C
Output Offset Current (I6–I9) 7 – Ioo– 14 80 µA
Average Temperature Coefficient of Output Offset Current
(TA = –55°C to +125°C) 7 – TCIoo– 90 – nA/°C
Common–Mode Input Swing, Signal Port, fS = 1.0 kHz 9 4 CMV – 5.0 – Vpp
Common–Mode Gain, Signal Port, fS = 1.0 kHz, |VC|= 0.5 Vdc 9 – ACM – –85 – dB
Common–Mode Quiescent Output Voltage (Pin 6 or Pin 9) 10 – Vout – 8.0 – Vpp
Differential Output Voltage Swing Capability 10 – Vout – 8.0 – Vpp
Power Supply Current I6 +I12
Power Supply Current I14 7 6 ICC
IEE –
–2.0
3.0 4.0
5.0 mAdc
DC Power Dissipation 7 5 PD– 33 – mW
1. Tlow =0°C for MC1496 Thigh= +70°C for MC1496
= –40°C for MC1496B = +125°C for MC1496B
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3
GENERAL OPERATING INFORMATION
Carrier Feedthrough
Carrier feedthrough is defined as the output voltage at
carrier frequency with only the carrier applied (signal
voltage = 0).
Carrier null is achieved by balancing the currents in the
differential amplifier by means of a bias trim potentiometer
(R1 of Figure 5).
Carrier Suppression
Carrier suppression is defined as the ratio of each
sideband output to carrier output for the carrier and signal
voltage levels specified.
Carrier suppression is very dependent on carrier input
level, as shown in Figure 22. A low value of the carrier does
not fully switch the upper switching devices, and results in
lower signal gain, hence lower carrier suppression. A higher
than optimum carrier level results in unnecessary device and
circuit carrier feedthrough, which again degenerates the
suppression figure. The MC1496 has been characterized
with a 60 mVrms sinewave carrier input signal. This level
provides optimum carrier suppression at carrier frequencies
in the vicinity of 500 kHz, and is generally recommended for
balanced modulator applications.
Carrier feedthrough is independent of signal level, VS.
Thus carrier suppression can be maximized by operating
with large signal levels. However, a linear operating mode
must be maintained in the signal–input transistor pair – or
harmonics of the modulating signal will be generated and
appear in the device output as spurious sidebands of the
suppressed carrier. This requirement places an upper limit
on input–signal amplitude (see Figure 20). Note also that an
optimum carrier level is recommended in Figure 22 for good
carrier suppression and minimum spurious sideband
generation.
At higher frequencies circuit layout is very important in
order to minimize carrier feedthrough. Shielding may be
necessary in order to prevent capacitive coupling between
the carrier input leads and the output leads.
Signal Gain and Maximum Input Level
Signal gain (single–ended) at low frequencies is defined
as the voltage gain,
AVS Vo
VSRL
Re2rewhere re26 mV
I5(mA)
A constant dc potential is applied to the carrier input
terminals to fully switch two of the upper transistors “on”
and two transistors “o ff” (VC = 0.5 Vdc). This in ef fect forms
a cascode differential amplifier.
Linear operation requires that the signal input be below a
critical value determined by RE and the bias current I5.
VS I5 RE (Volts peak)
Note that in the test circuit of Figure 10, VS corresponds to
a maximum value of 1.0 V peak.
Common Mode Swing
The common–mode swing is the voltage which may be
applied to both bases of the signal differential amplifier,
without saturating the current sources or without saturating
the differential amplifier itself by swinging it into the upper
switching devices. This swing is variable depending on the
particular circuit and biasing conditions chosen.
Power Dissipation
Power dissipation, PD, within the integrated circuit
package should be calculated as the summation of the
voltage–current products at each port, i.e. assuming
V12 = V6, I5 = I6 = I12 and ignoring base current,
PD = 2 I5 (V6 – V14) + I5)V5 – V14 where subscripts refer
to pin numbers.
Design Equations
The following is a partial list of design equations needed
to operate the circuit with other supply voltages and input
conditions.
A. Operating Current
The i nternal b ias c urrents a re s et b y t he c onditions a t P in 5.
Assume: I5 = I6 = I12,
IBIC for all transistors
then :
R5V
I5 500 where: R5 is the resistor between
where: Pin 5 and ground
where: φ = 0.75 at TA = +25°C
The MC1496 has been characterized for the condition
I5 = 1.0 mA and is the generally recommended value.
B. Common–Mode Quiescent Output Voltage
V6 = V12 = V+ – I5 RL
Biasing
The MC1496 requires three dc bias voltage levels which
must be set externally. Guidelines for setting up these three
levels include maintaining at least 2.0 V collector–base bias
on all transistors while not exceeding the voltages given in
the absolute maximum rating table;
30 Vdc [(V6, V12) – (V8, V10)] 2 Vdc
30 Vdc [(V8, V10) – (V1, V4)] 2.7 Vdc
30 Vdc [(V1, V4) – (V5)] 2.7 Vdc
The foregoing conditions are based on the following
approximations:
V6 = V12, V8 = V10, V1 = V4
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Bias currents flowing into Pins 1, 4, 8 and 10 are transistor
base currents and can normally be neglected if external bias
dividers are designed to carry 1.0 mA or more.
Transadmittance Bandwidth
Carrier t ransadmittance b andwidth i s t he 3 .0 d B b andwidth
of the device forward transadmittance as defined by:
21Cio(each sideband)
vs(signal)
Vo0
Signal transadmittance b andwidth is t he 3 .0 dB b andwidth
of the device forward transadmittance as defined by:
21Sio(signal)
v
s
(signal)
Vc0.5 Vdc, Vo0
Coupling and Bypass Capacitors
Capacitors C1 and C2 (Figure 5) should be selected for a
reactance of less than 5.0 Ω at the carrier frequency.
Output Signal
The output signal is taken from Pins 6 and 12 either
balanced or single–ended. Figure 11 shows the output levels
of each of the two output sidebands resulting from variations
in both the carrier and modulating signal inputs with a
single–ended output connection.
Negative Supply
VEE should be dc only. The insertion of an RF choke in
series with VEE can enhance the stability of the internal
current sources.
Signal Port Stability
Under certain values of driving source impedance,
oscillation may occur. In this event, an RC suppression
network should be connected directly to each input using
short leads. This will reduce the Q of the source–tuned
circuits that cause the oscillation.
Signal Input
(Pins 1 and 4) 510
10 pF
An alternate method for low–frequency applications is to
insert a 1.0 kΩ resistor in series with the input (Pins 1, 4). In
this case input current drift may cause serious degradation
of carrier suppression.
NOTE: Shielding of input and output leads may be needed
to properly perform these tests.
Figure 5. Carrier Rejection and Suppression Figure 6. Input–Output Impedance
Figure 7. Bias and Offset Currents Figure 8. Transconductance Bandwidth
0.01
µF
2.0 k
-8.0 Vdc
I6
I9
1.0 k
I7
I8
6.8 k
Zout
+Vo
+
+Vo
I9
3
RL
3.9 k
VCC
12 Vdc
8
C1
0.1 µF
MC1496
1.0 k
2
Re
1.0 k
C2
0.1 µF
51
10 k
Modulating
Signal Input
Carrier
Input
VC
Carrier Null
515110 k
50 k
R1
VS-Vo
RL
3.9 k
I6
I4
6
14 5
12
-
2
Re = 1.0 k
3
Zin
0.5 V 8
10
I1
4
1-Vo
10
16
4
14 5
12
6.8 k
V-
I10 I5
-8.0 Vdc
VEE
1.0 k
MC1496
MC1496
MC1496 6
14 5
12
I10 6.8 k
-8.0 Vdc
VEE
VCC
12 Vdc
2
Re = 1.0 k
3
1.0 k
Modulating
Signal Input
Carrier
Input
VC
VS
0.1 µF
0.1 µF
1.0 k
51
1.0 k
14 5
6
12
1.0 k
23
Re
VCC
12 Vdc
2.0 k
+Vo
-Vo
6.8 k
10 k
Carrier Null
5110 k
50 k
V-
-8.0 Vdc
VEE
50 50
8
10
4
1
8
10
4
1
51
TEST CIRCUITS
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5
+Vo
33.9 k
VCC
12 Vdc
8
MC1496
2
Re = 1.0 k
1.0 k
0.5 V
1.0 k
50
+
VS-Vo
10
16
4
14 5
12
6.8 k
-8.0 Vdc
VEE
3.9 k
-
ACM 20 logVo
VS
Figure 9. Common Mode Gain Figure 10. Signal Gain and Output Swing
V , OUTPUT AMPLITUDE OF EACH SIDEBAND (Vrms)
O
r , PARALLEL INPUT RESISTANCE (k
ip
Figure 11. Sideband Output versus
Carrier Levels Figure 12. Signal–Port Parallel–Equivalent
Input Resistance versus Frequency
c , PARALLEL INPUT CAPACITANCE (pF)
ip
c , PARALLEL OUTPUT CAPACITANCE (pF)
o
p
Figure 13. Signal–Port Parallel–Equivalent
Input Capacitance versus Frequency Figure 14. Single–Ended Output Impedance
versus Frequency
TYPICAL CHARACTERISTICS
Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave),
VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25°C, unless otherwise noted.
I5 =
1.0 mA
+Vo
33.9 k
VCC
12 Vdc
2
Re = 1.0 k
-Vo
6
14 5
12
6.8 k
-8.0 Vdc
VEE
3.9 k
0.5 V
+-
1.0 k
1.0 k
VS
50
1.0
2.0
0
140
-rip
+rip
14
12
10
8.0
6.0
4.0
0
10010
120
0
10
1.0
20
5.0 100
40
50
1.0
1.0
f, FREQUENCY (MHz)
80
200
2.0
5.0
10
100
100
500
1.0 M
60
50
100102.0
3.0
2.0
1.0
0
5.0
400 mV
Signal Input = 600 mV
4.0
VC, CARRIER LEVEL (mVrms)
1.6
0
0.8
0
0.4
1.2
10050 150
5.0
100 mV
200 mV
300 mV
5020
f, FREQUENCY (MHz)f, FREQUENCY (MHz)
MC1496
8
10
1
4
rop
Ω)
r , PARALLEL OUTPUT RESISTANCE (k
op Ω)
cop
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6
-30
f, FREQUENCY (MHz)
20
10
0
-10
-20
0.1 1.0 10 1000.01
RL = 3.9 k
Re = 500 Ω
RL = 3.9 k
Re = 2.0 k
|VC| = 0.5 Vdc RL = 500 Ω
Re = 1.0 k
RL = 3.9 k (Standard
Re = 1.0 k Test Circuit)
A , SINGLEENDED VOLTAGE GAIN (dB)
VS
1001.0
Side Band
0.3
0.4
01000
fC, CARRIER FREQUENCY (MHz)
0.6
0.9
1.0
10
0.8
0.7
0.1
0.2
0.5
0.1
21, TRANSADMITTANCE (mmho)
80 0
fC ±3fS
800600400200
VS, INPUT SIGNAL AMPLITUDE (mVrms)
fC ±2fS
0
60
50
40
30
20
10
70
SUPPRESSION BELOW EACH FUNDAMENTAL
CARRIER SIDEBAND (dB)
fC
2fC
505.00.05 0.1 0.5 1.0 10
3fC
0
60
50
40
30
20
10
70
fC, CARRIER FREQUENCY (MHz)
SUPPRESSION BELOW EACH FUNDAMENTAL
CARRIER SIDEBAND (dB)
TA, AMBIENT TEMPERATURE (°C)
MC1496
(70°C)
-75 -50
60
7550250-25
50
40
30
20
10
100 125 150 175
70
CS
V , CARRIER SUPPRESION (dB)
AV
RL
Re2re
TYPICAL CHARACTERISTICS (continued)
Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave),
VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25°C, unless otherwise noted.
0.1
5010
10
1.0
0.01 1.0 5.00.05 0.1 0.5
fC, CARRIER FREQUENCY (MHz)
V , CARRIER OUTPUT VOLTAGE (mVrms)
CFT
Signal Port
0
Figure 15. Sideband and Signal Port
Transadmittances versus Frequency Figure 16. Carrier Suppression
versus Temperature
Figure 17. Signal–Port Frequency Response Figure 18. Carrier Suppression
versus Frequency
Figure 19. Carrier Feedthrough
versus Frequency Figure 20. Sideband Harmonic Suppression
versus Input Signal Level
γ
21
Iout
Vin Vout 0|VC|0.5Vdc
21
Iout(EachSideband)
Vin(Signal) Vout 0
Sideband Transadmittance
Signal Port Transadmittance
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500100 4003000 200
VC, CARRIER INPUT LEVEL (mVrms)
fC = 10 MHz
0
60
50
40
30
20
10
70
CS
V , CARRIER SUPPRESSION (dB)
2fC ±fS
2fC ±2fS
3fC ±fS
fC, CARRIER FREQUENCY (MHz)
50101.0 5.00.05 0.1 0.5
0
60
50
40
30
20
10
70
SUPPRESSION BELOW EACH FUNDAMENTAL
CARRIER SIDEBAND (dB)
Figure 21. Suppression of Carrier Harmonic
Sidebands versus Carrier Frequency Figure 22. Carrier Suppression versus
Carrier Input Level
fC = 500 kHz
OPERATIONS INFORMATION
The MC1496, a monolithic balanced modulator circuit, is
shown in Figure 23.
This c ircuit c onsists o f a n u pper q uad d ifferential a mplifier
driven by a standard differential amplifier with dual current
sources. The output collectors are cross–coupled so that
full–wave balanced multiplication of the two input voltages
occurs. That is, the output signal is a constant times the
product of the two input signals.
Mathematical analysis of linear ac signal multiplication
indicates t hat t he o utput s pectrum w ill c onsist o f o nly t he sum
and dif ference o f t he t wo i nput f requencies. Thus, t he device
may b e u sed a s a b alanced m odulator , d oubly b alanced m ixer ,
product detector, frequency doubler, and other applications
requiring these particular output signal characteristics.
The lower dif ferential amplifier has its emitters connected
to the package pins so that an external emitter resistance may
be used. Also, external load resistors are employed at the
device output.
Signal Levels
The upper quad differential amplifier may be operated
either in a linear or a saturated mode. The lower differential
amplifier is operated in a linear mode for most applications.
For low–level operation at both input ports, the output
signal will contain sum and difference frequency
components and have an amplitude which is a function of the
product of the input signal amplitudes.
For high–level operation at the carrier input port and
linear operation at the modulating signal port, the output
signal will contain sum and difference frequency
components of the modulating signal frequency and the
fundamental and odd harmonics of the carrier frequency.
The output amplitude will be a constant times the
modulating signal amplitude. Any amplitude variations in
the carrier signal will not appear in the output.
The linear signal handling capabilities of a differential
amplifier are well defined. With no emitter degeneration, the
maximum input voltage for linear operation is
approximately 25 mV peak. Since the upper differential
amplifier has its emitters internally connected, this voltage
applies to the carrier input port for all conditions.
Since the lower dif ferential amplifier has provisions for an
external emitter resistance, its linear signal handling range
may be adjusted by the user. The maximum input voltage for
linear operation may be approximated from the following
expression: V = (I5) (RE) volts peak.
This expression may be used to compute the minimum
value of RE for a given input voltage amplitude.
Signal
Input
Carrier
Input 8 (+)
500500 500
14VEE
Bias
VC
(Pin numbers
per G package)
Vo,
Output
(-) 12
2Gain
Adjust
3
(+) 6
VS
10 (-)
4 (-)
1 (+)
5
-Vo
Re 1.0 k
2
12 Vdc
RL
3.9 k
+Vo
VEE
-8.0 Vdc
6.8 k
I5
14
0.1 µF
12
MC1496 6
8
1.0 k1.0 k
50 k
51
10 k
10 k
0.1 µF
Carrier
Input
Modulating
Signal
Input
VS
VC
Carrier Null
51
3
51
4
1
10
5
RL
3.9 k
Figure 23. Circuit Schematic Figure 24. Typical Modulator Circuit
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Carrier Input Signal (VC)Approximate Voltage Gain Output Signal Frequency(s)
Low–level dc RLVC
2(RE2re)KT
qfM
High–level dc RL
RE2refM
Low–level ac RLVC(rms)
22
KT
q(RE2re)fC ±fM
High–level ac 0.637 RL
RE2refC ±fM, 3fC ±fM, 5fC ±fM, . . .
2. Low–level Modulating Signal, VM, assumed in all cases. VC is Carrier Input Voltage.
3. When the output signal contains multiple frequencies, the gain expression given is for the output amplitude ofeach of the two desired outputs,
fC + fM and fC – fM.
4. All gain expressions are for a single–ended output. For a dif ferential output connection, multiply each expression by two.
5. RL = Load resistance.
6. RE = Emitter resistance between Pins 2 and 3.
7. re = Transistor dynamic emitter resistance, at 25°C;
re 26mV
I5(mA)
8. K = Boltzmann′s Constant, T = temperature in degrees Kelvin, q = the charge on an electron.
KT
q26mV at room temperature
Figure 25. Voltage Gain and Output Frequencies
The gain from the modulating signal input port to the
output is the MC1496 gain parameter which is most often of
interest t o the designer. This gain has significance only when
the lower differential amplifier is operated in a linear mode,
but this includes most applications of the device.
As previously mentioned, the upper quad differential
amplifier may be operated either in a linear or a saturated
mode. Approximate gain expressions have been developed
for the MC1496 for a low–level modulating signal input and
the following carrier input conditions:
1) Low–level dc
2) High–level dc
3) Low–level ac
4) High–level ac
These gains are summarized in Figure NO TAG, along
with the frequency components contained in the output
signal.
APPLICATIONS INFORMATION
Double sideband suppressed carrier modulation is the
basic application of the MC1496. The suggested circuit for
this application is shown on the front page of this data sheet.
In some applications, it may be necessary to operate the
MC1496 with a single dc supply voltage instead of dual
supplies. Figure 26 shows a balanced modulator designed
for operation with a single 12 Vdc supply. Performance of
this circuit is similar to that of the dual supply modulator.
AM Modulator
The circuit shown in Figure 27 may be used as an
amplitude modulator with a minor modification.
All that is required to shift from suppressed carrier to AM
operation is to adjust the carrier null potentiometer for the
proper amount of carrier insertion in the output signal.
However, the suppressed carrier null circuitry as shown in
Figure 27 does not have sufficient adjustment range.
Therefore, the modulator may be modified for AM
operation by changing two resistor values in the null circuit
as shown in Figure 28.
Product Detector
The MC1496 makes an excellent SSB product detector
(see Figure 29).
This product detector has a sensitivity of 3.0 microvolts
and a dynamic range of 90 dB when operating at an
intermediate frequency of 9.0 MHz.
The detector is broadband for the entire high frequency
range. For operation at very low intermediate frequencies
down t o 5 0 kHz the 0.1 µF capacitors on Pins 8 and 10 should
be increased to 1.0 µF. Also, the output filter at Pin 12 can
be tailored to a specific intermediate frequency and audio
amplifier input impedance.
As in all applications of the MC1496, the emitter
resistance between Pins 2 and 3 may be increased or
decreased to adjust circuit gain, sensitivity, and dynamic
range.
This circuit may also be used as an AM detector by
introducing carrier signal at the carrier input and an AM
signal at the SSB input.
The carrier signal may be derived from the intermediate
frequency signal or generated locally . The carrier signal may
be introduced with or without modulation, provided its level
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9
is sufficiently high to saturate the upper quad differential
amplifier. If the carrier signal is modulated, a 300 mVrms
input level is recommended.
Doubly Balanced Mixer
The MC1496 may be used as a doubly balanced mixer
with either broadband or tuned narrow band input and output
networks.
The local oscillator signal is introduced at the carrier input
port with a recommended amplitude of 100 mVrms.
Figure 30 shows a mixer with a broadband input and a
tuned output.
Frequency Doubler
The MC1496 will operate as a frequency doubler by
introducing the same frequency at both input ports.
Figures 31 and 32 show a broadband frequency doubler
and a tuned output very high frequency (VHF) doubler,
respectively.
Phase Detection and FM Detection
The MC1496 will function as a phase detector . High–level
input signals are introduced at both inputs. When both inputs
are at the same frequency the MC1496 will deliver an output
which is a function of the phase dif ference between the two
input signals.
An FM detector may be constructed by using the phase
detector principle. A tuned circuit is added at one of the
inputs to cause the two input signals to vary in phase as a
function of frequency. The MC1496 will then provide an
output which is a function of the input signal frequency.
VS
DSB
MC1496
VCC
12 Vdc
-
R1
+
Carrier Input
60 mVrms
Carrier
Input
1.0 k1.0 k
Carrier Null
Carrier Adjust
1.0 k
Re 1.0 k
2RL
3.9 k
3RL
3.9 k
-Vo
+Vo
12
6
6.8 k
I5
VEE
-8.0 Vdc
10 k10 k 51 51
Modulating
Signal
Input
VC
14 5
0.1 µF
0.1 µF
50 k
+-
MC1496
Output
0.1 µF
0.1 µF0.1 µF
VCC
12 Vdc
10 k 100 100
10 k
3.0 k 3.0 k
1.0 k
1.3 k820
50 k 10 k
10 µF
15 V
Signal Input
300 mVrms
Modulating
Carrier
Null
+
25 µF
15 V 51
25 µF
15 V
23
14 5
Modulating
Signal
Input
VS
VC
1.0 µF
Carrier
Input
50 k
750 51 51750
VEE
-8.0 Vdc
15 6.8 k
RL
3.9 k
Re 1.0 k
23
14 5
0.1 µF
-Vo
+Vo
VCC
12 Vdc
51
51
1.0 k1.0 k
MC1496
23
14 5
MC1496
1.3 k820
1.0 k
Carrier Input
300 mVrms
SSB Input
51
100 3.0 k 3.0 k
0.005
µF
10 k
0.1
µF
1.0 k
0.1 µF0.1 µF
0.1 µF
0.1 µF
VCC
12 Vdc
AF
Output
RL 10 k
0.005
µF
TYPICAL APPLICATIONS
1.0 k
8
4
1
10
12
6
12
6
12
6
RL
3.9 k
8
4
1
10
8
4
1
10 8
4
1
10
Figure 26. Balanced Modulator
(12 Vdc Single Supply) Figure 27. Balanced Modulator–Demodulator
Figure 28. AM Modulator Circuit Figure 29. Product Detector
(12 Vdc Single Supply)
1.0 k
0.005
µF
MC1496, MC1496B
http://onsemi.com
10
(f + 2f )
C S
C S
C S
RFC
100 µH
(2f - 2f )
fC
fS
fC ±fS
fC ±nfS
nfC
nfC ±nfS
DEFINITIONS
Figure 30. Doubly Balanced Mixer
(Broadband Inputs, 9.0 MHz Tuned Output) Figure 31. Low–Frequency Doubler
Frequency Balanced Modulator Spectrum
L1 = 44 Turns AWG No. 28 Enameled Wire, Wound
on Micrometals Type 44–6 Toroid Core.
VCC
+8.0 Vdc
1.0 k
1.0 k
Null Adjust
0.001 µF
51
23
5
6.8 k
VEE
-8.0 Vdc
10 k 51
51 10 k
MC1496
0.001 µF
Local
Oscillator
Input
RF Input
100 mVrms
50 k
0.001 µF
9.5 µF
L1
5.0-80
pF 90-480 pF
9.0 MHz
Output
RL = 50Ω
0.01
µF
VCC
12 Vdc
3.9 k
3.9 k
5
23
MC1496
6.8 k
I5
VEE
-8.0 Vdc
1.0 k
10 k 10 k
100
100
100 µF 15 Vdc
100 µF
25 Vdc
+-
-
+
100
C2
100 µF
15 Vdc Max
1.0 k
1.0 k
C2
50 k
Balance
Input
15 mVrms
L1 = 1 Turn AWG
No. 18 Wire, 7/32″ ID
Balance
MC1496
300 MHz
Output
RL = 50Ω
1.0-10 pF
L1
18 nH
RFC
0.68 µH
0.001
µF
0.001
µF
1.0 k1.0 k
VCC
+8.0 Vdc
Output
100
0.001 µF
150 MHz
Input
10 k
10 k 100
50 k
23
18 pF
6.8 k
AMPLITUDE
(f )
C
C S
100
V+
VEE
-8.0 Vdc
(f - 2f )
C S
(f - f )
(f + f )
(2f - 2f )
(2f + 2f )
(2f + 2f )
(3f - 2f )
(3f - f )
(3f )
(3f + f )
(3f + 2f )
C
C S
C S
C S
C S
C S
C S
C S
(2f )
C
8
4
1
10
12
6
8
4
1
10
8
4
1
10
12
6
14 5
14
14
12
6
Figure 32. 150 to 300 MHz Doubler
Carrier Fundamental
Modulating Signal
Fundamental Carrier Sidebands
Fundamental Carrier Sideband Harmonics
Carrier Harmonics
Carrier Harmonic Sidebands
1.0-10 pF
MC1496, MC1496B
http://onsemi.com
11
ORDERING INFORMATION
Device Package Shipping
MC1496D SO–14 55 Units/Rail
MC1496DR2 SO–14 2500 Tape & Reel
MC1496P PDIP–14 25 Units/Rail
MC1496P1 PDIP–14 25 Units/Rail
MC1496BD SO–14 55 Units/Rail
MC1496BDR2 SO–14 2500 Tape & Reel
MC1496BP PDIP–14 25 Units/Rail
PDIP–14
P SUFFIX
CASE 646
SO–14
D SUFFIX
CASE 751A
MARKING DIAGRAMS
A = Assembly Location
WL = Wafer Lot
YY, Y = Year
WW = Work Week
1
14
MC1496D
AWLYWW
1
14
MC1496BD
AWLYWW
1
14
MC1496BP
AWLYYWW
1
14
MC1496P
AWLYYWW
MC1496, MC1496B
http://onsemi.com
12
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P7 PL
14 8
71 M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
–T–
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
 
SO–14
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
ISSUE F
PDIP–8
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE M
17
14 8
B
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 18.80
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L
M--- 10 --- 10
N0.015 0.039 0.38 1.01

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
HG DK
C
SEATING
PLANE
N
–T–
14 PL
M
0.13 (0.005)
L
M
J0.290 0.310 7.37 7.87
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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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