Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-
ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service mark s of Alter a Corpo ration in t he U.S. an d othe r co untries . All ot her produ ct or serv ice n ames are the pr operty o f the ir respective holders. Al-
tera products are protected under nu merous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Alte ra warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-
plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-
formation and before placing orders for products or services.
ii Altera Corporation
Altera Corporation iii
Contents
Chapter Revision Dates .......................................................................... vii
About This Handbook .............................................................................. ix
How to Find Information .......................................... ...................... .................................. ...................... ix
How to Contact Altera ...................................................... ............................................ ........................... ix
Typographic Conventions ................ ....................... ................................. ...................... .......................... x
Section I. Stratix Device Family Data Sheet
Revision History ............................................................................................................................ Part I–1
Chapter 1. Introduction
Introduction ............................................................................................................................................ 1–1
Features ................................................................................................................................................... 1–2
Chapter 2. Stratix Architecture
Functional Description .......................................................................................................................... 2–1
Logic Array Blocks ................................................................................................................................ 2–3
LAB Interconnects .... ............ ........... ...................... ...................... ...................... ............................... 2–4
LAB Control Signals ................... .. ............ ........... ...................... ...................... .................... ............. 2–5
Logic Elements ....................................................................................................................................... 2–6
LUT Chain & Regist er Chain .................... ...................... ........... ........... ....................... ........... ........ 2–8
addnsub Signal ................................................................................................................................. 2–8
LE Operating Modes ........................................................................................................................ 2–8
Clear & Preset Logic Control ...................................... ...................... ................................. ........... 2–13
MultiTrack Interconnect ..................................................................................................................... 2–14
TriMatrix Memory ............................................................................................................................... 2–21
Memory Modes ............................................................................................................................... 2–22
Clear Signals ............ ........... ....................... ........... ........... ...................... ........... ............................... 2–24
Parity Bit Support .............. ....................... .. ........... ...................... .................................. ................. 2–24
Shift Register Support .................................................................................................................... 2–25
Memory Block Size ......................................................................................................................... 2–26
Independent Clock Mode .............................................................................................................. 2–44
Input/Output Clock Mode ........................................................................................................... 2–46
Read/Write Clock Mode ............................................................................................................... 2–49
Single-Port Mode ............................................................................................................................ 2–51
Multiplier Block .............................................................................................................................. 2–57
Adder/Output Blocks ............... .................................. ...................... ................................. ........... 2–61
Modes of Operation ................... .. ............ ........... ...................... ...................... ..................... .......... 2–64
iv Altera Corporation
Contents Stratix Device Handbook, Volume 1
DSP Block Interface ........................................................................................................................ 2–70
PLLs & Clock Networks ..................................................................................................................... 2–73
Global & Hierarchical Clocking ................................................................................................... 2–73
Enhanced & Fast PLLs ................................................................................................................... 2–81
Enhanced PLLs ............................................................................................................................... 2–87
Fast PLLs ......... ........... ............ ...................... ........... ...................... ........... ........... ........................... 2–100
I/O Structure ...................................................................................................................................... 2–104
Double-Data Rate I/O Pins ............................................. ............................................. ............... 2–111
External RAM Interfacing ........................................................................................................... 2–115
Programmable Drive Strength ................. ............................................... ................................... 2–119
Open-Drain Output .................... ...................... ....................... ........... ...................... .................... 2–120
Slew-Rate Control ............. ............................................. ............................................ .................. 2–120
Bus Hold ......... ....................... ........... ........... ...................... ........... ...................... ........................... 2–121
Programmable Pull-Up Resis tor ..... ............................................ ............................................. .. 2–122
Advanced I/O Standard Support .............................................................................................. 2–122
Differential On-Chip Termination ............................................................................................. 2–127
MultiVolt I/O Interface ........................... .. ........... ............................................ ........................... 2–129
High-Speed Differential I/O Support ............................................................................................ 2–130
Dedicated Circuitry ......... ........... ...................... ....................... ...................... ............................... 2–137
Byte Alignment ................ ........... ...................... ............ ........... ...................... ........... .................... 2–140
Power Sequencing & Hot Socketing ............................................................................................... 2–140
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ............................................................................ 3–1
SignalTap II Embedded Logic Analyzer .......... .. ............ ............................................ ........................ 3–5
Configuration ......................................................................................................................................... 3–5
Operating Modes ........... ...................... ...................... ....................... ...................... ........... ............... 3–5
Configuring Stratix FPGAs with JRunner .................................................................................... 3–7
Configuration Schemes ................................................................................................................... 3–7
Partial Reconfiguration ..... ... ............................................................................................................ 3–7
Remote Update Configuration Modes .... ...................... ................................................................ 3–8
Stratix Automated Single Event Upset (SEU) Detection ................................................................ 3–12
Custom-Built Ci rcuitry ............ .. ........... ........... ....................... ...................... ...................... ........... 3–13
Software Interface ........................................................................................................................... 3–13
Temperature Sensing Diode ............................................................................................................... 3–13
Chapter 4. DC & Switching Characteristics
Operating Conditions ..................... .................................. ...................... .............................................. 4–1
Power Consumption ........................................................................................................................... 4–17
Timing Model ....................................................................................................................................... 4–19
Preliminary & Final Timing .......................................................................................................... 4–19
Performance .................................................................................................................................... 4–20
Internal Timing Parameters .......................................................................................................... 4–22
External Timing Parameters ......................................................................................................... 4–33
Stratix External I/O Timing ........... ...................... .. ........... ............................................. ............... 4–36
I/O Timing Measurement Methodology .................................................................................... 4–60
External I/O Delay Param eters .................................................................................................... 4–66
Altera Corporation v
Contents Contents
Maximum Input & Output Clock Rates .. ................................................................... .. ........... .. .. 4–76
High-Speed I/O Specification ....................... ............................................ ........................................ 4–87
PLL Specifications ................... ....................... ........... ...................... ...................... ............................... 4–94
DLL Specifications ............................................................................................................................. 4–102
Chapter 5. Reference & Ordering Informatio n
Software .................................................................................................................................................. 5–1
Device Pin-Outs ..................................................................................................................................... 5–1
Ordering Information ..................... .. ............ ............................................ ............................................ 5–1
Index
vi Altera Corporation
Contents Stratix Device Handbook, Volume 1
Altera Corporation vii
Chapter Revision Dates
The chapters in this book, Stratix Device Handbook, Volume 1, were revised on the following dates.
Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1. Introduction
Revised: July 2005
Part number: S51001-3.2
Chapter 2. Stratix Architecture
Revised: July 2005
Part number: S51002-3.2
Chapter 3. Configuration & Testing
Revised: July 2005
Part number: S51003-1.3
Chapter 4. DC & Switching Characteristics
Revised: January 2006
Part number: S51004-3.4
Chapter 5. Reference & Ordering Information
Revised: September 2004
Part number: S51005-2.1
viii Altera Corporation
Chapter Revision Dates Stratix Device Handbook, Volume 1
Altera Corporation ix
About This Handbook
This handbook provides comprehensive information about the Altera®
Stratix family of devices.
How to Find
Information You can find more information in the following ways:
■The Adobe Acrobat Find feature, which searches the text of a PDF
document. Click the binoculars toolbar icon to open the Find dialog
box.
■Acrobat bookmarks, which serve as an additional table of contents in
PDF documents.
■Thumbnail icons, which provid e miniature previews of each page,
provide a link to the page s.
■Numerous links, shown in green text, which allow you to jump to
related inform ati on.
How to Contact
Altera For the most up-to-date information about Altera products, go to the
Altera world-wide web site at www.altera.com. For technical support on
this product, go to www.altera.com/mysupport. For additional
information about Altera products, consult the sources shown below.
Information Type USA & Canada All Other Locations
Technical support www.altera.com/mysupport/ www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:00 a.m. to 5:00 p.m. Pacific Time) +1 408-544-8767
7:00 a.m. to 5:00 p.m. (GMT -8:00)
Pacific Time
Product literature www.altera.com www.altera.com
Altera literature services literature@altera.com literature@altera.com
Non-technical customer
service (800) 767-3753 + 1 408-544-7000
7:00 a.m. to 5:00 p.m. (GMT -8:00)
Pacific Time
FTP site ftp.altera.com ftp.altera.com
x Altera Corporation
Typographic Conventions Stratix Device Handbook, Volume 1
Typographic
Conventions This document uses the typographic conventions shown below.
Visual Cue Meaning
Bold Type with Initial
Capital Letters Command names, dialog box titles, checkbo x options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold
type. Examples: fMAX, \qdesigns directory, d: dr ive, chiptrip.gdf file.
Italic Type with Initial Capital
Letters Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Designs.
Italic type Internal timing parameters and variables are shown in italic type.
Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Initial Capital Letters K eyboard k e ys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title” References to sections within a document and titles of on-line help topics are
shown in quotation marks. Example: “Typographic Conventions.”
Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,
tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and
a., b., c., etc. Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■●• Bullets are used in a list of items when the sequence of the items is not important.
v The checkmark indicates a procedure that consists of one step only.
1 The hand points to information that requires special attention.
r The angled arrow indicates you should press the Enter key.
f The feet direct you to more information on a particular topic.
Altera Corporation Section I–1
Section I. Stratix Device
Family Data Sheet
This section provides the data sheet specifications for Strat ix® devices.
They contain feature definitions of the internal architecture,
configuration and JTAG boundary-scan testing inform ati on, DC
operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Stratix devices.
This section contains the following chapters:
■Chapter 1, Introduction
■Chapter 2, Stratix Architecture
■Chapter 3, Configuration & Testing
■Chapter 4, DC & Switching Characteristics
■Chapter 5, Reference & Ordering Information
Revision History The table below shows the rev ision hist ory for Chapters 1 through 5.
Chapter Date/V ersion Changes Made
1 July 2005, v3.2 ●Minor content changes.
September 2004, v3.1 ●Updated Table 1–6 on page 1–5.
April 2004, v3.0 ●Main section page numbers changed on first page.
●Changed PCI-X to PCI-X 1.0 in “Features” on page 1–2.
●Global change from SignalTap to SignalTap II.
●The DSP blocks in “Features” on page 1–2 provide dedicated
implementation of multipliers that are now “faster than 300 MHz.”
January 2004, v2.2 ●Updated -5 speed grade device information in Table 1-6.
October 2003, v2.1 ●Add -8 speed grade device information.
July 2003, v2.0 ●Format changes throughout chapter.
Section I–2 Altera Corporation
Stratix Device Family Data Sheet Stratix Device Handbook, Volume 1
2 July 2005 v3.2 ●Added “Clear Signals” section.
●Updated “Power Sequencing & Hot Socketing” section.
●Format changes.
September 2004, v3.1 ●Updated fast regional clock networks description on page 2–73.
●Deleted the word preliminary from the “specification for the maximum
time to relock is 100 µs” on page 2–90.
●Added information about differential SSTL and HSTL outputs in
“External Clock Outputs” on page 2–92.
●Updated notes in Figure 2–55 on page 2–93.
●Added information about m counter to “Clock Multiplication &
Division” on page 2–101.
●Updated Note 1 in Table 2–58 on page 2–101.
●Updated description of “Clock Multiplication & Division” on
page 2–88.
●Updated Table 2–22 on page 2–102.
●Added references to AN 349 and AN 329 to “External RAM
Interfacing” on page 2–115.
●Table 2–25 on page 2–116: updated the table, updated Notes 3 and
4. Notes 4, 5, and 6, are now Notes 5, 6, and 7, respectively.
●Updated Table 2–26 on page 2–117.
●Added information about PCI Compliance to page 2–120.
●Table 2–32 on page 2–126: updated the table and deleted Note 1.
●Updated reference to device pin-outs no w being availab le on the web
on page 2–130.
●Added Notes 4 and 5 to Table 2–36 on page 2–130.
●Updated Note 3 in Table 2–37 on page 2–131.
●Updated Note 5 in Table 2–41 on page 2–135.
April 2004, v3.0 ●Added note 3 to rows 11 and 12 in Table 2–18.
●Deleted “Stratix and Stratix GX Device PLL Availability” table.
●Added I/O standards row in Table 2–28 that support max and min
strength.
●Row clk [1,3,8,10] was removed from Table 2–30.
●Added checkmarks in Enhanced column for LVPECL, 3.3-V PCML,
LVDS, and HyperTransport technology rows in Table 2–32.
●Removed the Left and Right I/O Banks row in Table 2–34.
●Changed RCLK values in Figures 2–50 and 2–51.
●External RAM Interfacing section replaced.
November 2003, v2.2 ●Added 672-pin BGA package information in Table 2–37.
●Removed support for series and parallel on-chip termination.
●Termination Technology renamed differential on-chip termination.
●Updated the number of channels per PLL in Tables 2-38 through 2-
42.
●Updated Figures 2–65 and 2–67.
October 2003, v2.1 ●Updated DDR I information.
●Updated Table 2–22.
●Added Tables 2–25, 2–29, 2–30, and 2–72.
●Updated Figures 2–59, 2–65, and 2–67.
●Updated the Lock Detect section.
Chapter Date/V ersion Changes Made
Altera Corporation Section I–3
Stratix Device Family Data Sheet
2 July 2003, v2.0 ●Added reference on page 2-73 to Figures 2-50 and 2-51 for RCLK
connections.
●Updated ranges f or EP LL post-scale and pre-scale dividers on page
2-85.
●Updated PLL Reconfiguration frequency from 25 to 22 MHz on page
2-87.
●New requirement to assert are set signal each PLL when it has to re-
acquire lock on either a new clock after loss of lock (page 2-96).
●Updated max input frequency for CLK[1,3,8,10] from 462 to 500,
Table 2-24.
●Renamed impedance matching to series termination throughout.
●Updated naming convention for DQS pins on page 2-112 to match pin
tables.
●Added DDR SDRAM Performance Specification on page 2-117.
●Added external reference resistor values for terminator technology
(page 2-136).
●Added Terminator Technology Specification on pages 2-137 and 2-
138.
●Updated Tables 2-45 to 2-49 to reflect PLL cross-bank support for
high speed differential channels at full speed.
●Wire bond package performance specification for “high” speed
channels was increased to 624 Mbps from 462 Mbps throughout
chapter.
3 July 2005, v1.3 ●Updated “Operating Modes” section.
●Updated “Temperature Sensing Diode” section.
●Updated “IEEE Std. 1149.1 (JTA G) Boundary-Scan Support” section.
●Updated “Configuration” section.
January 2005, v1.2 ●Updated limits for JTAG chain of devices.
September 2004, v1.1 ●Added new section, “Stratix Automated Single Event Upset (SEU)
Detection” on page 3–12.
●Updated description of “Custom-Built Circuitry” on page 3–13.
April 2003, v1.0 ●No new changes in Stratix Device Handbook v2.0.
4 January 2006, v3.4 ●Added Table 4–135.
July 2005, v3.3 ●Updated Tables 4–6 and 4–30.
●Updated Tables 4–103 through 4–108.
●Updated Tables 4–114 through 4–124.
●Updated Table 4–129.
●Added Table 4–130.
Chapter Date/V ersion Changes Made
Section I–4 Altera Corporation
Stratix Device Family Data Sheet Stratix Device Handbook, Volume 1
4 January 2005, 3.2 ●Updated rise and fall input values.
September 2004, v3.1 ●Updated Note 3 in Table 4–8 on page 4–4.
●Updated Table 4–10 on page 4–6.
●Updated Table 4–20 on page 4–12 through Table 4–23 on
page 4–13. Added rows VIL(AC) and VIH(AC) to each table.
●Updated Table 4–26 on page 4–14 through Table 4–29 on
page 4–15.
●Updated Table 4–31 on page 4–16.
●Updated description of “External Timing Parameters” on page 4–33.
●Updated Table 4–36 on page 4–20.
●Added signals tOUTCO, TXZ, and TZX to Figure 4–4 on page 4–33.
●Added rows tM512CLKENSU and tM512CLKENH to Table 4–40 on
page 4–24.
●Added rows tM4CLKENSU and tM4CLKENH to Table 4–41 on page 4–24.
●Updated Note 2 in Table 4–54 on page 4–35.
●Added rows tMRAMCLKENSU and tMRAMCLKENH to Table 4–42 on
page 4–25.
●Updated Table 4–46 on page 4–29.
●Updated Table 4–47 on page 4–29.
Chapter Date/V ersion Changes Made
Altera Corporation Section I–5
Stratix Device Family Data Sheet
4●Table 4–48 on page 4–30: added ro ws tM512CLKSENSU and tM512CLKENH,
and updated symbol names.
●Updated power-up current (ICCINT) required to power a Stratix
device on page 4–17.
●Updated Table 4–37 on page 4–22 through Table 4–43 on
page 4–27.
●Table 4–49 on page 4–31: added rows tM4KCLKENSU, tM4KCLKENH,
tM4KBESU, and tM4KBEH, deleted rows tM4KRADDRASU and tM4KRADDRH, and
updated symbol names.
●Table 4–50 on page 4–31: added rows tMRAMCLKENSU, tMRAMCLKENH,
tMRAMBESU, and tMRAMBEH, deleted rows tMRAMADDRASU and
tMRAMRADDRH, and updated symbol names.
●Table 4–52 on page 4–34: updated table, deleted “Conditions”
column, and added rows tXZ and tZX.
●Table 4–52 on page 4–34: updated table, deleted “Conditions”
column, and added rows tXZ and tZX.
●Table 4–53 on page 4–34: updated table and added rows tXZPLL and
tZXPLL.
●Updated Note 2 in Table 4–53 on page 4–34.
●Table 4–54 on page 4–35: updated table, deleted “Conditions”
column, and added rows tXZPLL and tZXPLL.
●Updated Note 2 in Table 4–54 on page 4–35.
●Deleted Note 2 from T able 4–55 on page 4–36 through Table 4–66 on
page 4–41.
●Updated Table 4–55 on page 4–36 through Table 4–96 on
page 4–56. Added rows TXZ, TZX, TXZPLL, and TZXPLL.
●Added Note 4 to Table 4–101 on page 4–62.
●Deleted Note 1 from T able 4–67 on page 4–42 through Table 4–84 on
page 4–50.
●Added new section “I/O Timing Measurement Methodology” on
page 4–60.
●Deleted Note 1 from T able 4–67 on page 4–42 through Table 4–84 on
page 4–50.
●Deleted Note 2 from T able 4–85 on page 4–51 through Table 4–96 on
page 4–56.
●Added Note 4 to Table 4–101 on page 4–62.
●Table 4–102 on page 4–64: updated table and added Note 4.
●Updated description of “External I/O Delay Parameters” on
page 4–66.
●Added Note 1 to Table 4–109 on page 4–73 and Table 4–110 on
page 4–74.
●Updated Table 4–103 on page 4–66 through Table 4–110 on
page 4–74.
●Deleted Note 2 from Table 4–103 on page 4–66 through Table 4–106
on page 4–69.
●Added new paragraph about output adder delays on page 4–68.
●Updated Table 4–110 on page 4–74.
●Added Note 1 to Table 4–111 through Table 4–113 on page 4–75.
Chapter Date/V ersion Changes Made
Section I–6 Altera Corporation
Stratix Device Family Data Sheet Stratix Device Handbook, Volume 1
4●Updated Table 4–123 on page 4–85 through Table 4–126 on
page 4–92.
●Updated Note 3 in Table 4–123 on page 4–85.
●Table 4–125 on page 4–88: moved to correct order in chapter, and
updated table.
●Updated Table 4–126 on page 4–92.
●Updated Table 4–127 on page 4–94.
●Updated Table 4–128 on page 4–95.
April 2004, v3.0 ●Table 4–129 on page 4–96: updated table and added Note 10.
●Updated Table 4–131 and Table 4–132 on page 4–100.
●Updated Table 4–110 on page 4–74.
●Updated Table 4–123 on page 4–85.
●Updated Table 4–124 on page 4–87. through Table 4–126 on
page 4–92.
●Added Note 10 to Table 4–129 on page 4–96.
●Moved Table 4–127 on page 4–94 to correct order in the chapter.
●Updated Table 4–131 on page 4–100 through Table 4–132 on
page 4–100.
●Deleted tXZ and tZX from Figure 4–4.
●Waveform was added to Figure 4–6.
●The minimum and maximum duty cycle v alues in Note 3 of Table 4–8
were moved to a new Table 4–9.
●Changes were made to values in SSTL-3 Class I and II rows in
Table 4–17.
●Note 1 was added to Table 4–34.
●Added tSU_R and tSU_C rows in Table 4–38.
●Changed Table 4–55 title from “EP1S10 Column Pin Fast Regional
Clock External I/O Timing Parameters” to “EP1S10 External I/O
Timing on Column Pins Using Fast Regional Clock Networks.”
●Changed values in Tables 4–46, 4–48 to 4–51, 4–128, and 4–131.
●Added tARESET row in Tables 4–127 to 4–132.
●Deleted -5 Speed Grade column in Tables 4–117 to 4–119 and 4–122
to 4–123.
●Fixed differential waveform in Figure 4–1.
●Added “Definition of I/O Skew” section.
●Added tSU and tCO_C rows and made changes to values in tPRE and
tCLKHL rows in Table 4–46.
●Values changed in the tSU and tH rows in Table 4–47.
●Values changed in the tM4KCLKHL row in Table 4–49.
●Values changed in the tMRAMCLKHL row in Table 4–50.
●Added Table 4–51 to “Internal Timing Parameters” section.
●The timing information is preliminary in Tables 4–55 through 4–96.
●Table 4–111 was separated into 3 tables: Tables 4–111 to 4–113.
November 2003, v2.2 ●Updated Tables 4–127 through 4–129.
Chapter Date/V ersion Changes Made
Altera Corporation Section I–7
Stratix Device Family Data Sheet
4 October 2003, v2.1 ●Added -8 speed grade information.
●Updated performance information in Table 4–36.
●Updated timing information in Tables 4–55 through 4–96.
●Updated delay information in Tables 4–103 through 4–108.
●Updated programmable delay information in Tables 4–100 and
4–103.
July 2003, v2.0 ●Updated clock rates in Tables 4–114 through 4–123.
●Updated speed grade information in the introduction on page 4-1.
●Corrected figures 4-1 & 4-2 and T ab le 4-9 to reflect how VID and VOD
are specified.
●Added note 6 to Table 4-32.
●Updated Stratix Performance Table 4-35.
●Updated EP1S60 and EP1S80 timing parameters in Tables 4-82 to 4-
93. The Stratix timing models are final for all devices.
●Updated Stratix IOE programmab le delay chains in Tabl es 4-100 to 4-
101.
●Added single-ended I/O standard output pin delay adders f or loading
in Table 4-102.
●Added spec for FPLL[10..7]CLK pins in Tables 4-104 and 4-107.
●Updated high-speed I/O specification for J=2 in Tables 4-114 and 4-
115.
●Updated EPLL specification and fast PLL specification in Tables 4-
116 to 4-120.
5 September 2004, v2.1 ●Updated reference to device pin-outs on page 5–1 to indicate that
device pin-outs are no longer included in this manual and are now
available on the Altera web site.
April 2003, v1.0 ●No new changes in Stratix Device Handbook v2.0.
Chapter Date/V ersion Changes Made
Section I–8 Altera Corporation
Stratix Device Family Data Sheet Stratix Device Handbook, Volume 1
Altera Corporation 1–1
July 2005
1. Introduction
Introduction The Stratix® family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper
SRAM process, with densities of up to 79,040 logic e lements (LEs) and up
to 7.5 Mbits of RAM. Stratix devices of fer up to 22 digital signal
processing (DSP) blocks with up to 176 (9-bit ×9-bit) embedded
multiplie rs , optimized for DSP applic ations that enable efficient
implementation of high-performance filters and multipliers. Stratix
devices support various I/O standards and also offer a complete clock
management solution with its hierarchical clock structure with up to
420-MHz performance and up to 12 phase-locked loops (PLLs).
The following shows the main s ections in t he Stratix Device Fami ly Data
Sheet:
Section Page
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
TriMatrix Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Digital Signal Processing Block . . . . . . . . . . . . . . . . . . . . . . . . 2–52
PLLs & Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–73
I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–104
High-Speed Differential I/O Support. . . . . . . . . . . . . . . . . . 2–130
Power Sequencing & Hot Socketing . . . . . . . . . . . . . . . . . . . 2–140
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support. . . . . . . . . . 3–1
SignalTap II Embedded Logic Analyzer . . . . . . . . . . . . . . . . . 3–5
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Temperature Sensing Diode. . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
S51001-3.2
1–2 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Features
Features The Stratix family offers the following features:
■10,570 to 79,040 LEs; see Table 1–1
■Up to 7,427,520 RAM bits (928,440 byt es) available without reducing
logic resources
■TriMatrixTM memory consisting of three RAM block sizes to
implement true dual-port memory and first-in first-out (FIFO)
buffers
■High-speed DSP blocks provide dedicated implementation of
multipliers (faster than 300 MHz), multiply-accumulate functions,
and finite impulse response (FIR) filters
■Up to 16 global clocks with 22 clocking resources per device region
■Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device
provide spread spectrum, programmable bandwidth, clock switch-
over, real-time PLL reconfiguration, and advanced multiplication
and phase shifting
■Support for numerous single-ended and diffe rential I/O standar ds
■High-speed differential I/O suppo rt on up to 116 channels with up
to 80 channels optimized for 840 megabits per second (Mbps)
■Support for high-speed networking and communications bus
standards including RapidIO, UTOPIA IV, CSIX, HyperTransportTM
technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PH Y Level 4),
and SFI-4
■Differ ential on-chip termination support for LVDS
■Support for high-speed external memory, including zero bus
turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM ,
double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM),
and single data rate (SDR) SDRAM
■Support for 66-MHz PCI (64 and 32 bit) in -6 and faster speed-grade
devices, support for 33-MHz PCI (64 and 32 bit) in -8 and faster
speed-grade devices
■Support for 133-MHz PCI-X 1.0 in -5 speed-grade devices
■Support for 100-MHz PCI-X 1.0 in -6 and faster speed-grade devices
■Support for 66-MHz PCI-X 1.0 in -7 speed-grade devices
■Support for multiple intell ectual property megafunctions from
Altera MegaCore® functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions
■Support for remote configuration updates
Altera Corporation 1–3
July 2005 Stratix Device Handbook, Volume 1
Introduction
Table 1–1. Stratix Device Features — EP1S10, EP1S20, EP1S25, EP1S30
Feature EP1S10 EP1S20 EP1S25 EP1S30
LEs 10,570 18,460 25,660 32,470
M512 RAM blocks (32 ×18 bits) 94 194 224 295
M4K RAM blocks (128 ×36 bits) 60 82 138 171
M-RAM blocks (4K ×144 bits) 1 2 2 4
Total RAM bits 920,448 1,669,248 1,944,576 3,317,184
DSP blocks 6 101012
Embedded multipliers (1) 48 80 80 96
PLLs 6 6 6 10
Maximum user I/O pins 426 586 706 726
Table 1–2. Stratix Device Features — EP1S40, EP1S60, EP1S80
Feature EP1S40 EP1S60 EP1S80
LEs 41,250 57,120 79,040
M512 RAM blocks (32 ×18 bits) 384 574 767
M4K RAM blocks (128 ×36 bits) 183 292 364
M-RAM blocks (4K ×144 bits) 4 6 9
Total RAM bits 3,423,744 5,215,104 7,427,520
DSP blocks 14 18 22
Embedded multipliers (1) 112 144 176
PLLs 12 12 12
Maximum user I/O pins 822 1,022 1,238
Note to Tables 1–1 and 1–2:
(1) This parameter lists the total number of 9 ×9-bit multipliers for each device. For the total number of 18 ×18-bit
multipliers per device, divide the total number of 9 ×9-bit multipliers by 2. For the total number of 36 ×36-bit
multipliers per device, divide the total number of 9 ×9-bit multipliers by 8.
1–4 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Features
Stratix devices ar e available in space-saving FineLine BGA® and ball-grid
array (BGA) packages (see Tables 1–3 through 1–5). All Stratix devices
support vertical migration within the same package (for example, you
can migrate between the EP1S10, EP1S20, and EP1S25 devices in the 672-
pin BGA package). Vertical migration means that you can migrate to
devices whose dedicated pins, configuration pins, and power pins are the
same for a given packag e across dev ice densities. For I/O pin migrat ion
across densities, you must cross-reference the available I/O pins us ing
the device pin-outs for all planned densities of a given package type to
identify which I/O pins are migrational. The Quartus®II software can
automatically cross reference and place all pins except differential pins
for migration when given a device migration list. You must use the pin-
outs for each device to verify the differential placement migration. A
future versio n of the Quartus II soft ware will support differential pin
migration.
Table 1–3. Stratix Package Options & I/O Pin Counts
Device 672-Pin
BGA 956-Pin
BGA
484-Pin
FineLine
BGA
672-Pin
FineLine
BGA
780-Pin
FineLine
BGA
1,020-Pin
FineLine
BGA
1,508-Pin
FineLine
BGA
EP1S10 345 335 345 426
EP1S20 426 361 426 586
EP1S25 473 473 597 706
EP1S30 683 597 726
EP1S40 683 615 773 822
EP1S60 683 773 1,022
EP1S80 683 773 1,203
Note to Table 1–3:
(1) All I/O pin counts include 20 dedicated clock input pins (clk[15..0]p, clk0n, clk2n, clk9n, and clk11n)
that can be used for data inputs.
Table 1–4. Stratix BGA Package Sizes
Dimension 672 Pin 956 Pin
Pitch (mm) 1.27 1.27
Area (mm2)1,225 1,600
Length ×width (mm ×mm) 35 ×35 40 ×40
Altera Corporation 1–5
July 2005 Stratix Device Handbook, Volume 1
Introduction
Stratix devices ar e available in up to four speed grades, -5, -6, -7, and -8,
with -5 being the fastest. Table 1–6 shows Stratix device speed-grade
offerings.
Table 1–5. Stratix FineLine BGA Package Size s
Dimension 484 Pin 672 Pin 780 Pin 1,020 Pin 1,508 Pin
Pitch (mm) 1.00 1.00 1.00 1.00 1.00
Area (mm2)529 729 841 1,089 1,600
Length ×width
(mm ×mm) 23 ×23 27 ×27 29 ×29 33 ×33 40 ×40
Table 1–6. Stratix Device Speed Grades
Device 672-Pin
BGA 956-Pin
BGA
484-Pin
FineLine
BGA
672-Pin
FineLine
BGA
780-Pin
FineLine
BGA
1,020-Pin
FineLine
BGA
1,508-Pin
FineLine
BGA
EP1S10 -6, -7 -5, -6, -7 -6, -7 -5, -6, -7
EP1S20 -6, -7 -5, -6, -7 -6, -7 -5, -6, -7
EP1S25 -6, -7 -6, -7, -8 -5, -6, -7 -5, -6, -7
EP1S30 -5, -6, -7 -5, -6, -7, -8 -5, -6, -7
EP1S40 -5, -6, -7 -5, -6, -7, -8 -5, -6, -7 -5, -6, -7
EP1S60 -6, -7 -5, -6, -7 -6, -7
EP1S80 -6, -7 -5, -6, -7 -5, -6, -7
1–6 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Features
Altera Corporation 2–1
July 2005
2. Stratix Architecture
Functional
Description Stratix® dev ices contain a two-dimensional row- and column-based
architecture to implement custom logic. A series of column and row
interconnects of varying length and speed provide signal interconnects
between logic array blocks (LABs), memory block structures, and DSP
blocks.
The logic array consists of LABs, with 10 logic elements (LEs) in each
LAB. An LE is a small unit of logic providing efficient implementation of
user logic functions. LABs are grouped into rows and columns across the
device.
M512 RAM blocks are simple dual-port memory blocks with 512 bits plus
parity (576 bits). These blocks provide dedicated simple dual-port or
single-port memory up to 18-bits wide at up to 318 MHz. M512 blocks are
grouped into columns across the device in between certain LABs.
M4K RAM blocks are true dual-port memory blocks with 4K bits plus
parity (4,608 bits). These blocks pr ovide dedicated tr ue dual-port, simple
dual-port, or single-port memory up to 36-bits wide at up to 291 MHz.
These blocks are grouped into columns across the device in between
certain LABs.
M-RAM blocks ar e true dual-port memory blocks with 512K bits plus
parity (589,824 bits). These blocks provide dedicated true dual-port,
simple dual-port, or single-port memory up to 144-bits wide at up to
269 MHz. Several M-RAM blocks are located individually or in pairs
within the device’s logic array.
Digital signal processing (DSP) blocks can implement up to either eight
full-precision 9 × 9-bit multipliers, four full-precision 18 × 18-bit
multipliers, or one full-precision 36 × 36-bit multiplier with add or
subtract featur es. These blocks also contain 18-bit input shift registers for
digital signal processing applications, including FIR and infinite impulse
respo nse (IIR) filters. DSP blocks are gr ouped into two columns in each
device.
Each Stratix device I/O pin is fed by an I/ O element ( IOE) located at the
end of LAB rows and columns around the periphery of the device. I/O
pins support numerous single-ended and differential I/O standards.
Each IOE contains a bidirectional I/O buffer and six registers for
registering input, output, and output-enab le si gnals. When used with
S51002-3.2
2–2 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Functional Description
dedicated clocks, these registers provide exceptional perform ance and
interface support with external memory devices suc h as DDR SDRAM,
FCRAM, ZBT, and QDR SRAM devices.
High-speed serial interface channels support transfers at up to 840 Mbps
using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O
standards.
Figure 2–1 shows an overview of the Stratix device.
Figure 2–1. Stratix Block Diagram
M512 RAM Blocks for
Dual-Port Memory, Shift
Registers, & FIFO Buffers
DSP Blocks for
Multiplication and Full
Implementation of FIR Filters
M4K RAM Blocks
for True Dual-Port
Memory & Other Embedded
Memory Functions
IOEs Support DDR, PCI, GTL+, SSTL-3,
SSTL-2, HSTL, LVDS, LVPECL, PCML,
HyperTransport & other I/O Standards
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs LABs
LABs
IOEs IOEs
LABs
LABs LABs
LABs LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
DSP
Block
M-RAM Block
Altera Corporation 2–3
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
The number of M512 RAM, M4K RAM, and DSP blocks varies by device
along with row and column numbers and M-RAM blocks. Table 2–1 lists
the resources available in Stratix devices.
Logic Array
Blocks Each LAB consists of 10 LEs, LE carry chai ns, LAB contr ol signals , local
interc onnect, LUT chain, and register chain connection lines. The local
interc onnect transfers signals between LEs in the same LAB. LUT chain
connections transfer the output of one LE’s LUT to the adjacent LE for fast
sequential LUT connections within the same LAB. Register chain
connections transfer the output of one LE’s register to th e a d j acent LE’s
register within an LAB. The Quartus®II Compile r places associated logic
within an LAB or adjacent LABs, allowing the use of local, LUT chai n,
and register chain connections for performance and area efficiency.
Figure 2–2 shows the Stratix LAB.
Table 2–1. Stratix Device Resources
Device M512 RAM
Columns/Blocks M4K RAM
Columns/Blocks M-RAM
Blocks DSP Block
Columns/Blocks LAB
Columns LAB Rows
EP1S10 4 / 94 2 / 60 1 2 / 6 40 30
EP1S20 6 / 194 2 / 82 2 2 / 10 52 41
EP1S25 6 / 224 3 / 138 2 2 / 10 62 46
EP1S30 7 / 295 3 / 171 4 2 / 12 67 57
EP1S40 8 / 384 3 / 183 4 2 / 14 77 61
EP1S60 10 / 574 4 / 292 6 2 / 18 90 73
EP1S80 11 / 767 4 / 364 9 2 / 22 101 91
2–4 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Logic Array Blocks
Figure 2–2. Stratix LAB Structure
LAB Interconnects
The LAB local interco nnect can drive L Es within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, M512 RAM blocks,
M4K RAM blocks, or DSP blocks fr om the left and right can also drive an
LAB’s local inte rconnect through the direct link connection. The direct
link connection feature minimizes the use of row and column
interconnects, providing higher performance and flexibility. Each LE can
drive 30 other LEs through fast local and direct link interconnects.
Figure 2–3 shows the direct link connection.
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Row Interconnects of
Variable Speed & Length
Column Interconnects of
Variable Speed & Length
Three-Sided Architecture—Local
Interconnect is Driven from Either Side by
Columns & LABs, & from Above by Rows
Local Interconnect LAB
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Altera Corporation 2–5
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–3. Direct Link Connection
LAB Control Signals
Each LAB contains dedicated logic for driving control si gnal s to its LEs.
The control signals include two clocks, two clock enables, two
asynchronous clears, synchronous clear, asynchronous preset/load,
synchronous load, and add/subtract control signals. This gives a
maximum of 10 contr ol signals at a time. Although synchronous load and
clear signals are generally used when implementing counters, they can
also be used with other functions.
Each LAB can use two clocks and two clock enable signals. Eac h LAB’s
clock and clock enable signals are linked. For example, any LE in a
particular LAB using the labclk1 signal will also use labclkena1. If
the LAB uses both the rising and falling edges of a clock, it also uses both
LAB-wide clock signals. De-asserting the clock enable signal will turn off
the LAB-wide clock.
Each LAB can use two asy n chrono us clear signals and an asy nc hronous
load/preset signal. The asynchronous load acts as a preset when the
asynchr onou s lo ad data input is tied high.
LAB
Direct link
interconnect
to right
Direct link interconnect from
right LAB, TriMatrix memory
block, DSP block, or IOE output
Direct link interconnect from
left LAB, TriMatrix memory
block, DSP block, or IOE output
Local
Interconnect
Direct link
interconnect
to left
2–6 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Logic Elements
W ith the LA B-wide addnsub control signal, a single LE can implement a
one-bit adder and subtractor. This saves LE resources and improves
performance for logic functions such as DSP correlators and signed
multipliers that alternate between addition and subtrac tion depending
on data.
The LAB ro w clocks [7..0] and LAB local interconnect generate the LAB-
wide control si gnals. The MultiTrackTM interconnect’s inhere nt low skew
allows clock and control signal distribution in addition to data. Figure 2–4
shows the LAB control signal generation circuit.
Figure 2–4. LAB-Wide Control Signals
Logic Elements The smallest unit of logic in the Stratix architecture, the LE, is compact
and provides advanced features with efficient logic utilization. Each LE
contains a four-input LUT, which is a function generator that can
implement any function of four variables. In ad dition, each LE contains a
programmable register and carry chain with carry select capability. A
single LE also supports dynamic single bit addition or subtraction mode
selectable by an LAB-wide control signal. Each LE drives all types of
interc onnects: local, row, column, LUT chain, register chain, and direct
link interconnects. See Figure 2–5.
labclkena1
labclk2labclk1
labclkena2
asyncload
or labpre
syncload
Dedicated
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect labclr1
labclr2
synclr
addnsub
8
Altera Corporation 2–7
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–5. Stratix LE
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. Each register has data, true asynchronous load d a ta, cl ock,
clock enable, clear, and asynchronous load/prese t inputs. Global signals,
general-purpose I/O pins, or any internal logic can drive the regis ter’s
clock and clear control signals. Ei ther general-purpose I/O pins or
internal logic can drive the clock enable, preset, asynchronous load, and
asynchronous data. The asynchronous load data input comes from the
data3 input of the LE. For combinatorial functions, the register is
bypassed and the output of the LUT drives directly to the outputs of the
LE.
Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs dri ve column or row and direct link
routing connections and one drives local interconnect resources. This
allows the LUT to drive one output while the register drives another
output. This feature, called register packing, i mproves de vic e u tilization
because the device can use the register and the LUT for unrelated
labclk1
labclk2
labclr2
labpre/aload
Carry-In1
Carry-In0
LAB Carry-In
Clock &
Clock Enable
Select
LAB Carry-Out
Carry-Out1
Carry-Out0
Look-Up
Table
(LUT)
Carry
Chain
Row, column,
and direct link
routing
Row, column,
and direct link
routing
Programmable
Register
PRN/ALD
CLRN
DQ
ENA
Register Bypass
Packed
Register Select
Chip-Wide
Reset
labclkena1
labclkena2
Synchronous
Load and
Clear Logic
LAB-wide
Synchronous
Load LAB-wide
Synchronous
Clear
Asynchronous
Clear/Preset/
Load Logic
data1
data2
data3
data4
LUT chain
routing to next LE
labclr1
Local Routing
Register chain
output
ADATA
addnsub
Register
Feedback
Register chain
routing from
previous LE
2–8 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Logic Elements
functions. Another special packing mode allows the register output to
feed back into the LUT of the same LE so that the register is packed with
its own fan-out LUT. Th is provides another mechanism for improved
fitting. The LE can also drive out registered and unr egister ed versions of
the LUT output.
LUT Chain & Register Chain
In addition to the three general routi n g ou tpu ts, t he LEs within an LAB
have LUT chain and register chain outputs. LUT chain connections allow
LUTs within the same LAB to cascade together for wide input functions.
Register chain outputs allow registers within the same LAB to cascade
together . The register chain output allows an LAB to use LUT s for a single
combinatorial function and the registers to be used for an unr elated shift
register implementati on. These r e sources speed up connections between
LABs while saving local interconnect resources. See “MultiTrack
Interconnect” on page 2–14 for more information on LUT chain and
register chain connections.
addnsub Signal
The LE’s dynamic adder/subtractor feature saves logic resources by
using one set of LEs to implement both an adder and a subtractor. This
featur e is controlled by the LAB-wide control signal addnsub. The
addnsub signal sets the LAB to perform either A + B or A – B. The LUT
computes addition, and subtraction is computed by adding the two’s
complement of the intended subtractor. The LAB-wide signal converts to
two’s complement by inverting the B bits within the LAB and setting
carry-in = 1 to add one to the least significant bit (LSB). The LSB of an
adder/subtractor must be placed in the first LE of the LA B, where the
LAB-wide addnsub signal automatically sets the carry-in to 1. The
Quartus II Compiler automatically places and uses the adder/subtractor
featur e when using adder/subtractor parameterized functions.
LE Operating Modes
The Stratix LE can operate in one of the following modes:
■Normal mode
■Dynamic arithmetic mode
Each mode uses LE resources differently. In each mode, eight available
inputs to the LE—the four data inputs from the LAB local interconnect;
carry-in0 and carry-in1 from the previous LE; the LAB carry-in
from the previous carry-chain LAB; and the register chain connection—
are directed to different destinations to implement the desired logic
function. LAB-wide signals provide clock, asynchronous clear,
Altera Corporation 2–9
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
asynchronous preset load, synchronous clear, synchronous load, and
clock enable control for the r egister . These LAB-wide signals are available
in all LE modes. The addnsub control signal is allowed in arithmetic
mode.
The Quartus II software, in conjunction with parameterized functions
such as library of parameterized modules (LPM) functions, automatically
chooses the appropriate mode for common functions such as counters,
adders, subtractors, and arithmetic functions. If required, you can also
create special-purpose functions that specify which LE operating mode to
use for optimal performance.
Normal Mode
The normal mode is suitable for general logic applications and
combinatorial functions. In normal mode, four data inputs from the LAB
local interconnect are inputs to a four-input LUT (see Figure 2–6). The
Quartus II Compiler automatically selects the carry-in or the data3
signal as one of the inputs to the LUT. Each LE can use LUT chain
connections to drive its combinatorial output directly to the next LE in the
LAB. Asynchronous load data for the register comes from the data3
input of the LE. LEs in normal mode support packed registers.
Figure 2–6. LE in Normal Mode
Note to Figure 2–6:
(1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.
data1
4-Input
LUT
data2
data3
cin (from cout
of previous LE)
data4
addnsub (LAB Wide)
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
aload
(LAB Wide)
ALD/PRE
CLRN
DQ
ENA
ADATA
sclear
(LAB Wide)
sload
(LAB Wide)
Register chain
connection
LUT chain
connection
Register
chain output
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
Register Feedback
(1)
2–10 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Logic Elements
Dynamic Arithmetic Mode
The dynamic arithmetic mode is ideal for implementing adders, counters,
accumulators, wide parity functions, and comparators. An LE in dynamic
arithmetic mode uses four 2-input LUTs configurable as a dynamic
adder/subtractor. The first two 2-input LUTs compute two summations
based on a possible carry-in of 1 or 0; the other two LUTs generate carry
outputs for the two chains of the carry select circuitry. As shown in
Figure 2–7, the LAB carry-in signal se le cts either the carry-in0 or
carry-in1 chain. The selecte d chain’ s logic level in turn determines
which parallel sum is generated as a combinatorial or register ed output.
For example, when implementing an adder, the sum output is the
selection of two possible calculated sums: data1 +data2 +carry-in0
or data1 + data2 + carry-in1. The other two LUTs use the data1 and
data2 signals to generate two possible carry-out signals—one for a carry
of 1 and the other for a carry of 0. The carry-in0 signal acts as the carry
select for the carry-out0 output and carry-in1 acts as the carry select
for the carry-out1 output. LEs in arithmetic mode can drive out
registered and unregistered versions of the LUT output.
The dynamic arithmetic mode also offers clock enable, counter enable,
synchronous up/dow n control, synchr onou s cl ear, synchronous load,
and dynamic adder/subtractor options. The LAB local interconnect data
inputs generate the counter enable and synchronous up/down control
signals. The synchronous clear and synchronous load options are LAB-
wide signals that affect all registers in the LAB. The Quartus II software
automatically places any registers that are not used by the counter into
other LABs . The addnsub LAB-wide signal contr ols whet her the LE ac ts
as an adder or subtractor.
Altera Corporation 2–11
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–7. LE in Dynamic Arithmetic Mode
Note to Figure 2–7:
(1) The addnsub signal is tied to the carry input for the first LE of a carry chain only.
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between
LEs in arithmetic mode. The carry-select chain uses the redundant carry
calculation to incr eas e the speed of ca rry functions. The LE is configur e d
to calculate outputs for a possible carry-in of 1 and carry-in of 0 in
parallel. The carry-in0 and carry-in1 signals from a lower -order bit
feed forward into the higher-order bit via the parallel carry chain and feed
into both the LUT and the next portion of the carry chain. Carry-select
chains can begin in any LE within an LAB.
The speed advantage of the carry-select chain is in the parallel pre-
computation of carry chains. Since the LAB carry-in selects the
precomputed carry chain, not every LE is in the critical path. Only the
propagation delay b etween LAB carry-in generation (LE 5 and LE 10) are
now part of the critical path. This f eature allows the Stratix architecture to
implement high-speed counters, adders, multipliers, parity functions,
and comparators of arbitrary width.
data1
LUT
data2
data3
addnsub
(LAB Wide)
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
ALD/PRE
CLRN
DQ
ENA
ADATA
Register chain
connection
LUT
LUT
LUT
Carry-Out1Carry-Out0
LAB Carry-In
Carry-In0
Carry-In1
(1)
sclear
(LAB Wide)
sload
(LAB Wide)
LUT chain
connection
Register
chain output
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
aload
(LAB Wide)
Register Feedback
2–12 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Logic Elements
Figure 2–8 shows the carry-select circuitry in an LAB for a 10-bit full
adder. One portion of the LUT generates the sum of two bits using the
input signals and the appropriate carry-in bit; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for accumulator functions. Another portion of the LUT generates carry-
out bits. An LAB-wide carry in bit sel ec ts which chain is used for the
addition of given inputs. The carry-in signal for each chain, carry-in0
or carry-in1, selects the carry-out to carry forward to the carry-in
signal of the next-higher-order bit. The final carry-out signal is routed to
an LE, where it is fed to local, row, or column interconnects.
The Quartus II Compiler automatically creates carry chain logic during
design pr ocessing, or you can create it manu ally during design entry.
Parameterized functions suc h as LPM functions automatically take
advantage of carry chains for the appropriate functions.
The Quartus II Compiler creates carry chains longer than 10 LEs by
linking LABs together auto matically. For enhanced fitting, a long carry
chain runs vertically allowing fast horizontal connections to TriMatrix™
memory and DSP blocks. A carry chain can continue as far as a full
column.
Altera Corporation 2–13
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–8. Carry Select Chain
Clear & Preset Logic Control
LAB-wide signals control the logic for the register’s clear and preset
signals. The LE directly supports an asynchronous clear and preset
function. The register preset is achieved through the asynchronous load
of a logic high. The direct asynchronous preset does not requir e a NOT-
gate push-back technique. Stratix devices support simu ltane ous preset/
LE4
LE3
LE2
LE1
A1
B1
A2
B2
A3
B3
A4
B4
Sum1
Sum2
Sum3
Sum4
LE10
LE9
LE8
LE7
A7
B7
A8
B8
A9
B9
A10
B10
Sum7
LE6
A6
B6 Sum6
LE5
A5
B5 Sum5
Sum8
Sum9
Sum10
01
01
LAB Carry-In
LAB Carry-Out
LUT
LUT
LUT
LUT
data1
LAB Carry-In
data2
Carry-In0
Carry-In1
Carry-Out0 Carry-Out1
Sum
2–14 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
MultiTrack Interconnect
asynchr onous load, and clear signals. A n asynchronous clear signal takes
precedence if both signals are asserted simultaneously. Each LAB
supports up to two clears and one preset signal.
In addition to the clear and preset ports, Stratix devices provide a chip-
wide reset pin (DEV_CLRn) that resets all registers in the device. An
option set before compilat ion in the Quartus II software controls this pin.
This chip-wide reset overrides all other control signals.
MultiTrack
Interconnect In the Stratix architecture, connections between LEs, TriMatrix memory,
DSP blocks, and device I/O pins are provided by the MultiTrack
interconnect structure with DirectDriveTM technology. The MultiTrack
interconnect consists of continuous, performance-optimized routing lines
of different lengths and speeds used for inter- and intra-design block
connectivity . The Quartus II Compiler automatically places critical design
paths on faster interconnects to improve design perf ormance.
DirectDrive technology is a deterministic routing technology that ensures
identical routing resource usage for any function regar dless of placement
within the device . Th e MultiTrack interconnect and DirectDrive
technology simplify the integration stage of block-based designing by
eliminating the re-optimization cycl es that typically follow design
changes and additions.
The MultiTrack interconnect consists of row and column interconnects
that span fixed d istances. A r outing str ucture with fixed length resour ces
for all devices allows predictable and repeatable performance when
migrating through different device densities. De di cate d row
interc onnects route signals t o and fr om LABs, DSP block s, and TriMatrix
memory within the same row. These row resources include:
■Direct link interconnects between LABs and adjacent blocks.
■R4 interconnects traversing four blocks to the right or left.
■R8 interconnects traversing eight blocks to the right or left.
■R24 row inter connects for high-speed access across the length of the
device.
The dire ct link interconnect allows an LAB, DSP block, or TriMatrix
memory block to drive into the local interconnect of its left and right
neighbors and then back into itself. Only one side of a M-RAM block
interfaces with direct link and row interconnects. This provides fast
communication between adjacent LABs and/or blocks without using row
interconnect resources.
The R4 interconnects span four LABs, thr ee LA Bs and one M512 RAM
block, two LABs and one M4K RAM block, or two LABs and one DSP
block to the right or left of a sour ce LAB. These r esources ar e used for fast
Altera Corporation 2–15
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
row connections in a four-LAB region. Every LAB has its own set of R4
interconnects to drive either left or right. Figure 2–9 shows R4
interconnect connections fr om an LAB. R4 interconnect s can drive and be
driven by DSP blocks and RAM blocks and horizontal IOE s. For LAB
interfacing, a primary LAB or LAB neighbor can driv e a giv en R4
interconnect. For R4 interconnects that drive to the right, the primary
LAB and right neighbor can drive on to the interconnect. For R4
interconnects that drive to the left, the primary LAB and its left neighbor
can drive on to the interconnect. R4 interconnects can drive other R4
interconnects to extend the range of LABs they can drive. R4
interc onnects can also drive C4 and C16 interconnects for connections
from one row to another. Additionally, R4 interconnects can drive R24
interconnects.
Figure 2–9. R4 Interconnect Connections
Notes to Figure 2–9:
(1) C4 interconnects can drive R4 interconnects.
(2) This pattern is repeated for every LAB in the LAB row.
The R8 interconnects span eight LABs, M512 or M4K RAM blocks, or DSP
blocks to the right or left from a sour ce LAB. These resources ar e used for
fast row connections in an eight-LAB region. Every LAB has its own set
of R8 interconnects to drive either left or right. R8 interconnect
connections between LABs in a row are similar to the R4 connections
shown in Figure 2–9, with the exception that they connect to eight LABs
to the right or left, not four. Like R4 interconnects, R8 interconnects can
drive and be driven by all types of architecture blocks. R8 interconnects
Primary
LAB (2)
R4 Interconnect
Driving Left
Adjacent LAB can
Drive onto Another
LAB's R4 Interconnect
C4, C8, and C16
Column Interconnects (1)
R4 Interconnect
Driving Right
LAB
Neighbor
LAB
Neighbor
2–16 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
MultiTrack Interconnect
can drive other R8 interconnects to extend their range as well as C8
interconnects for row-to-row connections. One R8 interconnect is faster
than two R4 interconnects connected toget he r.
R24 ro w int er c onnects span 2 4 LAB s and pr ov ide the fas test resource for
long row connections between LABs, T riMatrix memory, DSP blocks, and
IOEs. The R24 row interconnects can cross M-RAM blocks. R24 r ow
interconnect s drive to other r o w or column inter connects at every fourth
LAB and do not drive dir ectly to LAB local interconnects . R24 row
interconnects drive LAB local interconnects via R4 and C4 interconnects.
R24 interconnects can drive R24, R4, C16, and C4 interconnects.
The column interconnect operates similarly to the row interconnect and
vertically routes signal s to and from LABs , TriMatrix memory, DSP
blocks, and IOEs. Each column of LABs is served by a dedicated column
interconnect, which vertically routes signals to and from LABs, TriMatrix
memory and DSP blocks, and horizontal IOEs. These column resources
include:
■LUT chain interconnects within an LAB
■Register chain intercon nects within an LAB
■C4 interconnects trave rsing a distance of four blocks in up and down
direction
■C8 interconnects traversing a distance of eight blocks in up and
down direction
■C16 column interconnects for high-speed vertical routi ng through
the device
Stratix device s include an enhanced inter connect structure within LABs
for routing LE output to LE input connec tions faster using LUT ch ain
connections and register chain connections. The LUT chain connection
allows the combinatorial output of an LE to directly drive the fast input
of the LE right below it, bypassing the local inter connect. These r esources
can be used as a high-speed connection for wide fan-in functions from
LE 1 to LE 10 in the same LAB. The register chain connection allows the
register output of one LE to connect dir ectly to the register input of the
next LE in the LAB for fast shift r egisters. The Quartus II Compiler
automatically takes advantage of these resources to improve utilization
and performance. Figure 2–10 shows the LUT chain and registe r chain
interconnects.
Altera Corporation 2–17
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–10. LUT Chain & Register Chain Interconnects
The C4 interconnects span four LABs, M512, or M4K blocks up or down
from a source LAB. Every LAB has its own set of C4 interconnects to drive
either up or down. Figure 2–11 shows the C4 interconnect connections
from an LAB in a column. The C4 interconnects can drive and be driven
by all types of architecture blocks , in cluding DSP blocks, TriMatrix
memory blocks, and vertical IOEs. For LAB interconnection, a primary
LAB or its LAB neighbor can drive a given C4 interconnect.
C4 interconnects can drive each other to extend their range as well as
drive row interconnects for column-to-column connections.
LE 1
LE 2
LE 3
LE 4
LE 5
LE 6
LE 7
LE 8
LE 9
LE 10
LUT Chain
Routing to
Adjacent LE
Local
Interconnect
Register Chain
Routing to Adjacen
t
LE's Register Input
Local Interconnect
Routing Among LEs
in the LAB
2–18 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
MultiTrack Interconnect
Figure 2–11. C4 Interconnect Connections Note (1)
Note to Figure 2–11:
(1) Each C4 interconnect can drive either up or down four rows.
C4 Interconnect
Drives Local and R
4
Interconnects
up to Four Rows
Adjacent LAB can
drive onto neighboring
LAB's C4 interconnect
C4 Interconnect
Driving Up
C4 Interconnect
Driving Down
LAB
Row
Interconnect
Local
Interconnect
Altera Corporation 2–19
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
C8 interconnects span eight LABs, M512, or M4K blocks up or down fr om
a source LAB. Every LAB has its own set of C8 interconnects to drive
either up or down. C8 interconnect connections between the LABs in a
column are similar to the C4 connections shown in Figure 2–11 with the
exception that they connect to eight LABs ab ove and bel ow. The C8
interconnects can drive and be driven by all types of architecture blocks
similar to C4 interconnects. C8 interconnects can drive each other to
extend their range as well as R8 interconnects for column-to-column
connections. C8 interconnects are faster than two C4 interconnects.
C16 column interconnects span a length of 16 LABs and provide the
fastest resource for long column connections betwee n LABs, TriMatrix
memory blocks, DSP block s, and IOEs. C16 interconnects can cross M-
RAM blocks and also drive to row and column interconnects at every
fourth LAB. C16 inter connec ts drive LAB local interconnects via C4 and
R4 interconnects and do not drive LAB local in te rconnects di rectly.
All embedded blocks com m uni cate with the logic array similar to LAB-
to-LAB interfaces. Each block (i.e., TriMatrix memory and DSP blocks)
connects to r ow and column inter connec ts and has local interc onnect
regions driven by row and column interconnects. These blocks also have
direct link interconnects for fast connections to and from a neighboring
LAB. All blocks are fed by the row LAB clocks, labclk[7..0].
2–20 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
MultiTrack Interconnect
Table 2–2 shows the Stratix device’s routing scheme.
Table 2–2. Stratix Device Routing Scheme
Source
Destination
LUT Chain
Register Chain
Local Interconnect
Direct Link Interconnect
R4 Interconnect
R8 Interconnect
R24 Interconnect
C4 Interconnect
C8 Interconnect
C16 Interconnect
LE
M512 RAM Block
M4K RAM Block
M-RAM Block
DSP Blocks
Column IOE
Row IOE
LUT Chain v
Register Chain v
Local
Interconnect vvvvvvv
Direct Link
Interconnect v
R4 Interconnect vvvvv
R8 Interconnect vvv
R24
Interconnect vvvv
C4 Interconnect vv v
C8 Interconnect vvv
C16
Interconnect vvvv
LE vvvvvv vv
M512 RAM
Block vvvv vv
M4K RAM Block vvvv vv
M-RAM Block vv
DSP Blocks vvvv vv
Column IOE vvvv
Row IOE v vvvvv
Altera Corporation 2–21
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
TriMatrix
Memory TriMatrix memory consists of three types of RAM blocks: M512, M4K,
and M-RAM blocks. Although these memory blocks are different, they
can all implement various types of memory with or without parity,
including true dual-port, simple dual-port, and single-port RAM, ROM,
and FIFO buffers. Table 2–3 shows the size and features of the different
RAM blocks.
Table 2–3. TriMatrix Memory Features (Part 1 of 2)
Memory Feature M512 RAM Block
(32 × 18 Bits) M4K RAM Block
(128×36Bits) M-RAM Block
(4K × 144 Bits)
Maximum
performance (1) (1) (1)
True dual-port
memory vv
Simple dual-port
memory vvv
Single-port memory vvv
Shift register vv
ROM vv
(2)
FIFO buffer vvv
Byte enable vv
Parity bits vvv
Mixed clock mode vvv
Memory initialization vv
Simple dual-port
memory mixed width
support vvv
True dual-port
memory mixed width
support vv
Power-up conditions Outputs cleared Outputs cleared Outputs
unknown
Register clears Input and output
registers Input and output
registers Output registers
Mixed-port read-
during-write Unknown
output/old data Unknown
output/old data Unknown output
2–22 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
TriMatrix Memory
1Violating the setup or hold time on the address registe rs could
corrupt the memory contents. This applies to both r ead and
write operations.
Memory Modes
TriMatrix memory blocks include input registers that synchr onize writes
and output registers to pipeline designs and improve system
performance. M4K and M-RAM memory blocks offer a true dual-port
mode to support any combination of two-port operations: two reads, two
writes, or one read and one write at two different clock frequencies.
Figure 2–12 shows true dual-port memory.
Figure 2–12. True Dual-Port Memory Configuration
Configurations 512 ×1
256 ×2
128 ×4
64 ×8
64 ×9
32 ×16
32 ×18
4K ×1
2K ×2
1K ×4
512 ×8
512 ×9
256 ×16
256 ×18
128 ×32
128 ×36
64K ×8
64K ×9
32K ×16
32K ×18
16K ×32
16K ×36
8K ×64
8K ×72
4K ×128
4K ×144
Notes to Table 2–3:
(1) See Table 4–36 for maximum performance information.
(2) The M-RAM block does not support memory initializations. However, the
M-RAM block can emulate a ROM function using a dual-port RAM bock. The
Stratix device must write to the dual-po rt memory onc e and then disab le the
write-enable ports afterwards.
Table 2–3. TriMatrix Memory Features (Part 2 of 2)
Memory Feature M512 RAM Block
(32 × 18 Bits) M4K RAM Block
(128×36Bits) M-RAM Block
(4K × 144 Bits)
dataA[ ]
addressA[ ]
wrenA
clockA
clockenA
qA[ ]
aclrA
dataB[ ]
addressB[ ]
wrenB
clockB
clockenB
qB[ ]
aclrB
AB
Altera Corporation 2–23
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
In addition to true dual-port memory, the memory bl ocks support simple
dual-port and single-port RAM. Simple dual-port memory supports a
simultaneous read and write and can either read old data before the write
occurs or just read the don’t car e bits. Single-port memory supports non-
simultaneous reads and writes, but the q[] port will output the data once
it has been written to the memory (if the outputs are not registered) or
after the next rising edge of the clock (if the outputs are registered). For
more information, see Chapter 2, T riMatrix Embedded Memory Blocks in
Stratix & Stratix GX Devices of the Stratix Device Handbook, Volume 2.
Figure 2–13 shows these different RAM memory port configurations for
TriM atrix memory.
Figure 2–13. Simple Dual-Port & Single-Po rt Memory Configurations
Note to Figure 2–13:
(1) Two single-port memory blocks can be implemented in a single M4K block as long
as each of the two independent block sizes is equal to or less than half of the M4K
block size.
The memory blocks also enable mixed-width data ports for reading and
writing to the RAM port s in dual-port RAM configuratio n. For example,
the memory block can be written in ×1 mode at port A and read out in ×16
mode from port B.
data[ ]
wraddress[ ]
wren
inclock
inclocken
inaclr
rdaddress[ ]
rden
q[ ]
outclock
outclocken
outaclr
data[ ]
address[ ]
wren
inclock
inclocken
inaclr
q[ ]
outclock
outclocken
outaclr
Single-Port Memory (1)
Simple Dual-Port Memory
2–24 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
TriMatrix Memory
TriMatrix memory architecture can implement pipelined RAM by
registering both the input and output signals to the RAM block. All
TriM atrix memory block inputs are registered providing synchronous
write cycles. In synchronous operation, the memory block generates its
own self-timed strobe write enable (WREN) signal derived fro m the global
or regional clock. In contrast, a circuit using asynchronous RAM must
generate the RAM WREN signal while ensuring its data and address
signals meet setup and hold time specifications relative to the WREN
signal. The output registers can be bypassed. Flow-through reading is
possible in the simple dual-port mode of M512 and M4K RAM blocks by
clocking the read enable and r ead addr ess re gisters on the ne gative clock
edge and bypassing the output registers.
Two single-port memory blocks can be implemented in a single M4K
block as long as each of the two independent block sizes is equal to or less
than half of the M4K block size.
The Quartus II software automatically implements larger memory by
combining multiple TriMatrix memory blocks. For example, two
256 × 16-bit RAM blocks can be combined to form a 256 × 32-bit RAM
block. Memory performance does not degrade for memory blocks using
the maximum number of words available in one memory block. Logi cal
memory blocks using less than the maximum number of words use
physical blocks in parallel , eliminating any external control logic that
would increase delays. To create a larger high-speed memory block, the
Quartus II software automatically combines memory blocks with LE
control logic.
Clear Signals
When applied to input registers, the asynchronous clear signal for the
TriMatrix embedded memory immediately clears the input registers.
However , the output of the memory block does not show the effects until
the next clock edge. When applied to output r egist ers, the asynchronous
clear signal clears the output registers and the effects are seen
immediately.
Parity Bit Support
The memory blocks support a parity bit for each byte. The parity bit,
along with internal LE logic, can implement parity checking for error
detection to ensur e data integrity. You can also use parity-size data wor ds
to store user-specified control bits. In the M4K and M-RAM blocks, byte
enables are also available for data input masking during write operations.
Altera Corporation 2–25
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Shift Register Support
You can configure embedded memory blocks to implement shift registers
for DSP applications such as pseudo-random number generators, multi-
channel filtering, auto-correlation, and cr oss-correlation functions. These
and other DSP applications require local data storage, traditionally
implemented with standard flip-flops, which can quickly consume many
logic cells and routing resour ces for la r ge shift r egisters. A more ef ficient
alternative is to use embedded memory as a shift re giste r block, which
saves logic cell and routing resources and provides a more efficient
implementation with the dedicated circu i try.
The size of a w×m×n shift register is determined by the input data
width (w), the length of the taps (m), and the number of taps (n). The size
of a w×m×n shift register must be less than or equal to the maximum
number of memory bits in the respective block: 576 bits for the M512
RAM block and 4,608 bits for the M4K RAM block. The total number of
shift register outputs (number of taps n × width w) must be less than the
maximum data width of t he RAM blo ck (18 for M512 blocks, 36 for M4K
blocks). To create larger shift registers, the memory blocks are cascaded
together.
Data is written into each address location at the falling edge of the clock
and read from the address at the rising edge of the clock. The shift r egister
mode logic automatically controls the positive and negative edge
clocking to shift the data in one clock cycle. Figure 2–14 shows the
TriMatrix memory block in the shift register mode.
2–26 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
TriMatrix Memory
Figure 2–14. Shift Register Memory Configuration
Memory Block Size
TriMatrix memory provides three different memory sizes for efficient
application support. The large number of M512 blocks are ideal for
designs with many shallow first-in first-out (FIFO) buffers. M4K blocks
provide additional resources for channelized function s that do not
require larg e amounts of storage. The M-RAM blocks provide a large
single block of RAM ideal for data packet storage. The different-sized
blocks allow Stratix devices to efficiently support variable-sized memory
in designs.
The Quartus II software automatically partitions the user-defined
memory into the embedded memory blocks using the most efficient size
combinations. You can also manually assign the memory to a specific
block size or a mixture of block sizes.
m-Bit Shift Register
w w
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
ww
ww
ww
w × m × n Shift Register
n Numbe
r
of Taps
Altera Corporation 2–27
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
M512 RAM Block
The M512 RAM block is a simple du al-port memory block and is useful
for implementing sm all FIFO buffers, DSP, and clock domain transfer
applications. Each block conta ins 576 RAM bits (including parity bits ).
M512 RAM blocks can be configured in the following modes:
■Simple dual-port RAM
■Single-port RAM
■FIFO
■ROM
■Shift register
When configured as RAM or ROM, you can use an initialization file to
pre-lo ad the me mory contents.
The memory address depths and output widths can be configured as
512 × 1, 256 × 2, 128 × 4, 64 × 8 (64 × 9 bits with parity), and 32 × 16
(32 × 18 bits with parity). Mixed-width configurations are also possible,
allowing different read and write widths. Table 2–4 summarizes the
possible M512 RAM block configurations.
When the M512 RAM block is configured as a shift register block, a shift
register of size up to 576 bits is possible.
The M512 RAM block can also be configured to support serializer and
deserializer applications . By using the mixed-width support in
combination with DDR I/O standards, the block can function as a
SERDES to support low-speed serial I/O standards using global or
regional clocks. See “I/O Structure” on page 2–104 for details on
dedicated SERDES in Strati x devices.
Table 2–4. M512 RAM Block Configurations (Simple Dual-Port RAM)
Read Port Write Port
512 × 1 256 × 2 128 × 4 64 × 8 32 × 16 64 × 9 32 × 18
512 × 1 v v vvv
256 × 2v v vvv
128 × 4 vvv v
64 × 8 vv v
32 × 16 vvv v
64 × 9 v
32 × 18 v
2–28 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
TriMatrix Memory
M512 RAM blocks can have dif ferent clocks on its inputs and outputs.
The wren, datain, and write address registers are all clocked together
from one of the two clocks feeding the block. The r ead address, rden, and
output registers can be clocked by either of the two clocks driving the
block. This allows the RAM block to operate in read/write or
input/output clock modes. Only the output register can be bypassed. The
eight labclk signals or local interconnect can drive the inclock,
outclock, wren, rden, inclr, and outclr signal s. Because of the
advanced interconnect between th e LAB and M512 RAM blocks, LEs can
also control the wren and rden signals and the RAM clock, clock enable,
and asynchronous clear signals. Figure 2–15 shows the M512 RAM block
control signal generation logic.
The RAM blocks within Stratix devices have local interconnects to allow
LEs and interconnects to drive into RAM blocks. The M512 RAM block
local interconnect is driv en b y the R4, R8, C4, C8, and direct link
interconnect s from adjacent LABs. The M512 RAM blocks can
communicate with LA Bs on either the left or right side through these r ow
interconnects or with LAB columns on the left or right side with the
column interconnects. Up to 10 direct link input connections to the M512
RAM block are possible from the left adjacent LABs and another
10 possible from the right adjacent LAB. M512 RAM outputs can also
connect to left and right LABs through 10 direct link interconnects. The
M512 RAM block has equal opportunity for access and performance to
and from LABs on either its left or right side . Figure 2–16 shows the M512
RAM block to logic array interface.
Altera Corporation 2–29
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–15. M512 RAM Block Control Signals
inclocken
outclockinclock
outclocken
rden
wren
Dedicated
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect inclr
outclr
8
Local
Interconnect
Local
Interconnect
2–30 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
TriMatrix Memory
Figure 2–16. M512 RAM Block LAB Row Interface
M4K RAM Blo cks
The M4K RAM block includes support for true dual-port RAM. The M4K
RAM block is used to implement buffers for a wide variety of applications
such as storing processor code, implementing lookup schemes, and
implementing larger memory applications. Each block contains
4,608 RAM bits (including parity bits). M4K RAM blocks can be
configured in the following modes:
■True dual-port RAM
■Simple dual-port RAM
■Single-port RAM
■FIFO
■ROM
■Shift register
When configured as RAM or ROM, you can use an initialization file to
pre-lo ad the me mory contents.
dataout
M512 RAM
Block
datain
Clocks
10
Direct link
interconnect
from adjacent LAB
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
Direct link
interconnect
to adjacent LAB
Small RAM Block Local
Interconnect Region
C4 and C8
Interconnects R4 and R8
Interconnects
Control
Signals
address
LAB Row Clocks
2
8
Altera Corporation 2–31
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
The memory address depths and output widths can be configured as
4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or
256 × 18 bits), and 128 × 32 (or 128 × 36 bits). The 128 × 32- or 36-bit
configuration is not available in the true dual-port mode. Mixed-width
configurations are also possible, allowing different read and write
widths. Tables 2–5 and 2–6 summarize the possible M4K RAM block
configurations.
When the M4K RAM block is configured as a shift r egister block, you can
create a shift r egister up to 4,608 bits (w×m×n).
Table 2–5. M4K RAM Block Configurations (Simple Dual-Port)
Read Port Write Port
4K × 12K × 21K × 4 512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 128 × 36
4K × 1 vvvv v v
2K × 2 vvvv v v
1K × 4 vvvv v v
512 × 8 vvvv v v
256 × 16 vvvv v v
128 × 32 vvvv v v
512 × 9 vv v
256 × 18 vv v
128 × 36 vv v
Table 2–6. M4K RAM Block Configurations (True Dual-Port)
Port A Port B
4K × 12K × 21K × 4 512 × 8 256 × 16 512 × 9 256 × 18
4K × 1 vvvvv
2K × 2 vvvvv
1K × 4 vvvvv
512 × 8 vvvvv
256 × 16 vvvvv
512 × 9 vv
256 × 18 vv
2–32 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
TriMatrix Memory
M4K RAM blocks support byte writes when the write port has a data
width of 16, 18, 32, or 36 bits. The byte enables allow the input data to be
masked so the device can write to specific bytes. The unwritten bytes
retain the previous written value. Table 2–7 summarizes the byte
selection.
The M4K RAM blocks allow for different clocks on their inputs and
outputs. Either of the two clocks feeding the block can clock M4K RAM
block registers (renwe, address, byte enable, datain, and output
registers). Only the output register can be bypassed. The eight labclk
signals or local interconnects can drive the control signals for the A and B
ports of the M4K RAM block. LEs can also control the clock_a,
clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, an d
clocken_b signals, as shown in Figure 2–17.
The R4, R8, C4, C8, and direct link interconnects from adjacent LABs
drive the M4K RAM block local interconnect. The M4K RAM blocks can
communicate with LA Bs on either the left or right side through these r ow
reso urces or with LAB columns on either the right or left with the column
resources. Up to 10 direct link input connections to the M4K RAM Block
are possib le from the left adjac ent LABs and another 10 possible fr om the
right adjacent LAB. M4K RAM block outputs can also connect to left and
right LABs through 10 direct link interconnects each. Figure 2–18 shows
the M4K RAM block to logic array interface.
Table 2–7. Byte Enable for M4K Blocks Notes (1), (2)
byteena[3..0] datain ×18 datain ×36
[0] = 1 [8..0] [8..0]
[1] = 1 [17..9] [17..9]
[2] = 1 – [26..18]
[3] = 1 – [35..27]
Notes to Table 2–7:
(1) Any combination of byte enables is possible.
(2) Byte enables can be used in the same manner with 8-bit words, i.e., in ×16 and
×32 modes.
Altera Corporation 2–33
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–17. M4K RAM Block Control Signals
Figure 2–18. M4K RAM Block LAB Row Interface
clocken_a
renwe_aclock_a
alcr_a
alcr_b
renwe_b
Dedicated
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect clocken_b
clock_b
8
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
dataout
M4K RAM
Block
datainaddress
10
Direct link
interconnect
from adjacent LAB
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
Direct link
interconnect
to adjacent LAB
M4K RAM Block Local
Interconnect Region
C4 and C8
Interconnects R4 and R8
Interconnects
LAB Row Clocks
Clocks
Byte enable
Control
Signals
8
2–34 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
TriMatrix Memory
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for
applications where a lar g e volume of data must be stored on-chip. Each
block contains 589,824 RAM bits (including parity bits). The M-RAM
block can be configured in the following modes:
■True dual-port RAM
■Simple dual-port RAM
■Single-port RAM
■FIFO RAM
You cannot use an initialization file to initialize the contents of a M- RAM
block. All M-RAM block contents po wer up to an unde fined value. Only
synchronous operation is supported in the M-RAM block, so all inputs
are registered. Output r egisters can be bypassed. The memory address
and output width can be configured as 64K × 8 (or 64K × 9 bits), 32K × 16
(or 32K × 18 bits), 16K × 32 (or 16K × 36 bits), 8K × 64 (or 8K × 72 bits), and
4K × 128 (or 4K × 144 bits). The 4K × 128 configuration is unavailable in
true dual-port mode because ther e are a total of 144 data output drivers
in the block. Mixed-width configurations are also possibl e, allowi ng
different read and write widths. Tables 2–8 and 2–9 summarize the
possible M-RAM block configurations:
Table 2–8. M-RAM Block Configurations (Simple Dual-Port)
Read Port Write Port
64K × 932K × 18 16K × 36 8K × 72 4K × 144
64K × 9 vvvv
32K × 18 vvvv
16K × 36 vvvv
8K × 72 vvvv
4K × 144 v
Altera Corporation 2–35
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
The read and write operation of the memory is controlled by the WREN
signal, which sets the ports into either read or write modes. There is no
separate read enable (RE) signal.
Writing into RAM is controlled by both the WREN and byte enable
(byteena) signals for each port. The defa ul t value for the byteena
signal is high, in which case writing is controlled only by the WREN signal.
The byte enables are available for the ×18, ×36, and ×72 modes. In the
×144 simple dual-port mode, the two sets of byteena signals
(byteena_a and byteena_b) are combined to form the necessary
16 byte enables. Tables 2–10 and 2–11 summarize the byte selection.
Table 2–9. M-RAM Block Configurations (True Dual-Port)
Port A Port B
64K × 932K × 18 16K × 36 8K × 72
64K × 9 vvvv
32K × 18 vvvv
16K × 36 vvvv
8K × 72 vvvv
Table 2–10. Byte Enable for M-RAM Blocks Notes (1), (2)
byteena[3..0] datain ×18 datain ×36 datain ×72
[0] = 1 [8..0] [8..0] [8..0]
[1] = 1 [17..9] [17..9] [17..9]
[2] = 1 – [26..18] [26..18]
[3] = 1 – [35..27] [35..27]
[4] = 1 – – [44..36]
[5] = 1 – – [53..45]
[6] = 1 – – [62..54]
[7] = 1 – – [71..63]
2–36 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
TriMatrix Memory
Similar to all RAM blocks, M-RAM blocks can have different clocks on
their inputs and outputs. All input registers—renwe, datain, address,
and byte enable registers—are clocked together fro m either of the two
clocks feeding the block. The output register can be bypassed. The eight
labclk signals or local inter connect ca n drive the contr ol sig nals for the
A and B ports of the M-RAM block. LEs can also control the clock_a,
clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and
clocken_b signals as shown in Figure 2–19.
Table 2–11. M-RAM Combined Byte Selection for ×144 Mode Notes (1), (2)
byteena[15..0] datain ×144
[0] = 1 [8..0]
[1] = 1 [17..9]
[2] = 1 [26..18]
[3] = 1 [35..27]
[4] = 1 [44..36]
[5] = 1 [53..45]
[6] = 1 [62..54]
[7] = 1 [71..63]
[8] = 1 [80..72]
[9] = 1 [89..81]
[10] = 1 [98..90]
[11] = 1 [107..99]
[12] = 1 [116..108]
[13] = 1 [125..117]
[14] = 1 [134..126]
[15] = 1 [143..135]
Notes to Tables 2–10 and 2–11:
(1) Any combination of byte enables is possible.
(2) Byte enables can be used in the same manner with 8-bit words, i.e., in ×16, ×32,
×64, and ×128 modes.
Altera Corporation 2–37
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–19. M-RAM Block Control Signals
One of the M-RAM block’s horizontal sides driv e the address and contr ol
signal (clock, renwe, byteena, etc.) inputs. Typically, the horizontal side
closest to the device perimeter contains the interfaces. The one exception
is when two M-RAM blocks are paired next to each other. In this case, the
side of the M-RAM block opposite the common side of the two blocks
contains the input interface. The top and bottom sides of any M-RAM
block contain data input and output interfaces to the lo gic array. The top
side has 72 data inputs and 72 data outputs for port B, and the bottom side
has another 72 data inputs and 72 data outputs for port A. Figure 2–20
shows an example floorplan for the EP1S6 0 device and the location of the
M-RAM interfaces.
clocken_a
clock_bclock_a
clocken_b
aclr_a
aclr_b
Dedicated
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect renwe_a
renwe_b
8
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
2–38 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
TriMatrix Memory
Figure 2–20. EP1S60 Device with M-RAM Interface Locations Note (1)
Note to Figure 2–20:
(1) Device shown is an EP1S60 device. The number and position of M-RAM blocks varies in other devices.
The M-RAM block local interc onnect is driven by the R4, R8, C4, C8, and
direct link interconnects from adjacent LABs. For independent M-RAM
blocks, up to 10 direct link address and control s ignal input connections
to the M-RAM block are possible fr om the left adjacent LABs for M-RAM
M-RAM
Block M-RAM
Block
DSP
Blocks
DSP
Blocks
M4K
Blocks
M512
Blocks
LABs
M-RAM
Block
M-RAM
Block M-RAM
Block M-RAM
Block
M-RAM pairs interface to
top, bottom, and side opposite
of block-to-block border.
Independent M-RAM blocks
interface to top, bottom, and side facing
device perimeter for easy access
to horizontal I/O pins.
Altera Corporation 2–39
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
blocks facing to the left, and another 10 possible from the right adjacent
LABs for M-RAM blocks facing to the right. For column interfacing, every
M-RAM column unit connects to the right and le ft column lines, allowing
each M-RAM column unit to communicate directly with three columns of
LABs. Figures 2–21 through 2–23 show the interface between the M-RAM
block and the logic array.
2–40 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
TriMatrix Memory
Figure 2–21. Left-Facing M-RAM to Interconnect Interface Notes (1), (2)
Notes to Figure 2–21:
(1) Only R24 and C16 interconnects cross the M-RAM block boundaries.
(2) The right-facing M-RAM block has interface blocks on the right side, but none on the left. B1 to B6 and A1 to A6
orientation is clipped across the vertical axis for right-facing M-RAM blocks.
M-RAM Block
Port B
Port A
Row Unit Interface
Allows LAB Rows to
Drive Address and
Control Signals to
M-RAM Block
Column Interface Block
Allows LAB Columns to
Drive datain and dataout to
and from M-RAM Block
LABs in Row
M-RAM Boundary
LABs in Column
M-RAM Boundary
M512 RAM Block Columns
Column Interface Block
Drives to and from
C4 and C8 Interconnects
LAB Interface
Blocks
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
A1 A2 A3 A4 A5 A6
B1 B2 B3 B4 B5 B6
Altera Corporation 2–41
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–22. M-RAM Row Unit Interface to Interconnect
LAB
Row Interface Block
M-RAM Block
10
Up to 24
addressa
addressb
renwe_a
renwe_b
byteenaA[ ]
byteenaB[ ]
clocken_a
clocken_b
clock_a
clock_b
aclr_a
aclr_b
M-RAM Block to
LAB Row Interface
Block Interconnect Region
R4 and R8 InterconnectsC4 and C8 Interconnects
Direct Link
Interconnects
2–42 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
TriMatrix Memory
Figure 2–23. M-RAM Column Unit Interface to Interconnect
12 12
Column Interface
Block
M-RAM Block to
LAB Row Interface
Block Interconnec
t
Region
datain dataout
LAB LABLAB
C4 and C8 Interconnects
M-RAM Block
Altera Corporation 2–43
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Table 2–12 shows the input and output data signal connections for the
column units (B1 to B6 and A1 to A6). It also shows the address and
control signal input connections to the row units (R1 to R11).
Table 2–12. M-RAM Row & Column Interface Unit Signals
Unit Interface Block Input SIgnals Output Signals
R1 addressa[7..0]
R2 addressa[15..8]
R3 byte_enable_a[7..0]
renwe_a
R4 -
R5 -
R6 clock_a
clocken_a
clock_b
clocken_b
R7 -
R8 -
R9 byte_enable_b[7..0]
renwe_b
R10 addressb[15..8]
R11 addressb[7..0]
B1 datain_b[71..60] dataout_b[71..60]
B2 datain_b[59..48] dataout_b[59..48]
B3 datain_b[47..36] dataout_b[47..36]
B4 datain_b[35..24] dataout_b[35..24]
B5 datain_b[23..12] dataout_b[23..12]
B6 datain_b[11..0] dataout_b[11..0]
A1 datain_a[71..60] dataout_a[71..60]
A2 datain_a[59..48] dataout_a[59..48]
A3 datain_a[47..36] dataout_a[47..36]
A4 datain_a[35..24] dataout_a[35..24]
A5 datain_a[23..12] dataout_a[23..12]
A6 datain_a[11..0] dataout_a[11..0]
2–44 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
TriMatrix Memory
Independent Clock Mode
The memory blocks implement independent clock mode for true dual-
port memory. In this mode, a separate clock is available for each port
(ports A and B). Clock A controls all registers on the port A side, while
clock B controls all registers on the port B side. Each port, A and B, also
supports independent clock enables and asynchronous clear signals for
port A and B regi sters. Figure 2–24 shows a TriMatrix memory block in
independent clock mode.
Altera Corporation 2–45
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–24. Independent Clock Mode Notes (1), (2)
Notes to Figure 2–24
(1) All registers shown have asynchronous clear ports.
(2) V iolating the setup or hold time on the address registers could corrupt the memory
contents. This applies to both read and write operations.
8
D
ENA Q
D
ENA
Q
D
ENA
Q
dataA[ ]
addressA[ ]
Memory Block
256 ´ 16 (2)
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
Data In
Address A
Write/Read
Enable
Data Out
Data In
Address B
Write/Read
Enable
Data Out
clkenA
clockA
D
ENA Q
wrenA
8 LAB Row Clocks
qA[ ]
8dataB[ ]
addressB[ ]
clkenB
clockB
wrenB
qB[ ]
ENA
AB
ENA
DQ
D
ENA Q
byteenaA[ ] Byte Enable A Byte Enable B byteenaB[ ]
ENA
DQ
ENA
DQ
ENA
DQ
DQ
Write
Pulse
Generator
Write
Pulse
Generator
2–46 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
TriMatrix Memory
Input/Output Clock Mode
Input/output clock mode can be imple me nt ed for both the true and
simple dual-port memory modes. On each of the two ports, A or B, one
clock controls all registers for inputs into the memory block: data input,
wren, and address. The other clock controls the block’s data output
registers. Each memory block port, A or B, also supports independent
clock enables and asynchronous clear signals for input and output
registers. Figures 2–25 and 2–26 show the memory block in input/output
clock mode.
Altera Corporation 2–47
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–25. Input/Output Clock Mode in True Dual-Port Mode Notes (1), (2)
Notes to Figure 2–25:
(1) All registers shown have asynchronous clear ports.
(2) V iolating the setup or hold time on the address registers could corrupt the memory
contents. This applies to both read and write operations.
8
D
ENA Q
D
ENA
Q
D
ENA
Q
dataA[ ]
addressA[ ]
Memory Block
256 × 16 (2)
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Data In
Address A
Write/Read
Enable
Data Out
Data In
Address B
Write/Read
Enable
Data Out
clkenA
clockA
D
ENA Q
wrenA
8 LAB Row Clocks
qA[ ]
8
dataB[ ]
addressB[ ]
clkenB
clockB
wrenB
qB[ ]
ENA
AB
ENA
DQ
ENA
DQ
ENA
DQ
DQ
D
ENA Q
byteenaA[ ] Byte Enable A Byte Enable B byteenaB[ ]
ENA
DQ
Write
Pulse
Generator
Write
Pulse
Generator
2–48 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
TriMatrix Memory
Figure 2–26. Input/Output Clock Mode in Simple Dual-Port Mode Notes (1), (2)
Notes to Figure 2–26:
(1) All registers shown except the rden register have asynchronous clear ports.
(2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
8
D
ENA Q
D
ENA Q
D
ENA Q
D
ENA Q
D
ENA Q
data[ ]
D
ENA Q
wraddress[ ]
address[ ]
Memory Block
256 ´ 16
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
Data In
Read Address
Write Address
Write Enable
Read Enable
Data Out
outclken
inclken
wrclock
rdclock
wren
rden
8 LAB Row
Clocks
To MultiTrac
k
Interconnect
D
ENA Q
byteena[ ] Byte Enable
Write
Pulse
Generator
Altera Corporation 2–49
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Read/Write Clock Mode
The memory blocks implement read/write clock mode for simple dual-
port memory. You can use up to two clocks in this mode. The write clock
controls the block’s data inputs, wraddress, and wren. The read clock
controls the data output, rdaddress, and rden. The memory block s
support independent clock enables for each clock and asynchronous clear
signals for the read- and write-side registers. Figure 2–27 shows a
memory block in read/write clock mode.
2–50 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
TriMatrix Memory
Figure 2–27. Read/Write Clock Mode in Simple Dual-Port Mode Notes (1), (2)
Notes to Figure 2–27:
(1) All registers shown except the rden register have asynchronous clear ports.
(2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
8D
ENA Q
D
ENA Q
D
ENA Q
D
ENA Q
D
ENA Q
data[ ]
D
ENA Q
wraddress[ ]
address[ ]
Memory Block
256 × 16
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Data In
Read Address
Write Address
Write Enable
Read Enable
Data Out
outclken
inclken
wrclock
rdclock
wren
rden
8 LAB Row
Clocks
To MultiTrac
k
Interconnect
D
ENA Q
byteena[ ] Byte Enable
Write
Pulse
Generator
Altera Corporation 2–51
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Single-Port Mode
The memory blocks also support single-port mode, used when
simultaneous reads and writes are not r equired. See Figure 2–28. A single
block in a memory block can support up to two single-port mode RAM
blocks in the M4K RAM blocks if each RAM block i s less than or equal to
2K bits in size.
Figure 2–28. Single-Port Mode Note (1)
Note to Figure 2–28:
(1) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
8
D
ENA Q
D
ENA Q
D
ENA Q
D
ENA Q
data[ ]
address[ ]
RAM/ROM
256 × 16
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Data In
Address
Write Enable
Data Out
outclken
inclken
inclock
outclock
Write
Pulse
Generator
wren
8 LAB Row
Clocks
To MultiTrac
k
Interconnect
2–52 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Digital Signal Processing Block
Digital Signal
Processing
Block
The most commonly used DSP functions are finite impulse response (FIR)
filters, complex FIR filters, infinite impulse response (IIR) filters, fast
Fourier transform (FFT) functions, direct cosine transform (DCT)
functions, and correlators. All of these blocks have the same fundamental
building block: the multiplier. Additionally, some applications need
specialized operations such as multiply-add and multiply-accumulate
operations. Stratix devices pr ovide DSP blocks to meet the arithmetic
requirements of these functions.
Each Stratix device has two columns of DSP blocks to efficiently
implement DSP functions faster than LE-based implementations. Lar g er
Stratix devices have more DSP blocks per column (see Table 2–13). Each
DSP block can be configured to support up to:
■Eight 9 × 9-bit multipliers
■Four 18 × 18-bit multipliers
■One 36 × 36-bit multiplier
As indicated, the Stratix DSP block can support one 36 × 36-bit multiplier
in a single DSP block. This is tr u e for any matched sign multiplications
(either unsigned by unsigned or signed by signed), but the capabilities for
dynamic and mixe d sign multiplications are handled differently. The
following list pr ovides the lar gest functions that can fit into a single DSP
block.
■36 × 36-bit unsigned by unsigned multiplication
■36 × 36-bit signed by signed multiplication
■35 × 36-bit unsigned by signe d mu ltiplication
■36 × 35-bit signed by unsigned multipli cation
■36 × 35-bit signed by dynamic sign mu ltiplication
■35 × 36-bit dynamic sign by sig ne d mu ltiplication
■35 × 36-bit unsigned by dynamic sign multiplicati on
■36 × 35-bit dynamic sign by unsigned multiplication
■35 × 35-bit dynamic sign multiplication when the sign controls for
each operand are different
■36 × 36-bit dynamic sign mult iplication when the same sign co ntrol
is used for both operands
1This list only shows functions that can fit into a single DSP block.
Multiple DSP blocks can support larger multipl ic ation
functions.
Figure 2–29 shows one of the columns with surrounding LAB rows.
Altera Corporation 2–53
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–29. DSP Blocks Arranged in Columns
DSP Block
Column
8 LAB
Rows
DSP Block
2–54 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Digital Signal Processing Block
Table 2–13 shows the number of DSP blocks in each Stratix device.
DSP block multipliers can optionally feed an adder/subtractor or
accumulator within the block depending on the configuration. This
makes r outing to LEs easier, saves LE ro u t ing resources, and inc rease s
performance, because all connections and blocks are within the DSP
block. Additionally, the DSP block input registers can efficiently
implement shift registers for FIR filter applications.
Figure 2–30 shows the top-level diagram of the DSP block configure d for
18 × 18-bit multiplier mode. Figure 2–31 shows the 9 × 9-bit multiplier
configuration of the DSP block.
Table 2–13. DSP Blocks in Stratix Devices Notes (1), (2)
Device DSP Blocks Total 9 × 9
Multipliers Total 18 × 18
Multipliers Total 36 × 36
Multipliers
EP1S10 6 48 24 6
EP1S20 10 80 40 10
EP1S25 10 80 40 10
EP1S30 12 96 48 12
EP1S40 14 112 56 14
EP1S60 18 144 72 18
EP1S80 22 176 88 22
Notes to Table 2–13:
(1) Each device has either the number of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers
shown. The total number of multipliers for each device is not the sum of all the
multipliers.
(2) The number of supported multiply functions shown is based on signed/signed
or unsigned/unsigned implementations.
Altera Corporation 2–55
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–30. DSP Block Diagram for 18 × 18-Bit Configuration
Adder/
Subtractor/
Accumulator
2
Adder/
Subtractor/
Accumulator
1
Summation
Optional Pipeline
Register Stage
Multiplier Stage
Output Selection
Multiplexer
Optional Output
Register Stage
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
Optional Serial Shift Register
Inputs from Previous
DSP Block
Optional Stage Configurable
as Accumulator or Dynamic
Adder/Subtractor
Summation Stage
for Adding Four
Multipliers Together
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
Optional Serial
Shift Register
Outputs to
Next DSP Block
in the Column
to MultiTrack
Interconnect
2–56 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Digital Signal Processing Block
Figure 2–31. DSP Block Diagram for 9 × 9-Bit Configuration
CLRN
DQ
ENA
CLRN
DQ
ENA CLRN
DQ
ENA
Adder/
Subtractor/
1a
Summation
Summation
CLRN
DQ
ENA
CLRN
DQ
ENA CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA CLRN
DQ
ENA
CLRN
DQ
ENA
Adder/
Subtractor/
1b
CLRN
DQ
ENA
CLRN
DQ
ENA CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA CLRN
DQ
ENA
Adder/
Subtractor/
2a
CLRN
DQ
ENA
CLRN
DQ
ENA CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA CLRN
DQ
ENA
Adder/
Subtractor/
2b
CLRN
DQ
ENA
CLRN
DQ
ENA CLRN
DQ
ENA
Output
Selection
Multiplexer
To MultiTrack
Interconnect
Altera Corporation 2–57
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
The DSP block consists of the following elements:
■Multiplier block
■Adder/output block
Multiplier Block
The DSP block multiplier block consists of the input registers, a
multiplier, and pipeline register for pipelining multiply-accumulate and
multiply-add/subtract functions as shown in Figure 2–32.
Figure 2–32. Multiplier Sub-Block within Stratix DSP Block
Note to Figure 2–32:
(1) These signals can be unregistered or registered once to match data path pipelines if required.
CLRN
DQ
ENA
Data A
Data B
Result
to Adder
blocks
shiftout B shiftout A
shiftin A
shiftin B
aclr[3..0]
clock[3..0]
ena[3..0]
Optional
Multiply-Accumulate
and Multiply-Add
Pipeline
sign_a (1)
sign_b (1)
CLRN
DQ
ENA
CLRN
DQ
ENA
2–58 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Digital Signal Processing Block
Input Registers
A bank of optional input registers is located at the input of each multiplier
and multiplicand inputs to the multiplier. When these registers are
configured for parallel data inputs, they are driven by regular routing
resources. You can use a clock signal, asynchronous clear signal, and a
clock enable signal to independently control each set of A and B inputs for
each multiplier in the DSP block. You select these control signals from a
set of four different clock[3..0], aclr[3..0], and ena[3..0]
signals that drive the entire DSP block.
You can also configure the input regis ters for a shift registe r application.
In this case, the input registers feed the multiplier and drive two
dedicated shif t o utpu t lines: shiftoutA and shiftoutB. Th e sh ift
outputs of one multiplier block dir ectly feed the adjacent multiplier block
in the same DSP block (or the next DSP block) as shown in Figure 2–33, to
form a shift register chain. This chain can terminate in any block, that is,
you can create any length of shift register chain up to 224 registers. You
can use the input shift registers for FIR filter applications. One set of shift
inputs can provide data for a filter, and the other are coeffici ents that are
optionally loaded in serial or parallel. When implementing 9 × 9- and
18 × 18-bit multipliers, you do not need to implement external shift
registers in LAB LEs. Y ou implement all the filter circuitry within the DSP
block and its routing resources, saving LE and general routing resources
for general logic. External registers are needed for shift re gister inputs
when using 36 × 36-bit multipliers.
Altera Corporation 2–59
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–33. Multiplier Sub-Blocks Using Input Shift Register Connections
Note (1)
Note to Figure 2–33:
(1) Either Data A or Data B input can be set to a parallel input for constant coefficient
multiplication.
CLRN
DQ
ENA
Data A
Data B
A[n] × B[n]
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
Data A
Data B
A[n Ð 1] × B[n Ð 1]
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
Data A
Data B
A[n Ð 2] × B[n Ð 2]
CLRN
DQ
ENA
CLRN
DQ
ENA
2–60 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Digital Signal Processing Block
Table 2–14 shows the summary of input register modes for the DSP block.
Multiplier
The multiplier supports 9 × 9-, 18 × 18-, or 36 × 36-bit multiplication. Each
DSP block supports eight possible 9 × 9-bit or smaller mu ltipliers. Ther e
are four multiplier blocks available for multipliers larger than 9 × 9 bits
but smaller than 18 × 18 bits. There is one multiplier block available for
multipliers larger than 18 × 18 bits but smaller than or equal to 36 × 36
bits. The ability to have several sm all multipliers is useful in applications
such as video processing. Large multipliers greater than 18 × 18 bits are
useful for applications such as the mantissa multiplication of a single-
precision floating-point number.
The multiplier operands can be signed or unsigned numbers, where the
result is signed if either input is signed as shown in Table 2–15. The
sign_a and sign_b signals pr ovide dynamic control of eac h operand’s
repr esentation: a logic 1 indicates the operand is a signed number, a logic
0 indicates the operand is an unsigned number. These si gn signals affect
all multipliers and adders within a single DSP block and you can register
them to match the data path pipeline. The multipliers are full precis ion
(that is, 18 bits for the 18-bit multiply, 36-bits for the 36-bit multiply, and
so on) regardless of whether sign_a or sign_b set the operands as
signed or unsigned numbers.
Table 2–14. Input Register Modes
Register Input Mode 9 × 9 18 × 18 36 × 36
Parallel input vvv
Shift register input vv
Table 2–15. Multiplier Signed Representation
Data A Data B Result
Unsigned Unsigned Unsigned
Unsigned Signed Signed
Signed Unsigned Signed
Signed Signed Signed
Altera Corporation 2–61
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Pipeline/Post Multiply Register
The output of 9 × 9- or 18 × 18-bit multipliers can optionally feed a register
to pipeline multiply-accumulate and multiply-add/ subtract functions.
For 36 × 36-bit multipliers, this registe r will pipeline the multiplier
function.
Adder/Output Blocks
The result of the multiplier sub-blocks ar e sent to the adder/output block
which consist of an adder/subtractor/accumulator unit, summation unit,
output select multiplexer, and output registers. The results are used to
configure the adder/output block as a pure output, accumulator , a simple
two-multiplier adder, four-multiplier adder, or final stage of the 36-bit
multiplie r. You can configure the adder/output block to use output
registers in any mode, and must use output r egisters for the accumulator.
The system cannot use adder/output blocks independently of the
multiplier. Figure 2–34 shows the adder and output stages.
2–62 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Digital Signal Processing Block
Figure 2–34. Adder/Output Blocks Note (1)
Notes to Figure 2–34:
(1) Adder/output block shown in Figure 2–34 is in 18 × 18-bit mode. In 9 × 9-bit mode, there are four adder/subtractor
blocks and two summation blocks.
(2) These signals are either not registered, registered once, or r egistered twice to match the data path pipeline.
Adder/
Subtractor/
Accumulator1
Summation
Result A
Result B
Result C
Result D
addnsub1 (2)
accum_sload0 (2)
addnsub3 (2)
signa (2)
signb (2)
accum_sload1 (2)
Accumulator Feedback
Accumulator Feedback
overflow0
Adder/
Subtractor/
Accumulator2
Output Selectio
n
Multiplexer
Output
Register Block
overflow1
Altera Corporation 2–63
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Adder/Subtractor/Accumulator
The adder/subtractor/accumulator is the first level of the adder/output
block and can be used as an accumulator or as an adder/subtractor.
Adder/Subtractor
Each adder/subtractor/accumulator block can perform addition or
subtraction using the addnsub independent control signal for each first-
level adder in 18 × 18-bit mode. There are two addnsub[1..0] signals
available in a DSP block for any configuration. For 9 × 9-bit mode, one
addnsub[1..0] signal controls the top two one-level adders and
another addnsub[1..0] signal controls the bottom two one-level
adders. A high addnsub signal indicates addition, and a low signal
indicates subtraction. The addnsub control signal can be unregistered or
registered once or twice when feeding the adder blocks to match data
path pipelines.
The signa and signb signals serve the same function as the multiplier
block signa and signb signals. The only difference is that these signals
can be registered up to two times. These signals are tied to the same
signa and signb signals from the multiplier and must be connected to
the same clocks and control signals.
Accumulator
When configured for accumulation, the adder/ output block output feeds
back to the accumulator as shown in Figure 2–34. The
accum_sload[1..0] signal synchronously loads the multiplier result
to the accumulator output. This signal can be unregistered or registered
once or twice. Additionally, the overflow signal in dicates the
accumulator has overflowed or underflowed in accumulation mode. This
signal is always regis tered and must be externally latched in LEs if the
design requires a latched overflow sign al.
Summation
The output of the adder/subtractor/accumulator block feeds to an
optional summation block. This block sums the outputs of the DSP block
multipliers. In 9 × 9-bit mode, there ar e two su mmation blocks provid ing
the sums of two sets of four 9 × 9-bit multipliers. In 18 × 18-bit mode, ther e
is one summation providing the sum of one set of four 18 × 18-bit
multipliers.
2–64 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Digital Signal Processing Block
Output Selection Multiplexer
The outputs from the various elements of the adder/output block are
routed through an output selection multiplexer. Based on the DSP block
operational mode and user se ttings, the multiplexer selects whether the
output from the multiplier, the adder/subtractor/accumulator, or
summation block feeds to the output.
Output Registers
Optional output registers for the DSP block outputs are controlled by four
sets of control signals: clock[3..0], aclr[3..0], and ena[3..0].
Output registers can be used in any mode.
Modes of Operation
The adder , subtractor, and accumulate functions of a DSP block have four
modes of operation:
■Simple multiplier
■Multiply-accumulator
■Two-multipliers adder
■Four-multipliers adder
1Each DSP block can only support one mode. Mixed modes in the
same DSP block is not supported.
Simple Multiplier Mode
In simple multiplier mode, the DSP block drive s the multiplier sub-block
result dir ectly to the output with or without an output register. Up to four
18 × 18-bit multipliers or eight 9 × 9-bit multipliers can drive their r esults
directly out of one DSP block. See Figure 2–35.
Altera Corporation 2–65
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–35. Simple Multiplier Mode
Note to Figure 2–35:
(1) These signals are not registered or registered once to match the dat a pa th pipeline.
DSP blocks can also implement one 36 × 36-bit multiplier in multiplier
mode. DSP blocks use four 18 × 18-bit multipliers combined with
dedicated adder and internal shift circuitry to achieve 36-bit
multiplication. The input shift register feature is not available for the
36 × 36-bit multiplier. In 36 × 36-bit mode, the device can use t he r egi ster
that is normally a multi plier -r esult-out put register as a pipeline stage for
the 36 × 36-bit multiplier. Figure 2–36 shows the 36 × 36-bit multiply
mode.
CLRN
DQ
ENA
Data A
Data B
Data Out
shiftout B shiftout A
shiftin A
shiftin B
aclr
clock
ena
signa (1)
signb (1)
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
2–66 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Digital Signal Processing Block
Figure 2–36. 36 × 36 Multiply Mode
Notes to Figure 2–36:
(1) These signals are not registered or registered once to match the pipeline.
(2) These signals are not registered, registered once, o r registered twice for latency to match the pipeline.
CLRN
DQ
ENA
A[17..0]
A[17..0]
B[17..0]
B[17..0]
A[35..18]
A[35..18]
B[35..18]
B[35..18]
aclr
clock
ena
signa (1)
signb (1)
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
Data Ou
t
36 × 36
Multiplier
Adder
signa (2)
signb (2)
Altera Corporation 2–67
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Multiply-Accumulator Mode
In multiply-accumulator mode (see Figure 2–37), the DSP block drives
multiplied results to the adder/subtractor/accumulator block configured
as an accumulator . Y ou can implement one or two multiply-accumulators
up to 18 × 18 bits in one DSP block. The first and third mu l t ipl ier su b-
blocks are unused in this mode, because only one multiplier can fe ed one
of two accumulators. The multiply-accumulator output can be up to 52
bits—a maximum of a 36-bit result with 16 bits of accumulation. The
accum_sload and overflow signals are only available in this mode.
The addnsub signal can set the accumulator for decimation and the
overflow signal indicates underflow condi t ion.
Figure 2–37. Multiply-Accumulate Mode
Notes to Figure 2–37:
(1) These signals are not registered or registered once to match the dat a pa th pipeline.
(2) These signals are not registered, registered once, or registered twice for latency to match the data path pipeline.
Two-Multipliers Adder Mode
The two-multipliers adder mode uses the adder/subtractor/accumulator
block to add or subtract the outputs of the multiplier block, which is
useful for applicatio ns such as FFT functions and complex FIR filt ers. A
CLRN
DQ
ENA
CLRN
DQ
ENA
Data A
Data B
Data Out
overflow
Shiftout B Shiftout A
Shiftin A
Shiftin B
aclr
clock
ena
signa (1)
signb (1)
CLRN
DQ
ENA
CLRN
DQ
ENA
Accumulator
addnsub (2)
signa (2)
signb (2)
accum_sload (2)
2–68 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Digital Signal Processing Block
single DSP block can implement two sums or differences from two
18 × 18-bit mult ipliers each or four sums or dif ferences fr om two 9 × 9-bit
multipliers each.
You can use the two-multipliers adder mode for complex multiplications,
which are written as:
(a + jb) × (c + jd) = [(a × c) – (b × d)] + j × [(a × d) + (b × c)]
The two-multipliers adder mode allows a single DSP block to calculate
the real part [(a × c) – (b × d)] using one subtractor and the imaginary part
[(a × d) + (b × c)] using one adder, for data widths up to 18 bits. Two
complex multiplications are possible for data widths up to 9 bits using
four adder/subtractor/accumulator blocks. Figure 2–38 shows an 18-bit
two-multipliers ad der.
Figure 2–38. Two-Multipliers Adder Mode Implementing Complex Multiply
Four-Multipliers Adder Mode
In the four -multipliers adder mode, the DSP block adds the results of two
first -stage adder/subtractor blocks. One sum of four 18 × 18-bit
multipliers or two differ ent sums of two sets of four 9 × 9-bit multipliers
can be implemented in a single DSP block. The product width for each
multiplier must be the same size. The four-multipliers adder mode is
useful for FIR filter applic ations. Figure 2–39 shows the four multipliers
adder mode.
Subtractor
36
36
18
18
18 37
A
18
(A × C) − (B × D)
(Real Part)
Adder
36
36
18
18 37
A
18
18
18
(A × D) + (B × C)
(Imaginary Part)
18
18
18
DSP Block
C
B
D
D
B
C
Altera Corporation 2–69
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–39. Four-Multipliers Adder Mode
Notes to Figure 2–39:
(1) These signals are not registered or registered once to match the dat a pa th pipeline.
(2) These signals are not registered, registered once, or registered twice for latency to match the data path pipeline.
CLRN
DQ
ENA
Data A
Data B
shiftin A
shiftin B
aclr
clock
ena
signa (1)
signb (1)
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
Data A
Data B
CLRN
DQ
ENA
CLRN
DQ
ENA
Adder/Subtractor
CLRN
DQ
ENA
Data A
Data B
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
Data A
Data B
shiftout B shiftout A
CLRN
DQ
ENA
CLRN
DQ
ENA
Adder/Subtractor
addnsub1 (2)
signa (2)
signb (2)
CLRN
DQ
ENA
Data Ou
t
addnsub3 (2)
Summation
2–70 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Digital Signal Processing Block
For FIR filters, the DSP block combines the four-multipli ers ad der mode
with the shift register inputs. One set of shift inputs contains the filter
data, while the other holds the coefficients loaded in serial or parallel. The
input shift register eliminates the need for shift registers external to the
DSP block (i.e., implemente d in LEs). This archit ecture simp lifies filter
design since the DSP block implements all of the filter circuitry.
One DSP block can implement an entire 18-bit FIR filter with up to four
taps. For FIR filters larger than four taps, DSP blocks can be cascaded with
additional adder st ages implemented in LEs.
Table 2–16 shows the different number of multipliers possible in each
DSP block mode accord ing to size. The se modes allow the DSP blo cks to
implement numerous applications for DSP including FFTs, complex FIR,
FIR, and 2D FIR filters, equalizers, IIR, correlators, matrix mult iplicat ion
and many other functions.
DSP Block Interface
Stratix device DSP block outputs can cascade down within the same DSP
block column. Dedicated connec ti o ns between DSP blocks provide fast
connections between the shift r egister inputs to cascade t he shift register
chains. You can cascade DSP blocks for 9 × 9- or 18 × 18-bit FIR filters
larger than fou r t aps, with addi tional adder stages implemented in LEs.
If the DSP block is configured as 36 × 36 bits, the adder, subtractor, or
accumulator stages are implemented in LEs. Each DSP block can route the
shift register chain out of the block to cascade two full columns of DSP
blocks.
Table 2–16. Multiplier Size & Configurations per DSP block
DSP Block Mode 9 × 9 18 × 18 36 × 36 (1)
Multiplier Eight multipliers with
eight product outputs Four multipliers with four
product outputs One multiplier with one
product output
Multiply-accumulator Two multiply and
accumulate (52 bits) Two multiply and
accumulate (52 bits) –
Two-multipliers adder Four sums of two
multiplier products each Two sums of two
multiplier products each –
Four-multipliers adder Two sums of four
multiplier products each One sum of four multiplier
products each –
Note to Table 2–16:
(1) The number of supported multiply functions shown is based on signed/signed or unsigned/unsigned
implementations.
Altera Corporation 2–71
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
The DSP block is divided into eight block units that interface with eight
LAB rows on the left and right. Eac h block unit c an be consid er ed half of
an 18 × 18-bit multiplier sub-block with 18 inputs and 18 outputs. A local
interconnect region is associated with each DSP block. Like an LAB , this
interconnect region can be fed with 10 direct link interconnects from the
LAB to the left or right of the DSP block in the same row. All row and
column routing resources can access the DSP block’s local interconnect
region. The outputs also work similarly to LA B ou tputs as well. Nine
outputs fr om the DSP block can drive to t he left LAB through direct link
interconnects and nine can drive to the right LAB though direct link
interc onnects. All 18 outputs can drive to all types of row and column
routing. Outputs can drive right- or left-column routing. Figures 2–40
and 2–41 show the DSP block interfaces to LAB rows.
Figure 2–40. DSP Block Interconnect Interface
A1[17..0]
B1[17..0]
A2[17..0]
B2[17..0]
A3[17..0]
B3[17..0]
A4[17..0]
B4[17..0]
OA[17..0]
OB[17..0]
OC[17..0]
OD[17..0]
OE[17..0]
OF[17..0]
OG[17..0]
OH[17..0]
DSP Block
MultiTrack
Interconnec
t
MultiTrack
Interconnect
2–72 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Digital Signal Processing Block
Figure 2–41. DSP Block Interface to Interconnect
A bus of 18 control signals feeds the entire DSP block. These si g na ls
include clock[0..3] clocks, aclr[0..3] asynchronous clears,
ena[1..4] clock enables, signa, signb signed/unsigned control
signals, addnsub1 and addnsub3 addition and subtraction control
signals, and accum_sload[0..1] accumulator synchronous loads. The
LAB LAB
Row Interface
Block
DSP Block
Row Structure
10
[17..0][17..0]
DSP Block to
LAB Row Interface
Block Interconnect Region
18 Inputs per Row 18 Outputs per Row
R4 and R8 Interconnects
C4 and C8
Interconnects
Direct Link Interconnect
from Adjacent LAB
Nine Direct Link Outputs
to Adjacent LABs
Direct Link Interconnect
from Adjacent LAB
18
18
18
Control
3
99
10
Altera Corporation 2–73
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
clock signals are routed from LAB row clocks and are generated from
specific LAB rows at the DSP block interface. The LAB row source for
control signals, data inputs, and outputs is shown in Table 2–17.
PLLs & Clock
Networks Stratix devices provide a hierarchical clock structure and multiple PLLs
with advanced features. The large number of clocking resources in
combination with the clock synthesis precision provided by enhanced
and fast PLLs provides a complete clock management solution.
Global & Hierarchical Clocking
Stratix devices provide 16 dedicated global clock networks, 16 regional
clock networks (four per device quadrant), and 8 d edicate d fast regional
clock networks (for EP1S10, EP1S20, and EP1S25 devices), and
16 dedicated fast regional clock networks (for EP1S30 EP1S40, and
EP1S60, and EP1S80 devices). These clocks are organized into a
hierarchical clock struct ure that allows for up to 22 clocks per device
region with low skew and de lay. This hierarchical clocking scheme
provides up to 48 unique clock domains within Stratix de vic es.
Table 2–17. DSP Block Signal Sources & Destinations
LAB Row at
Interface Control Signals
Generated Data Inputs Data Outputs
1signa A1[17..0] OA[17..0]
2aclr0
accum_sload0 B1[17..0] OB[17..0]
3addnsub1
clock0
ena0
A2[17..0] OC[17..0]
4aclr1
clock1
ena1
B2[17..0] OD[17..0]
5aclr2
clock2
ena2
A3[17..0] OE[17..0]
6sign_b
clock3
ena3
B3[17..0] OF[17..0]
7clear3
accum_sload1 A4[17..0] OG[17..0]
8addnsub3 B4[17..0] OH[17..0]
2–74 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
PLLs & Clock Networks
There are 16 dedicated clock pins (CLK[15..0]) to drive either the global
or regional clock networks. Four clock pins drive each side of the device,
as shown in Figure 2–42. Enhanced and fast PLL outputs can also drive
the global and regional clock networ ks.
Global Clock Network
These clocks drive thro ughout the entire device, feeding all device
quadrants. The glo bal clock netwo rks can be used as c lock sour ce s for all
resources within the device—IOEs, LE s, DSP blocks, and all memo ry
blocks. These resources can also be used for control signals, such as clock
enables and synchronous or asynchronous clears fed from the external
pin. The global clock networks can also be driven by internal logic for
internally generated global clo cks and asynchronous clears, clock
enables, or other control signals with large fanout. Figure 2–42 shows the
16 dedicated CLK pins driving global clock networks.
Altera Corporation 2–75
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–42. Global Clocking Note (1)
Note to Figure 2–42:
(1) The corner fast PLLs can also be driven through the global or regional clock
networks. The global or regional clock input to the fast PLL can be driven by an
output from another PLL, a pin-driven global or regional clock, or internally-
generated global signals.
Regional Clock Network
There are four regional clock networks within each quadrant of the Stratix
device that ar e driven by the same dedicated CLK[15..0] input pins or
from PLL outputs. Fr om a top view of the silicon, RCLK[0..3] are i n the
top left quadrant, RCLK[8..11] ar e in the top-right quadrant,
RCLK[4..7] are in the bottom-left quadrant, and RCLK[12..15] ar e in
the bottom-right quadrant. The region al clock networks only pertain to
the quadrant they drive into. The regional clock networks provide the
lowest clock delay and skew for logic contained within a single quadrant.
RCLK cannot be driven by internal logic. The CLK cl ock pins
symmetrically dri ve the RCLK networks within a particular quadrant, as
shown in Figure 2–43. See Figures 2–50 and 2–51 for RCLK connections
from PLLs and CLK pins.
Global Clock [15..0]
CLK[15..12]
CLK[3..0]
CLK[7..4]
CLK[11..8]
Global Clock [15..0]
2–76 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
PLLs & Clock Networks
Figure 2–43. Regional Clocks
Fast Regional Clock Network
In EP1S25, EP1S20, and EP1S10 device s, ther e ar e two fast regional clock
networks, FCLK[1..0], within each quadrant, fed by input pins that can
connect to fast regional clock networks (see Figure 2–44). In EP1S30 and
larger devices, there are two fast regional clock networks within each
half-quadrant (see Figure 2–45). Dual-purpose FCLK pins drive the fast
clock networks. All devices have eight FCLK pins to drive fast r egional
clock networks. Any I/O pin can drive a clock or contro l signal onto any
fast regional clock network with the addition of a delay. This signal is
driven via the I/O interconnect. The fast regi onal clock networks can also
be driven from internal logic elements.
RCLK[1..0]
RCLK[4..5]
RCLK[6..7] RCLK[12..13]
RCLK[2..3] RCLK[11..10]
RCLK[14..15]
RCLK[9..8]
CLK[15..12]
CLK[3..0]
CLK[7..4]
CLK[11..8]
Regional Clocks Only Drive a Device
Quadrant from Specified CLK Pins or
PLLs within that Quadrant
Altera Corporation 2–77
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–44. EP1S25, EP1S20 & EP1S10 Device Fast Clock Pin Connections to
Fast Regional Clocks
Notes to Figure 2–44:
(1) This is a set of two multiplexers.
(2) In addition to the FCLK pin inputs, there is also an input f rom the I/O inter connect.
FCLK[1..0]
FCLK[1..0]
FCLK[1..0]
FCLK[1..0]
FCLK[1..0] FCLK[7..6]
FCLK[5..4]
FCLK[3..2]
22
22
22
22
(1), (2)
(1), (2)
(1), (2)
(1), (2)
2–78 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
PLLs & Clock Networks
Figure 2–45. EP1S30 Device Fast Regional Clock Pin Connections to Fast
Regional Clocks
Notes to Figure 2–45:
(1) This is a set of two multiplexers.
(2) In addition to the FCLK pin inputs, there is also an input f rom the I/O inter connect.
Combined Resources
Within each region, there are 22 distinct dedicated clocking resources
consisting of 16 global clock lines, four regional clock lines, and two fast
regional clock lines. Multiplexers are used with these clocks to form eight
bit busses to drive LAB row clocks, column IOE clocks, or row IOE clocks.
Another multiplexer is used at the LAB level to select two of the eight row
clocks to feed the LE registers within the LAB. See Figure 2–46.
fclk[1..0]
FCLK4FCLK5FCLK2FCLK3
FCLK6FCLK7FCLK0FCLK1
(1), (2)
(1), (2) (1), (2)
(1), (2)
(1), (2)
(1), (2) (1), (2)
(1), (2)
Altera Corporation 2–79
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–46. Regional Clock Bus
IOE clocks have horizontal and vertical bloc k r egions that are clocke d by
eight I/O clock signals chosen from the 22 quadrant or half-quadrant
clock resources. Figures 2–47 and 2–48 show the quadrant and half-
quadrant relationship to the I/O clock regions, respectively. The vertical
regions (column pins) have less clock delay than the horizontal regions
(row pins).
Clock [21..0]
Vertical I/O Cell
IO_CLK[7..0]
Lab Row Clock [7..0]
Horizontal I/O
Cell IO_CLK[7..0]
Global Clock Network [15..0]
Fast Regional Clock Network [1..0]
Regional Clock Network [3..0]
Clocks Available
to a Quadrant
or Half-Quadrant
2–80 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
PLLs & Clock Networks
Figure 2–47. EP1S10, EP1S20 & EP1S25 Device I/O Clock Groups
IO_CLKC[7..0]
IO_CLKF[7..0] IO_CLKE[7..0]
IO_CLKA[7..0] IO_CLKB[7..0]
IO_CLKD[7..0]
IO_CLKH[7..0]
IO_CLKG[7..0]
8
8
22 Clocks in
the Quadrant
22 Clocks in
the Quadrant
22 Clocks in
the Quadrant
22 Clocks in
the Quadrant
8
8
8
8
8 8
I/O Clock Region
s
Altera Corporation 2–81
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–48. EP1S30, EP1S40, EP1S60, EP1S80 Device I/O Clock Groups
You can use the Quartus II software to control whether a clock input pin
is either global, regional, or fast regional. The Quartus II software
automatically selects the cl ocki ng resources if not specified.
Enhanced & Fast PLLs
Stratix devices pr ovide robust clock management and synthesis using up
to four enhanced PLLs and eight fast PLLs. These PLLs increase
performance and provide advanced clock interfacing and clock-
frequency synthesis. With features suc h as c loc k swi t c ho ver, spread
spectrum cloc king, programmable bandwidth, phase and delay control,
and PLL reconfiguration, the Stratix device’s enhanced PLLs provide you
with complete control of your clocks and system timing. The fast PLLs
IO_CLKJ[7:0] IO_CLKI[7:0]
IO_CLKA[7:0] IO_CLKB[7:0]
8
22 Clocks in the
Half-Quadrant
22 Clocks in the
Half-Quadrant
22 Clocks in the
Half-Quadrant
22 Clocks in the
Half-Quadrant
22 Clocks in the
Half-Quadrant
22 Clocks in the
Half-Quadrant
22 Clocks in the
Half-Quadrant
22 Clocks in the
Half-Quadrant
8 8 8
I/O Clock Region
s
IO_CLKL[7:0] IO_CLKK[7:0]
IO_CLKC[7:0] IO_CLKD[7:0]
8888
8
8
8
8
8
8
8
8
IO_CLKE[7:0]
IO_CLKF[7:0]
IO_CLKG[7:0]
IO_CLKH[7:0]
IO_CLKN[7:0]
IO_CLKM[7:0]
IO_CLKP[7:0]
IO_CLKO[7:0]
2–82 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
PLLs & Clock Networks
provide general purpose clocking with multiplication and phase shifting
as well as high-speed outputs for high-speed differential I/O support.
Enhanced and fast PLLs work together with the Stratix high-speed I/O
and advanced clock architecture to pr ovide significant improvements in
system performance and bandwidth.
The Quartus II software enables the PLLs and their features without
requiring any external devices. Table 2–18 shows the PLLs available for
each Stratix devi ce.
Table 2–18. Stratix Device PLL Availability
Device Fast PLLs Enhanced PLLs
12347 8 9105(1) 6(1) 11(2) 12(2)
EP1S10 vvvv vv
EP1S20 vvvv vv
EP1S25 vvvv vv
EP1S30 vvvv
v (3) v (3) v (3) v (3) vv
EP1S40 vvvv
v (3) v (3) v (3) v (3) vvv(3) v(3)
EP1S60 vvvvvvvvvvvv
EP1S80 vvvvvvvvvvvv
Notes to Table 2–18:
(1) PLLs 5 and 6 each have eight single-ended outputs or four differential outputs.
(2) PLLs 11 and 12 each have one single-ended output.
(3) EP1S30 and EP1S40 devices do not support these PLLs in the 780-pin FineLine BGA® package.
Altera Corporation 2–83
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Table 2–19 shows the enhanced PLL and fast PLL features in Stratix
devices.
Table 2–19. Stratix PLL Features
Feature Enhanced PLL Fast PLL
Clock multiplication and division m/(n × post-scale counter) (1) m/(post-scale counter) (2)
Phase shift Down to 156.25-ps increments (3), (4) Down to 125-ps increments (3), (4)
Delay shift 250-ps increments for ±3 ns
Clock switchover v
PLL reconfiguration v
Programmable bandwidth v
Spread spectrum clocking v
Programmable duty cycle vv
Number of internal clock outputs 6 3 (5)
Number of ex ternal clock outputs Four differential/eight singled-ended
or one single-ended (6) (7)
Number of feedback clock inputs 2 (8)
Notes to Table 2–19:
(1) For enhanced PLLs, m, n, range from 1 to 512 and post-scale counters g, l, e range from 1 to 1024 with 50% duty
cycle. With a non-50% duty cycle the post-scale counters g, l, e range from 1 to 512.
(2) For fast PLLs, m and post-scale counters range from 1 to 32.
(3) The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8.
(4) For degree increments, Stratix devices can shift all output frequencies in incr ements of at least 45°. Smaller degree
increments are possibl e de p e ndi ng on the frequency and divide parameters.
(5) PLLs 7, 8, 9, and 10 have two output ports per PLL. PLLs 1, 2, 3, and 4 have three output por ts per PLL.
(6) Every Stratix device has two enhanced PLLs (PLLs 5 and 6) with either eight single-ended outputs or four
differential outputs each. Two additional enhanced PLLs (PLLs 11 and 12) in EP1S80, EP1S60, and EP1S40 devices
each have one single-e nded output. Devices in t he 780 pin FineLine BGA packages do not support PLLs 1 1 and 12.
(7) Fast PLLs can driv e to any I/O pin as an external c lock. For high-speed differential I/O pins, the device uses a data
channel to generate txclkout.
(8) Every Stratix device has two enhan ced PLLs with one single-ended or differential ex ternal feedback input per PLL.
2–84 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
PLLs & Clock Networks
Figure 2–49 shows a top-level diagram of the Stratix device and PLL
floorplan.
Figure 2–49. PLL Locations
FPLL7CLK FPLL10CL
K
FPLL9CLK
CLK[8..11]
FPLL8CLK
CLK[3..0]
7
1
2
8
10
4
3
9
115
126
CLK
[
7..4
]
CLK[15..12]
PLLs
Altera Corporation 2–85
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–50 shows the global and r egional clocking from the PLL outputs
and the CLK pins.
Figure 2–50. Global & Regional Clock Connections from Side Pins & Fast PLL Outputs Note (1), (2)
Notes to Figure 2–50:
(1) PLLs 1 to 4 and 7 to 10 are fast PLLs. PLLs 5, 6, 1 1, and 12 are enhanced PLLs.
(2) The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A pin or other PLL must drive
the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL.
Figure 2–51 shows the global and regional clocking from enhanced PLL
outputs and top CLK pins.
2
CLK0
CLK1
CLK2
CLK3
G0
FPLL7CLK
G1 G2 G3
RCLK0
RCLK1
RCLK4
RCLK5
G10
G11
G8
G9 RCLK9
RCLK8
RCLK15
RCLK14
Global
Clocks
Regional
Clocks
PLL 7 l0
l1
g0
PLL 1
PLL 2
FPLL8CLK
PLL 8
2
CLK10
CLK11
CLK8
CLK9
FPLL10CL
K
PLL 10
PLL 4
PLL 3
FPLL9CLK
PLL 9
Regional
Clocks
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
2–86 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
PLLs & Clock Networks
Figure 2–51. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs Note (1)
Notes to Figure 2–51:
(1) PLLs 1 to 4 and 7 to 10 are fast PLLs. PLLs 5, 6, 1 1, and 12 are enhanced PLLs.
(2) CLK4, CLK6, CLK12, and CLK14 feed the corresponding PLL’s inclk0 port.
(3) CLK5, CLK7, CLK13, and CLK15 feed the corresponding PLL’s inclk1 port.
(4) The EP1S40 device in the 780-pin FineLine BGA package does not support PLLs 11 and 12.
G12
G13
G14
G15
RCLK10
RCLK11
RCLK2
RCLK3
G7
G6
G5
G4
RCLK13
RCLK12
RCLK7
RCLK6
PLL 12
L0 L1 G0 G1 G2 G3
CLK7
CLK6
CLK5
CLK4
PLL 6
G0 G1 G2 G3 L0 L1
PLL 11
L0 L1 G0 G1 G2 G3
CLK13
CLK12
CLK14
CLK15
PLL 5
G0 G1 G2 G3 L0 L1
E[0..3]
PLL12_OUT
PLL6_OUT[3..0]
PLL11_OUT
PLL5_OUT[3..0]
PLL5_FB
PLL6_FB
Global
Clocks
Regional
Clocks
Regional
Clocks
(1)
(2)
(1)
(2)
(2)
(2)(1)
(1)
Altera Corporation 2–87
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Enhanced PLLs
Stratix devices contain up to four enhanced PLLs with advanced clock
management features. Figure 2–52 shows a diagram of the enhanced PLL.
Figure 2–52. Stratix Enhanced PLL
Notes to Figure 2–52:
(1) External feedback is available in PLLs 5 and 6.
(2) This single-ended external output is available from the g0 counter for PLLs 11 and 12.
(3) These four counters and external outputs are available in PLLs 5 and 6.
(4) This connection is only available on EP1S40 and larger Stratix devices. For example, PLLs 5 and 11 ar e adjacent and
PLLs 6 and 12 are adjacent. The EP1S40 device in the 780-pin FineLine BGA package does not support PLLs 11
and 12.
/n Charge
Pump VCO /g0
/g1
/g2
/e0
8
4
Global
Clocks
/e1
/e2
I/O Buffers (3)
/e3 Δt
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Lock Detect To I/O buffers or general
routing
INCLK0
INCLK1
FBIN
PFD
/g3
/l1
/l0
From Adjacent PLL
/m
Spread
Spectrum
I/O buffers (2)
(1)
Loop
Filter
& Filter
Programmable
Time Delay on
Each PLL Port
Post-Scale
Counters
Clock
Switch-Over
Circuitry Phase Frequency
Detector
VCO Phase Selection
Selectable at Each
PLL Output Port
VCO Phase Selection
Affecting All Outputs
Δt
Δt
Δt
Δt
Regional
Clocks
4
2–88 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
PLLs & Clock Networks
Clock Multiplication & Division
Each Stratix device enhanced PLL provides clock syn th esis for PLL
output ports using m/(n × post-scale counter) scaling factors. The input
clock is divided by a pre-scale divider, n, and is then multiplied by the m
feedback factor. The control loop drives the VCO to match fIN × (m/n).
Each output port has a unique post -sc a le counter that divides down the
high-frequency VCO. For multiple PLL outputs with different
frequencies, the VCO is set to the least common multiple of the output
frequencies that meets its frequency specifications . Then, the post-sca le
dividers scale down the output frequency for each output port. For
example, if output frequencies r equired fr om one PLL are 33 and 66 MHz,
set the VCO to 330 MHz (the least common multiple in the VCO’s range).
There is one pr e-scale counter, n, and one multiply counter, m, per PLL,
with a range of 1 to 512 on each. There are two post-scale counters (l) for
regional clock output ports, four counters (g) for global clock output
ports, and up to four counters (e) for external clock outputs, all ranging
from 1 to 1024 with a 50% duty cycle setting. The post-scale counte rs
range from 1 to 512 with any non-50% duty cycle setting. The Quartus II
software automatically chooses the appr opriate scaling factors according
to the input frequenc y, multiplication, and division values entered.
Clock Switchover
T o effectively develop high-reliability network systems, clocking schemes
must support multiple cloc ks to provide redundancy. For this reason,
Stratix device enhanced PLLs support a flexible clock switchover
capability. Figure 2–53 shows a block diagram of the switch over
circuit.The switchover circuit is configurable, so you can define how to
implement it. Clock-sense circuitry automatically switches from the
primary to secondary clock for PLL re ference when the primary clock
signal is not present.
Altera Corporation 2–89
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–53. Clock Switchover Circuitry
There are two possible ways to use the clock switchov er feature.
■Use automatic switchover circuitry for switching between inputs of
the same frequency. For example, in applications that require a
redundant clock with the same frequency as the primary clock, the
switchover state machine generates a signal that controls the
multiplexer select input on the bottom of Figure 2–53. In this case, the
secondary clock becomes the reference clock for the PLL.
■Use the clkswitch input for user- or system-controlled switch
conditions. This is possible for same-frequency switchover or to
switch between inputs of differ ent frequencies. For example, if
inclk0 is 66 MHz and inclk1 is 100 MHz, you must control the
switchover because the automatic clock-sense circuitry cannot
monitor primary and secondary clock frequencies with a frequency
difference of more than ±20%. This feature is useful when clock
sources can originate from multiple cards on the backplane,
requiring a system-controlled switchover between frequencies of
operation. You can use clkswitch together with the lock signal to
trigger the switch from a clock that is running but becomes unstable
and cannot be locked onto.
n
Counter
CLKLOSS
INCLK0
INCLK1
CLK1_BAD
CLK0_BAD
CLKSWITCH
PFD
FBCLK
Clock
Sense
SMCLKSW
Enhanced PLL
Active Clock
Switch-Over
State Machine
Δt
MUXOUT
2–90 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
PLLs & Clock Networks
During switchover, the PLL VCO continues to run and will either slow
down or speed up, generating frequency drift on the PLL outputs. The
clock switchover transitions without any glitches. After the switch, ther e
is a finite resynchronization period to lock onto new clock as the VCO
ramps up. The exact amount of time it takes for the PLL to relock re late s
to the PLL configuration and may be adjusted by using the
programmable bandwidth feature of the PL L. The specificatio n for the
maximum time to relock is 100 µs.
fFor more information on clock switchover, see AN 313, Implementing
Clock Switchover in Stratix & Stratix GX Devices.
PLL Reconfiguration
The PLL reconfiguration featur e enables system logic to change Stratix
device enhanced PLL counters and delay elements without reloading a
Programmer Object File (.pof). This pr ovides considerable flexibility for
frequency synthesis, allowing real-time PLL fr e quency and output clock
delay variation. You can sweep the PLL output frequencies and clock
delay in prototype environments. The PLL r econfiguration feature can
also dynamically or in telligently cont rol system clock speeds or tCO
delays in end systems.
Clock delay elements at each PLL output port implement variab le delay.
Figure 2–54 shows a diagram of the overa ll dynami c PL L control feature
for the counters and the clock delay elements. The configuration time is
less than 20 μs for the enhanced PLL using a input shift clock rate of
22 MHz. The charge pump, loop filter components, and phase shifting
using VCO phase taps ca nno t be dynamically adjusted.
Altera Corporation 2–91
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–54. Dynamically Programmable Counters & Delays in Stratix Device Enhanced PLLs
PLL reconfiguration data is shifted into serial re gisters from the logic
array or external devices. The PLL input shift data uses a r efer ence input
shift clock. Once the last bit of the serial chain is clocked in, the register
chain is synchronously loaded into the PLL configuration bits. The shift
circuitry also provides an asynchronous clear for the serial registers.
fFor more information on PLL reconfiguratio n, see AN 282: Implementing
PLL Reconfiguration in Stratix & Stratix GX Devices.
Programmable Bandwidth
You have advanced control of the PLL bandwidth using the
programmable control of the PLL loop characteristics, including loop
filter and char ge pump. The PLL’s bandwidth is a measure of its ability t o
track the input clock and jitter. A high-bandwidth PLL can quickly lock
onto a reference clock and react to any changes in the clock. It also wil l
allow a wide band of input jitter spectrum to pass to the output. A low-
bandwidth PLL will take longer to lock, but it will attenuate all high-
frequency jitter components. The Quartus II software can adjust PLL
characteristics to achieve the desired bandwidth. The programmable
÷n Δt
Δt÷m
÷gΔt
÷l Δt
÷eΔt
PFD VCO
Charge
Pump Loop
Filter
f
REF
scandata
scanclk
scanaclr
Counters and Clock
Delay Settings are
Programmable
All Output Counters and
Clock Delay Settings can
be Programmed Dynamically
2–92 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
PLLs & Clock Networks
bandwidth is tuned by varying the charge pump current, loop filter
resi stor value, hig h frequency capacito r valu e, and m co unter value . You
can manually adjust these values if desired. Bandwidth is pr ogrammable
from 200 kHz to 1.5 MHz.
External Clock Outputs
Enhanced PLLs 5 and 6 each support up to eight single-ended clock
outputs (or four differential pairs). Differential SSTL and HSTL outputs
are implemente d using 2 single-e nded output buffers which are
programmed to have opposite polarity. In Quartus II software, simply
assign the appropriate differential I/ O standard and the software will
implement the inversion. See Figure 2–55.
Altera Corporation 2–93
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–55. External Clock Outputs for PLLs 5 & 6
Notes to Figure 2–55:
(1) The design can use each external clock output pin as a general-purpose output pin from the logic array. These pins
are multiplexed with IOE outputs.
(2) Two single-ended outputs are possible per output counter⎯either two outputs of the same frequency and phase or
one shifted 180°.
(3) EP1S10, EP1S20, and EP1S25 devices in 672-pin BGA and 484- and 672-pin FineLine BGA packages only have two
pairs of external clocks (i.e., pll_out0p, pll_out0n, pll_out1p, and pll_out1n).
(4) Differential SSTL and HSTL outputs are implemented using two single-ended output buffers, which are
programmed to have opposite polarity.
e0 Counter
pll_out0p (3), (4
)
pll_out0n (3), (4
)
pll_out1p (3), (4
)
pll_out1n (3), (4
)
pll_out2p (3), (4
)
pll_out2n (3), (4
)
pll_out3p (3), (4
)
pll_out3n (3), (4
)
e1 Counter
e2 Counter
e3 Counter
From IOE (1), (2)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
4
(3)
2–94 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
PLLs & Clock Networks
Any of the four external output counters can drive the single-ended or
differential clock outputs for PLLs 5 and 6. This means one counter or
frequency can drive all output pins available from PLL 5 or PLL 6. Each
pair of output pins (four pins total) has dedicated VCC and GND pins to
reduce the output clock’s overall jitter by providing improved isolation
from switching I/O pins.
For PLLs 5 and 6, each pin of a single-ended output pair can either be in
phase or 180° out of phase. The clock output pin pairs support the same
I/O standards as standard output pins (in the top and bottom banks) as
well as LVDS, LVPECL, 3.3-V PCML, HyperTransport technology,
differential HSTL, and differ ential SSTL. Table 2–20 shows which I/O
standards the enhanced PLL clock pins support. When in single-ended or
differential mode, the two outputs operate off the same power supply.
Both outputs use the same standards in single-ended mode to maintain
performance. You can also use the external clock output pins as user
output pins if external enhanced PLL clocking is not needed.
Table 2–20. I/O Standards Supported for Enhanced PLL Pins (Part 1 of 2)
I/O Standard Input Output
INCLK FBIN PLLENABLE EXTCLK
LVTTL vv v v
LVCMOS vv v v
2.5 V vv v
1.8 V vv v
1.5 V vv v
3.3-V PCI vv v
3.3-V PCI-X 1.0 vv v
LVPECL vv v
3.3-V PCML vv v
LVDS vv v
HyperTransport technology vv v
Differential HSTL vv
Differential SSTL v
3.3-V GTL vv v
3.3-V GTL+ vv v
1.5-V HSTL Class I vv v
Altera Corporation 2–95
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Enhanced PLLs 11 and 12 support one single-ended output each (see
Figure 2–56). These outputs do not have their own VCC and GND sig nal s.
Therefor e, to minimi ze jitter, do not place switching I/O pins next to this
output pin.
Figure 2–56. External Clock Outputs for Enhanced PLLs 11 & 12
Note to Figure 2–56:
(1) For PLL 1 1 , this pin is CLK13n; for PLL 12 this pin is CLK7n.
Stratix devices can drive any enhanced PLL dri ven through the global
clock or regional clock network to any general I/O pin as an external
output clock. The jitter on the output clock is not guaranteed for these
cases.
1.5-V HSTL Class II vv v
1.8-V HSTL Class I vv v
1.8-V HSTL Class II vv v
SSTL-18 Class I vv v
SSTL-18 Class II vv v
SSTL-2 Class I vv v
SSTL-2 Class II vv v
SSTL-3 Class I vv v
SSTL-3 Class II vv v
AGP (1× and 2×)vv v
CTT vv v
Table 2–20. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2)
I/O Standard Input Output
INCLK FBIN PLLENABLE EXTCLK
CLK13n, I/O, PLL11_OUT
or CLK6n, I/O, PLL12_OUT
(1
)
From Internal
Logic or IOE
g
0
Counter
2–96 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
PLLs & Clock Networks
Clock Feedback
The following four feedback modes in Stratix device enhanced PLLs
allow multiplication and/or phase and delay shifting:
■Zero delay buffer: The external clock output pin is phase-aligned
with the clock input pin for zer o delay. Altera recommends using the
same I/O standard on the input clock and the output clocks for
optimum performance.
■External feedback: The external feedback input pin, FBIN, is phase-
aligned with the clock input, CLK, pin. Aligning these clocks allows
you to remove clock delay and skew between devices. This mode is
only possible for PLLs 5 and 6. PLLs 5 and 6 each support feedback
for one of the dedicated external ou tputs, either one single-ended or
one differential pair . In this mode, one e counter feeds back to the PLL
FBIN input, becoming part of the feedback loop. Altera recommends
using the same I/O standard on the input clock, the FBIN pin, and
the output clocks for optimum performance.
■Normal mode: If an inter n al cl ock is used in this mode, it is phase-
aligned to the input clock pin. The external clock output pin will
have a phase delay relative to the clock input pin if connected in this
mode. You define which internal clock output from the PLL should
be phase-aligned to the internal cloc k pin.
■No compensation: In this mode, the PLL will not compensate for any
clock networks or external clock outputs.
Phase & Delay Shifting
Stratix device enhanced PLLs provide advanced programmable phase
and clock delay shifting. These parameters are set in the Quartus II
software.
Phase Delay
The Quartus II software automatically sets the phase taps and counter
settings according to the phase shift entry. You enter a desired phase shift
and the Quartus II software automatically sets the closest setting
achievable. This type of phase shift is not reconfigurable during syste m
operation. For phase shifting, enter a phase shift (in degrees or time units)
for each PLL clock output port or for all outputs together in one shift. Y ou
can select phase-shifting values in time units with a resolution of 156.25
to 416.66 ps. This resolution is a function of fr e quency input and the
multiplication and division factors (that is, it is a functio n of the VCO
period), with the finest step being equal to an eighth (×0.12 5) of the VCO
period. Each clock output counter can choose a different phase of th e
Altera Corporation 2–97
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
VCO period from up to eight taps for individual fine step selection. Also,
each clock output counter can use a unique initial count setting to achieve
individual coarse sh ift se le cti o n in st e ps of one VCO period. The
combination of coarse and fine shifts allows phase shifting for the entire
input clock period.
The equation to determine the precision of the phase shifting in degrees
is: 45°÷post-scale counter val ue . Therefore, the maximum step size is
45°, and smaller steps are possible depending on the mul tiplication and
division ratio necessary on the output counter port.
This type of phase shift provides the highest precision since it is the least
sensitive to process, supply, and temperature variation.
Clock Delay
In addition to the phase shift feature, the ability to fine tune the Δt clock
delay provides advanced time delay shift control on each of the four PLL
outputs. There ar e time dela ys for each post-scale c ounter (e, g, or l) fr om
the PLL, the n counter, and m counter. Each of these can shift in 250-ps
increments for a range of 3.0 ns. The m delay shifts all outputs earlier in
time, while n delay shifts all outputs later in time. Indi vidual delays on
post-scale counters (e, g, and l) provide positiv e delay for each output.
Table 2–21 shows the combined delay for each output for normal or zero
delay buffer mode where Δte, Δtg, or Δtl is unique for ea ch PL L output.
The tOUTPUT for a single output can range from –3 ns to +6 ns. The total
delay shift difference between any two PLL outputs, however, must be
less than ±3 ns. For example, shifts on two outputs of –1 and +2 ns is
allowed, but not –1 and +2.5 ns because these shifts would result in a
differ ence of 3.5 ns. If the design uses external feedback, the Δte delay will
remove delay from outputs, represente d by a negative sign (see
Table 2–21). This effect occurs because the Δte delay is then part of the
feedback loop.
Table 2–21. Output Clock Delay for Enhanced PLLs
Normal or Zero Delay Buffer Mode External Feedback Mode
ΔteOUTPUT = Δtn − Δtm + Δte
ΔtgOUTPUT = Δtn − Δtm + Δtg
ΔtlOUTPUT = Δtn − Δtm + Δtl
ΔteOUTPUT = Δtn − Δtm − Δte (1)
ΔtgOUTPUT = Δtn − Δtm + Δtg
ΔtlOUTPUT = Δtn − Δtm + Δtl
Note to Table 2–21:
(1) Δte removes delay from o utputs in externa l feedback mode .
2–98 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
PLLs & Clock Networks
The variation due to process, voltage, and temperature is about ±15% on
the delay settings. PLL reconfiguration can control the clock delay shift
elements, but not the VCO phase shift multiplexers, during system
operation.
Spread-Spectrum Clocking
Stratix device enhanced PLLs use spread-spectrum technology to reduce
electromagnetic interference generation from a system by distributing the
energy over a broader frequency range. The enhanced PLL typically
provides 0.5% down spread modulation using a triangular profile. The
modulation frequency is programmable. Enabling spread-spectrum for a
PLL affects all of its outputs.
Lock Detect
The lock output indicates that there is a stable clock output signal in
phase with the refer ence clock. Without any additional cir cuitry, the lock
signal may toggle as the PLL begins tracking the refer ence clock. Y ou may
need to gate the lock signal for use as a system control. The lock signal
from the locked port can drive the logic array or an output pin.
Whenever the PLL loses lock (for example, inclk jitter , clock switchover ,
PLL reconfiguration, power su pply noise, and so on), the PLL must be
reset with the areset signal to guarantee corre ct phase relationship
between the PLL output clocks. If the phase relationship between the
input clock versus output clock, and between different output clocks
from the PLL is not important in the design, then the PLL need not be
reset.
fSee the Stratix FPGA Errata Sheet for more informatio n on implementi ng
the gated lock signal in a design.
Programmable Duty Cycle
The programmable duty cycle allows enhanced PLLs to generate clock
outputs with a variable duty cycle. This feature is supported on each
enhanced PLL post-scale counter (g0..g3, l0..l3, e0..e3). The duty cycle
setting is achieved by a low and high time count setting for the post-scale
dividers. The Quartus II software uses the frequency input and the
required multiply or divide rate to determine the duty cycle choices.
Advanced Clear & Enable Control
There ar e several control signals for clearing and enabling PLLs and their
outputs. You can use these signals to control PL L resynchronization and
gate PLL output clocks for low-power applications.
Altera Corporation 2–99
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
The pllenable pin is a dedicated pin that enables/disables PLLs. When
the pllenable pin is low, the clock output ports are driven by GND and
all the PLLs go out of lock. When the pllenable pin goes high again, the
PLLs relock and r esynchronize to the input clocks. You can choose which
PLLs are controlled by the pllenable signal by connecting the
pllenable input port of the altpll megafunction to the common
pllenable input pin.
The areset signals are reset/resynchronization inputs for each PLL. The
areset signal should be asserted every time the PLL loses lock to
guarantee correct phase relationship b etween the PLL output clocks.
Users should include the areset signal in designs if any of the following
conditions are true:
■PLL Reconfiguration or Clock switchover enables in the design.
■Phase relationships betwee n output clocks need to be maintained
after a loss of lock condition
The device input pins or logic elements (LEs) can drive these input
signals. When driven high, the PL L cou n ters will reset , cl earing the PLL
output and placing the PLL out of lock. The VCO will set back to its
nominal setting (~700 MHz). When driven low again, the PLL will
resynchronize to its input as it relocks. If the targ et VCO frequency is
below this nominal frequency, then the output frequency will start at a
higher value than desired as the PLL locks. If the system cannot tolerate
this, the clkena signal ca n disable the outp ut clocks until the PLL locks.
The pfdena signals control the phase frequency detector (PFD) output
with a programmable gate. If you disabl e the PFD, the VCO operates at
its last set value of control voltage and frequency with some long-term
drift to a lower frequency. The system continues runni ng when the PLL
goes out of lock or the input clock is disabled. By maintaining the last
locked frequency, the system has time to store its current settings before
shutting down. You can either use your own control signal or a clkloss
status signal to trigger pfdena.
The clkena signals control the enhanced PLL re gional and global
outputs. Each regional and global output port has its own clkena signal.
The clkena signals synchronously disable or enable the clock at the PLL
output port by gating the outputs of the g and l counters. The clkena
signals are r egistered on the falling edge of the counter output clock to
enable or disable the clock without glitches. Figure 2–57 shows the
waveform example for a PLL clock port enable. The PLL can remain
locked independent of the clkena signals since the loop-related counters
are not affected. This feature is useful for applications that require a low
power or sleep mode. Upon re-enabling, the PLL doe s not need a
2–100 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
PLLs & Clock Networks
resynchronization or relo ck p eriod. Th e clkena signal can also disable
clock outputs if the system is not tolerant to fr eq uency oversho ot during
resynchronization.
The extclkena signals work in the same way as the clkena signals, but
they control the external clock output counters (e0, e1, e2, and e3). Upon
re-enabling, the PLL does not need a resynchronization or relock period
unless the PLL is using external feedback mode. In order to lock in
external feedback mode, the external output must drive the board trace
back to the FBIN pin.
Figure 2–57. extclkena Signals
Fast PLLs
Stratix devices contain up to eight fast PLLs with high-speed serial
interfacing ability, along with general-purpose features. Figure 2–58
shows a diagram of the fast PLL.
COUNTER
OUTPUT
CLKENA
CLKOUT
Altera Corporation 2–101
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–58. Stratix Device Fast PLL
Notes to Figure 2–58:
(1) The global or regional clock input can be driven by an output from another PLL or any dedicated CLK or FCLK pin.
It cannot be driven by internally-generated global signals.
(2) In high-speed differential I/O support mode, this high-s peed PLL clock feeds the SERDES. Stratix devices only
support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
(3) This signal is a high-speed differ ential I/O support SERDES control signal.
Clock Multiplication & Division
Stratix device fast PLLs pr ovide clock synthesis for PL L ou tput ports
using m/(post scale r) scaling factors. The input clock is multiplied by the
m feedback factor. Each output port has a unique post scale counter to
divide down the high-frequency VCO. There is one mult iply divider, m,
per fast PLL with a range of 1 to 32. There are two post scale L dividers
for regional and/or LVDS interface clocks, and g0 counter for global clock
output port; all range from 1 to 32.
In the case of a high-speed dif ferential interface, set the output counter to
1 to allow the high-speed VCO frequency to drive the SERDES. When
used for clocking the SERDES, the m counter can range from 1 to 30. T he
VCO frequency is equal to fIN×m, where VCO frequency must be between
300 and 1000 MHz.
Charge
Pump VCO ÷g0
8
Clock
Input PFD
÷l1
÷l0
÷m
Loop
Filter
Phase
Frequency
Detector
VCO Phase Selection
Selectable at each PLL
Output Port
Post-Scale
Counters
Global or
regional cloc
k
Global or
regional cloc
k
Global or
regional cloc
k
diffioclk2 (2)
diffioclk1 (2)
txload_en (3)
rxload_en (3)
Global or
regional clock
(1)
2–102 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
PLLs & Clock Networks
External Clock Inputs
Each fast PLL supports single-ended or differential inputs for source
synchronous transmit ters or fo r general-purpose use. Source-
synchronous receivers support differential clock inputs. The fast PLL
inputs are fed by CLK[0..3], CLK[8..11], and FPLL[7..10]CLK
pins, as shown in Figure 2–50 on page 2–85.
Table 2–22 shows the I/O standards supported by fast PLL input pins.
Table 2–22. Fast PLL Port I/O Standards (Part 1 of 2)
I/O Standard Input
INCLK PLLENABLE
LVTTL vv
LVCMOS vv
2.5 V v
1.8 V v
1.5 V v
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL v
3.3-V PCML v
LVDS v
HyperTransport technology v
Differential HSTL v
Differential SSTL
3.3-V GTL
3.3-V GTL+ v
1.5-V HSTL Class I v
1.5-V HSTL Class II
1.8-V HSTL Class I v
1.8-V HSTL Class II
SSTL-18 Class I v
SSTL-18 Class II
SSTL-2 Class I v
Altera Corporation 2–103
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Table 2–23 shows the performance on each of the fast PLL clock inputs
when using LVDS, L V PECL, 3.3-V PCML, or HyperTransport technology.
External Clock Outputs
Each fast PLL supports differential or single-ended outputs for source-
synchronous transmitters or for general-purpose external clocks. Ther e
are no dedicated external clock outp ut pins. Any I/O pin can be driven
by the fast PLL global or regional outputs as an external output pin. The
I/O standard s su pported by any particular bank determines what
standards ar e possible for an external clock output driven by the fast PLL
in that bank.
Phase Shifting
Stratix device fa st PLLs have advance d clock shift capability that enables
programmable phase shifts. You can enter a phase shift (in degrees or
time units) for each PLL clock output port or for all outputs together in
one shift. You can perform phase shifting in time units with a resolution
range of 125 to 416.66 ps. This resolut ion is a function of the VCO period,
with the finest step being equal to an eighth (×0.125) of the VCO period.
SSTL-2 Class II v
SSTL-3 Class I v
SSTL-3 Class II v
AGP (1× and 2×)
CTT v
Table 2–23. LVDS Performance on Fast PLL Input
Fast PLL Clock Input Maximum Input Frequency (MHz)
CLK0, CLK2, CLK9, CLK11,
FPLL7CLK, FPLL8CLK, FPLL9CLK,
FPLL10CLK
717(1)
CLK1, CLK3, CLK8, CLK10 645
Note to Table 2–23:
(1) See the chapter DC & Switching Characteristics of the Stratix Device Ha ndbook,
Volume 1 for more information.
Table 2–22. Fast PLL Port I/O Standards (Part 2 of 2)
I/O Standard Input
INCLK PLLENABLE
2–104 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
I/O Structure
Control Signals
The fast PLL has the same lock output, pllenable input, and areset
input control signals as the enhanced PLL.
If the input clock stops and causes the PLL to lose lock, then the PLL must
be reset for correct phase shift operation.
For more information on high-spe ed dif fer ential I/O suppo rt, see “High-
Speed Diffe rential I/O Support” on page 2–130.
I/O Structure IOEs provide many features, including:
■Dedicated differential and single-ended I/O buffers
■3.3-V, 64-bit, 66-MHz PCI compliance
■3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
■Joint Test Action Group (JTAG) boundary-scan test (BST) support
■Differential on-chip termination for LVDS I/O standard
■Programmable pull-up during configuration
■Output drive strength co ntrol
■Slew-rate control
■Tri-state buffers
■Bus-hold circuitry
■Programma ble pu ll-up resis tors
■Programmable input and output delays
■Open-drain outputs
■DQ and DQS I/O pins
■Double-data rate (DDR) Registers
The IOE in Stratix devices contains a bidirect ional I/O buffer, six
registers, and a latch for a complete embedded bidirectional single data
rate or DDR transfer. Figure 2–59 shows the Stratix IOE structure. The
IOE contains two input registe rs (pl us a latch), two out put registers, and
two output enable registers. The design can use both input registers and
the latch to capture DDR input and both output registers to drive DDR
outputs. Additionally, the design can use the output enable (OE) register
for fast clock-to-output enable timing. The negative edge-clocked OE
register is used for DDR SDRAM interfacing . The Quartus II software
automatically duplicates a single OE register that controls multiple
output or bidirectional pins.
Altera Corporation 2–105
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–59. Stratix IOE Structure
The IOEs are located in I/O blocks around the periphery of the Stratix
device. There are up to four IOEs per row I/O block and six IOEs per
column I/O block. The row I/O blocks drive row, column, or direct link
interconnects. The column I/O blocks drive column interconnects.
Figure 2–60 shows how a row I/O block connects to the logic array.
Figure 2–61 shows ho w a column I/O block connects to the logi c array.
DQ
Output Register
Output A
DQ
Output Register
Output B
Input A
Input B
DQ
OE Register
OE
DQ
OE Register
DQ
Input Register
DQ
Input Register
DQ
Input Latch
Logic Array
CLK
ENA
2–106 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
I/O Structure
Figure 2–60. Row I/O Block Connection to the Interconnect
Notes to Figure 2–60:
(1) The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0],
four clocks io_clk[3..0], and four clear signal s io_bclr[3..0].
(2) The 28 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_coe[3..0], four input cloc k enab les
io_cce_in[3..0], four output clock enables io_cce_out[3..0], four clocks io_cclk[3..0], and four clear
signals io_cclr[3..0].
16
28
R4, R8 & R24
Interconnects C4, C8 & C16
Interconnects
I/O Block Local
Interconnect
16 Control Signals
from I/O Interconnect (1)
I/O Interconnect
28 Data & Control
Signals from
Logic Array (2)
io_dataouta[3..0]
io_dataoutb[3..0]
io_clk[7:0]
Horizontal I/O
Block Contains
up to Four IOEs
Direct Link
Interconnect
to Adjacent LAB
Direct Link
Interconnect
to Adjacent LAB
LAB Local
Interconnect
LAB Horizontal
I/O Block
Altera Corporation 2–107
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–61. Column I/O Block Connection to the Interconnect
Notes to Figure 2–61:
(1) The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0],
four clocks io_bclk[3..0], and four clear signals io_bclr[3..0].
(2) The 42 data and control signals consist of 12 data out lines; six lines each for DDR applications
io_dataouta[5..0] and io_dataoutb[5..0], six output enables io_coe[5..0], six input clock enables
io_cce_in[5..0], six output clock enables io_cce_out[5..0], six clocks io_cclk[5..0], and six clear
signals io_cclr[5..0].
16 Control
Signals from I/O
Interconnect (1)
42 Data &
Control Signals
from Logic Array (2) Vertical I/O
Block Contains
up to Six IOEs
I/O Block
Local Interconnect
I/O Interconnec
t
IO_datain[3:0]
R4, R8 & R24
Interconnects
LAB Local
Interconnect
C4, C8 & C16
Interconnects
16 42
LAB LAB LAB
io_clk[7..0]
Vertical I/O Block
2–108 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
I/O Structure
Stratix devices have an I/O interconnect similar to the R4 and C4
interconnect to drive high-fanout signal s to a n d from the I/O blocks .
There are 16 signals that drive into the I/O blocks composed of f our
output enables io_boe[3..0], four clock enables io_bce[3..0], four
clocks io_bclk[3..0], and four clear signals io_bclr[3..0]. The
pin’s datain signa ls can drive the IO inte r connect, which in turn driv es
the logic array or other I/O blocks. In addition, the control and data
signals can be driven from the logic array, providing a slower but more
flexible routing resource. The row or column IOE clocks, io_clk[7..0],
provide a dedicated routing resource for low-skew, high-speed clocks.
I/O clocks are generated from regional, global, or fast regional clocks (see
“PLLs & Clock Networks” on page 2–73). Figure 2–62 illustrates the
signal paths through the I/O block.
Figure 2–62. Signal Path through the I/O Block
Row or Column
io_clk[7..0]
io_boe[3..0]
io_bce[3..0]
io_bclk[3..0]
io_bclr[3..0]
io_datain0
io_datain1
io_dataout0
io_dataout1
io_coe
oe
ce_in
ce_out
io_cce_in aclr/apreset
io_cce_out sclr/spreset
io_cclr clk_in
io_cclk clk_out
Control
Signal
Selection
IOE
From I/O
Interconnect
To Logic
Array
From Logic
Array
To Other
IOEs
Altera Corporation 2–109
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset,
clk_in, and clk_out. Figure 2–63 illustrate s the control signal
selection.
Figure 2–63. Control Signal Selection per IOE
In normal bidirectional operation, the input register can be used for input
data requiring fast setup times. The input registe r can have its own cl ock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. The OE register can be used f or fast clock-to-output enable
timing. The OE and output registe r share the same clock source and the
same clock enable source from local interconnect in the associated LAB,
dedicated I/O clocks, and the column and r ow interconnects. Figure 2–64
shows the IOE in bidi rectional configuration.
clk_out
ce_inclk_in
ce_out
aclr/preset
sclr/preset
I/O Interconnect
[15..0]
Dedicated I/O
Clock [7..0]
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
oe
io_coe
io_cclr
io_cce_out
io_cce_in
io_cclk
io_bclk[3..0] io_bce[3..0] io_bclr[3..0] io_boe[3..0]
2–110 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
I/O Structure
Figure 2–64. Stratix IOE in Bidirectional I/O Configuration Note (1)
Note to Figure 2–64:
(1) All input signals to the IOE can be inverted at the IOE.
The Stratix device IOE includes programmable delays that can be
activated to ensure zero hold times, input IOE register-to-logic array
register transfers, or logic array-to-output IOE register transfers.
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not r equire the delay. Programmable
delays exist for decreas ing input -pin-to-logic-array and IOE input
register delays. The Quartus II Compiler can program these delays to
automatically minimize setup time while providing a zero hold time.
Programmable delays can increase the register-to-pin delays for output
CLRN/PRN
DQ
ENA
Chip-Wide Reset
OE Register
CLRN/PRN
DQ
ENA
Output Register
V
CCIO
V
CCIO
Optional
PCI Clamp
Programmable
Pull-Up
Resistor
Column or Row
Interconnect
I/O Interconnect
[15..0]
ioe_clk[7..0]
Bus-Hold
Circuit
Output
Enable Clock
Enable Delay
Output Clock
Enable Delay
Logic Array
to Output
Register Delay
Output
t
ZX
Delay
OE Register
t
CO
Delay
CLRN/PRN
DQ
ENA
Input Register
Input Clock
Enable Delay
Input Pin to
Input Register Delay
Input Pin to
Logic Array Delay
Drive Strength Control
Open-Drain Output
Slew Control
sclr/preset
OE
clkout
ce_out
aclr/prn
clkin
ce_in
Output
Pin Delay
Altera Corporation 2–111
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
and/or output enable registers. A pro grammable delay exists to increase
the tZX delay to the output pin, which is required for ZBT interfaces.
Table 2–24 shows the programmable delays for Stratix devices.
The IOE registers in Stratix devices share the same source for clear or
preset. You can program preset or clear for each individu al IOE. You can
also program the r egisters to power up high or low after configuration is
complete. If programmed to power up low, an asynchronous clear can
control the registers. If programmed to power up high, an asynchronous
preset can control the registers. This feature prevents the inadvertent
activation of another device’s active-low input upon power-up. If one
register in an IOE uses a pr eset or clear signal then a ll registers in the IOE
must use that same signal if they require pre set or clear. Additionally a
synchronous reset signal is available for the IOE registers.
Double-Data Rate I/O Pins
Stratix devices have six registers in the IOE, which support DDR
interfacing by clocking data on both positive and negative clock edges.
The IOEs in Stratix devi ces support DDR inputs, DDR outputs, and
bidir ectional DDR modes.
When using the IOE for D DR inputs, the two input r egisters clock double
rate input data on alternating edges. An input latch is also used within the
IOE for DDR input acquisition. The latch holds the data that is present
during the clock high times. This allows both bits of data to be
synchronous with the same clock edge (either rising or falling).
Figure 2–65 shows an IOE confi gured for DDR input. Figure 2–66 shows
the DDR input timing diagram.
Table 2–24. Stratix Programmable Delay Chain
Programmable Delays Quartus II Logic Option
Input pin to logic array delay Decrease input delay to internal cells
Input pin to input register delay Decrease input delay to input register
Output pin delay Increase delay to output pin
Output enable register tCO delay Increase delay to output enable pin
Output tZX delay Increase tZX delay to output pin
Output clock enable delay Increase output clock enable delay
Input clock enable delay Increase input clock enable delay
Logic array to output register delay Decrease input delay to output register
Output enable clock enable delay Increase output enable clock enable delay
2–112 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
I/O Structure
Figure 2–65. Stratix IOE in DDR Input I/O Configuration Note (1)
Notes to Figure 2–65:
(1) All input signals to the IOE can be inverted at the IOE.
(2) This signal connection is only allowed on dedicated DQ function pins.
(3) This signal is for dedicated DQS function pins only.
CLRN/PRN
DQ
ENA
Chip-Wide Reset
Input Register
CLRN/PRN
DQ
ENA
Input Register
VCCIO
VCCIO
Optional
PCI Clamp
Programmable
Pull-Up
Resistor
Column or Row
Interconnect
I/O Interconnect
[15..0] DQS Local
Bus
(1), (2)
To DQS Local
Bus
(3)
ioe_clk[7..0]
Bus-Hold
Circuit
Output Clock
Enable Delay
CLRN/PRN
DQ
ENA
Latch
Input Pin to
Input Register Delay
sclr
clkin
aclr/prn
(1)
(1)
Altera Corporation 2–113
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–66. Input Timing Diagram in DDR Mode
When using the IOE for DDR outputs, the two output r e gisters are
configured to clock two data paths fr om LEs on rising clock edges. These
output registers ar e multiplexed by the clo ck to drive the output pin at a
×2 rate. One output r egister clocks the first bit out on the clock high t ime,
while the other output register clocks the second bit out on the clock low
time. Figure 2–67 shows the IOE configured for DDR output. Figure 2–68
shows the DDR output timing diagram.
Data at
input pin
A'
B'
CLK
A0 B1 A1
A1
B2 A2 A3
A2 A3
B1 B2 B3
B3 B4
Input To
Logic Array
2–114 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
I/O Structure
Figure 2–67. Stratix IOE in DDR Output I/O Configuration Notes (1), (2)
Notes to Figure 2–67:
(1) All input signals to the IOE can be inverted at the IOE.
(2) The tristate is by default active high. It can, however, be designed to be active low.
CLRN/PRN
DQ
ENA
Chip-Wide Reset
OE Register
CLRN/PRN
DQ
ENA
OE Register
CLRN/PRN
DQ
ENA
Output Register
V
CCIO
V
CCIO
Optional
PCI Clamp
Programmabl
e
Pull-Up
Resistor
Column or Row
Interconnect
I/O Interconnect
[15..0]
IOE_CLK[7..0]
Bus-Hold
Circuit
Logic Array
to Output
Register Delay
Output
t
ZX
Delay
OE Register
t
CO
Delay
CLRN/PRN
DQ
ENA
Output Register
Logic Array
to Output
Register Delay
Drive Strength Control
Open-Drain Output
Slew Control
Used for
DDR SDRAM
clk
sclr
aclr/prn
clkout
Output
Pin Delay
Output
Enable Clock
Enable Delay
Output Clock
Enable Delay
Altera Corporation 2–115
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–68. Output Timing Diagram in DDR Mode
The Stratix IOE operates in bidirectional DDR mode by combining the
DDR input and DDR output configurations. Stratix device I/ O pins
transfer data on a DDR bidirectional bus to support DDR SDRAM. The
negative-edge-clocked OE register holds the OE signal inactive until the
falling edge of the clock. This is done to meet DDR SDRAM timing
requirements.
External RAM Interfacing
Stratix devices support DDR SDRAM at up to 200 MHz (400-Mbps data
rate) through dedicated phase-shift circuitry, QDR and QDRII SRAM
interfaces up to 167 MHz, and ZBT SRAM interfaces up to 200 MHz.
Stratix devices also provide preliminary support for reduced latency
DRAM II (RLDRAM II) at rates up to 200 MHz through the dedicated
phase-shift circuitry.
1In addition to the r equ ired signals for external memory
interfacing, Stratix devices offer the optional clock enable signal.
By default the Quartus II software sets the clock enable signal
high, which tells the output r egi ster to update with new values.
The output regist ers hold their own values if the design sets the
clock enable signal low. See Figure 2–64.
fTo find out more about the DDR SDRAM specification, see the JEDEC
web site (www.jedec.org). For information on memory controller
megafunctions for Stratix devices, see the Altera web site
(www.altera.com). See AN 342: Interfacing DDR SDRAM with Stratix &
Stratix GX Devices for more information on DDR SDRAM interface in
Stratix. Also see AN 349: QDR SRAM Controller Reference Design for
Stratix & Stratix GX Devices and AN 329: ZBT SRAM Controller Reference
Design for Stratix & Stratix GX Devices.
From Internal
Registers
DDR output
CLK
A
B
B1 A1 B2 A2 B3 A3
A2A1 A3 A4
B1 B2 B3 B4
2–116 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
I/O Structure
Tables 2–25 and 2–26 show the performance specification for DDR
SDRAM, RLDRAM II, QDR SRAM, QDRII SRAM, and ZBT SRAM
interfaces in EP1S10 through EP1S40 devices and in EP1S60 and EP1S80
devices. The DDR SDRAM and QDR S RAM numbers in Table 2–25 have
been verified with hardware characterization with third-party DDR
SDRAM and QDR SRAM devices over temperature and voltage
extremes.
Table 2–25. External RAM Support in EP1S10 through EP1S40 Devices
DDR Memor y Type I/O
Standard
Maximum Clock Rate (MHz)
-5 Speed
Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Flip-Chip Flip-Chip Wire-
Bond Flip-
Chip Wire-
Bond Flip-
Chip Wire-
Bond
DDR SDRAM (1), (2) SSTL-2 200 167 133 133 100 100 100
DDR SDRAM - side
banks (2), (3), (4) SSTL-2 150 133 110 133 100 100 100
RLDRAM II (4) 1.8-V HSTL 200 (5) (5) (5) (5) (5) (5)
QDR SRAM (6) 1.5-V HSTL 167 167 133 133 100 100 100
QDRII SRAM (6) 1.5-V HSTL 200 167 133 133 100 100 100
ZBT SRAM (7) LVTTL 200 200 200 167 167 133 133
Notes to Table 2–25:
(1) These maximum clock rates apply if the Stratix device uses DQS phase-shift circuitry to interface with DDR
SDRAM. DQS phase-shift circuitry is only available in the top and bottom I/O banks (I/O banks 3, 4, 7, and 8).
(2) For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices.
(3) DDR SDRAM is supported on the Stratix device side I/O banks (I/O banks 1, 2, 5, and 6) without dedicated DQS
phase-shift circuitry. The read DQS signal is ignored in this mode.
(4) These performance specifications are preliminary.
(5) This device does not support RLDRAM II.
(6) For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Reference Desi gn fo r St ra ti x &
Stratix GX Devices.
(7) For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX
Devices.
Altera Corporation 2–117
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
In addition to six I/O registers and one input latch in the IOE for
interfacing to these high-spee d memory interfaces, Stratix de vi ces also
have dedicated circuitry for interfacing with DDR SDRAM. In every
Stratix device, the I/O banks at the top (I/O banks 3 and 4) and bottom
(I/O banks 7 and 8) of the device support DDR SDRAM up to 200 MHz.
These pins support DQS signals with DQ bu s modes of ×8, ×16, or ×32.
Table 2–27 shows the number of DQ and DQS buses that are supported
per device.
Table 2–26. External RAM Support in EP1S60 & EP1S80 Devices
DDR Memory T y pe I/O Standard Maximum Clock Rate (MHz)
-5 Speed Grade -6 Speed Grade -7 Speed Grade
DDR SDRAM (1), (2) SSTL-2 167 167 133
DDR SDRAM - side banks (2), (3) SSTL-2 150 133 133
QDR SRAM (4) 1.5-V HSTL 133 133 133
QDRII SRAM (4) 1.5-V HSTL 167 167 133
ZBT SRAM (5) LVTTL 200 200 167
Notes to Table 2–26:
(1) These maximum clock rates apply if the Stratix device uses DQS phase-shift circuitry to interface with DDR
SDRAM. DQS phase-shift circuitry is only available in the top and bottom I/O banks (I/O banks 3, 4, 7, and 8).
(2) For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices.
(3) DDR SDRAM is supported on the Stratix device side I/O banks (I/O banks 1, 2, 5, and 6) without dedicated DQS
phase-shift circuitry. The read DQS signal is ignored in this mode. Numbers are preliminary.
(4) For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Reference Desi gn fo r St ra ti x &
Stratix GX Devices.
(5) For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX
Devices.
Table 2–27. DQS & DQ Bus Mode Support (Part 1 of 2) Note (1)
Device Package Number of ×8
Groups Number of ×16
Groups Number of ×32
Groups
EP1S10 672-pin BGA
672-pin FineLine BGA 12 (2) 00
484-pin FineLine BGA
780-pin FineLine BGA 16 (3) 04
EP1S20 484-pin FineLine BGA 18(4) 7 (5) 4
672-pin BGA
672-pin FineLine BGA 16(3) 7 (5) 4
780-pin FineLine BGA 20 7 (5) 4
2–118 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
I/O Structure
A compensated delay element on each DQS pin automatically aligns
input DQS synchronization signals with the data window of their
corresponding DQ data signals. The DQS signals drive a local DQS bus in
the top and bottom I/O banks. This DQS bus is an additional resource to
the I/O clocks and is used to clock DQ input register s with the DQS
signal.
Two separate single phase-shifting reference circuits are located on the
top and bottom of the Stratix device. Each circuit is driven by a system
reference clock through the CLK pins that is the same frequency as the
DQS signal. Clock pins CLK[15..12]p feed the phase-shift cir cuitry on
the top of the device and clock pins CLK[7..4]p feed the phase-shift
circuitry on the bottom of the device. The phase-shifting reference circuit
on the top of the device controls the compensated delay elements for all
10 DQS pins located at the top of the dev ice. The phase-shifting r eference
circuit on the bottom of the device controls the compensated delay
elements for all 10 DQS pins located on the bottom of the device. All
10 delay elements (DQS signals) on either the top or bottom of the device
EP1S25 672-pin BGA
672-pin FineLine BGA 16 (3) 84
780-pin FineLine BGA
1,020-pin FineLine BGA 20 8 4
EP1S30 956-pin BGA
780-pin FineLine BGA
1,020-pin FineLine BGA
20 8 4
EP1S40 956-pin BGA
1,020-pin FineLine BGA
1,508-pin FineLine BGA
20 8 4
EP1S60 956-pin BGA
1,020-pin FineLine BGA
1,508-pin FineLine BGA
20 8 4
EP1S80 956-pin BGA
1,508-pin FineLine BGA
1,923-pin FineLine BGA
20 8 4
Notes to Table 2–27:
(1) See the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, V olume 2
for VREF guidelines.
(2) These packages have six groups in I/O banks 3 and 4 and six groups in I/O banks 7 and 8.
(3) These packages have eight groups in I/O banks 3 and 4 and eight groups in I/O banks 7 and 8.
(4) This package has nine groups in I/O banks 3 and 4 and nine groups in I/O banks 7 and 8.
(5) These packages have three groups in I/O banks 3 and 4 and four groups in I/O banks 7 and 8.
Table 2–27. DQS & DQ Bus Mode Support (Part 2 of 2) Note (1)
Device Package Number of ×8
Groups Number of ×16
Groups Number of ×32
Groups
Altera Corporation 2–119
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
shift by the same degree amount. For example, all 10 DQS pins on the top
of the device can be shifted by 90° and all 10 DQS pins on the bottom of
the device can be shifted by 72°. The refer ence circuits require a maximum
of 256 system reference clock cycles to set the correct phase on the DQS
delay elements. Figure 2–69 illustrat es the phase-shift refere nce ci rcuit
contro l of each DQS delay shift on the top of the device. This same cir cuit
is duplicated on the bottom of the device.
Figure 2–69. Simplified Diagram of the DQS Phase-Shift Circuitry
See the External Memory Interfaces chapter in the Stratix Device Handbook,
Volume 2 for more information on external memory interfaces.
Programmable Drive Strength
The output buffer for each Stratix device I/O pin has a programmable
drive strength control for certain I/O standa rds. The LVTTL and
LVCMOS standard has several levels of drive strength that the user can
control. SSTL-3 Class I and II, SSTL-2 Class I and II, HSTL Class I and II,
and 3.3-V GTL+ support a minimum setting, the lowest drive strength
that guarantees the IOH/IOL of the standard. Using minimum settings
provides signal slew rate control to reduce system noise and signal
overshoot.
Phase
Comparator Up/Down
Counter
Delay Chains
Input
Reference
Clock
Control Signals
to DQS Pins
6
2–120 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
I/O Structure
Table 2–28 shows the possible settings for the I/O standards with drive
strength contr ol.
Quartus II software version 4.2 and later will report current strength as
“PCI Compliant” for 3.3-V PCI, 3.3-V PCI-X 1.0, and Compact PCI I/O
standards.
Stratix device s su pport series on-chip termination (OCT) using
programmable drive strength. For mor e information, contact your Altera
Support Representative.
Open-Drain Output
Stratix devices provide an optional open-drain (equivalent to an open-
collector) output for each I/O pin. Th is open-drain output enables the
device to provide system-level control signals (e.g., interrupt and write-
enable signals) that can be asserted by any of several devices.
Slew-Rate Control
The output buffer for each Stratix device I/O pin has a programmable
output slew-rate control that can be co nfigured for low-noise or high -
speed performance. A faster slew rate pr ovides high-speed transitions for
high-performance systems. However, these fast transitions may
introduce noise transien ts into the system. A slow slew rate reduces
system noise, but adds a nominal delay to ri sing and falling edges. Each
Table 2–28. Programmable Drive Strength
I/O Standard IOH / IOL Current Strength Setting (mA)
3.3-V LVTTL 24 (1), 16, 12, 8, 4
3.3-V LVCMOS 24 (2), 12 (1), 8, 4, 2
2.5-V LVTTL/LVCMOS 16 (1), 12, 8, 2
1.8-V LVTTL/LVCMOS 12 (1), 8, 2
1.5-V LVCMOS 8 (1), 4, 2
GTL/GTL+
1.5-V HSTL Class I and II
1.8-V HSTL Class I and II
SSTL-3 Class I and II
SSTL-2 Class I and II
SSTL-18 Class I and II
Support max and min strength
Notes to Table 2–28:
(1) This is the Quartus II software default current setting.
(2) I/O banks 1, 2, 5, and 6 do not support this setting.
Altera Corporation 2–121
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
I/O pin has an individual slew-rate control, allowing you to spe ci fy the
slew rate on a pin-by-pin basis. The slew-rate control af fe cts both the
rising and falling edges.
Bus Hold
Each Stratix device I/O pin provides an optional bus-hold feature. The
bus-hold circuitry can weakly hold the signal on an I/O pin at its last-
driven state. Since the bus-hold feature holds the last-driven state of the
pin until the next input signal is present, an external pull-up or pull-down
resistor is not needed to hold a signal level when the bus is tri-stated.
Table 2–29 shows bus hold support for different pin types.
The bus-hold circuitry also pulls undriven pins away from the input
threshold vol tage where noise can cause unintended high-fr equency
switching. You can select t hi s feature individually for each I/O pin. The
bus-hold outpu t dr ives no higher than VCCIO to prevent overdriving
signals. If the bus-hold feature is enabled, the programmable pull-up
option cannot be used. Disable the bus-hold feature when using open-
drain outputs with the GTL+ I/O standar d or when the I/O pin has been
configured for differential signals.
The bus-hold cir c uitry uses a resistor with a nominal resistanc e (RBH) of
approximately 7 kΩ to weakly pull the signal level to the last-driven state.
See the DC & Switching Characteristics chapter of the Stratix Device
Handbook, V olume 1 for the specific sustaining current driven thr ough this
resistor and overdrive current used to identif y the ne xt-driven input
level. This information is provided for each VCCIO voltage level.
The bus-hold circuitry is activ e only after configuration. When going into
user mode, the bus-hold circ uit captures the value on the pin present at
the end of configuration.
Table 2–29. Bus Hold Support
Pin Type Bus Hold
I/O pins v
CLK[15..0]
CLK[0,1,2,3,8,9,10,11]
FCLK v
FPLL[7..10]CLK
2–122 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
I/O Structure
Programmable Pull-Up Resistor
Each Stratix device I/O pin provides an optional progra mmable pull-up
resistor during user mode. If this feature is enabled for an I/O pin, the
pull-up resistor (typically 25 kΩ) weakly holds the output to the VCCIO
level of the output pin’s bank. Table 2–30 shows which pin types support
the weak pull-up resistor feature.
Advanced I/O Standard Support
Stratix device IOEs support the following I/O standards:
■LVTTL
■LVCMOS
■1.5 V
■1.8 V
■2.5 V
■3.3-V PCI
■3.3-V PCI-X 1.0
■3.3-V AGP (1× and 2×)
■LVDS
■LVPECL
■3.3-V PCML
■HyperTransport
■Differential HSTL (on input/output clocks only)
■Differential SSTL (on output column clock pins only)
■GTL/GTL+
■1.5-V HSTL Class I and II
Table 2–30. Programmable Weak Pull-Up Resistor Support
Pin Type Programmable Weak Pull-Up Resistor
I/O pins v
CLK[15..0]
FCLK v
FPLL[7..10]CLK
Configuration pins
JTAG pins v (1)
Note to Table 2–30:
(1) TDO pins do not support programmable weak pull-up resistors.
Altera Corporation 2–123
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
■1.8-V HSTL Class I and II
■SSTL-3 Class I and II
■SSTL-2 Class I and II
■SSTL-18 Class I and II
■CTT
Table 2–31 describes the I/O standards supported by Stratix devices.
Table 2–31. Stratix Supported I/O Standards
I/O Standard Type Input Reference
Voltage (VREF)
(V)
Output Supply
Voltage (VCCIO)
(V)
Board
Termination
Voltage (VTT)
(V)
LVTTL Single-ended N/A 3.3 N/A
LVCMOS Single-ended N/A 3.3 N/A
2.5 V Single-ended N/A 2.5 N/A
1.8 V Single-ended N/A 1.8 N/A
1.5 V Single-ended N/A 1.5 N/A
3.3-V PCI Single-ended N/A 3.3 N/A
3.3-V PCI-X 1.0 Single-ended N/A 3.3 N/A
LVDS Differential N/A 3.3 N/A
LVPECL Differential N/A 3.3 N/A
3.3-V PCML Differential N/A 3.3 N/A
HyperTransport Differential N/A 2.5 N/A
Differential HSTL (1) Differential 0.75 1.5 0.75
Differential SSTL (2) Differential 1.25 2.5 1.25
GTL Voltage-referenced 0.8 N/A 1.20
GTL+ Voltage-referenced 1.0 N/A 1.5
1.5-V HSTL Class I and II V oltage-ref erenced 0.75 1.5 0.75
1.8-V HSTL Class I and II V oltage-ref erenced 0.9 1.8 0.9
SSTL-18 Class I and II Voltage-referenced 0.90 1.8 0.90
SSTL-2 Class I and II Voltage-referenced 1.25 2.5 1.25
SSTL-3 Class I and II Voltage-referenced 1.5 3.3 1.5
AGP (1× and 2°)Voltage-referenced 1.32 3.3 N/A
CTT Voltage-referenced 1.5 3.3 1.5
Notes to Table 2–31:
(1) This I/O standard is only available on input and output clock pins.
(2) This I/O standard is only available on output column clock pins.
2–124 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
I/O Structure
fFor more inform ation on I/O standard s supported by Stratix devices, se e
the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the
Stratix Device Handbook, Volume 2.
Stratix devices contain eight I/O banks in addition to the four enhanced
PLL external clock out banks, as shown in Figure 2–70. The four I/O
banks on the right and left of the device contain circuitry to support high-
speed differential I/O for LVDS, LVPECL, 3.3-V PCML, and
HyperTransport inputs and outputs. These banks support all I/O
standards listed in Table 2–31 except PCI I/O pins or PCI-X 1.0, GTL,
SSTL-18 Class II, and HSTL Class II outputs. The top and bottom I/O
banks support all single-ended I/O standards. Ad ditionally, Stratix
devices support four enhanced PLL external cl ock output banks,
allowing clock output capabilities such as differential support for SSTL
and HSTL. Table 2–32 shows I/O standard support for each I/O bank.
Altera Corporation 2–125
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–70. Stratix I/O Banks Notes (1), (2), (3)
Notes to Figure 2–70:
(1) Figure 2–70 is a top view of the silicon die. This will correspond to a top-down view for non-flip-chip packages, but
will be a reverse view for flip-chip packages.
(2) Figure 2–70 is a graphic representation only. See the device pin-outs on the web (www.altera.com) and the
Quartus II software for exact locations.
(3) Banks 9 through 12 are enhanced PLL external clock output banks.
(4) If the high-speed differential I/O pins are not use d for high-speed differ ential signaling, they can support all of the
I/O standards except HSTL Class I and II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and AGP 1×/2×.
(5) For guidelines for placing single-ended I/O pads next to differential I/O pads, see the Selectable I/O Standards in
Stratix and Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2.
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
I/O Banks 3, 4, 9 & 10 Support
All Single-Ended I/O Standards
I/O Banks 7, 8, 11 & 12 Support
All Single-Ended I/O Standards
I/O Banks 1, 2, 5, and 6 Support All
Single-Ended I/O Standards Except
Differential HSTL Output Clocks,
Differential SSTL-2 Output Clocks,
HSTL Class II, GTL, SSTL-18 Class II,
PCI, PCI-X 1.0, and AGP 1×/2×
DQS9T DQS8T DQS7T DQS6T DQS5T DQS4T DQS3T DQS2T DQS1T DQS0T
PLL5
VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3 VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4
VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7
PLL6
DQS9B DQS8B DQS7B DQS6B DQS5B DQS4B DQS3B DQS2B DQS1B DQS0B
910
VREF1B2 VREF2B2 VREF3B2 VREF4B2VREF1B1 VREF2B1 VREF3B1 VREF4B1
VREF4B6 VREF3B6 VREF2B6 VREF1B6 VREF4B5 VREF3B5 VREF2B5 VREF1B5
Bank 5Bank 6
PLL3
PLL4PLL1
PLL2
Bank 1 Bank 2
Bank 3 Bank 4
11 12Bank 8 Bank 7
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
PLL7 PLL10
PLL8 PLL9
PLL12
PLL11
(5)
(5)
(5)
(5)
2–126 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
I/O Structure
Table 2–32 shows I/O standard support for each I/O bank.
Table 2–32. I/O Support by Bank (Part 1 of 2)
I/O Standard Top & Bottom Banks
(3, 4, 7 & 8) Left & Right Banks
(1, 2, 5 & 6)
Enhanced PLL External
Clock Output Banks
(9, 10, 11 & 12)
LVTTL vvv
LVCMOS vvv
2.5 V vvv
1.8 V vvv
1.5 V vvv
3.3-V PCI vv
3.3-V PCI-X 1.0 vv
LVPECL vv
3.3-V PCML vv
LVDS vv
HyperTranspor t techno logy vv
Differential HSTL (clock
inputs) vv
Differential HSTL (clock
outputs) v
Differential SSTL (clock
outputs) v
3.3-V GTL vv
3.3-V GTL+ vvv
1.5-V HSTL Class I vvv
1.5-V HSTL Class II vv
1.8-V HSTL Class I vvv
1.8-V HSTL Class II vv
SSTL-18 Class I vvv
SSTL-18 Class II vv
SSTL-2 Class I vvv
SSTL-2 Class II vvv
SSTL-3 Class I vvv
Altera Corporation 2–127
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Each I/O bank has its own VCCIO pins. A single device can support 1.5-,
1.8-, 2.5-, and 3.3-V interfaces; each bank can support a differ ent standard
independently. Each bank also has dedicated VREF pins to support any
one of the voltage-referenced standards (such as SSTL-3) independently.
Each I/O bank can support multiple standards with the same VCCIO for
input and output pins. Each bank can support one voltage-referenced
I/O standard. For example, when VCCIO is 3.3 V, a bank can support
LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
Differential On-Chip Termination
Stratix devices provide differential on-chip termination (LVDS I/O
standard) to r educe r eflections and maintain signal integrity. Differential
on-chip termination simplifies board design by minimizing the number
of external termination resistors required. Termination can be placed
inside the package, eliminating small stubs that can still lead to
reflections. The internal termination is designed using transistors in the
linear region of operation.
Stratix device s support internal dif ferential termination with a nominal
resistance value of 137.5 Ω for LVDS input receiver buffers. LVPECL
signals require an external termination resistor. Figure 2–71 shows the
device with differ ential termination.
SSTL-3 Class II vvv
AGP (1× and 2×)vv
CTT vvv
Table 2–32. I/O Support by Bank (Part 2 of 2)
I/O Standard Top & Bottom Banks
(3, 4, 7 & 8) Left & Right Banks
(1, 2, 5 & 6)
Enhanced PLL External
Clock Output Banks
(9, 10, 11 & 12)
2–128 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
I/O Structure
Figure 2–71. LVDS Input Differential On-Chip Termination
I/O banks on the left and right side of the device support LVDS receiver
(far-end) differential termination.
Table 2–33 shows the Stratix device differential termination support.
Table 2–34 shows the termination support for different pin types.
The differential on-chip r esistance at the recei ver input buffer is
118 Ω±20 %.
RD+
Ð
+
Ð
Transmitting
Device Receiving Device with
Differential Termination
Z0
Z0
Table 2–33. Differential Termination Supported by I/O Banks
Differential Termination Support I/O Standard Support Top & Bottom
Banks (3, 4, 7 & 8) Left & Right Banks
(1,2,5 & 6)
Differential termination (1),(2) LVDS v
Notes to Table 2–33:
(1) Clock pin CLK0, CLK2, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential termination.
(2) Differential termination is only supported for LVDS because of a 3.3-V VCCIO.
Table 2–34. Differential Termination Support Across Pin Types
Pin Type RD
Top and bottom I/O banks (3, 4, 7, and 8)
DIFFIO_RX[] v
CLK[0,2,9,11],CLK[4-7],CLK[12-15]
CLK[1,3,8,10] v
FCLK
FPLL[7..10]CLK
Altera Corporation 2–129
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
However, there is additional resistance present between the device ball
and the input of the receiver buffer, as shown in Figure 2–72. This
resista nce is because of packag e trace resi stance (which can be calcu lated
as the resistance from the package ball to the pad) and the parasitic layout
metal routing r esistance (which is shown between the pad and the
intersection of the on-chip termination and input buffer).
Figure 2–72. Differential Resistance of LVDS Differential Pin Pair (RD)
Table 2–35 defines the specification for internal termination resistance for
commercial devices.
MultiVolt I/O Interface
The Stratix archi tecture supports the MultiVolt I/O interface feature,
which allows Stratix devices in all packages to interface with systems of
different supply voltages.
The Stratix VCCINT pins must always be connected to a 1.5-V power
supply. With a 1.5-V VCCINT level, input pins are 1.5-V, 1.8-V, 2.5-V, and
3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-V, 1.8-V,
2.5-V, or 3.3-V power supply, depending on the output requirements.
LVDS
Input Buffer
Differential On-Chip
Termination Resisto
r
9.3 Ω
9.3 Ω
0.3 Ω
0.3 Ω
R
D
Pad
Package Ball
Table 2–35. Differential On-Chip Termination
Symbol Description Conditions Resistance Unit
Min Typ Max
RD (2) Internal differential termination for LVDS Commercial (1),(3) 110 135 165 W
Industrial (2),(3) 100 135 170 W
Notes to Table 2–35:
(1) Data measured over minimum conditions (Tj = 0 C, VCCIO +5%) and maximum conditions (Tj = 85 C,
VCCIO =–5%).
(2) Data measured over minimum conditions (Tj = –40 C, VCCIO +5%) and maximum conditions (Tj = 100 C,
VCCIO =–5%).
(3) LVDS data rate is supported for 840 Mbps using internal differ ential termination.
2–130 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
High-Speed Differential I/O Support
The output levels are co mpatible with systems of the same voltage as the
power supply (i.e., when VCCIO pins are connected to a 1.5-V power
supply, the output levels are compatible with 1.5-V systems). When
VCCIO pins are connected to a 3.3-V power supply, the output high is
3.3 V and is compatible with 3.3-V or 5.0-V systems.
Table 2–36 summarizes Stratix MultiVolt I/O support.
High-Speed
Differential I/O
Support
Stratix device s contain dedicated circuitry for supporting di fferential
standards at speeds up to 840 Mbps. The following differential I/O
standards are supported in the Stratix device: LVDS, LVPECL,
HyperTransport, and 3.3-V PCML.
There are four dedicated high-speed PLLs in the EP1S10 to EP1S25
devices and eight dedicat ed high-speed PLLs in the EP1S30 to EP1S80
devices to multiply reference clocks and drive high-speed differential
SERDES channels.
fSee the Stratix device pin-outs at www.altera.com for additional high
speed DIFFIO pin information for Stratix devices.
Table 2–36. Stratix MultiVolt I/O Support Note (1)
VCCIO (V) Input Signal (5) Output Signal (6)
1.5 V1.8 V2.5 V3.3 V5.0 V1.5 V1.8 V2.5 V3.3 V5.0 V
1.5 vv
v (2) v (2) v
1.8 v (2) vv (2) v (2) v (3) v
2.5 vv v (3) v (3) v
3.3 v (2) vv (4) v (3) v (3) v (3) vv
Notes to Table 2–36:
(1) To drive inputs higher than VCCIO but less than 4.1 V, disable the PCI clampi ng diode. However, to drive 5.0-V
inputs to the device, enable the PCI clamping diode to prevent VI from rising above 4.0 V.
(2) The input pin current may be slightly higher than the typica l v alue.
(3) Although VCCIO specifies the vo ltage nec essary for the Str atix d evice to drive out, a receiving device powered at a
different level can still interface with the Stratix device if it has inputs that tolerate th e VCCIO va lue.
(4) Stratix devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode.
(5) This is the external signal that is driving the Stratix device.
(6) This repr esents the system voltage that Stratix supports when a VCCIO pin is connected to a specific voltage level.
For example, when VCCIO is 3.3 V and if the I/O standard is LVTTL/LVCMOS, the output high of the signal
coming out from Stratix is 3.3 V and is compatible with 3.3-V or 5.0-V systems.
Altera Corporation 2–131
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Table 2–37 shows the number of channels that each fast PLL can clock in
EP1S10, EP1S20, and EP1S25 devices. Tables 2–38 through Table 2–41
show this information for EP1S30, EP1S40, EP1S60, and EP1S80 devices .
Table 2–37. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 1 of 2) Note (1)
Device Package Transmitter/
Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs
PLL 1 PLL 2 PLL 3 PLL 4
EP1S10 484-pin FineLine BGA Transmitter (2) 20 840 (4) 5555
840 (3) 10 10 10 10
Receiver 20 840 (4) 5555
840 (3) 10 10 10 10
672-pin FineLine BGA
672-pin BGA Transmitter (2) 36 624 (4) 9999
624 (3) 18 18 18 18
Receiver 36 624 (4) 9999
624 (3) 18 18 18 18
780-pin FineLine BGA Transmitter (2) 44 840 (4) 11 11 11 11
840 (3) 22 22 22 22
Receiver 44 840 (4) 11 11 11 11
840 (3) 22 22 22 22
EP1S20 484-pin FineLine BGA Transmitter (2) 24 840 (4) 6666
840 (3) 12 12 12 12
Receiver 20 840 (4) 5555
840 (3) 10 10 10 10
672-pin FineLine BGA
672-pin BGA Transmitter (2) 48 624 (4) 12 12 12 12
624 (3) 24 24 24 24
Receiver 50 624 (4) 13 12 12 13
624 (3) 25 25 25 25
780-pin FineLine BGA Transmitter (2) 66 840 (4) 17 16 16 17
840 (3) 33 33 33 33
Receiver 66 840 (4) 17 16 16 17
840 (3) 33 33 33 33
2–132 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
High-Speed Differential I/O Support
When you span two I/O banks using cross-bank support, you can route
only two load enable signals total between the PLLs. When you enable
rx_data_align, you use both rxloadena and txloadena of a PLL.
That leaves no loadena for the second PLL.
EP1S25 672-pin FineLine BGA
672-pin BGA Transmitter (2) 56 624 (4) 14 14 14 14
624 (3) 28 28 28 28
Receiver 58 624 (4) 14 15 15 14
624 (3) 29 29 29 29
780-pin FineLine BGA Transmitter (2) 70 840 (4) 18 17 17 18
840 (3) 35 35 35 35
Receiver 66 840 (4) 17 16 16 17
840 (3) 33 33 33 33
1,020-pin FineLine
BGA Transmitter (2) 78 840 (4) 19 20 20 19
840 (3) 39 39 39 39
Receiver 78 840 (4) 19 20 20 19
840 (3) 39 39 39 39
Notes to Table 2–37:
(1) The first row for each transmitter or receiver reports the number of channels driven directly by the PLL. The second
row below it shows the maximum channels a PLL can drive if cross bank ch annels are used fr om the adjacent center
PLL. For example, in the 484-pin FineLine BGA EP1S10 device, PLL 1 can drive a maximum of five channels at
840 Mbps or a maximum of 10 channels at 840 Mbps. The Quartus II software may also merge r eceiver and
transmitter PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive both the maximum
numbers of receiver and transmitter channels.
(2) The number of channels listed includes the transmitter clock output (tx_outclock) channel. If the design require s
a DDR clock, it can use an extra data channel.
(3) These channels span across two I/O banks per side of the device. When a center PLL clocks channels in the opposite
bank on the same side of the device it is called cross-bank PLL support. Both center PLLs can clock cross-bank
channels simultaneously if, for example, PLL_1 is clocking all receiver channels and PLL_2 is clocking all
transmitter channels. You cannot have two adjacent PLLs simultaneously clocking cross-bank receiver channels or
two adjacent PLLs simultaneously clocking transmitter channels. Cross-bank allows for all receiver channels on
one side of the device to be clocked on one clock while all transmitter channels on the device are clocked on the
other center PLL. Crossbank PLLs are supported at full-speed, 840 Mbps. For wi re-bond de vices, th e full -spe e d is
624 Mbps.
(4) These values show the channels available for each PLL without crossing another bank.
Table 2–37. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 2 of 2) Note (1)
Device Package Transmitter/
Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs
PLL 1 PLL 2 PLL 3 PLL 4
Altera Corporation 2–133
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
The only way you can use the rx_data_align is if one of the following
is true:
■The receiver PLL is only clocking receive channels (no resources for
the transmitter)
■If all channels can fit in one I/O bank
Table 2–38. EP1S30 Differential Channels Note (1)
Package Transmitter
/Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs Corner Fast PLLs (2), (3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
780-pin
FineLine
BGA
Transmitter
(4) 70 840 18 17 17 18 (6) (6) (6) (6)
840 (5) 35 35 35 35 (6) (6) (6) (6)
Receiver 66 840 17 16 16 17 (6) (6) (6) (6)
840 (5) 33 33 33 33 (6) (6) (6) (6)
956-pin
BGA Transmitter
(4) 80 840 19 20 20 19 20 20 20 20
840 (5) 39 39 39 39 20 20 20 20
Receiver 80 840 20 20 20 20 19 20 20 19
840 (5) 40 40 40 40 19 20 20 19
1,020-pin
FineLine
BGA
Transmitter
(4) 80 (2) (7) 840 19
(1) 20 20 19
(1) 20 20 20 20
840 (5),(8) 39
(1) 39
(1) 39
(1) 39
(1) 20 20 20 20
Receiver 80 (2) (7) 840 20 20 20 20 19 (1) 20 20 19 (1)
840 (5),(8) 40 40 40 40 19 (1) 20 20 19 (1)
Table 2–39. EP1S40 Differential Ch annels (Part 1 of 2) Note (1)
Package Transmitter/
Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs Corner Fast PLLs (2), (3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
780-pin
FineLine
BGA
Transmitter
(4) 68 840 18 16 16 18 (6) (6) (6) (6)
840 (5) 34 34 34 34 (6) (6) (6) (6)
Receiver 66 840 17 16 16 17 (6) (6) (6) (6)
840 (5) 33 33 33 33 (6) (6) (6) (6)
2–134 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
High-Speed Differential I/O Support
956-pin
BGA Transmitter
(4) 80 840 18 17 17 18 20 20 20 20
840 (5) 35 35 35 35 20 20 20 20
Receiver 80 840 20 20 20 20 18 17 17 18
840 (5) 40 40 40 40 18 17 17 18
1,020-pin
FineLine
BGA
Transmitter
(4) 80 (10)
(7) 840 18
(2) 17
(3) 17
(3) 18
(2) 20 20 20 20
840 (5),(8) 35
(5) 35
(5) 35
(5) 35
(5) 20 20 20 20
Receiver 80 (10)
(7) 840 20 20 20 20 18
(2) 17
(3) 17
(3) 18 (2)
840 (5),(8) 40 40 40 40 18
(2) 17
(3) 17
(3) 18 (2)
1,508-pin
FineLine
BGA
Transmitter
(4) 80 (10)
(7) 840 18
(2) 17
(3) 17
(3) 18
(2) 20 20 20 20
840 (5),(8) 35
(5) 35
(5) 35
(5) 35
(5) 20 20 20 20
Receiver 80 (10)
(7) 840 20 20 20 20 18
(2) 17
(3) 17
(3) 18 (2)
840 (5),(8) 40 40 40 40 18
(2) 17
(3) 17
(3) 18 (2)
Table 2–40. EP1S60 Differential Ch annels (Part 1 of 2) Note (1)
Package Transmitter/
Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs Corner Fast PLLs (2), (3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
956-pin
BGA Transmitter
(4) 80 840 12 10 10 12 20 20 20 20
840 (5),(8) 22 22 22 22 20 20 20 20
Receiver 80 840 20 20 20 20 12 10 10 12
840 (5),(8) 40 40 40 40 12 10 10 12
Table 2–39. EP1S40 Differential Ch annels (Part 2 of 2) Note (1)
Package Transmitter/
Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs Corner Fast PLLs (2), (3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
Altera Corporation 2–135
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
1,020-pin
FineLine
BGA
Transmitter
(4) 80 (12)
(7) 840 12
(2) 10
(4) 10
(4) 12
(2) 20 20 20 20
840 (5),(8) 22
(6) 22
(6) 22
(6) 22
(6) 20 20 20 20
Receiver 80 (10)
(7) 840 20 20 20 20 12
(8) 10
(10) 10
(10) 12 (8)
840 (5),(8) 40 40 40 40 12
(8) 10
(10) 10
(10) 12 (8)
1,508-pin
FineLine
BGA
Transmitter
(4) 80 (36)
(7) 840 12
(8) 10
(10) 10
(10) 12
(8) 20 20 20 20
840 (5),(8) 22
(18) 22
(18) 22
(18) 22
(18) 20 20 20 20
Receiver 80 (36)
(7) 840 20 20 20 20 12
(8) 10
(10) 10
(10) 12 (8)
840 (5),(8) 40 40 40 40 12
(8) 10
(10) 10
(10) 12 (8)
Table 2–41. EP1S80 Differential Ch annels (Part 1 of 2) Note (1)
Package Transmitter/
Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs Corner Fast PLLs (2),(3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
956-pin
BGA Transmitter
(4) 80 (40)
(7) 840 10 10 10 10 20 20 20 20
840 (5),(8) 20 20 20 20 20 20 20 20
Receiver 80 840 20 20 20 20 10 10 10 10
840 (5),(8) 40 40 40 40 10 10 10 10
1,020-pin
FineLine
BGA
Transmitter
(4) 92 (12)
(7) 840 10
(2) 10
(4) 10
(4) 10
(2) 20 20 20 20
840 (5),(8) 20
(6) 20
(6) 20
(6) 20
(6) 20 20 20 20
Receiver 90 (10)
(7) 840 20 20 20 20 10
(2) 10
(3) 10 (3) 10 (2)
840 (5),(8) 40 40 40 40 10
(2) 10
(3) 10 (3) 10 (2)
Table 2–40. EP1S60 Differential Ch annels (Part 2 of 2) Note (1)
Package Transmitter/
Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs Corner Fast PLLs (2), (3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
2–136 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
High-Speed Differential I/O Support
The high-speed diff erential I/O circuitry supports the following high
speed I/O interconnect standards and applications:
■UTOPIA IV
■SPI-4 Phase 2 (POS-PHY Level 4)
■SFI-4
■10G Ethernet XSBI
1,508-pin
FineLine
BGA
Transmitter
(4) 80 (72)
(7) 840 10
(10) 10
(10) 10
(10) 10
(10) 20
(8) 20
(8) 20 (8) 20 (8)
840 (5),(8) 20
(20) 20
(20) 20
(20) 20
(20) 20
(8) 20
(8) 20 (8) 20 (8)
Receiver 80 (56)
(7) 840 20 20 20 20 10
(14) 10
(14) 10
(14) 10
(14)
840 (5),(8) 40 40 40 40 10
(14) 10
(14) 10
(14) 10
(14)
Notes to Tables 2–38 through 2–41:
(1) The first row for each transmitter or receiver reports the number of channels driven directly by the PLL. The second
row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center
PLL. For example, in the 780-pin FineLine BGA EP1S30 device, PLL 1 can drive a maximum of 18 transmitter
channels at 840 Mbps or a maximum of 35 transmitter channels at 840 Mbps. The Quartus II software may also
merge transmitter and receiver PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive
both the maximum numbers of receiver and transmitter channels.
(2) Some of the channels accessible by the center fast PLL and the channels accessible by the corner fast PLL overlap.
Therefor e, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and
4 with the number o f channels ac cessible by P LLs 7, 8, 9, and 10. For more information on which channels overlap,
see the Stratix device pin-outs at www.altera.com.
(3) The corner fast PLLs in this device support a data rate of 840 Mbps for channels labeled “high” speed in the device
pin-outs at www.altera.com.
(4) The numbers of channels listed include the transmitter clock output (tx_outclock) channel. An extra data
channel can be used if a DDR clock is needed.
(5) These channels span across two I/O banks per side of the device. When a center PLL clocks channels in the opposite
bank on the same side of the device it is called cross-bank PLL support. Both center PLLs can clock cross-bank
channels simultaneously if say PLL_1 is clocking all receiver channels and PLL_2 is clocking all transmitter
channels. You cannot have two adjacent PLLs simultaneously clocking cr oss-bank receiver channels or two adjacent
PLLs simultaneously clocking transmitter channels. Cross-bank allows for all receiver channels on one side of the
device to be clocked on one clo ck wh ile all tr ansmi tter channels on the device ar e clocked on the other center PLL.
Crossbank PLLs are supported at full-speed, 840 Mbps. For wire-bond devices, the full-speed is 624 Mbps.
(6) PLLs 7, 8, 9, and 10 are not available in this device.
(7) The number in parentheses is the number of slow-speed channels, guaranteed to operate at up to 462 Mbps. These
channels ar e independent of the high- speed dif feren tial channels. For the loc ation of these channels, see the dev ice
pin-outs at www.altera.com.
(8) See the Stratix devi ce pin -outs at www.altera.com. Channels marked “high” speed are 840 MB ps and “ low” speed
channels are 462 MBps.
Table 2–41. EP1S80 Differential Ch annels (Part 2 of 2) Note (1)
Package Transmitter/
Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs Corner Fast PLLs (2),(3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
Altera Corporation 2–137
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
■RapidIO
■HyperTransport
Dedicated Circuitry
Stratix device s support sourc e-s ynchronou s int erfacing with LVDS,
LVPECL, 3.3-V PCML, or HyperTransport signaling at up to 840 Mbps.
Stratix devices can transm it or receive seri al channels along with a
low-speed or high-speed clock. The receiving device PLL multiplies the
clock by a integer factor W (W = 1 thr ough 32). For example, a
HyperTransport application where the data rate is 800 Mbps and the
clock rate is 400 MHz would r equire that W be set to 2. The SERDES factor
J determines the parallel data width to deserial ize from receivers or to
serialize for transmitters. The SERDES factor J can be set to 4, 7, 8, or 10
and does not have to equal the PLL clock-mu ltiplicat ion W value. For a J
factor of 1, the Stratix device bypa sses the SERDES block. Fo r a J factor of
2, the Stratix device bypasses the SERDES block, a nd the DDR input and
output registers ar e used in the IOE. See Figure 2–73.
Figure 2–73. High-Speed Differential I/O Receiver / Transmitter Interface Example
An external pin or global or regional clock can drive the fast PLLs, which
can output up to three clocks: two multiplied high-speed dif ferential I/O
clocks to drive the SERDES block and/or external pin, and a low-speed
clock to drive the logic array.
+
–
8
Data
Data
Fast
PLL
105 MHz
8×
840 Mbps
Dedicated
Receiver
Interface
Dedicated
Transmitter
Interface
R4, R8, and R24
Interconnect
Local
Interconnect
8+
–
8×
840 Mbps
tx_load_en
rx_load_en
Regional or
global cloc
k
8
2–138 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
High-Speed Differential I/O Support
The Quartus II MegaWizard® Plug-In Manager only allows the
implementation of up to 20 receiver or 20 transmitter channels for each
fast PLL. These channels operate at up to 840 Mbps. The receiver and
transmitter channels are interleaved such that each I/O bank on the left
and right side of the device has one r eceiver channel and one transmitter
channel per LAB row. Figure 2–74 shows the fast PLL and channel layout
in EP1S10, EP1S20, and EP1S25 devices. Figure 2–75 shows the fast PLL
and channel layout in the EP1S30 to EP1S80 devices.
Figure 2–74. Fast PLL & Channel Layout in the EP1S10, EP1S20 or EP1S25 Devices Note (1)
Notes to Figure 2–74:
(1) Wire-bond packages support up to 624 Mbps.
(2) See Table 2–41 for the number of channels each device supports.
(3) There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of
its bank quadrant, those clocked channels support up to 840 Mbps for “high” speed channels and 462 Mbps for
“low” speed channels, as labele d in the device pin-outs at www.altera.com.
Transmitter
Receiver
Transmitter
Receiver
CLKIN
CLKIN
Transmitter
Receiver
Transmitter
Receiver
CLKIN
CLKIN
Fast
PLL 1
Fast
PLL 2
(3)
Fast
PLL 4
Fast
PLL 3
(3)
Up to 20 Receiver and
Transmitter Channels (2)
Up to 20 Receiver and
Transmitter Channels (2)
Up to 20 Receiver and
Transmitter Channels (2)
Up to 20 Receiver and
Transmitter Channels (2)
Altera Corporation 2–139
July 2005 Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–75. Fast PLL & Channel Layout in the EP1S30 to EP1S80 Devices Note (1)
Notes to Figure 2–75:
(1) Wire-bond packages support up to 624 Mbps.
(2) See Table 2–38 through 2–41 for the number of channels each device supports.
(3) There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of
its bank quadrant, those clocked channels support up to 840 Mbps for “high” speed channels and 462 Mbps for
“low” speed channels as labeled in the device pin-outs a t www.altera.com.
Transmitter
Receiver
Transmitter
Receiver
CLKIN
FPLL7CLK
Transmitter
Receiver
Transmitter
Receiver
CLKIN
FPLL10CLK
Transmitter
Receiver
Transmitter
Receiver
FPLL9CLK
CLKIN
Fast
PLL 7
Fast
PLL 1
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
Transmitter
Receiver
Transmitter
Receiver
FPLL8CLK
CLKIN Fast
PLL 2
Fast
PLL 8
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
(3) (3)
Fast
PLL 10
Fast
PLL 4
Fast
PLL 3
Fast
PLL 9
2–140 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Power Sequencing & Hot Socketing
The transmitter external clock output is transmitted on a data channel.
The txclk pin for each bank is located in betwee n data transmitter pins.
For ×1 clocks (e.g., 622 Mbps, 622 MHz), the high-speed PLL clock
bypasses the SERDES to drive the output pins. For half-rate clocks (e.g.,
622 Mbps, 31 1 MHz) or any other even-numbered factor such as 1/4, 1/7,
1/8, or 1/10, the SERDES automatically generates the clock in the
Quartus II software.
For systems that require more than four or eight high-speed di ffer ential
I/O clock domains, a SERDES bypass implementation is possible using
IOEs.
Byte Alignment
For high-speed sour ce s ynchr onous in terfaces such as POS -PHY 4, XS BI,
RapidIO, and HyperTransport technology, the source synchronous clock
rate is not a byte- or SERDES-rate multiple of the data rate. Byte
alignment is necessary for these protocols since the source sy nchronous
clock does not provide a byte or word boundary since the clock is one half
the data rate, not one eighth. The Stratix device’s high-speed differential
I/O circuitry provides dedicated data real ignm ent circu itry for u ser-
contro lled byte boundary shifting. This simpl ifie s des igns while saving
LE resources. An input signal to eac h fast PLL can stal l de s erializer
parallel data outputs by one bit period. You can use an LE-based state
machine to signal the shift of receiver byte boundarie s unti l a specified
pattern is detected to indicate byte alignment.
Power
Sequencing &
Hot Socketing
Because Stratix devices can be used in a mixed-voltage environment, they
have been designed specifically to tolerate any possible power-up
sequence. Therefore, the VCCIO and VCCINT power supplies may be
powered in any order.
Although you can power up or down the VCCIO and VCCINT power
supplies in any sequence, you should not power down any I/O banks
that contain configuration pins while leaving other I/O banks powered
on. For power up and power down, all supplies (VCCINT and all VCCIO
power planes) must be powered up and down within 100 ms of each
other. This pr events I/O pins from driving out.
Signals can be driven into Stratix devices before and during power up
without damaging the device. In addition, Stratix devices do not drive
out during power up. Once operating conditions are reached and the
device is configured, Stratix devices operate as specified by the user. For
more information, see Hot Socketing in the Selectable I/O Standards in
Stratix & Stratix GX Devices chapter in the Stratix Device Handbook,
Volume 2.
Altera Corporation 3–1
July 2005
3. Configuration & Testing
IEEE Std. 1149.1
(JTAG)
Boundary-Scan
Support
All Stratix® devices provide JTAG BST cir cuitry that complies with the
IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be
performed either before or after, but not during configuration. Stratix
devices can also use the JTAG port for configuration together with either
the Quartus®II software or hardware using either Jam Files (.jam) or Jam
Byte-Code Files (.jbc).
Stratix devices support IOE I/O standard setting reconfiguration through
the JTAG BST chain. The JTAG chain can update the I/O standard for all
input and output pins any time before or during user mode thr ough the
CONFIG_IO instruction. You can use this ability for JTAG testing before
configuration when some of the Stratix pins drive or receive from other
devices on the board using voltage-referenced standards. Since the Stratix
device may not be configur ed befor e JTAG testing, the I/O pins may no t
be configured for appropriate electrical standards for chip-to-chip
communication. Programming those I/O standards via JTAG allows you
to fully test the I/O connection to other devices.
The enhanced PLL reconfiguration bit s ar e part of the JTAG chain before
configuration and after power-up. After device configuration, the PLL
reco nfiguration bits are not part of the JTAG chain.
The JTAG pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O standards. The
TDO pin voltage is determined by the VCCIO of the bank where it resides.
The VCCSEL pin selects whether the JT AG inputs are 1.5-V, 1.8-V, 2.5-V, or
3.3-V compatible.
Stratix devices also use the JT AG port to monitor the logic operation of the
device with the SignalTap®II embedded logic analyzer. Stratix devices
support the JTAG instructions shown in Table 3–1.
The Quartus II software has an Auto Usercode feature where you can
choose to use the checksum value of a programming file as the JT A G user
code. If selected , the checksum is au tomatically load ed to the USERCODE
register. In the Settings dialog box in the Assignments menu, click Device
& Pin Options, then General, and then turn on the Auto Usercode
option.
S51003-1.3
3–2 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Table 3–1. Stratix JTAG Instructions
JTAG Instruction Instruction Code Description
SAMPLE/PRELOAD 00 0000 0101 Allows a snapshot of signals at the de vice pins to be captured and
examined during normal device operation, and permits an initial
data pattern to be output at the device pins. Also used by the
SignalTap II embedded logic analyzer.
EXTEST (1) 00 0000 0000 Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
BYPASS 11 1111 1111 Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
USERCODE 00 0000 0111 Selects the 32-bit USERCODE register and places it between the
TDI and TDO pins, allowing the USERCODE to be serially shifted
out of TDO.
IDCODE 00 0000 0110 Selects the IDCODE register and places it between TDI and TDO,
allowing the IDCODE to be serially shifted out of TDO.
HIGHZ (1) 00 0000 1011 Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent de vices during normal device operation, while
tri-stating all of the I/O pins.
CLAMP (1) 00 0000 1010 Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.
ICR instructions Used when configuring an Stratix device via the JTAG port with a
MasterBlasterTM, ByteBlasterMVTM, or ByteBlasterTM II download
cable, or when using a Jam File or Jam Byte-Code File via an
embedded processor or JRunner.
PULSE_NCONFIG 00 0000 0001 Emulates pulsing the nCONFIG pin low to trigger reconfiguration
even though the physical pin is unaffected.
CONFIG_IO 00 0000 1101 Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, after, or during
configuration. Stops configuration if ex ecuted during configuration.
Once issued, the CONFIG_IO instruction will hold nSTATUS low
to reset the configuration device. nSTATUS is held low until the
device is reconfigured.
SignalTap II
instructions Monitors internal device operation with the SignalTap II embedded
logic analyzer.
Note to Table 3–1:
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
Altera Corporation 3–3
July 2005 Stratix Device Handbook, Volume 1
Configuration & Testing
The Stratix device instruction register length is 10 bits and the USERCODE
register length is 32 bits. Tables 3–2 and 3–3 show the boundary-scan
register length and de vice IDCODE information for Stratix devices.
Table 3–2. Stratix Boundary-Scan Register Length
Device Boundary-Scan Register Length
EP1S10 1,317
EP1S20 1,797
EP1S25 2,157
EP1S30 2,253
EP1S40 2,529
EP1S60 3,129
EP1S80 3,777
Table 3–3. 32-Bit Stratix Device IDCODE
Device
IDCODE (32 Bits) (1)
Version (4 Bits) Part Number (16 Bits) Manufacturer Identity
(11 Bits) LSB (1 Bit) (2)
EP1S10 0000 0010 0000 0000 0001 000 0110 1110 1
EP1S20 0000 0010 0000 0000 0010 000 0110 1110 1
EP1S25 0000 0010 0000 0000 0011 000 0110 1110 1
EP1S30 0000 0010 0000 0000 0100 000 0110 1110 1
EP1S40 0000 0010 0000 0000 0101 000 0110 1110 1
EP1S60 0000 0010 0000 0000 0110 000 0110 1110 1
EP1S80 0000 0010 0000 0000 0111 000 0110 1110 1
Notes to Tables 3–2 and 3–3:
(1) The most significant bit (MSB) is on the left.
(2) The IDCODE’s least significant bit (LSB) is always 1.
3–4 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Figure 3–1 shows the timing requirements for the JTAG signals.
Figure 3–1. Stratix JTAG Waveforms
Table 3–4 shows the JTAG timing parameters and value s for Stratix
devices.
Table 3–4. Stratix JTAG Timing Parameters & Values
Symbol Parameter Min Max Unit
tJCP TCK clock period 100 ns
tJCH TCK clock high time 50 ns
tJCL TCK clock low time 50 ns
tJPSU JTAG port setup time 20 ns
tJPH JTAG port hold time 45 ns
tJPCO JTAG port clock to output 25 ns
tJPZX JTAG port high impedance to valid output 25 ns
tJPXZ JTAG port valid output to high impedance 25 ns
tJSSU Capture register setup time 20 ns
tJSH Capture register hold time 45 ns
tJSCO Update register clock to output 35 ns
tJSZX Update register high impedance to valid output 35 ns
tJSXZ Update register valid output to high impedance 35 ns
TDO
TCK
tJPZX tJPCO
tJPH
tJPXZ
tJCP tJPSU
tJCL
tJCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
tJSZX
tJSSU tJSH
tJSCO tJSXZ
Altera Corporation 3–5
July 2005 Stratix Device Handbook, Volume 1
Configuration & Testing
1Stratix, Stratix II, Cyclone®, and Cyclone II devic e s must be
within the first 17 devices in a JTAG chain. All of these devices
have the same JTAG controlle r. If any of the Stratix, Stratix II,
Cyclone, and Cyclone II devices ar e in the 18th or after they will
fail configuration. This does not affect SignalTap II.
fFor more information on JTAG, see the following documents:
■AN 39: IEEE Std. 1 149.1 (JT AG) Boundary-Scan Testing in Altera Devices
■Jam Programming & Test Language Speci f ica tion
SignalTap II
Embedded Logic
Analyzer
Stratix devices feature the SignalTap I I e m b edded logic analyzer, which
monitors design operation over a period of time through the IEEE Std.
1149.1 (JTAG) circuitry. You can analyze interna l logic at speed without
bringing internal signals to the I/O pins. This feature is particularly
important for advanced packages, such as FineLine BGA® packages,
because it can be difficult to add a connection to a pin during the
debugging process after a board is designed and manufactured.
Configuration The logic, circuitry, and interconnects in the Stratix architectur e are
configured with CMOS SRAM elements. Altera® devices are
reconfigurable. Because every device is tested with a high-coverag e
production test program, you do not have to perform fault testing and can
focus on simulation and design verificati on.
Stratix devices are configured at system power -up with data stor ed in an
Altera serial configuration device or provided by a system controller.
Altera offers in-system programmability (ISP)-capable configuration
devices that configure Strat ix devices via a seri al data stream. Stratix
devices can be configured in under 100 ms using 8-bit parallel data at
100 MHz. The Stratix device’s optimized interface allows
micr opr ocessors to co nfigur e it se rially or in parallel, and synchr onously
or asynchronously. The interface also enables microprocessors to treat
Stratix devices as memory and configure them by writing to a virtual
memory location, making reconfiguration easy. After a Stratix device has
been configured, it can be reconfigured in-circuit by resetting the device
and loading new data. Real-time changes can be made during system
operation, enabling innovative reconfigurable computing applications.
Operating Modes
The Stratix architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
3–6 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Configuration
configuration, the devic e resets registers, enable s I/O pins, and begins to
operate as a logic device . The I/O pins are tri-stated during power-up,
and before and during configuration. Together, the configuration and
initialization processes are called command mode. Normal device
operation is called us er mode.
SRAM configuration elements allow Stratix devices to be reconfigured in-
circuit by loading new configuration data into the device. With real-time
reco nfiguration, the device is forced into command mode with a device
pin. The configuration process loads different configuration data,
reinitializes the device, and resumes user-mode operation. You can
perform in-field upgrades by distributing new configuration files either
within the system or remotely.
PORSEL is a dedicated input pin used to select POR delay times of 2 ms
or 100 ms during power-up. When the PORSEL pin is connected to
ground, the POR time is 100 ms; when the PORSEL pin is connected to
VCC, the POR time is 2 ms.
The nIO_PULLUP pin enables a built-in weak pull-up resistor to pull all
user I/O pins to VCCIO before and during device configurat ion. If
nIO_PULLUP is connected to VCC during configuration, the weak pull-
ups on all user I/O pins are disabled. If connected to ground, the pull-ups
are enable d during configuration. The nIO_PULLUP pin can be pulled to
1.5, 1.8, 2.5, or 3.3 V for a logic level high.
VCCSEL is a dedicated input that is used to choose whether all dedicated
configuration and JTAG input pins can accept 1.5 V/1.8 V or 2.5 V/3.3 V
during configuration. A logic low sets 3.3 V/2.5 V, and a logic high sets
1.8 V/1.5 V. VCCSEL affects the following pins: TDI, TMS, TCK, TRST,
MSEL0, MSEL1, MSEL2, nCONFIG, nCE, DCLK, PLL_ENA, CONF_DONE,
nSTATUS. The VCCSEL pin can be pulled to 1.5, 1.8, 2.5, or 3.3 V for a logic
level high.
The VCCSEL signal does not contr ol the dual-purpose configuration pins
such as the DATA[7..0] and PPA pins (nWS, nRS, CS, nCS, and
RDYnBSY). During configuration, these dual-purpose pins will drive out
voltage levels corr esponding to the VCCIO supply voltage that powers the
I/O bank containing the pin. After configuration, the dual-purpose pins
use I/O standar ds specified in the user desig n .
TDO and nCEO drive out at the same voltages as the VCCIO supply that
powers the I/O bank containing the pin. Users must select the VCCIO
supply for bank containing TDO accordingly. For example, when using
the ByteBlaster™ MV cable, the VCCIO for the bank containing TDO must
be powered up at 3.3 V.
Altera Corporation 3–7
July 2005 Stratix Device Handbook, Volume 1
Configuration & Testing
Configuring Stratix FPGAs with JRunner
JRunner is a software driver that configures Altera FPGAs, including
Stratix FPGAs, through the ByteBlaster II or ByteBlasterMV cables in
JTAG mode. The programming input file supported is in Raw Binary File
(.rbf) format. JRunner also requires a Chain Description File (.cdf)
generated by the Quartus II software. JRunner is targeted for embedded
JTAG configuration. The source code is developed for the Windows NT
operating system (OS), but can be customized to run on o ther platforms.
For more information on the JRunner software driver, see the JRunner
Software Driver: An Embedded Solution to the JTAG Configuration
White Paper and the source files on the Altera web site (www.altera.com).
Configuration Schemes
You can load the configuration data for a Stratix device with one of five
configuration sche mes (see Table 3–5), chosen on the basis of the target
application. You can use a configuration device, intelligent controller, or
the JTAG port to configure a Stratix device. A configuration device can
automatically configure a Stratix device at system power-up.
Multiple Stratix devices can be configur ed in any of five configuration
schemes by connecting the configuration enable (nCE) and configuration
enable output (nCEO) pins on each device.
Partial Reconfiguration
The enhanced PLLs within the Stra ti x de vice family support partial
reco nfiguration of their multiply, divide, and time delay settings w ithout
reconfiguring the entire device. You can use either serial data from the
logic array or regular I/O pins to pr ogram t he PLL’s counter settings in a
serial chain. This option provides considerable flexibility for frequency
Table 3–5. Data Sources for Configuration
Configuration Scheme Data Source
Configuration device Enhanced or EPC2 configuration device
Passive serial (PS) MasterBlaster, ByteBlasterMV, or ByteBlaster II
download cable or serial data source
Passive parallel
asynchronous (PPA) Parallel data source
Fast passive parallel Parallel data source
JTAG MasterBlaster, ByteBlasterMV, or ByteBlaster II
download cable, a microprocessor with a Jam or
JBC file, or JRunner
3–8 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Configuration
synthesis, allowing real-time variation of the PLL frequency and delay.
The rest of the device is functional while reconfiguring the PLL. See the
Stratix Architecture chapter of the Stratix Device Handbook, Volume 1 for
more information on Stratix PLLs.
Remote Update Configuration Modes
Stratix devices also support remote configuration using an Altera
enhanced configuration dev ic e (e.g. , EPC16, EPC8, and EPC4 devices)
with page mode selection. Fac tory configu r ation data is stored in the
default page of the configuration device. This is the default configuration
that contains the design required to control remote updates and handle
or recover from errors. You write the factory configuration once into the
flash memory or configuration device. Remote update data can update
any of the re maining pages of the configuration device. If there is an erro r
or corruption in a remote update configuration, the configuration device
reverts back to the factory configuration information.
There are two remote configuration modes: remote and local
configuration. You can use the remote update configuration mode for all
three configuration modes: serial, parallel synchronous, and parallel
asynchronous. Configuration devices (for example, EPC16 devices) only
support serial and parallel synchronous modes. Asynchronous parallel
mode allows remote updates when an intelligent host is used to configure
the Stratix device. This host must support page mode settings similar to
an EPC16 device.
Remote Update Mode
When the Stratix device is first powered up in remote update
programming mode, it loads the configuration located at page address
“000.” The factory configuration should always be located at page
address “000,” and should never be remotely updated. The factory
configuration contains the required logic to perform the following
operations:
■Determine the page addr ess/lo ad location for the next application’s
configuration data
■Recover from a previo us configuration error
■Receive new configuration dat a and write it into the confi gur ation
device
The factory configuration is the default and takes control if an error
occurs while loading the application configuration.
Altera Corporation 3–9
July 2005 Stratix Device Handbook, Volume 1
Configuration & Testing
While in the factory configuration, the factory-configuration logic
performs the following operations:
■Loads a remote update-control register to determine the page
address of the new application configuration
■Determines whether to enable a user watchdog timer for the
application configuration
■Determines what the watchdog timer setting should be if it is
enabled
The user watchdog timer is a counter that must be continually reset
within a specific amount of time in the user mode of an application
configuration to ensure that valid configuration occurred during a remote
update. Only valid application confi gur ations designed for remot e
update can reset the user watchdog timer in user mode. If a valid
application configuration does not reset the user watchdog timer in a
specific amount of time, the timer up dates a status register a nd loads the
factory configuration. The user watchdog timer is automatically disabled
for factory configurations.
If an error occu rs in load ing th e application configuration, the
configuration logic writes a status register to specify the cause of the error .
Once this occurs, the Stratix device automatically loads the factory
configuration, which reads the status register and determines the reason
for reconfiguration. Based on the reason, the factory configuration will
take appropriate st eps and will write the remot e update control register
to specify the next application conf iguration page to be loaded.
When the Stratix devic e successfully loads the application configuration,
it enters into user mode. The Stratix device then executes the main
application of the user. Intellectual property (IP), su ch as a Nios® (16-bit
ISA) and Nios®II (32-bit ISA) embedded processors, can help the Stratix
device determine when remote update is coming. The Nios embedded
processor or user logic receives incoming data, writes it to the
configuration device, and loads the factory configuration. The factory
configuration will r ead the remote update status register and determine
the valid application configuration to load. Figure 3–2 shows the Stratix
remote update. Figure 3–3 shows the transition diagram for remote
update mode.
3–10 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Configuration
Figure 3–2. Stratix Device Remote Update
Note to Figure 3–2:
(1) When the Stratix device is configured with the factory configuration, it can handle update data from EPC16, EPC8,
or EPC4 configuration device pages and point to the next page in the configuration device .
Watchdog
Timer
Stratix Device
New Remote
Configuration Data
Configuration
Device
Application Configuration
Application Configuration
Factory Configuration
(1)
Configuration Device Updates
Stratix Device with Factory
Configuration (to Handle Update)
or New Application Configuration
Page 7
Page 6
Page
0
Altera Corporation 3–11
July 2005 Stratix Device Handbook, Volume 1
Configuration & Testing
Figure 3–3. Remote Update Transition Diagram Notes (1), (2)
Notes to Figure 3–3:
(1) Remote update of Application Configuration is controlled by a Nios embedded processor or user logic programmed
in the Factory or Application configurations.
(2) Up to seven pages can be specified allowing up to seven diffe rent co nfiguration applications.
Configuration
Error
Configuration
Error
Application 1
Configuration
Configuration
Error
Factory
Configuration
Reload an
Application
Reload an
Application
Application n
Configuration
Power-Up
3–12 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Stratix Automated Single Event Upset (SEU) Detection
Local Update Mode
Local update mo de is a simplified version of the remot e update. This
featur e is intended for simple systems that need to loa d a single
application configuration immediately upon power up without loading
the factory configuration first. Local update designs have only one
application configuration to load, so it does not require a factory
configuration to determine which applicatio n configurat ion to us e.
Figure 3–4 shows the transition diagram for local update mode.
Figure 3–4. Local Update Transition Diagram
Stratix
Automated
Single Event
Upset (SEU)
Detection
Stratix devices offer on-chip circuitry for automated checking of single
event upset (SEU) detection. FPGA devices that operate at high elevations
or in close proximity to earth’s North or South Pole require periodic
checks to ensur e conti nued data integrity. The error detection cyclic
redundancy check (CRC) feature contr olled by the Device & Pin Options
dialog box in the Quartus II software uses a 32-bit CRC circuit to ensure
data reliability and is one of the best options for mitigating SEU.
nCONFIG
nCONFIG
Configuration
Error
Application
Configuration
Configuration
Error
Factory
Configuration
Power-Up
or nCONFIG
Altera Corporation 3–13
July 2005 Stratix Device Handbook, Volume 1
Configuration & Testing
For Stratix, the CRC is computed by the Quartus II software and
downloaded into the device as a part of the configuration bit stream. The
CRC_ERROR pin reports a soft error when configuratio n SRA M data is
corrupted, triggering devic e reconfiguration.
Custom-Built Circuitry
Dedicated circuitry is built in the Stratix devices to perform error
detection automatically. You can use the buil t-in de d ic a ted circuitry for
error detection using CRC feature in Stratix devices, eliminating the need
for external logic. This circuitry will perform error detection
automatically when enabled. Th is error detection circuitry in Stratix
devices constantly checks for errors in the configuration SRAM cells
while the device is in us er mode. Y o u can monitor one external pin for the
error and use it to trigger a r e-configuration cycle. Select t he desired time
between checks by adjusting a built-in clo ck divider.
Software Interface
In the Quartus II software version 4.1 and later, you can turn on the
automated error detection CRC feature in the Device & Pin Options
dialog box. This dialog box allows you to enable the feature and set the
internal frequency of the CRC between 400 kHz to 100 MHz. This controls
the rate that the CRC circuitry verifies the inte rnal config ura tion SRAM
bits in the FPGA device.
For more information on CRC, see AN 357: Error Detection Using CRC in
Altera FPGA Devices.
Temperature
Sensing Diode Stratix device s include a diode-connected transi stor for use as a
temperature sensor in powe r manageme nt. This diode is used with an
external digital thermometer device such as a MAX1617A or MAX1619
from MAXIM Integrated Products. These devices steer bias current
through the Stratix diode, measuring forward voltage and converting this
reading to temperatur e in the form of a n 8-bit signed number (7 bits plus
sign). The external device’s output r epresents the junction temperatur e of
the Stratix device and can be used for inte lli gent power managem ent.
The diode requires two pins (tempdiodep and tempdioden) on the
Stratix device to connect to the external temperature-sensing device, as
shown in Figure 3–5. The temperatur e sensing diode is a passive element
and therefore can be used before the Stratix device is powered.
3–14 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Temperature Sensing Diode
Figure 3–5. External Temperature-Sensing Diode
Table 3–6 shows the specifications for bias voltage and current of the
Stratix temperature sensing diode.
Table 3–6. Temperature-Sensing Diode Electrical Characteristics
Parameter Minimum Typical Maximum Unit
IBIAS high 80 100 120 μA
IBIAS low 8 10 12 μA
VBP – VBN 0.3 0.9 V
VBN 0.7 V
Series resistance 3 W
Stratix Device
Temperature-Sensing
Device
tempdiodep
tempdioden
Altera Corporation 3–15
July 2005 Stratix Device Handbook, Volume 1
Configuration & Testing
The temperature-sensing diode works for the entire operating range
shown in Figure 3–6.
Figure 3–6. Temperature vs. Temperature-Sensing Diode Voltage
0.90
0.85
0.95
0.75
0.65
Voltage
(Across Diode)
Temperature ( C)
0.55
0.45
0.60
0.50
0.40
0.70
0.80
–55 –30 –520457095120
10 μA Bias Current
100 μA Bias Current
3–16 Altera Corporation
Stratix Device Handbook, Volume 1 July 2005
Temperature Sensing Diode
Altera Corporation 4–1
January 2006
4. DC & Switching
Characteristics
Operating
Conditions Stratix® dev ices are offered in both commercial and industrial grades.
Industrial devi ce s are offered in -6 and -7 spee d grad es and commercial
devices are of fer ed in -5 (faste st), -6, -7, and -8 speed grades. This section
specifies the operation conditions for operating junction temperature,
VCCINT and VCCIO voltage leve ls, and input voltage requirements. The
voltage specificat ions in this section ar e specified at the pins of the device
(and not the power supply). If the device operates outside these ranges,
then all DC and AC specifications are not guaranteed. Furthermore, the
reli abil ity of the device may be affected. The timing paramet ers in this
chapter apply to both commercial and industrial temperature ranges
unless otherwise stated.
Tables 4–1 through 4–8 provide information on absolute maximum
ratings.
Table 4–1. Stratix Device Absolute Maximum Ratings Notes (1), (2)
Symbol Parameter Conditions Minimum Maximum Unit
VCCINT Supply voltage With respect to ground –0.5 2.4 V
VCCIO –0.5 4.6 V
VIDC input voltage (3) –0.5 4.6 V
IOUT DC output current, per pin –25 40 mA
TSTG Storage temperature No bias –65 150 °C
TJJunction temperature BGA packages under bias 135 °C
Table 4–2. Stratix Device Recommended Operating Conditions (Part 1 of 2)
Symbol Parameter Conditions Minimum Maximum Unit
VCCINT Supply voltage for internal
logic and input buffers (4) 1.425 1.575 V
S51004-3.4
4–2 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Operating Conditions
VCCIO Supply voltage for output
buffers, 3.3-V operation (4), (5) 3.00 (3.135) 3.60 (3.465) V
Supply voltage for output
buffers, 2.5-V operation (4) 2.375 2.625 V
Supply voltage for output
buffers, 1.8-V operation (4) 1.71 1.89 V
Supply voltage for output
buffers, 1.5-V operation (4) 1.4 1.6 V
VIInput voltage (3), (6) –0.5 4.0 V
VOOutput voltage 0 VCCIO V
TJOperating junction
temperature For commercial use 0 85 °C
For industrial use –40 100 °C
Table 4–3. Stratix Device DC Operating Conditions Note (7) (Part 1 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Unit
IIInput pin leakage
current VI = VCCIOmax to 0 V (8) –10 10 μA
IOZ Tri-stated I/O pin
leakage current VO = VCCIOmax to 0 V (8) –10 10 μA
ICC0 VCC supply current
(standby) (All
memory blocks in
power-down mode)
VI = ground, no load, no
toggling inputs mA
EP1S10. VI = ground, no
load, no toggling inputs 37 mA
EP1S20. VI = ground, no
load, no toggling inputs 65 mA
EP1S25. VI = ground, no
load, no toggling inputs 90 mA
EP1S30. VI = ground, no
load, no toggling inputs 114 mA
EP1S40. VI = ground, no
load, no toggling inputs 145 mA
EP1S60. VI = ground, no
load, no toggling inputs 200 mA
EP1S80. VI = ground, no
load, no toggling inputs 277 mA
Table 4–2. Stratix Device Recommended Operating Conditions (Part 2 of 2)
Symbol Parameter Conditions Minimum Maximum Unit
Altera Corporation 4–3
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
RCONF V alue of I/O pin pull-
up resistor before
and during
configuration
VCCIO = 3.0 V (9) 20 50 kΩ
VCCIO = 2.375 V (9) 30 80 kΩ
VCCIO = 1.71 V (9) 60 150 kΩ
Table 4–4. LV TTL Specifications
Symbol Parameter Conditions Minimum Maximum Unit
VCCIO Output supply voltage 3.0 3.6 V
VIH High-level input voltage 1.7 4.1 V
VIL Low-level input voltage –0.5 0.7 V
VOH High-level output voltage IOH = –4 to –24 mA (10) 2.4 V
VOL Low-level output voltage IOL = 4 to 24 mA (10) 0.45 V
Table 4–5. LVCMOS Specifications
Symbol Parameter Conditions Minimum Maximum Unit
VCCIO Output supply voltage 3.0 3.6 V
VIH High-level input voltage 1.7 4.1 V
VIL Low-level input voltage –0.5 0.7 V
VOH High-level output voltage VCCIO = 3.0,
IOH = –0.1 mA VCCIO – 0.2 V
VOL Low-level output voltage VCCIO = 3.0,
IOL = 0.1 mA 0.2 V
Table 4–6. 2.5-V I/O Specifications
Symbol Parameter Conditions Minimum Maximum Unit
VCCIO Output supply voltage 2.375 2.625 V
VIH High-level input voltage 1.7 4.1 V
VIL Low-level input voltage –0.5 0.7 V
VOH High-level output voltage IOH = –1 mA (10) 2.0 V
VOL Low-level output voltage IOL = 1 mA (10) 0.4 V
Table 4–3. Stratix Device DC Operating Conditions Note (7) (Part 2 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Unit
4–4 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Operating Conditions
Table 4–7. 1.8-V I/O Specifications
Symbol Parameter Conditions Minimum Maximum Unit
VCCIO Output supply voltage 1.65 1.95 V
VIH High-level input voltage 0.65 × VCCIO 2.25 V
VIL Low-level input voltage –0.3 0.35 × VCCIO V
VOH High-level output voltage IOH = –2 to –8 mA (10) VCCIO – 0.45 V
VOL Low-level output voltage IOL = 2 to 8 mA (10) 0.45 V
Table 4–8. 1.5-V I/O Specifications
Symbol Parameter Conditions Minimum Maximum Unit
VCCIO Output supply voltage 1.4 1.6 V
VIH High-level input voltage 0.65 × VCCIO VCCIO + 0.3 V
VIL Low-level input voltage –0.3 0.35 × VCCIO V
VOH High-level output voltage IOH = –2 mA (10) 0.75 × VCCIO V
VOL Low-level output voltage IOL = 2 mA (10) 0.25 × VCCIO V
Notes to Tables 4–1 through 4–8:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Conditions beyond those listed in Table 4–1 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
(3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than
100 mA and periods shorter than 20 ns, or overshoot to the voltage shown in Table 4–9, based on input duty cycle
for input currents less than 100 mA. The oversh oot is dependent upon duty cycle of the signal. The DC ca se is
equivalent to 100% duty cycle.
(4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5) VCCIO maximum and minimum conditions for LVPECL, LVDS, and 3.3-V PCML are shown in parentheses.
(6) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(7) Typical values are for TA = 25°C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
(8) This value is specified for normal device operation. The value may vary during power-up. This applies for all
VCCIO settings (3.3, 2.5, 1.8, and 1.5 V).
(9) Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO.
(10) Drive strength is programmable a cco rding to the values shown in the Stratix Architecture chapter of the Stratix
Device Handbook, Volume 1.
Table 4–9. Overshoot Input V oltage with Respect to Duty Cycle (Part 1 of 2)
Vin (V) Maximum Duty Cycle (%)
4.0 100
4.1 90
4.2 50
Altera Corporation 4–5
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Figures 4–1 and 4–2 show receiver input and transmitter output
waveforms, respectively, for all differential I/O standards (LVDS, 3.3-V
PCML, LVPECL, and HyperTransport technology).
Figure 4–1. Receiver Input Waveforms for Differe ntial I/O Standards
4.3 30
4.4 17
4.5 10
Table 4–9. Overshoot Input V oltage with Respect to Duty Cycle (Part 2 of 2)
Vin (V) Maximum Duty Cycle (%)
Single-Ended Waveform
Differential W aveform
Positive Channel (p) = VIH
Negative Channel (n) = VIL
Ground
VID
VID
VID
VCM
p − n = 0 V
4–6 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Operating Conditions
Figure 4–2. Transmitter Output Waveforms for Differential I/O Standards
Tables 4–10 through 4–33 recommend operating conditions,
DC operating conditions, and capacitance for 1.5-V Stratix
devices.
Single-Ended W aveform
Differential W aveform
Positive Channel (p) = VOH
Negative Channel (n) = VOL
Ground
VOD
VOD
VOD
p − n = 0 V
VCM
Table 4–10. 3.3-V LVDS I/O Specifications (Part 1 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO I/O supply voltage 3.135 3.3 3.465 V
VID (6) Input differential voltage
swing (single-ended) 0.1 V ≤ VCM < 1.1 V
W = 1 through 10 300 1,000 mV
1.1 V ≤ VCM ≤ 1.6 V
W = 1 200 1,000 mV
1.1 V ≤ VCM ≤ 1.6 V
W = 2 through10 100 1,000 mV
1.6 V < VCM ≤ 1.8 V
W = 1 through 10 300 1,000 mV
Altera Corporation 4–7
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
VICM Input common mode
voltage (6) LVDS
0.3 V ≤ VID ≤ 1.0 V
W = 1 through 10
100 1,100 mV
LVDS
0.3 V ≤ VID ≤ 1.0 V
W = 1 through 10
1,600 1,800 mV
LVDS
0.2 V ≤ VID ≤ 1.0 V
W = 1
1,100 1,600 mV
LVDS
0.1 V ≤ VID ≤ 1.0 V
W = 2 through 10
1,100 1,600 mV
VOD (1) Output differential voltage
(single-ended) RL = 100 Ω250 375 550 mV
Δ VOD Change in VOD between
high and low RL = 100 Ω50 mV
VOCM Output common mode
voltage RL = 100 Ω1,125 1,200 1,375 mV
Δ VOCM Change in VOCM between
high and low RL = 100 Ω50 mV
RLReceiver differential input
discrete resistor (external
to Stratix devices)
90 100 110 Ω
Table 4–10. 3.3-V LVDS I/O Specifications (Part 2 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Unit
4–8 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Operating Conditions
Table 4–11. 3.3-V PCML Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO I/O supply voltage 3.135 3.3 3.465 V
VID (peak-
to-peak) Input differential voltage
swing (single-ended) 300 600 mV
VICM Input common mode
voltage 1.5 3.465 V
VOD Output differential voltage
(single-ended) 300 370 500 mV
Δ VOD Change in VOD between
high and low 50 mV
VOCM Output common mode
voltage 2.5 2.85 3.3 V
Δ VOCM Change in VOCM between
high and low 50 mV
VTOutput termination voltage VCCIO V
R1Output external pull-up
resistors 45 50 55 Ω
R2Output external pull-up
resistors 45 50 55 Ω
Table 4–12. LVPECL Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO I/O supply voltage 3.135 3.3 3.465 V
VID (peak-
to-peak) Input differential voltage
swing (single-ended) 300 1,000 mV
VICM Input common mode
voltage 12V
VOD Output differential voltage
(single-ended) RL = 100 Ω525 700 970 mV
VOCM Output common mode
voltage RL = 100 Ω1.5 1.7 1.9 V
RLReceiver differential input
resistor 90 100 110 Ω
Altera Corporation 4–9
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Table 4–13. HyperTransport Technology Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO I/O supply voltage 2.375 2.5 2.625 V
VID (peak-
to-peak) Input differential voltage
swing (single-ended) 300 900 mV
VICM Input common mode
voltage 300 900 mV
VOD Output differential voltage
(single-ended) RL = 100 Ω380 485 820 mV
Δ VOD Change in VOD between
high and low RL = 100 Ω50 mV
VOCM Output common mode
voltage RL = 100 Ω440 650 780 mV
Δ VOCM Change in VOCM between
high and low RL = 100 Ω50 mV
RLReceiver differential input
resistor 90 100 110 Ω
Table 4–14. 3.3-V PCI Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO Output supply voltage 3.0 3.3 3.6 V
VIH High-level input voltage 0.5 ×
VCCIO
VCCIO +
0.5 V
VIL Low-level input voltage –0.5 0.3 ×
VCCIO
V
VOH High-level output voltage IOUT = –500 μA0.9 ×
VCCIO
V
VOL Low-level output voltage IOUT = 1,500 μA0.1 ×
VCCIO
V
4–10 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Operating Conditions
Table 4–15. PCI-X 1.0 Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO Output supply voltage 3.0 3.6 V
VIH High-level input voltage 0.5 ×
VCCIO
VCCIO +
0.5 V
VIL Low-level input voltage –0.5 0.35 ×
VCCIO
V
VIPU Input pull-up voltage 0.7 ×
VCCIO
V
VOH High-level output voltage IOUT = –500 μA0.9 ×
VCCIO
V
VOL Low-level output voltage IOUT = 1,500 μA0.1 ×
VCCIO
V
Table 4–16. GTL+ I/O Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VTT Termination voltage 1.35 1.5 1.65 V
VREF Reference voltage 0.88 1.0 1.12 V
VIH High-level input voltage VREF + 0.1 V
VIL Low-level input voltage VREF – 0.1 V
VOL Low-level output voltage IOL = 34 mA (3) 0.65 V
Table 4–17. GTL I/O Specificatio ns
Symbol Parameter Conditions Minimum Typical Maximum Unit
VTT Termination voltage 1.14 1.2 1.26 V
VREF Reference voltage 0.74 0.8 0.86 V
VIH High-level input voltage VREF +
0.05 V
VIL Low-level input voltage VREF –
0.05 V
VOL Low-level output voltage IOL = 40 mA (3) 0.4 V
Altera Corporation 4–11
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Table 4–18. SSTL-18 Class I Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO Output supply voltage 1.65 1.8 1.95 V
VREF Reference voltage 0.8 0.9 1.0 V
VTT Termination voltage V REF – 0.04 VREF VREF + 0.04 V
VIH(DC) High-lev el DC input v oltage VREF +
0.125 V
VIL(DC) Low-level DC input voltage VREF – 0.125 V
VIH(AC) High-le v el A C input v oltage VREF +
0.275 V
VIL(AC) Low-level AC input voltage VREF – 0.275 V
VOH High-level output voltage IOH = –6.7 mA
(3) VTT + 0.475 V
VOL Low-level output voltage IOL = 6.7 mA (3) VTT – 0.475 V
Table 4–19. SSTL-18 Class II Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO Output supply voltage 1.65 1.8 1.95 V
VREF Reference voltage 0.8 0.9 1.0 V
VTT Termination voltage V REF – 0.04 VREF VREF + 0.04 V
VIH(DC) High-lev el DC input v oltage VREF +
0.125 V
VIL(DC) Low-level DC input voltage VREF – 0.125 V
VIH(AC) High-le v el A C input v oltage VREF +
0.275 V
VIL(AC) Low-level AC input voltage VREF – 0.275 V
VOH High-level output voltage IOH = –13.4 mA
(3) VTT + 0.630 V
VOL Low-level output voltage IOL = 13.4 mA (3) VTT – 0.630 V
4–12 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Operating Conditions
Table 4–20. SSTL-2 Class I Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO Output supply voltage 2.375 2.5 2.625 V
VTT Termination voltage V REF – 0.04 VREF VREF + 0.04 V
VREF Reference voltage 1.15 1.25 1.35 V
VIH(DC) High-lev el DC input v oltage VREF + 0.18 3.0 V
VIL(DC) Low-level DC input voltage –0.3 VREF – 0.18 V
VIH(AC) High-le v el A C input v oltage VREF + 0.35 V
VIL(AC) Low-level AC input voltage VREF – 0.35 V
VOH High-level output voltage IOH = –8.1 mA
(3) VTT + 0.57 V
VOL Low-level output voltage IOL = 8.1 mA (3) VTT – 0.57 V
Table 4–21. SSTL-2 Class II Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO Output supply voltage 2.375 2.5 2.625 V
VTT Termination voltage V REF – 0.04 VREF VREF + 0.04 V
VREF Reference voltage 1.15 1.25 1.35 V
VIH(DC) High-lev el DC input v oltage VREF + 0.18 VCCIO + 0.3 V
VIL(DC) Low-level DC input voltage –0.3 VREF – 0.18 V
VIH(AC) High-le v el A C input v oltage VREF + 0.35 V
VIL(AC) Low-level AC input voltage VREF – 0.35 V
VOH High-level output voltage IOH = –16.4 mA
(3) VTT + 0.76 V
VOL Low-level output voltage IOL = 16.4 mA (3) VTT – 0.76 V
Table 4–22. SSTL-3 Class I Specificatio ns (Part 1 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO Output supply voltage 3.0 3.3 3.6 V
VTT Termination voltage V REF – 0.05 VREF VREF + 0.05 V
VREF Reference voltage 1.3 1.5 1.7 V
VIH(DC) High-lev el DC input v oltage VREF + 0.2 VCCIO + 0.3 V
VIL(DC) Low-level DC input voltage –0.3 VREF – 0.2 V
VIH(AC) High-le v el A C input v oltage VREF + 0.4 V
Altera Corporation 4–13
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
VIL(AC) Low-level AC input voltage VREF – 0.4 V
VOH High-level output voltage IOH = –8 mA (3) VTT + 0.6 V
VOL Low-level output voltage IOL = 8 mA (3) VTT – 0.6 V
Table 4–23. SSTL-3 Class II Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO Output supply voltage 3.0 3.3 3.6 V
VTT Termination voltage V REF – 0.05 VREF VREF + 0.05 V
VREF Reference voltage 1.3 1.5 1.7 V
VIH(DC) High-lev el DC input v oltage VREF + 0.2 VCCIO + 0.3 V
VIL(DC) Low-level DC input voltage –0.3 VREF – 0.2 V
VIH(AC) High-le v el A C input v oltage VREF + 0.4 V
VIL(AC) Low-level AC input voltage VREF – 0.4 V
VOH High-level output voltage IOH = –16 mA (3) VTT + 0.8 V
VOL Low-level output voltage IOL = 16 mA (3) VTT – 0.8 V
Table 4–24. 3.3-V AGP 2× Sp ecifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO Output supply voltage 3.15 3.3 3.45 V
VREF Reference voltage 0.39 × VCCIO 0.41 × VCCIO V
VIH High-level input voltage (4) 0.5 × VCCIO VCCIO + 0.5 V
VIL Low-level input voltage (4) 0.3 × VCCIO V
VOH High-level output voltage IOUT = –0.5 mA 0.9 × VCCIO 3.6 V
VOL Low-level output voltage IOUT = 1.5 mA 0.1 × VCCIO V
Table 4–25. 3.3-V AGP 1× Sp ecifications (Part 1 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO Output supply voltage 3.15 3.3 3.45 V
VIH High-level input voltage (4) 0.5 × VCCIO VCCIO + 0.5 V
VIL Low-level input voltage (4) 0.3 × VCCIO V
Table 4–22. SSTL-3 Class I Specificatio ns (Part 2 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Unit
4–14 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Operating Conditions
VOH High-level output voltage IOUT = –0.5 mA 0.9 × VCCIO 3.6 V
VOL Low-level output voltage IOUT = 1.5 mA 0.1 × VCCIO V
Table 4–26. 1.5-V HSTL Class I Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO Output supply voltage 1.4 1.5 1.6 V
VREF Input reference voltage 0.68 0.75 0.9 V
VTT Termination voltage 0.7 0.75 0.8 V
VIH (DC) DC high-level input voltage VREF + 0.1 V
VIL (DC) DC low-level input voltage –0.3 VREF – 0.1 V
VIH (AC) AC high-level input voltage VREF + 0.2 V
VIL (AC) AC low-level input voltage VREF – 0.2 V
VOH High-level output voltage IOH = –8 mA (3) VCCIO – 0.4 V
VOL Low-level output voltage IOL = 8 mA (3) 0.4 V
Table 4–27. 1.5-V HSTL Class II Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO Output supply voltage 1.4 1.5 1.6 V
VREF Input reference voltage 0.68 0.75 0.9 V
VTT Termination voltage 0.7 0.75 0.8 V
VIH (DC) DC high-level input voltage VREF + 0.1 V
VIL (DC) DC low-level input voltage –0.3 VREF – 0.1 V
VIH (AC) AC high-level input voltage VREF + 0.2 V
VIL (AC) AC low-level input voltage VREF – 0.2 V
VOH High-level output voltage IOH = –16 mA (3) VCCIO – 0.4 V
VOL Low-level output voltage IOL = 16 mA (3) 0.4 V
Table 4–25. 3.3-V AGP 1× Sp ecifications (Part 2 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Unit
Altera Corporation 4–15
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Table 4–28. 1.8-V HSTL Class I Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO Output supply voltage 1.65 1.80 1.95 V
VREF Input reference voltage 0.70 0.90 0.95 V
VTT Termination voltage VCCIO ×
0.5 V
VIH (DC) DC high-level input voltage VREF + 0.1 V
VIL (DC) DC low-level input voltage –0.5 VREF – 0.1 V
VIH (AC) AC high-level input voltage VREF + 0.2 V
VIL (AC) AC low-level input voltage VREF – 0.2 V
VOH High-level output voltage IOH = –8 mA (3) VCCIO – 0.4 V
VOL Low-level output voltage IOL = 8 mA (3) 0.4 V
Table 4–29. 1.8-V HSTL Class II Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO Output supply voltage 1.65 1.80 1.95 V
VREF Input reference voltage 0.70 0.90 0.95 V
VTT Termination voltage VCCIO ×
0.5 V
VIH (DC) DC high-level input voltage VREF + 0.1 V
VIL (DC) DC low-level input voltage –0.5 VREF – 0.1 V
VIH (AC) AC high-level input voltage VREF + 0.2 V
VIL (AC) AC low-level input voltage VREF – 0.2 V
VOH High-level output voltage IOH = –16 mA (3) VCCIO – 0.4 V
VOL Low-level output voltage IOL = 16 mA (3) 0.4 V
Table 4–30. 1.5-V Differential HSTL Class I & Class II Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO I/O supply voltage 1.4 1.5 1.6 V
VDIF (DC) DC input differential
voltage 0.2 V
VCM (DC) DC common mode input
voltage 0.68 0.9 V
VDIF (AC) AC differential input
voltage 0.4 V
4–16 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Operating Conditions
Table 4–31. CTT I/O Specifications
Symbol Parameter Conditions Minimum Typical Maximum Unit
VCCIO Output supply voltage 2.05 3.3 3.6 V
VTT/VREF Termination and input
reference voltage 1.35 1.5 1.65 V
VIH High-level input voltage VREF + 0.2 V
VIL Low-level input voltage VREF – 0.2 V
VOH High-level output voltage IOH = –8 mA VREF + 0.4 V
VOL Low-level output voltage IOL = 8 mA VREF – 0.4 V
IOOutput leakage current
(when output is high Z)GND ≤ VOUT ≤
VCCIO
–10 10 μA
Table 4–32. Bus Hold Parameters
Parameter Conditions
VCCIO Level
Unit
1.5 V1.8 V2.5 V3.3 V
Min Max Min Max Min Max Min Max
Low sustaining
current VIN > VIL
(maximum) 25 30 50 70 μA
High sustaining
current VIN < VIH
(minimum) -25 –30 –50 –70 μA
Low overdrive
current 0 V < VIN <
VCCIO
160 200 300 500 μA
High overdrive
current 0 V < VIN <
VCCIO
-160 –200 –300 –500 μA
Bus-hold trip
point 0.5 1.0 0.68 1.07 0.7 1.7 0.8 2.0 V
Altera Corporation 4–17
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Power
Consumption Altera® offers two ways to calculate power for a design: the Altera web
power calculator and the PowerGaug eTM feature in the Quartus®II
software.
The interactive power calculator on the Altera web site is typically used
prior to designing the FPGA in order to get a magnitude estimate of the
device power . The Quartus II software PowerGauge feature allows you to
apply test vectors against your design for more accurate power
consumption modeling.
In both cases, these calcu lati ons should only be used as an estimation of
power, not as a specification.
Stratix devices r equire a certain amount of power-up current to
successfully power up because of the small process geometry on which
they are fabricated.
Table 4–34 shows the maximum power-up current (ICCINT) required to
power a Stratix device. This specification is for commercial operating
conditions. Measurements were performed with an isolated Stratix
device on the board to characterize the power-up current of an isolated
Table 4–33. Stratix Device Capacitance Note (5)
Symbol Parameter Minimum Typical Maximum Unit
CIOTB Input capacitance on I/O pins in I/O banks
3, 4, 7, and 8. 11.5 pF
CIOLR Input capacitance on I/O pins in I/O banks
1, 2, 5, and 6, including high-speed
differential receiver and transmitter pins.
8.2 pF
CCLKTB Input capacitance on top/bottom clock input
pins: CLK[4:7] and CLK[12:15].11.5 pF
CCLKLR Input capacitance on left/right clock inputs:
CLK1, CLK3, CLK8, CLK10.7.8 pF
CCLKLR+ Input capacitance on left/right clock inputs:
CLK0, CLK2, CLK9, and CLK11.4.4 pF
Notes to Tables 4–10 through 4–33:
(1) When tx_outclock port of altlvds_tx megafunctio n is 717 MHz, VOD(min) = 235 mV on the o utput clock pin.
(2) Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO.
(3) Drive strength is programmable according to the values shown in the Stratix Architecture chapter of the Stratix
Device Handbook, Volume 1.
(4) VREF specifies the center point of the switching range.
(5) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR ). Measurement
accuracy is within ±0.5 pF.
(6) VIO and VCM have multiple ranges and values for J=1 through 10.
4–18 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Power Consumption
device. Decoupl ing c apacitors were not used in thi s measu rement. To
factor in the current for decoupling capacitors, su m u p the current for
each capacitor using the following equation:
I = C (dV/dt)
If the regulator or power supply minimum output current is mor e than
the Stratix device requires, then the device may consume more current
than the maximum current listed in Table 4–34. However, the device does
not requir e any more curr ent to successfully power up than what is listed
in Table 4–34.
The exact amount of current consumed varies according to the process,
temperature, and power ramp rate. Stratix devices typically require less
current during power up than shown in Table 4–34. The user-mode
current during device operation is generally higher than the power-up
current.
The duration of the ICCINT power-up requirement depends on the VCCINT
voltage supply rise time. The power-up current consumption drops when
the VCCINT supply reaches approximately 0.75 V.
Table 4–34. Stratix Power-Up Current (ICCINT) Requirements Note (1)
Device Power-Up Cu rrent Requirement Unit
Typical Maximum
EP1S10 250 700 mA
EP1S20 400 1,200 mA
EP1S25 500 1,500 mA
EP1S30 550 1,900 mA
EP1S40 650 2,300 mA
EP1S60 800 2,600 mA
EP1S80 1,000 3,000 mA
Note to Table 4–34:
(1) The maximum test conditions are for 0°C and typical test conditions are for
40°C.
Altera Corporation 4–19
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Timing Model The DirectDrive™ technology and Mult iTrack™ interconnect ensure
predicta ble performance, accurate simulation, and accurate timing
analysis acr oss all Stratix device densities and speed grad es. This section
describes and specifies the performance, internal, external, and PLL
timing specific ations .
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
Preliminary & Final Timing
T iming models ca n have either pre liminary or final status. The Quartus II
software issues an informational message d uring the d esign compil ation
if the timing models are preliminary. Table 4–35 shows the status of the
Stratix device timing models.
Prelim inary status mea ns the timing mode l is subjec t to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These test s are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers r efle ct the actual perf ormance of the device under worst-
case voltage and junction temperature conditions.
Table 4–35. Stratix Device T iming Model Status
Device Preliminary Final
EP1S10 v
EP1S20 v
EP1S25 v
EP1S30 v
EP1S40 v
EP1S60 v
EP1S80 v
4–20 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Performance
Table 4–36 shows Stratix performance for some common designs. All
performance values were obtaine d with Quartus II software compilation
of LPM, or MegaCore® functions for the FIR and FFT designs.
Table 4–36. Stratix Performance (Part 1 of 2) Notes (1),(2)
Applications
Resources Used Performance
LEs TriMatrix
Memory
Blocks
DSP
Blocks
-5
Speed
Grade
-6
Speed
Grade
-7
Speed
Grade
-8
Speed
Grade Units
LE 16-to-1 multiplexer (1) 22 0 0 407.83 324.56 288.68 228.67 MHz
32-to-1 multiplexer (3) 46 0 0 318.26 255.29 242.89 185.18 MHz
16-bit counter 16 0 0 422.11 422.11 390.01 348.67 MHz
64-bit counter 64 0 0 321.85 290.52 261.23 220.5 MHz
TriMatrix
memory
M512 block
Simple dual-port RAM
32 × 18 bit 0 1 0 317.76 277.62 241.48 205.21 MHz
FIFO 32 × 18 bit 30 1 0 319.18 278.86 242.54 206.14 MHz
TriMatrix
memory
M4K block
Simple dual-port RAM
128 × 36 bit 0 1 0 290.86 255.55 222.27 188.89 MHz
True dual-port RAM
128 × 18 bit 0 1 0 290.86 255.55 222.27 188.89 MHz
FIFO 128 × 36 bit 34 1 0 290.86 255.55 222.27 188.89 MHz
TriMatrix
memory
M-RAM
block
Single port
RAM 4K × 144 bit 1 1 0 255.95 223.06 194.06 164.93 MHz
Simple dual-port
RAM 4K × 144 bit 0 1 0 255.95 233.06 194.06 164.93 MHz
True dual-port
RAM 4K × 144 bit
0 1 0 255.95 233.06 194.06 164.93 MHz
Single port
RAM 8K × 72 bit 0 1 0 278.94 243.19 211.59 179.82 MHz
Simple dual-port
RAM 8K × 72 bit
0 1 0 255.95 223.06 194.06 164.93 MHz
True dual-port
RAM 8K × 72 bit
0 1 0 255.95 223.06 194.06 164.93 MHz
Single port
RAM 16K × 36 bit 0 1 0 280.66 254.32 221.28 188.00 MHz
Simple dual-port
RAM 16K × 36 bit
0 1 0 269.83 237.69 206.82 175.74 MHz
Altera Corporation 4–21
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
TriMatrix
memory
M-RAM
block
True dual-port
RAM 16K × 36 bit
0 1 0 269.83 237.69 206.82 175.74 MHz
Single port
RAM 32K × 18 bit 0 1 0 275.86 244.55 212.76 180.83 MHz
Simple dual-port
RAM 32K × 18 bit
0 1 0 275.86 244.55 212.76 180.83 MHz
True dual-port
RAM 32K × 18 bit
0 1 0 275.86 244.55 212.76 180.83 MHz
Single port
RAM 64K × 9 bit 0 1 0 287.85 253.29 220.36 187.26 MHz
Simple dual-port
RAM 64K × 9 bit
0 1 0 287.85 253.29 220.36 187.26 MHz
True dual-port
RAM 64K × 9 bit
0 1 0 287.85 253.29 220.36 187.26 MHz
DSP block 9 × 9-bit multiplier (3) 0 0 1 335.0 293.94 255.68 217.24 MHz
18 × 18-bit multiplier
(4) 0 0 1 278.78 237.41 206.52 175.50 MHz
36 × 36-bit multiplier
(4) 0 0 1 148.25 134.71 117.16 99.59 MHz
36 × 36-bit multiplier
(5) 0 0 1 278.78 237.41 206.52 175.5 MHz
18-bit, 4-tap FIR filter 0 0 1 278.78 237.41 206.52 175.50 MHz
Larger
Designs 8-bit, 16-tap parallel
FIR filter 58 0 4 141.26 133.49 114.88 100.28 MHz
8-bit, 1,024-point FFT
function 870 5 1 261.09 235.51 205.21 175.22 MHz
Notes to Table 4–36:
(1) These design performance numbers were obtained using the Quartus II software.
(2) Numbers not listed will be included in a future version of the data sheet.
(3) This application uses registered inputs and outputs.
(4) This application uses registered multiplier input and output stages within the DSP block.
(5) This application use s r eg ister ed multi plier i nput, p ipeli ne, and outpu t stage s within t he DSP
block.
Table 4–36. Stratix Performance (Part 2 of 2) Notes (1),(2)
Applications
Resources Used Performance
LEs TriMatrix
Memory
Blocks
DSP
Blocks
-5
Speed
Grade
-6
Speed
Grade
-7
Speed
Grade
-8
Speed
Grade Units
4–22 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of dev ic e dens ity. Tables 4–37 through 4–42 describe the
Stratix device internal timing microparameters for LEs, IOEs, TriMatrix™
memory structures, DSP blocks, and MultiTrack interconnects.
Table 4–37. LE Internal Timing Microparameter Descriptions
Symbol Parameter
tSU LE register setup time before clock
tHLE register hold time after clock
tCO LE register clock-to-output delay
tLUT LE combinatorial LUT delay for data-in to data-out
tCLR Minimum clear pulse width
tPRE Minimum preset pulse width
tCLKHL Register minimum clock high or low time. The maximum core
clock frequency can be calculated by 1/(2 × tCLKHL).
Table 4–38. IOE Internal Timing Microparameter Descriptions
Symbol Parameter
tSU_R Row IOE input register setup time
tSU_C Column IOE input register setup time
tHIOE input and output register hold time after clock
tCO_R Row IOE input and output register clock-to-output delay
tCO_C Column IOE input and output register clock-to-output delay
tPIN2COMBOUT_R Row input pin to IOE combinatorial output
tPIN2COMBOUT_C Column input pin to IOE combinatorial output
tCOMBIN2PIN_R Row IOE data input to combinatorial output pin
tCOMBIN2PIN_C Column IOE data input to combinatorial output pin
tCLR Minimum clear pulse width
tPRE Minimum preset pulse width
tCLKHL Register minimum clock high or lo w time. The maximum I/O
clock frequency can be calculated by 1/(2 × tCLKHL).
P erformance may also be aff ected by I/O timing, use of PLL,
and I/O programmable settings.
Altera Corporation 4–23
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Table 4–39. DSP Block Internal Timing Microparameter Descriptions
Symbol Parameter
tSU Input, pipeline, and output register setup time before clock
tHInput, pipeline, and output register hold time after clock
tCO Input, pipeline, and output register clock-to-output delay
tINREG2PIPE9 Input Register to DSP Block pipeline register in 9 ×9-bit
mode
tINREG2PIPE18 Input Register to DSP Block pipeline register in 18 ×18-bit
mode
tPIPE2OUTREG2ADD DSP Block Pipeline Register to output register delay in Two-
Multipliers Adder mode
tPIPE2OUTREG4ADD DSP Block Pipeline Register to output register dela y in F our-
Multipliers Adder mode
tPD9 Combinatorial input to output delay for 9 ×9
tPD18 Combinatorial input to output delay for 18 ×18
tPD36 Combinatorial input to output delay for 36 ×36
tCLR Minimum clear pulse width
tCLKHL Register minimum clock high or low time. This is a limit on
the min time for the clock on the registers in these blocks.
The actual performance is dependent upon the internal
point-to-point delays in the blocks and may give slower
performance as shown in Table 4–36 on page 4–20 and as
reported by the timing analyzer in the Quartus II software.
4–24 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Table 4–40. M512 Block Internal Timing Microparameter Descriptions
Symbol Parameter
tM512RC Synchronous read cycle time
tM512WC Synchronous write cycle time
tM512WERESU Write or read enable setup time before clock
tM512WEREH Write or read enable hold time after clock
tM512CLKENSU Clock enable setup time before clock
tM512CLKENH Clock enable hold time after clock
tM512DATASU Data setup time before clock
tM512DATAH Data hold time after clock
tM512WADDRSU Write address setup time before clock
tM512WADDRH Write address hold time after clock
tM512RADDRSU Read address setup time before clock
tM512RADDRH Read address hold time after clock
tM512DATACO1 Clock-to-output delay when using output registers
tM512DATACO2 Clock-to-output delay without output registers
tM512CLKHL Register minimum clock high or low time. This is a limit on
the min time for the clock on the registers in these blocks.
The actual performance is dependent upon the internal
point-to-point delays in the blocks and may give slower
performance as shown in Table 4–36 on page 4–20 and as
reported by the timing analyzer in the Quartus II software.
tM512CLR Minimum clear pulse width
Table 4–41. M4K Block Internal Timing Microparameter Descriptio ns (Part
1 of 2)
Symbol Parameter
tM4KRC Synchronous read cycle time
tM4KWC Synchronous write cycle time
tM4KWERESU Write or read enable setup time before clock
tM4KWEREH Write or read enable hold time after clock
tM4KCLKENSU Clock enable setup time before clock
tM4KCLKENH Clock enable hold time after clock
tM4KBESU Byte enable setup time before clock
tM4KBEH Byte enable hold time after clock
tM4KDATAASU A port data setup time before clock
Altera Corporation 4–25
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
tM4KDATAAH A port data hold time after clock
tM4KADDRASU A port address setup time before clock
tM4KADDRAH A port address hold time after clock
tM4KDATABSU B port data setup time before clock
tM4KDATABH B port data hold time after clock
tM4KADDRBSU B port address setup time before clock
tM4KADDRBH B port address hold time after clock
tM4KDATACO1 Clock-to-output delay when using output registers
tM4KDATACO2 Clock-to-output delay without output registers
tM4KCLKHL Register minimum clock high or low time. This is a limit on
the min time for the clock on the registers in these blocks.
The actual performance is dependent upon the internal
point-to-point delays in the blocks and may give slower
performance as shown inTable 4–36 on page 4–20 and as
reported by the timing analyzer in the Quartus II software.
tM4KCLR Minimum clear pulse width
Table 4–42. M-RAM Block Internal Timing Microparameter
Descriptions (Part 1 of 2)
Symbol Parameter
tMRAMRC Synchronous read cycle time
tMRAMWC Synchronous write cycle time
tMRAMWERESU Write or read enable setup time before clock
tMRAMWEREH Write or read enable hold time after clock
tMRAMCLKENSU Clock enable setup time before clock
tMRAMCLKENH Clock enable hold time after clock
tMRAMBESU Byte enable setup time before clock
tMRAMBEH Byte enable hold time after clock
tMRAMDATAASU A port data setup time before clock
tMRAMDATAAH A port data hold time after clock
tMRAMADDRASU A port address setup time before clock
tMRAMADDRAH A port address hold time after clock
tMRAMDATABSU B port setup time before clock
Table 4–41. M4K Block Internal Timing Microparameter Descriptio ns (Part
2 of 2)
Symbol Parameter
4–26 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
tMRAMDATABH B port hold time after clock
tMRAMADDRBSU B port address setup time before clock
tMRAMADDRBH B port address hold time after clock
tMRAMDATACO1 Clock-to-output delay when using output registers
tMRAMDATACO2 Clock-to-output delay without output registers
tMRAMCLKHL Register minimum clock high or low time. This is a limit on
the min time for the clock on the registers in these blocks.
The actual performance is dependent upon the internal
point-to-point delays in the blocks and may give slower
performance as shown in Table 4–36 on page 4–20 and as
reported by the timing analyzer in the Quartus II software.
tMRAMCLR Minimum clear pulse width.
Table 4–42. M-RAM Block Internal Timing Microparameter
Descriptions (Part 2 of 2)
Symbol Parameter
Altera Corporation 4–27
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Figure 4–3 shows the TriMatrix memory waveforms for the M512, M4K,
and M-RAM timing parameters shown in Tables 4–40 through 4–42.
Figure 4–3. Dual-Port RAM Timing Microparameter Waveform
Internal timing parameters are specified on a speed grade basis
independent of dev ic e dens ity. Tables 4–44 through 4–50 show the
internal timing microparamet e r s for LEs, IOEs, TriMatrix memory
structures, DSP blocks, and MultiTrack interconnects.
wrclock
wren
wraddress
data-in
reg_data-out
an-1 an a0 a1 a2 a3 a4 a5
din-1 din din4 din5
rdclock
a6
din6
unreg_data-out
rden
rdaddress bn b0 b1 b2 b3
doutn-2 doutn-1 doutn
doutn-1 doutn dout0
t
WERESU
t
WEREH
t
DATACO1
t
DATACO2
t
DATASU
t
DATAH
t
WEREH
t
WERESU
t
WADDRSU
t
WADDRH
dout0
t
RC
Table 4–43. Routing Delay Internal Timing Microparameter
Descriptions (Part 1 of 2)
Symbol Parameter
tR4 Delay for an R4 line with average loading; covers a distance of four
LAB columns.
tR8 Delay for an R8 line with aver age loading; cov ers a distance of eight
LAB columns.
tR24 Delay for an R24 line with average loading; covers a distance of 24
LAB columns.
4–28 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
tC4 Delay for a C4 line with average loading; covers a distance of four
LAB rows.
tC8 Delay for a C8 line with average loading; covers a distance of eight
LAB rows.
tC16 Delay for a C16 line with average loading; covers a distance of 16
LAB rows.
tLOCAL Local interconnect delay, for connections within a LAB, and for the
final routing hop of connections to LABs, DSP blocks, RAM blocks
and I/Os.
Table 4–43. Routing Delay Internal Timing Microparameter
Descriptions (Part 2 of 2)
Symbol Parameter
Table 4–44. LE Internal Timing Microparameters
Parameter -5 -6 -7 -8 Unit
Min Max Min Max Min Max Min Max
tSU 10 10 11 13 ps
tH100 100 114 135 ps
tCO 156 176 202 238 ps
tLUT 366 459 527 621 ps
tCLR 100 100 114 135 ps
tPRE 100 100 114 135 ps
tCLKHL 1000 1111 1190 1400 ps
Table 4–45. IOE Internal TSU Microparameter by Device Density (Part 1 of 2)
Device Symbol -5 -6 -7 -8 Unit
Min Max Min Max Min Max Min Max
EP1S10 tSU_R 76 80 80 80 ps
tSU_C 176 80 80 80 ps
EP1S20 tSU_R 76 80 80 80 ps
tSU_C 76 80 80 80 ps
EP1S25 tSU_R 276 280 280 280 ps
tSU_C 276 280 280 280 ps
EP1S30 tSU_R 76 80 80 80 ps
tSU_C 176 180 180 180 ps
Altera Corporation 4–29
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
EP1S40 tSU_R 76 80 80 80 ps
tSU_C 376 380 380 380 ps
EP1S60 tSU_R 276 280 280 280 ps
tSU_C 276 280 280 280 ps
EP1S80 tSU_R 426 430 430 430 ps
tSU_C 76 80 80 80 ps
Table 4–46. IOE Internal Timing Microparameters
Symbol -5 -6 -7 -8 Unit
Min Max Min Max Min Max Min Max
tH68 71 82 96 ps
tCO_R 171 179 206 242 ps
tCO_C 171 179 206 242 ps
tPIN2COMBOUT_R 1,234 1,295 1,490 1,753 ps
tPIN2COMBOUT_C 1,087 1,141 1,312 1,544 ps
tCOMBIN2PIN_R 3,894 4,089 4,089 4,089 ps
tCOMBIN2PIN_C 4,299 4,494 4,494 4,494 ps
tCLR 276 289 333 392 ps
tPRE 260 273 313 369 ps
tCLKHL 1,000 1,111 1,190 1,400 ps
Table 4–47. DSP Block Internal Timing Microparameters (Part 1 of 2)
Symbol -5 -6 -7 -8 Unit
Min Max Min Max Min Max Min Max
tSU 0000ps
tH67 75 86 101 ps
tCO 142 158 181 214 ps
tINREG2PIPE9 2,613 2,982 3,429 4,035 ps
tINREG2PIPE18 3,390 3,993 4,591 5,402 ps
Table 4–45. IOE Internal TSU Microparameter by Device Density (Part 2 of 2)
Device Symbol -5 -6 -7 -8 Unit
Min Max Min Max Min Max Min Max
4–30 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
tPIPE2OUTREG2ADD 2,002 2,203 2,533 2,980 ps
tPIPE2OUTREG4ADD 2,899 3,189 3,667 4,314 ps
tPD9 3,709 4,081 4,692 5,520 ps
tPD18 4,795 5,275 6,065 7,135 ps
tPD36 7,495 8,245 9,481 11,154 ps
tCLR 450 500 575 676 ps
tCLKHL 1,350 1,500 1,724 2,029 ps
Table 4–48. M512 Block Internal Timing Microparameters
Symbol -5 -6 -7 -8 Unit
Min Max Min Max Min Max Min Max
tM512RC 3,340 3,816 4,387 5,162 ps
tM512WC 3,138 3,590 4,128 4,860 ps
tM512WERESU 110 123 141 166 ps
tM512WEREH 34 38 43 51 ps
tM512CLKENSU 215 215 247 290 ps
tM512CLKENH –70 –70 –81 –95 ps
tM512DATASU 110 123 141 166 ps
tM512DATAH 34 38 43 51 ps
tM512WADDRSU 110 123 141 166 ps
tM512WADDRH 34 38 43 51 ps
tM512RADDRSU 110 123 141 166 ps
tM512RADDRH 34 38 43 51 ps
tM512DATACO1 424 472 541 637 ps
tM512DATACO2 3,366 3,846 4,421 5,203 ps
tM512CLKHL 1,000 1,111 1,190 1,400 ps
tM512CLR 170 189 217 255 ps
Table 4–47. DSP Block Internal Timing Microparameters (Part 2 of 2)
Symbol -5 -6 -7 -8 Unit
Min Max Min Max Min Max Min Max
Altera Corporation 4–31
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Table 4–49. M4K Block Internal Timing Microparameters
Symbol -5 -6 -7 -8 Unit
Min Max Min Max Min Max Min Max
tM4KRC 3,807 4,320 4,967 5,844 ps
tM4KWC 2,556 2,840 3,265 3,842 ps
tM4KWERESU 131 149 171 202 ps
tM4KWEREH 34 38 43 51 ps
tM4KCLKENSU 193 215 247 290 ps
tM4KCLKENH –63 –70 –81 –95 ps
tM4KBESU 131 149 171 202 ps
tM4KBEH 34 38 43 51 ps
tM4KDATAASU 131 149 171 202 ps
tM4KDATAAH 34 38 43 51 ps
tM4KADDRASU 131 149 171 202 ps
tM4KADDRAH 34 38 43 51 ps
tM4KDATABSU 131 149 171 202 ps
tM4KDATABH 34 38 43 51 ps
tM4KADDRBSU 131 149 171 202 ps
tM4KADDRBH 34 38 43 51 ps
tM4KDATACO1 571 635 729 858 ps
tM4KDATACO2 3,984 4,507 5,182 6,097 ps
tM4KCLKHL 1,000 1,111 1,190 1,400 ps
tM4KCLR 170 189 217 255 ps
Table 4–50. M-RAM Block Internal Timing Microparameters (Part 1 of 2)
Symbol -5 -6 -7 -8 Unit
Min Max Min Max Min Max Min Max
tMRAMRC 4,364 4,838 5,562 6,544 ps
tMRAMWC 3,654 4,127 4,746 5,583 ps
tMRAMWERESU 25 25 28 33 ps
tMRAMWEREH 18 20 23 27 ps
tMRAMCLKENSU 99 111 127 150 ps
tMRAMCLKENH –48 –53 –61 –72 ps
4–32 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Routing delays vary depending on the load on that specific routing line.
The Quartus II software r eports the routing delay information when
running the timing analysis for a design.
tMRAMBESU 25 25 28 33 ps
tMRAMBEH 18 20 23 27 ps
tMRAMDATAASU 25 25 28 33 ps
tMRAMDATAAH 18 20 23 27 ps
tMRAMADDRASU 25 25 28 33 ps
tMRAMADDRAH 18 20 23 27 ps
tMRAMDATABSU 25 25 28 33 ps
tMRAMDATABH 18 20 23 27 ps
tMRAMADDRBSU 25 25 28 33 ps
tMRAMADDRBH 18 20 23 27 ps
tMRAMDATACO1 1,038 1,053 1,210 1,424 ps
tMRAMDATACO2 4,362 4,939 5,678 6,681 ps
tMRAMCLKHL 1,000 1,111 1,190 1,400 ps
tMRAMCLR 135 150 172 202 ps
Table 4–51. Routing Delay Internal Timing Parameters
Symbol -5 -6 -7 -8 Unit
Min Max Min Max Min Max Min Max
tR4 268 295 339 390 ps
tR8 371 349 401 461 ps
tR24 465 512 588 676 ps
tC4 440 484 557 641 ps
tC8 577 634 730 840 ps
tC16 445 489 563 647 ps
tLOCAL 313 345 396 455 ps
Table 4–50. M-RAM Block Internal Timing Microparameters (Part 2 of 2)
Symbol -5 -6 -7 -8 Unit
Min Max Min Max Min Max Min Max
Altera Corporation 4–33
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
External Timing Parameters
External timing parameters are specified by device density and speed
grade. Figure 4–4 shows the pin-to-pin timing model for bidirectional
IOE pin timing. All r egisters are within the IOE.
Figure 4–4. External Timing in Stratix Devices
All external timing parameters reported in this section are defined with
respect to the dedicated clock pin as the starting point. All external I/O
timing parameters shown are for 3.3-V LVTTL I/O standard with the
24-mA current strength and fast slew rate. For external I/O timing using
standards other than L VTTL or for different current str engths, use the I/O
standard input and output delay adders in Tables 4–103 through 4–108.
PRN
CLRN
DQ
OE Register
PRN
CLRN
DQ
Input Register
PRN
CLRN
DQ
Output Register
Bidirectional
Pin
Dedicated
Clock
t
INSU
t
INH
t
OUTCO
t
XZ
t
ZX
4–34 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Table 4–52 shows the external I/O timing parameters when using fast
regional clock networks.
Table 4–53 shows the external I/O timing parameters when using
regional clock networks.
Table 4–52. Stratix Fast Regional Clock External I/O Timing Parameters
Notes (1), (2)
Symbol Parameter
tINSU Setup time for input or bidirectional pin using IOE input register with
fast regional clock fed by FCLK pin
tINH Hold time for input or bidirectional pin using IOE input register with
fast regional clock fed by FCLK pin
tOUTCO Clock-to-output delay output or bidirectional pin using IOE output
register with fast regional clock fed by FCLK pin
tXZ Synchronous IOE output enable register to output pin disable delay
using fast regional clock fed by FCLK pin
tZX Synchronous IOE output enable register to output pin enable delay
using fast regional clock fed by FCLK pin
Notes to Table 4–52:
(1) These timing parameters are samp le-tested only.
(2) These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
Table 4–53. Stratix Regional Clock External I/O Ti ming Parameters (Part 1
of 2) Notes (1), (2)
Symbol Parameter
tINSU Setup time for input or bidirectional pin using IOE input register with
regional clock fed by CLK pin
tINH Hold time for input or bidirectional pin using IOE input register with
regional clock fed by CLK pin
tOUTCO Clock-to-output delay output or bidirectional pin using IOE output
register with regional clock fed by CLK pin
tINSUPLL Setup time for input or bidirectional pin using IOE input register with
regional clock fed by Enhanced PLL with default phase setting
tINHPLL Hold time for input or bidirectional pin using IOE input register with
regional clock fed by Enhanced PLL with default phase setting
tOUTCOPLL Clock-to-output delay output or bidirectional pin using IOE output
register with regional clock Enhanced PLL with default phase setting
Altera Corporation 4–35
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Table 4–54 shows the external I/O timing parameters when using global
clock networks.
tXZPLL Synchronous IOE output enable register to output pin disable delay
using regional clock fed by Enhanced PLL with default phase setting
tZXPLL Synchronous IOE output enable register to output pin enable delay
using regional clock fed by Enhanced PLL with default phase setting
Notes to Table 4–53:
(1) These timing parameters are samp le-tested only.
(2) These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
Table 4–54. Stratix Global Clock External I/O Timing Parameters Notes (1),
(2)
Symbol Parameter
tINSU Setup time for input or bidirectional pin using IOE input register with
global clock fed by CLK pin
tINH Hold time for input or bidirectional pin using IOE input register with
global clock fed by CLK pin
tOUTCO Clock-to-output delay output or bidirectional pin using IOE output
register with global clock fed by CLK pin
tINSUPLL Setup time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
tINHPLL Hold time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
tOUTCOPLL Clock-to-output delay output or bidirectional pin using IOE output
register with global clock Enhanced PLL with default phase setting
tXZPLL Synchronous IOE output enable register to output pin disable delay
using global clock fed by Enhanced PLL with default phase setting
tZXPLL Synchronous IOE output enable register to output pin enable delay
using global clock fed by Enhanced PLL with default phase setting
Notes to Table 4–54:
(1) These timing parameters are samp le-tested only.
(2) These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
Table 4–53. Stratix Regional Clock External I/O Ti ming Parameters (Part 2
of 2) Notes (1), (2)
Symbol Parameter
4–36 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Stratix External I/O Timing
These timing parameters are for both column IOE and row IOE pins. In
EP1S30 devices and above , you can decrease the tSU time by using the
FPLLCLK, but may get positive hold time in EP1S60 and EP1S80 devices.
You should use the Quartus II software to verify the external devices for
any pin.
Tables 4–55 through 4–60 show the external timing parameters on column
and row pins for EP1S10 devices.
Table 4–55. EP1S10 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMin Max
tINSU 2.238 2.325 2.668 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.240 4.549 2.240 4.836 2.240 5.218 NA NA ns
tXZ 2.180 4.423 2.180 4.704 2.180 5.094 NA NA ns
tZX 2.180 4.423 2.180 4.704 2.180 5.094 NA NA ns
Table 4–56. EP1S10 External I/O Timing on Column Pins Using Regional Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max
tINSU 1.992 2.054 2.359 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.395 4.795 2.395 5.107 2.395 5.527 NA NA ns
tXZ 2.335 4.669 2.335 4.975 2.335 5.403 NA NA ns
tZX 2.335 4.669 2.335 4.975 2.335 5.403 NA NA ns
tINSUPLL 0.975 0.985 1.097 NA ns
tINHPLL 0.000 0.000 0.000 NA NA ns
tOUTCOPLL 1.262 2.636 1.262 2.680 1.262 2.769 NA NA ns
tXZPLL 1.202 2.510 1.202 2.548 1.202 2.645 NA NA ns
tZXPLL 1.202 2.510 1.202 2.548 1.202 2.645 NA NA ns
Altera Corporation 4–37
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Table 4–57. EP1S10 External I/O Timing on Column Pins Using Global Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 1.647 1.692 1.940 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.619 5.184 2.619 5.515 2.619 5.999 NA NA ns
tXZ 2.559 5.058 2.559 5.383 2.559 5.875 NA NA ns
tZX 2.559 5.058 2.559 5.383 2.559 5.875 NA NA ns
tINSUPLL 1.239 1.229 1.374 NA ns
tINHPLL 0.000 0.000 0.000 NA ns
tOUTCOPLL 1.109 2.372 1.109 2.436 1.109 2.492 NA NA ns
tXZPLL 1.049 2.246 1.049 2.304 1.049 2.368 NA NA ns
tZXPLL 1.049 2.246 1.049 2.304 1.049 2.368 NA NA ns
Table 4–58. EP1S10 External I/O Timing on Row Pin Using Fast Regional Clock Network Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
tINSU 2.212 2.403 2.759 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.391 4.838 2.391 5.159 2.391 5.569 NA NA ns
tXZ 2.418 4.892 2.418 5.215 2.418 5.637 NA NA ns
tZX 2.418 4.892 2.418 5.215 2.418 5.637 NA NA ns
4–38 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Table 4–59. EP1S10 External I/O Timing on Row Pins Using Regional Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
tINSU 2.161 2.336 2.685 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.434 4.889 2.434 5.226 2.434 5.643 NA NA ns
tXZ 2.461 4.493 2.461 5.282 2.461 5.711 NA NA ns
tZX 2.461 4.493 2.461 5.282 2.461 5.711 NA NA ns
tINSUPLL 1.057 1.172 1.315 NA ns
tINHPLL 0.000 0.000 0.000 NA ns
tOUTCOPLL 1.327 2.773 1.327 2.848 1.327 2.940 NA NA ns
tXZPLL 1.354 2.827 1.354 2.904 1.354 3.008 NA NA ns
tZXPLL 1.354 2.827 1.354 2.904 1.354 3.008 NA NA ns
Table 4–60. EP1S10 External I/O Timing on Row Pins Using Global Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 1.787 1.944 2.232 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.647 5.263 2.647 5.618 2.647 6.069 NA NA ns
tXZ 2.674 5.317 2.674 5.674 2.674 6.164 NA NA ns
tZX 2.674 5.317 2.674 5.674 2.674 6.164 NA NA ns
tINSUPLL 1.371 1.1472 1.654 NA ns
tINHPLL 0.000 0.000 0.000 NA ns
tOUTCOPLL 1.144 2.459 1.144 2.548 1.144 2.601 NA NA ns
tXZPLL 1.171 2.513 1.171 2.604 1.171 2.669 NA NA ns
tZXPLL 1.171 2.513 1.171 2.604 1.171 2.669 NA NA ns
Note to Tables 4–55 to 4–60:
(1) Only EP1S25, EP1S30, and EP1S40 have speed grade of -8.
Altera Corporation 4–39
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Tables 4–61 through 4–66 show the external timing parameters on column
and row pins for EP1S20 devices.
Table 4–61. EP1S20 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.065 2.245 2.576 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.283 4.622 2.283 4.916 2.283 5.310 NA NA ns
tXZ 2.223 4.496 2.223 4.784 2.223 5.186 NA NA ns
tZX 2.223 4.496 2.223 4.784 2.223 5.186 NA NA ns
Table 4–62. EP1S20 External I/O Timing on Column Pins Using Regional Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 1.541 1.680 1.931 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.597 5.146 2.597 5.481 2.597 5.955 NA NA ns
tXZ 2.537 5.020 2.537 5.349 2.537 5.831 NA NA ns
tZX 2.537 5.020 2.537 5.349 2.537 5.831 NA NA ns
tINSUPLL 0.777 0.818 0.937 NA ns
tINHPLL 0.000 0.000 0.000 NA ns
tOUTCOPLL 1.296 2.690 1.296 2.801 1.296 2.876 NA NA ns
tXZPLL 1.236 2.564 1.236 2.669 1.236 2.752 NA NA ns
tZXPLL 1.236 2.564 1.236 2.669 1.236 2.752 NA NA ns
4–40 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Table 4–63. EP1S20 External I/O Timing on Column Pins Using Global Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
tINSU 1.351 1.479 1.699 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.732 5.380 2.732 5.728 2.732 6.240 NA NA ns
tXZ 2.672 5.254 2.672 5.596 2.672 6.116 NA NA ns
tZX 2.672 5.254 2.672 5.596 2.672 6.116 NA NA ns
tINSUPLL 0.923 0.971 1.098 NA ns
tINHPLL 0.000 0.000 0.000 NA ns
tOUTCOPLL 1.210 2.544 1.210 2.648 1.210 2.715 NA NA ns
tXZPLL 1.150 2.418 1.150 2.516 1.150 2.591 NA NA ns
tZXPLL 1.150 2.418 1.150 2.516 1.150 2.591 NA NA ns
Table 4–64. EP1S20 External I/O Timing on Row Pins Using Fast Regional Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.032 2.207 2.535 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.492 5.018 2.492 5.355 2.492 5.793 NA NA ns
tXZ 2.519 5.072 2.519 5.411 2.519 5.861 NA NA ns
tZX 2.519 5.072 2.519 5.411 2.519 5.861 NA NA ns
Altera Corporation 4–41
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Table 4–65. EP1S20 External I/O Timing on Row Pins Using Regional Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 1.815 1.967 2.258 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.633 5.235 2.663 5.595 2.663 6.070 NA NA ns
tXZ 2.660 5.289 2.660 5.651 2.660 6.138 NA NA ns
tZX 2.660 5.289 2.660 5.651 2.660 6.138 NA NA ns
tINSUPLL 1.060 1.112 1.277 NA ns
tINHPLL 0.000 0.000 0.000 NA ns
tOUTCOPLL 1.325 2.770 1.325 2.908 1.325 2.978 NA NA ns
tXZPLL 1.352 2.824 1.352 2.964 1.352 3.046 NA NA ns
tZXPLL 1.352 2.824 1.352 2.964 1.352 3.046 NA NA ns
Table 4–66. EP1S20 External I/O Timing on Row Pins Using Global Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 1.742 1.887 2.170 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.674 5.308 2.674 5.675 2.674 6.158 NA NA ns
tXZ 2.701 5.362 2.701 5.731 2.701 6.226 NA NA ns
tZX 2.701 5.362 2.701 5.731 2.701 6.226 NA NA ns
tINSUPLL 1.353 1.418 1.613 NA ns
tINHPLL 0.000 0.000 0.000 NA ns
tOUTCOPLL 1.158 2.447 1.158 2.602 1.158 2.642 NA NA ns
tXZPLL 1.185 2.531 1.158 2.602 1.185 2.710 NA NA ns
tZXPLL 1.185 2.531 1.158 2.602 1.185 2.710 NA NA ns
Note to Tables 4–61 to 4–66:
(1) Only EP1S25, EP1S30, and EP1S40 have a speed grade of -8.
4–42 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Tables 4–67 through 4–72 show the external timing parameters on column
and row pins for EP1S25 devices.
Table 4–67. EP1S25 External I/O Timing on Column Pins Using Fast Regional Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.412 2.613 2.968 3.468 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.196 4.475 2.196 4.748 2.196 5.118 2.196 5.603 ns
tXZ 2.136 4.349 2.136 4.616 2.136 4.994 2.136 5.488 ns
tZX 2.136 4.349 2.136 4.616 2.136 4.994 2.136 5.488 ns
Table 4–68. EP1S25 External I/O Timing on Column Pins Using Regional Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 1.535 1.661 1.877 2.125 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.739 5.396 2.739 5.746 2.739 6.262 2.739 6.946 ns
tXZ 2.679 5.270 2.679 5.614 2.679 6.138 2.679 6.831 ns
tZX 2.679 5.270 2.679 5.614 2.679 6.138 2.679 6.831 ns
tINSUPLL 0.934 0.980 1.092 1.231 ns
tINHPLL 0.000 0.000 0.000 0.000 ns
tOUTCOPLL 1.316 2.733 1.316 2.839 1.316 2.921 1.316 3.110 ns
tXZPLL 1.256 2.607 1.256 2.707 1.256 2.797 1.256 2.995 ns
tZXPLL 1.256 2.607 1.256 2.707 1.256 2.797 1.256 2.995 ns
Altera Corporation 4–43
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Table 4–69. EP1S25 External I/O Timing on Column Pins Using Global Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
tINSU 1.371 1.471 1.657 1.916 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.809 5.516 2.809 5.890 2.809 6.429 2.809 7.155 ns
tXZ 2.749 5.390 2.749 5.758 2.749 6.305 2.749 7.040 ns
tZX 2.749 5.390 2.749 5.758 2.749 6.305 2.749 7.040 ns
tINSUPLL 1.271 1.327 1.491 1.677 ns
tINHPLL 0.000 0.000 0.000 0.000 ns
tOUTCOPLL 1.124 2.396 1.124 2.492 1.124 2.522 1.124 2.602 ns
tXZPLL 1.064 2.270 1.064 2.360 1.064 2.398 1.064 2.487 ns
tZXPLL 1.064 2.270 1.064 2.360 1.064 2.398 1.064 2.487 ns
Table 4–70. EP1S25 External I/O Timing on Row Pins Using Fast Regional Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
tINSU 2.429 2.631 2.990 3.503 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.376 4.821 2.376 5.131 2.376 5.538 2.376 6.063 ns
tXZ 2.403 4.875 2.403 5.187 2.403 5.606 2.403 6.145 ns
tZX 2.403 4.875 2.403 5.187 2.403 5.606 2.403 6.145 ns
4–44 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Table 4–71. EP1S25 External I/O Timing on Row Pins Using Regional Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 1.793 1.927 2.182 2.542 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.759 5.457 2.759 5.835 2.759 6.346 2.759 7.024 ns
tXZ 2.786 5.511 2.786 5.891 2.786 6.414 2.786 7.106 ns
tZX 2.786 5.511 2.786 5.891 2.786 6.414 2.786 7.106 ns
tINSUPLL 1.169 1.221 1.373 1.600 ns
tINHPLL 0.000 0.000 0.000 0.000 ns
tOUTCOPLL 1.375 2.861 1.375 2.999 1.375 3.082 1.375 3.174 ns
tXZPLL 1.402 2.915 1.402 3.055 1.402 3.150 1.402 3.256 ns
tZXPLL 1.402 2.915 1.402 3.055 1.402 3.150 1.402 3.256 ns
Table 4–72. EP1S25 External I/O Timing on Row Pins Using Global Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 1.665 1.779 2.012 2.372 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.834 5.585 2.834 5.983 2.834 6.516 2.834 7.194 ns
tXZ 2.861 5.639 2.861 6.039 2.861 6.584 2.861 7.276 ns
tZX 2.861 5.639 2.861 6.039 2.861 6.584 2.861 7.276 ns
tINSUPLL 1.538 1.606 1.816 2.121 ns
tINHPLL 0.000 0.000 0.000 0.000 ns
tOUTCOPLL 1.164 2.492 1.164 2.614 1.164 2.639 1.164 2.653 ns
tXZPLL 1.191 2.546 1.191 2.670 1.191 2.707 1.191 2.735 ns
tZXPLL 1.191 2.546 1.191 2.670 1.191 2.707 1.191 2.735 ns
Altera Corporation 4–45
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Tables 4–73 through 4–78 show the external timing parameters on column
and row pins for EP1S30 devices.
Table 4–73. EP1S30 External I/O Timing on Column Pins Using Fast Regional Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
tINSU 2.502 2.680 3.062 3.591 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.473 4.965 2.473 5.329 2.473 5.784 2.473 6.392 ns
tXZ 2.413 4.839 2.413 5.197 2.413 5.660 2.413 6.277 ns
tZX 2.413 4.839 2.413 5.197 2.413 5.660 2.413 6.277 ns
Table 4–74. EP1S30 External I/O Timing on Column Pins Using Regional Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.286 2.426 2.769 3.249 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.641 5.225 2.641 5.629 2.641 6.130 2.641 6.796 ns
tXZ 2.581 5.099 2.581 5.497 2.581 6.006 2.581 6.681 ns
tZX 2.581 5.099 2.581 5.497 2.581 6.006 2.581 6.681 ns
tINSUPLL 1.200 1.185 1.344 1.662 ns
tINHPLL 0.000 0.000 0.000 0.000 ns
tOUTCOPLL 1.108 2.367 1.108 2.534 1.108 2.569 1.108 2.517 ns
tXZPLL 1.048 2.241 1.048 2.402 1.048 2.445 1.048 2.402 ns
tZXPLL 1.048 2.241 1.048 2.402 1.048 2.445 1.048 2.402 ns
Table 4–75. EP1S30 External I/O Timing on Column Pins Using Global Clock Networks (Part 1 of 2)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 1.935 2.029 2.310 2.709 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.814 5.532 2.814 5.980 2.814 6.536 2.814 7.274 ns
4–46 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
tXZ 2.754 5.406 2.754 5.848 2.754 6.412 2.754 7.159 ns
tZX 2.754 5.406 2.754 5.848 2.754 6.412 2.754 7.159 ns
tINSUPLL 1.265 1.236 1.403 1.756 ns
tINHPLL 0.000 0.000 0.000 0.000 ns
tOUTCOPLL 1.068 2.302 1.068 2.483 1.068 2.510 1.068 2.423 ns
tXZPLL 1.008 2.176 1.008 2.351 1.008 2.386 1.008 2.308 ns
tZXPLL 1.008 2.176 1.008 2.351 1.008 2.386 1.008 2.308 ns
Table 4–76. EP1S30 External I/O Timing on Row Pins Using Fast Regional Clock Networks
Parameters -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.616 2.808 3.223 3.797 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.542 5.114 2.542 5.502 2.542 5.965 2.542 6.581 ns
tXZ 2.569 5.168 2.569 5.558 2.569 6.033 2.569 6.663 ns
tZX 2.569 5.168 2.569 5.558 2.569 6.033 2.569 6.663 ns
Table 4–75. EP1S30 External I/O Timing on Column Pins Using Global Clock Networks (Part 2 of 2)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
Altera Corporation 4–47
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Table 4–77. EP1S30 External I/O Timing on Row Pins Using Regional Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.322 2.467 2.828 3.342 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.731 5.408 2.731 5.843 2.731 6.360 2.731 7.036 ns
tXZ 2.758 5.462 2.758 5.899 2.758 6.428 2.758 7.118 ns
tZX 2.758 5.462 2.758 5.899 2.758 6.428 2.758 7.118 ns
tINSUPLL 1.291 1.283 1.469 1.832 ns
tINHPLL 0.000 0.000 0.000 0.000 ns
tOUTCOPLL 1.192 2.539 1.192 2.737 1.192 2.786 1.192 2.742 ns
tXZPLL 1.219 2.539 1.219 2.793 1.219 2.854 1.219 2.824 ns
tZXPLL 1.219 2.539 1.219 2.793 1.219 2.854 1.219 2.824 ns
Table 4–78. EP1S30 External I/O Timing on Row Pins Using Global Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
tINSU 1.995 2.089 2.398 2.830 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.917 5.735 2.917 6.221 2.917 6.790 2.917 7.548 ns
tXZ 2.944 5.789 2.944 6.277 2.944 6.858 2.944 7.630 ns
tZX 2.944 5.789 2.944 6.277 2.944 6.858 2.944 7.630 ns
tINSUPLL 1.337 1.312 1.508 1.902 ns
tINHPLL 0.000 0.000 0.000 0.000 ns
tOUTCOPLL 1.164 2.493 1.164 2.708 1.164 2.747 1.164 2.672 ns
tXZPLL 1.191 2.547 1.191 2.764 1.191 2.815 1.191 2.754 ns
tZXPLL 1.191 2.547 1.191 2.764 1.191 2.815 1.191 2.754 ns
4–48 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Tables 4–79 through 4–84 show the external timing parameters on column
and row pins for EP1S40 devices.
Table 4–79. EP1S40 External I/O Timing on Column Pins Using Fast Regional Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.696 2.907 3.290 2.899 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.506 5.015 2.506 5.348 2.506 5.809 2.698 7.286 ns
tXZ 2.446 4.889 2.446 5.216 2.446 5.685 2.638 7.171 ns
tZX 2.446 4.889 2.446 5.216 2.446 5.685 2.638 7.171 ns
Table 4–80. EP1S40 External I/O Timing on Column Pins Using Regional Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.413 2.581 2.914 2.938 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.668 5.254 2.668 5.628 2.668 6.132 2.869 7.307 ns
tXZ 2.608 5.128 2.608 5.496 2.608 6.008 2.809 7.192 ns
tZX 2.608 5.128 2.608 5.496 2.608 6.008 2.809 7.192 ns
tINSUPLL 1.385 1.376 1.609 1.837 ns
tINHPLL 0.000 0.000 0.000 0.000 ns
tOUTCOPLL 1.117 2.382 1.117 2.552 1.117 2.504 1.117 2.542 ns
tXZPLL 1.057 2.256 1,057 2.420 1.057 2.380 1.057 2.427 ns
tZXPLL 1.057 2.256 1,057 2.420 1.057 2.380 1.057 2.427 ns
Altera Corporation 4–49
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Table 4–81. EP1S40 External I/O Timing on Column Pins Using Global Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.126 2.268 2.558 2.930 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.856 5.585 2.856 5.987 2.856 6.541 2.847 7.253 ns
tXZ 2.796 5.459 2.796 5.855 2.796 6.417 2.787 7.138 ns
tZX 2.796 5.459 2.796 5.855 2.796 6.417 2.787 7.138 ns
tINSUPLL 1.466 1.455 1.711 1.906 ns
tINHPLL 0.000 0.000 0.000 0.000 ns
tOUTCOPLL 1.092 2.345 1.092 2.510 1.092 2.455 1.089 2.473 ns
tXZPLL 1.032 2.219 1.032 2.378 1.032 2.331 1.029 2.358 ns
tZXPLL 1.032 2.219 1.032 2.378 1.032 2.331 1.029 2.358 ns
Table 4–82. EP1S40 External I/O Timing on Row Pins Using Fast Regional Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.472 2.685 3.083 3.056 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.631 5.258 2.631 5.625 2.631 6.105 2.745 7.324 ns
tXZ 2.658 5.312 2.658 5.681 2.658 6.173 2.772 7.406 ns
tZX 2.658 5.312 2.658 5.681 2.658 6.173 2.772 7.406 ns
4–50 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Table 4–83. EP1S40 External I/O Timing on Row Pins Using Regional Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
tINSU 2.349 2.526 2.898 2.952 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.725 5.381 2.725 5.784 2.725 6.290 2.725 7.426 ns
tXZ 2.752 5.435 2.752 5.840 2.752 6.358 2.936 7.508 ns
tZX 2.752 5.435 2.752 5.840 2.752 6.358 2.936 7.508 ns
tINSUPLL 1.328 1.322 1.605 1.883 ns
tINHPLL 0.000 0.000 0.000 0.000 ns
tOUTCOPLL 1.169 2.502 1.169 2.698 1.169 2.650 1.169 2.691 ns
tXZPLL 1.196 2.556 1.196 2.754 1.196 2.718 1.196 2.773 ns
tZXPLL 1.196 2.556 1.196 2.754 1.196 2.718 1.196 2.773 ns
Table 4–84. EP1S40 External I/O Timing on Row Pins Using Global Clock Networks
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
tINSU 2.020 2.171 2.491 2.898 ns
tINH 0.000 0.000 0.000 0.000 ns
tOUTCO 2.912 5.710 2.912 6.139 2.912 6.697 2.931 7.480 ns
tXZ 2.939 5.764 2.939 6.195 2.939 6.765 2.958 7.562 ns
tZX 2.939 5.764 2.939 6.195 2.939 6.765 2.958 7.562 ns
tINSUPLL 1.370 1.368 1.654 1.881 ns
tINHPLL 0.000 0.000 0.000 0.000 ns
tOUTCOPLL 1.144 2.460 1.144 2.652 1.144 2.601 1.170 2.693 ns
tXZPLL 1.171 2.514 1.171 2.708 1.171 2.669 1.197 2.775 ns
tZXPLL 1.171 2.514 1.171 2.708 1.171 2.669 1.197 2.775 ns
Altera Corporation 4–51
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Tables 4–85 through 4–90 show the external timing parameters on column
and row pins for EP1S60 devices.
Table 4–85. EP1S60 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 3.029 3.277 3.733 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.446 4.871 2.446 5.215 2.446 5.685 NA NA ns
tXZ 2.386 4.745 2.386 5.083 2.386 5.561 NA NA ns
tZX 2.386 4.745 2.386 5.083 2.386 5.561 NA NA ns
Table 4–86. EP1S60 External I/O Timing on Column Pins Using Regional Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.491 2.691 3.060 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.767 5.409 2.767 5.801 2.767 6.358 NA NA ns
tXZ 2.707 5.283 2.707 5.669 2.707 6.234 NA NA ns
tZX 2.707 5.283 2.707 5.669 2.707 6.234 NA NA ns
tINSUPLL 1.233 1.270 1.438 NA ns
tINHPLL 0.000 0.000 0.000 NA ns
tOUTCOPLL 1.078 2.278 1.078 2.395 1.078 2.428 NA NA ns
tXZPLL 1.018 2.152 1.018 2.263 1.018 2.304 NA NA ns
tZXPLL 1.018 2.152 1.018 2.263 1.018 2.304 NA NA ns
4–52 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Table 4–87. EP1S60 External I/O Timing on Column Pins Using Global Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
tINSU 2.000 2.152 2.441 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 3.051 5.900 3.051 6.340 3.051 6.977 NA NA ns
tXZ 2.991 5.774 2.991 6.208 2.991 6.853 NA NA ns
tZX 2.991 5.774 2.991 6.208 2.991 6.853 NA NA ns
tINSUPLL 1.315 1.362 1.543 NA ns
tINHPLL 0.000 0.000 0.000 NA ns
tOUTCOPLL 1.029 2.196 1.029 2.303 1.029 2.323 NA NA ns
tXZPLL 0.969 2.070 0.969 2.171 0.969 2.199 NA NA ns
tZXPLL 0.969 2.070 0.969 2.171 0.969 2.199 NA NA ns
Table 4–88. EP1S60 External I/O Timing on Row Pins Using Fast Regional Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
tINSU 3.144 3.393 3.867 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.643 5.275 2.643 5.654 2.643 6.140 NA NA ns
tXZ 2.670 5.329 2.670 5.710 2.670 6.208 NA NA ns
tZX 2.670 5.329 2.670 5.710 2.670 6.208 NA NA ns
Altera Corporation 4–53
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Table 4–89. EP1S60 External I/O Timing on Row Pins Using Regional Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.775 2.990 3.407 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.867 5.644 2.867 6.057 2.867 6.600 NA NA ns
tXZ 2.894 5.698 2.894 6.113 2.894 6.668 NA NA ns
tZX 2.894 5.698 2.894 6.113 2.894 6.668 NA NA ns
tINSUPLL 1.523 1.577 1.791 NA ns
tINHPLL 0.000 0.000 0.000 NA ns
tOUTCOPLL 1.174 2.507 1.174 2.643 1.174 2.664 NA NA ns
tXZPLL 1.201 2.561 1.201 2.699 1.201 2.732 NA NA ns
tZXPLL 1.201 2.561 1.201 2.699 1.201 2.732 NA NA ns
Table 4–90. EP1S60 External I/O Timing on Row Pins Using Global Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.232 2.393 2.721 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 3.182 6.187 3.182 6.654 3.182 7.286 NA NA ns
tXZ 3.209 6.241 3.209 6.710 3.209 7.354 NA NA ns
tZX 3.209 6.241 3.209 6.710 3.209 7.354 NA NA ns
tINSUPLL 1.651 1.612 1.833 NA ns
tINHPLL 0.000 0.000 0.000 NA ns
tOUTCOPLL 1.154 2.469 1.154 2.608 1.154 2.622 NA NA ns
tXZPLL 1.181 2.523 1.181 2.664 1.181 2.690 NA NA ns
tZXPLL 1.181 2.523 1.181 2.664 1.181 2.690 NA NA ns
Note to Tables 4–85 to 4–90:
(1) Only EP1S25, EP1S30, a nd EP1S40 devi ces have the -8 speed grade.
4–54 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Tables 4–91 through 4–96 show the external timing parameters on column
and row pins for EP1S80 devices.
Table 4–91. EP1S80 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.328 2.528 2.900 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.422 4.830 2.422 5.169 2.422 5.633 NA NA ns
tXZ 2.362 4.704 2.362 5.037 2.362 5.509 NA NA ns
tZX 2.362 4.704 2.362 5.037 2.362 5.509 NA NA ns
Table 4–92. EP1S80 External I/O Timing on Column Pins Using Regional Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 1.760 1.912 2.194 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.761 5.398 2.761 5.785 2.761 6.339 NA NA ns
tXZ 2.701 5.272 2.701 5.653 2.701 6.215 NA NA ns
tZX 2.701 5.272 2.701 5.653 2.701 6.215 NA NA ns
tINSUPLL 0.462 0.606 0.785 NA ns
tINHPLL 0.000 0.000 0.000 NA ns
tOUTCOPLL 1.661 2.849 1.661 2.859 1.661 2.881 NA NA ns
tXZPLL 1.601 2.723 1.601 2.727 1.601 2.757 NA NA ns
tZXPLL 1.601 2.723 1.601 2.727 1.601 2.757 NA NA ns
Altera Corporation 4–55
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Table 4–93. EP1S80 External I/O Timing on Column Pins Using Global Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 0.884 0.976 1.118 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 3.267 6.274 3.267 6.721 3.267 7.415 NA NA ns
tXZ 3.207 6.148 3.207 6.589 3.207 7.291 NA NA ns
tZX 3.207 6.148 3.207 6.589 3.207 7.291 NA NA ns
tINSUPLL 0.506 0.656 0.838 NA ns
tINHPLL 0.000 0.000 0.000 NA ns
tOUTCOPLL 1.635 2.805 1.635 2.809 1.635 2.828 NA NA ns
tXZPLL 1.575 2.679 1.575 2.677 1.575 2.704 NA NA ns
tZXPLL 1.575 2.679 1.575 2.677 1.575 2.704 NA NA ns
Table 4–94. EP1S80 External I/O Timing on Row Pins Using Fast Regional Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.792 2.993 3.386 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.619 5.235 2.619 5.609 2.619 6.086 NA NA ns
tXZ 2.646 5.289 2.646 5.665 2.646 6.154 NA NA ns
tZX 2.646 5.289 2.646 5.665 2.646 6.154 NA NA ns
4–56 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Table 4–95. EP1S80 External I/O Timing on Row Pins Using Regional Clock Networks Note (1)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Unit
MinMaxMinMaxMinMaxMinMax
tINSU 2.295 2.454 2.767 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 2.917 5.732 2.917 6.148 2.917 6.705 NA NA ns
tXZ 2.944 5.786 2.944 6.204 2.944 6.773 NA NA ns
tZX 2.944 5.786 2.944 6.204 2.944 6.773 NA NA ns
tINSUPLL 1.011 1.161 1.372 NA ns
tINHPLL 0.000 0.000 0.000 NA ns
tOUTCOPLL 1.808 3.169 1.808 3.209 1.808 3.233 NA NA ns
tXZPLL 1.835 3.223 1.835 3.265 1.835 3.301 NA NA ns
tZXPLL 1.835 3.223 1.835 3.265 1.835 3.301 NA NA ns
Table 4–96. EP1S80 External I/O Timing on Rows Using Pin Global Clock Networks Note (1)
Symbol -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
MinMaxMinMaxMinMaxMinMax
tINSU 1.362 1.451 1.613 NA ns
tINH 0.000 0.000 0.000 NA ns
tOUTCO 3.457 6.665 3.457 7.151 3.457 7.859 NA NA ns
tXZ 3.484 6.719 3.484 7.207 3.484 7.927 NA NA ns
tZX 3.484 6.719 3.484 7.207 3.484 7.927 NA NA ns
tINSUPLL o.994 1.143 1.351 NA ns
tINHPLL 0.000 0.000 0.000 NA ns
tOUTCOPLL 1.821 3.186 1.821 3.227 1.821 3.254 NA NA ns
tXZPLL 1.848 3.240 1.848 3.283 1.848 3.322 NA NA ns
tZXPLL 1.848 3.240 1.848 3.283 1.848 3.322 NA NA ns
Note to Tables 4–91 to 4–96:
(1) Only EP1S25, EP1S30, a nd EP1S40 devi ces have the -8 speed grade.
Altera Corporation 4–57
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Definition of I/O Skew
I/O skew is defined as the absolute value of the worst-case differ ence in
clock-to-out times (tCO) between any two output registers fed by a
common clock source.
I/O bank skew is made up of the following components:
■Clock network skews: This is the differ ence between the arrival times
of the clock at the clock input port of the two IOE registers.
■Package skews: This is the package trace length dif fe r ences between
(I/O pad A to I/O pin A) and (I/O pad B to I/O pin B).
Figure 4–5 shows an example of two IOE r egisters located in the same
bank, being fed by a common clock source. The clock can come from an
input pin or from a PLL output.
Figure 4–5. I/O Skew within an I/O Bank
Common Source of GCLK
Fast Edge
Slow Edge
I/O Skew
I/O Bank
I/O Skew
I/O Pin
A
I/O Pin
B
I/O Pin A
I/O Pin B
4–58 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Figure 4–6 shows the case where four IOE registers are located in two
different I/O banks.
Figure 4–6. I/O Skew Across Two I/O Banks
Table 4–97 defines the timing parameters used to define the timing for
horizontal I/O pins (side banks 1, 2, 5, 6) and vertical I/O pins (top and
bottom banks 3, 4, 7, 8). The timing parameters de fine the skew within an
I/O bank, across two neighboring I/O banks on the same side of the
device, acr oss all horizontal I/O banks, acro ss all vertical I/O banks, and
the skew for the overall device.
Table 4–97. Output Pin Timing Skew Definitions (Part 1 of 2)
Symbol Definition
tSB_HIO Row I/O (HIO) within one I/O bank (1)
tSB_VIO Column I/O (VIO) within one I/O bank (1)
tSS_HIO Row I/O (HIO) same side of the device, across two
banks (2)
tSS_VIO Column I/O (VIO) same side of the de vice , across two
banks (2)
Common Source of GCLK
I/O Bank
I/O Bank
I/O Pin
A
I/O Pin
B
I/O Pin C
I/O Pin
D
I/O Pin A
I/O Pin B
I/O Pin C
I/O Pin D
I/O Pin Skew across
two Banks
Altera Corporation 4–59
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Table 4–98 shows the I/O skews when using the same global or regional
clock to feed IOE registers in I/O banks around each device. These values
can be used for calculating the timing budget on the output (write) side
of a memory interface. These values already factor in the package skew.
tLR_HIO Across all HIO banks (1, 2, 5, 6); across four similar
type I/O banks
tTB_VIO Across all VIO banks (3, 4, 7, 8); across four similar
type I/O banks
tOVERALL Output timing skew for all I/O pins on the device.
Notes to Table 4–97:
(1) See Figure 4–5 on page 4–57.
(2) See Figure 4–6 on page 4–58.
Table 4–98. Output Skew for Stratix by Device Density
Symbol Skew (ps) (1)
EP1S10 to EP1S30 EP1S40 EP1S60 & EP1S80
tSB_HIO 90 290 500
tSB_VIO 160 290 500
tSS_HIO 90 460 600
tSS_VIO 180 520 630
tLR_HIO 150 490 600
tTB_VIO 190 580 670
tOVERALL 430 630 880
Note to Table 4–98:
(1) The skew numbers in Table 4–98 account for worst case package skews.
Table 4–97. Output Pin Timing Skew Definitions (Part 2 of 2)
Symbol Definition
4–60 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Skew on Input Pins
Table 4–99 shows the package skews that were considered to get the
worst case I/O skew value. You can use these values, for example, when
calculating the timing budget on the input (read) side of a memory
interface.
PLL Counter & Clock Network Skews
Table 4–100 shows the clock skews between dif ferent clock outputs from
the Stratix device PLL.
I/O Timing Measurement Methodology
Differ ent I/ O standards r equir e dif fer ent baseline load ing techniques for
reporting timing delays. Altera characterizes timing delays with the
required termination and loading for each I/O standard . The timing
information is specified from the input clock pin up to the output pin of
Table 4–99. Package Skew on Input Pins
Package Parameter Worst-Case Skew (ps)
Pins in the same I/O bank 50
Pins in top/bottom (vertical I/O) banks 50
Pins in left/right side (horizontal I/O) banks 50
Pins across the entire device 100
Table 4–100. PLL Counter & Clock Network Skews
Parameter Wo rst-Case Skew (ps)
Clock ske w betw een two e xternal clock outputs driven
by the same counter 100
Clock ske w betw een two e xternal clock outputs driven
by the different counters with the same settings 150
Dual-purpose PLL dedicated clock output used as I/O
pin vs. regular I/O pin 270 (1)
Clock skew between any two outputs of the PLL that
drive global clock networks 150
Note to Table 4–100:
(1) The Quartus II software models 270 ps of delay on the PLL dedicated clock
output (PLL6_OUT[3..0]p/n and PLL5_OUT[3..0]p/n) pins both when
used as clocks and when used as I/O pins.
Altera Corporation 4–61
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
the FPGA device. The Quartus II software calculates the I/O timing for
each I/O standar d with a default baseline loading as specified by the I/O
standard.
Altera measures clock-to-output delays (tCO) at worst-case process,
minimum voltage, and maximum temperature (PVT) for the 3.3-V LVTTL
I/O standard with 24 mA (default case) current drive strength setting and
fast slew rate setting. I/O adder delays are measur ed to calculate t he tCO
change at worst-case PVT across all I/O standards and cu rrent drive
strength settings with the default loading shown in Table 4–101 on
page 4–62. Timing derating data for additional loading is taken for tCO
across wors t-cas e PVT for all I /O standards and driv e strength setting s .
These three pie ces of data are used to predict the timing at the output pin.
tCO at pin = tOUTCO max for 3.3-V 24 mA LVTTL + I/O Adder +
Output Delay Adder for Loading
Simulation using IBIS models is required to determine the delays on the
PCB traces in addition to the output pin delay timing reported by the
Quartus II software and the timing model in the device handbook.
1. Simulate the output driver of choice into the generalized test setup
using values from Table 4–101 on page 4–62.
2. Reco rd the time to VMEAS.
3. Simulate the output driver of choice into the actual PCB trace and
load, using the appro priate IBIS i nput buffer model or an equivalent
capacitance value to represent the load.
4. Reco rd the time to VMEAS.
5. Compare the results of steps 2 and 4. The increa se or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-input) of the PCB tr ace .
The Quartus II software reports ma ximum timing with the conditions
shown in Table 4–101 on page 4–62 using the proceeding equation.
Figure 4–7 on page 4–62 shows the model of the circuit that is represented
by the Quartus II output timing.
4–62 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Figure 4–7. Output Delay Timing Reporting Setup Modeled by Quartus II
Notes to Figure 4–7:
(1) Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
(2) VCCINT is 1.42-V unless otherwise specified.
VCCIO
GND
OUTPUT
GND
RT
VTT
RS
CL
Output
Buffer
Single-Ended Outputs
VMEAS
GND
RUP
VCCIO
RDN
Table 4–101. Reporting Methodology For Maximum Timing For Single-Ended Output Pins (Part 1 of 2)
Notes (1), (2), (3)
I/O Standard
Loading and Termination Measurement
Point
RUP
ΩRDN
ΩRS
ΩRT
ΩVCCIO
(V) VTT
(V) CL
(pF) VMEAS
3.3-V LVTTL – – 0 – 2.950 2.9 5 10 1.500
2.5-V LVTTL – – 0 – 2.370 2.3 7 10 1.200
1.8-V LVTTL – – 0 – 1.650 1.6 5 10 0.880
1.5-V LVTTL – – 0 – 1.400 1.4 0 10 0.750
3.3-V LVCMOS – – 0 – 2.950 2.95 10 1.500
2.5-V LVCMOS – – 0 – 2.370 2.37 10 1.200
1.8-V LVCMOS – – 0 – 1.650 1.65 10 0.880
1.5-V LVCMOS – – 0 – 1.400 1.40 10 0.750
3.3-V GTL – – 0 25 2.950 1.14 30 0.740
2.5-V GTL – – 0 25 2.370 1.14 30 0.740
3.3-V GTL+ – – 0 25 2.950 1.35 30 0.880
2.5-V GTL+ – – 0 25 2.370 1.35 30 0.880
3.3-V SSTL-3 Class II – – 25 25 2.950 1.25 30 1.250
Altera Corporation 4–63
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
3.3-V SSTL-3 Class I – – 25 50 2.950 1.250 30 1.250
2.5-V SSTL-2 Class II – – 25 25 2.370 1.110 30 1.110
2.5-V SSTL-2 Class I – – 25 50 2.370 1.110 30 1.110
1.8-V SSTL-18 Class II – – 25 25 1.650 0.760 30 0.760
1.8-V SSTL-18 Class I – – 25 50 1.650 0.760 30 0.760
1.5-V HSTL Class II – – 0 25 1.400 0.700 20 0.680
1.5-V HSTL Class I – – 0 50 1.400 0.700 20 0.680
1.8-V HSTL Class II – – 0 25 1.650 0.700 20 0.880
1.8-V HSTL Class I – – 0 50 1.650 0.700 20 0.880
3.3-V PCI (4) –/25 25/– 0 – 2.950 2.950 10 0.841/1.814
3.3-V PCI-X 1.0 (4) –/25 25/– 0 – 2.950 2.950 10 0.841/1.814
3.3-V Compact PCI (4) –/25 25/– 0 – 2.950 2.950 10 0.841/1.814
3.3-V AGP 1X (4) –/25 25/– 0 – 2.950 2.950 10 0.841/1.814
3.3-V CTT – – 25 50 2.050 1.350 30 1.350
Notes to Table 4–101:
(1) Input measurement point at internal node is 0.5 × VCCINT.
(2) Output measuring point for data is VMEAS.
(3) Input stimulus edge rate is 0 to VCCINT in 0.5 ns (internal signal) from the driver preceding the IO buffer.
(4) The first value is for output rising edge and th e second value is for output falling edge. The hyphen (-) indicates
infinite resistance or disconnection.
Table 4–101. Reporting Methodology For Maximum Timing For Single-Ended Output Pins (Part 2 of 2)
Notes (1), (2), (3)
I/O Standard
Loading and Termination Measurement
Point
RUP
ΩRDN
ΩRS
ΩRT
ΩVCCIO
(V) VTT
(V) CL
(pF) VMEAS
4–64 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Table 4–102 shows the reporting methodology used by the Quartus II
software for minimum timing information for output pins.
Table 4–102. Reporting Methodology For Minimum Timing For Single-Ended Output Pins (Part 1 of 2)
Notes (1), (2), (3)
I/O Standard
Loading and Termination Measurement
Point
RUP
ΩRDN
ΩRS
ΩRT
ΩVCCIO
(V) VTT
(V) CL
(pF) VMEAS
3.3-V LVTTL – – 0 – 3.600 3.600 10 1.800
2.5-V LVTTL – – 0 – 2.630 2.630 10 1.200
1.8-V LVTTL – – 0 – 1.950 1.950 10 0.880
1.5-V LVTTL – – 0 – 1.600 1.600 10 0.750
3.3-V LVCMOS – – 0 – 3.600 3.600 10 1.800
2.5-V LVCMOS – – 0 – 2.630 2.630 10 1.200
1.8-V LVCMOS – – 0 – 1.950 1.950 10 0.880
1.5-V LVCMOS – – 0 – 1.600 1.600 10 0.750
3.3-V GTL – – 0 25 3.60 0 1.260 30 0.860
2.5-V GTL – – 0 25 2.63 0 1.260 30 0.860
3.3-V GTL+ – – 0 25 3.600 1.650 30 1.120
2.5-V GTL+ – – 0 25 2.630 1.650 30 1.120
3.3-V SSTL-3 Class II – – 25 25 3.600 1.750 30 1.750
3.3-V SSTL-3 Class I – – 25 50 3.600 1.750 30 1.750
2.5-V SSTL-2 Class II – – 25 25 2.630 1.390 30 1.390
2.5-V SSTL-2 Class I – – 25 50 2.630 1.390 30 1.390
1.8-V SSTL-18 Class II – – 25 25 1.950 1.040 30 1.040
1.8-V SSTL-18 Class I – – 25 50 1.950 1.040 30 1.040
1.5-V HSTL Class II – – 0 25 1.600 0.800 20 0.900
1.5-V HSTL Class I – – 0 50 1.600 0.800 20 0.900
1.8-V HSTL Class II – – 0 25 1.950 0.900 20 1.000
1.8-V HSTL Class I – – 0 50 1.950 0.900 20 1.000
3.3-V PCI (4) –/25 25/– 0 – 3.600 1.950 10 1.026/2.214
3.3-V PCI-X 1.0 (4) –/25 25/– 0 – 3.600 1.950 10 1.026/2.214
3.3-V Compact PCI (4) –/25 25/– 0 – 3.600 3.600 10 1.026/2.214
3.3-V AGP 1× (4) –/25 25/– 0 – 3.600 3.600 10 1.026/2.214
Altera Corporation 4–65
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Figure 4–8 shows the measur ement set up for out put disable and output
enable timing. The TCHZ stands for clock to high Z time delay and is the
same as TXZ. The T CLZ stands for clock to low Z (driving) time delay and
is the same as TZX.
Figure 4–8. Measurement Setup for TXZ and TZX
3.3-V CTT – – 25 50 3.600 1.650 30 1.650
Notes to Table 4–102:
(1) Input measurement point at internal node is 0.5 × VCCINT.
(2) Output measuring point for data is VMEAS. When two values are given, the first is the measurement point on the
rising edge and the other is for the falling edge.
(3) Input stimulus edge rate is 0 to VCCINT in 0.5 ns (internal signal) from the driver preceding the I/O buf fer.
(4) The first value is fo r the output rising edge and the second value is for the output falling edge. The hyphen (-)
indicates infinite resistance or disconnection.
Table 4–102. Reporting Methodology For Minimum Timing For Single-Ended Output Pins (Part 2 of 2)
Notes (1), (2), (3)
I/O Standard
Loading and Termination Measurement
Point
RUP
ΩRDN
ΩRS
ΩRT
ΩVCCIO
(V) VTT
(V) CL
(pF) VMEAS
200mV
200mV
200mV
200mV
CLK
OUT
OUT
T
CHZ
T
CLZ
V
T
=1.5V
C
TOTAL
=10pF
R
=50Ω
4–66 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
External I/O Delay Parameters
External I/O delay timing parameters for I/O standard input and output
adders and programmable input and output delays are specified by
speed grade independent of device density. All of the timing parameters
in this section apply to both flip-chip and wire-bond packages.
Tables 4–103 and 4–104 show the input adder delays associated with
column and row I/O pins. If an I/O standard is selected other than 3.3-V
LVTTL or LVCMOS, add the selected delay to the external tINSU and
tINSUPLL I/O parameters shown in Tables 4–54 through 4–96.
Table 4–103. Stratix I/O Standard Column Pin Input Delay Adders
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
LVCMOS 0 0 0 0 ps
3.3-V LVTTL 0 0 0 0 ps
2.5-V LVTTL 19 19 22 26 ps
1.8-V LVTTL 221 232 266 313 ps
1.5-V LVTTL 352 369 425 500 ps
GTL –45 –48 –55 –64 ps
GTL+ –75 –79 –91 –107 ps
3.3-V PCI 0 0 0 0 ps
3.3-V PCI-X 1.0 0 0 0 0 ps
Compact PCI 0 0 0 0 ps
AGP 1× 0 0 0 0 ps
AGP 2× 0 0 0 0 ps
CTT 120 126 144 170 ps
SSTL-3 Class I –162 –171 –196 –231 ps
SSTL-3 Class II –162 –171 –196 –231 ps
SSTL-2 Class I –202 –213 –244 –287 ps
SSTL-2 Class II –202 –213 –244 –287 ps
SSTL-18 Class I 78 81 94 110 ps
SSTL-18 Class II 78 81 94 110 ps
1.5-V HSTL Class I –76 –80 –92 –108 ps
1.5-V HSTL Class II –76 –80 –92 –108 ps
1.8-V HSTL Class I –52 –55 –63 –74 ps
1.8-V HSTL Class II –52 –55 –63 –74 ps
Altera Corporation 4–67
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Table 4–104. Stratix I/O Standard Row Pin Input Delay Adders
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
LVCMOS 0 0 0 0 ps
3.3-V LVTTL 0 0 0 0 ps
2.5-V LVTTL 21 22 25 29 ps
1.8-V LVTTL 181 190 218 257 ps
1.5-V LVTTL 300 315 362 426 ps
GTL+ –152 –160 –184 –216 ps
CTT –168 –177 –203 –239 ps
SSTL-3 Class I –193 –203 –234 –275 ps
SSTL-3 Class II –193 –203 –234 –275 ps
SSTL-2 Class I –262 –276 –317 –373 ps
SSTL-2 Class II –262 –276 –317 –373 ps
SSTL-18 Class I –105 –111 –127 –150 ps
SSTL-18 Class II 0 0 0 0 ps
1.5-V HSTL Class I –151 –159 –183 –215 ps
1.8-V HSTL Class I –126 –133 –153 –179 ps
LVDS –149 –157 –180 –212 ps
LVPECL –149 –157 –180 –212 ps
3.3-V PCML –65 –69 –79 –93 ps
HyperTransport 77 –81 –93 –110 ps
4–68 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Tables 4–105 through 4–108 show the output adder delays associated
with column and row I/O pins for both fast and slow slew rates. If an I/O
standard is selected other than 3.3-V LVTTL 4mA or LVCMOS 2 mA with
a fast slew rate, add the selected delay to the external tOUTCO, tOUTCOPLL,
tXZ, tZX, tXZPLL, and tZXPLL I/O parameters shown in Table 4–55 on
page 4–36 through Table 4–96 on page 4–56.
Table 4–105. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
LVCMOS 2 mA 1,895 1,990 1,990 1,990 ps
4 mA 956 1,004 1,004 1,004 ps
8 mA 189 198 198 198 ps
12 mA 0 0 0 0ps
24 mA –157 –165 –165 –165 ps
3.3-V LVTTL 4 mA 1,895 1,990 1,990 1,990 ps
8 mA 1,347 1,414 1,414 1,414 ps
12 mA 636 668 668 668 ps
16 mA 561 589 589 589 ps
24 mA 0 0 0 0ps
2.5-V LVTTL 2 mA 2,517 2,643 2,643 2,643 ps
8 mA 834 875 875 875 ps
12 mA 504 529 529 529 ps
16 mA 194 203 203 203 ps
1.8-V LVTTL 2 mA 1,304 1,369 1,369 1,369 ps
8 mA 960 1,008 1,008 1,008 ps
12 mA 960 1,008 1,008 1,008 ps
1.5-V LVTTL 2 mA 6,680 7,014 7,014 7,014 ps
4 mA 3,275 3,439 3,439 3,439 ps
8 mA 1,589 1,668 1,668 1,668 ps
GTL 16 17 17 17 ps
GTL+ 9 9 9 9ps
3.3-V PCI 50 52 52 52 ps
3.3-V PCI-X 1.0 50 52 52 52 ps
Compact PCI 50 52 52 52 ps
AGP 1× 50 52 52 52 ps
AGP 2× 1,895 1,990 1,990 1,990 ps
Altera Corporation 4–69
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
CTT 973 1,021 1,021 1,021 ps
SSTL-3 Class I 719 755 755 755 ps
SSTL-3 Class II 146 153 153 153 ps
SSTL-2 Class I 678 712 712 712 ps
SSTL-2 Class II 223 234 234 234 ps
SSTL-18 Class I 1,032 1,083 1,083 1,083 ps
SSTL-18 Class II 44 7 469 469 469 ps
1.5-V HSTL Class I 660 693 693 693 ps
1.5-V HSTL Class II 537 564 564 564 ps
1.8-V HSTL Class I 304 319 319 319 ps
1.8-V HSTL Class II 231 242 242 242 ps
Table 4–106. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 1 of 2)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
LVCMOS 2 mA 1,518 1,594 1,594 1,594 ps
4 mA 746 783 783 783 ps
8 mA 96 100 100 100 ps
12 mA 0 0 0 0ps
3.3-V LVTTL 4 mA 1,518 1,594 1,594 1,594 ps
8 mA 1,038 1,090 1,090 1,090 ps
12 mA 521 547 547 547 ps
16 mA 414 434 434 434 ps
24 mA 0 0 0 0ps
2.5-V LVTTL 2 mA 2,032 2,133 2,133 2,133 ps
8 mA 699 734 734 734 ps
12 mA 374 392 392 392 ps
16 mA 165 173 173 173 ps
1.8-V LVTTL 2 mA 3,714 3,899 3,899 3,899 ps
8 mA 1,055 1,107 1,107 1,107 ps
12 mA 830 871 871 871 ps
Table 4–105. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 2 of 2)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
4–70 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
1.5-V LVTTL 2 mA 5,460 5,733 5,733 5,733 ps
4 mA 2,690 2,824 2,824 2,824 ps
8 mA 1,398 1,468 1,468 1,468 ps
GTL+ 6 6 6 6ps
CTT 845 887 887 887 ps
SSTL-3 Class I 638 670 670 670 ps
SSTL-3 Class II 144 151 151 151 ps
SSTL-2 Class I 604 634 634 634 ps
SSTL-2 Class II 211 221 221 221 ps
SSTL-18 Class I 955 1,002 1,002 1,002 ps
1.5-V HSTL Class I 733 769 769 769 ps
1.8-V HSTL Class I 372 390 390 390 ps
LVDS –196 –206 –206 –206 ps
LVPECL –148 –156 –156 –156 ps
PCML –147 –155 –155 –155 ps
HyperTransport
technology –93 –98 –98 –98 ps
Note to Table 4–103 through 4–106:
(1) These parameters are only available on row I/O pins.
Table 4–107. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 1 of 2)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
LVCMOS 2 mA 1,822 1,913 1,913 1,913 ps
4 mA 684 718 718 718 ps
8 mA 233 245 245 245 ps
12 mA1111ps
24 mA –608 –638 –638 –638 ps
Table 4–106. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 2 of 2)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
Altera Corporation 4–71
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
3.3-V LVTTL 4 mA 1,822 1,913 1,913 1,913 ps
8 mA 1,586 1,665 1,665 1,665 ps
12 mA 686 720 720 720 ps
16 mA 630 662 662 662 ps
24 mA0000ps
2.5-V LVTTL 2 mA 2,925 3,071 3,071 3,071 ps
8 mA 1,496 1,571 1,571 1,571 ps
12 mA 937 984 984 984 ps
16 mA 1,003 1,053 1,053 1,053 ps
1.8-V LVTTL 2 mA 7,101 7,456 7,456 7,456 ps
8 mA 3,620 3,801 3,801 3,801 ps
12 mA 3,109 3,265 3,265 3,265 ps
1.5-V LVTTL 2 mA 10,941 11,488 11,488 11,488 ps
4 mA 7,431 7,803 7,803 7,803 ps
8 mA 5,990 6,290 6,290 6,290 ps
GTL –959 –1,007 –1,007 –1,007 ps
GTL+ –438 –460 –460 –460 ps
3.3-V PCI 660 693 693 693 ps
3.3-V PCI-X 1.0 660 693 693 693 ps
Compact PCI 660 693 693 693 ps
AGP 1×660 693 693 693 ps
AGP 2×288 303 303 303 ps
CTT 631 663 663 663 ps
SSTL-3 Class I 301 316 316 316 ps
SSTL-3 Class II –359 –377 –377 –377 ps
SSTL-2 Class I 523 549 549 549 ps
SSTL-2 Class II –49 –51 –51 –51 ps
SSTL-18 Class I 2,315 2,431 2,431 2,431 ps
SSTL-18 Class II 723 759 759 759 ps
1.5-V HSTL Class I 1,687 1,771 1,771 1,771 ps
1.5-V HSTL Class II 1,095 1,150 1,150 1,150 ps
1.8-V HSTL Class I 599 629 678 744 ps
1.8-V HSTL Class II 87 102 102 102 ps
Table 4–107. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 2 of 2)
Parameter -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
4–72 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Table 4–108. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins
I/O Standard -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Sp eed Grade Unit
Min Max Min Max Min Max Min Max
LVCMOS 2 mA 1,571 1,650 1,650 1,650 ps
4 mA 594 624 624 624 ps
8 mA 208 218 218 218 ps
12 mA 0 0 0 0ps
3.3-V LVTTL 4 mA 1,571 1,650 1,650 1,650 ps
8 mA 1,393 1,463 1,463 1,463 ps
12 mA 596 626 626 626 ps
16 mA 562 590 590 590 ps
2.5-V LVTTL 2 mA 2,562 2,690 2,690 2,690 ps
8 mA 1,343 1,410 1,410 1,410 ps
12 mA 864 907 907 907 ps
16 mA 945 992 992 992 ps
1.8-V LVTTL 2 mA 6,306 6,621 6,621 6,621 ps
8 mA 3,369 3,538 3,538 3,538 ps
12 mA 2,932 3,079 3,079 3,079 ps
1.5-V LVTTL 2 mA 9,759 10,247 10,247 10,247 ps
4 mA 6,830 7,172 7,172 7,172 ps
8 mA 5,699 5,984 5,984 5,984 ps
GTL+ –333 –350 –350 –350 ps
CTT 591 621 621 621 ps
SSTL-3 Class I 267 280 280 280 ps
SSTL-3 Class II –346 –363 –363 –363 ps
SSTL-2 Class I 481 505 505 505 ps
SSTL-2 Class II –58 –61 –61 –61 ps
SSTL-18 Class I 2,207 2,317 2,317 2,317 ps
1.5-V HSTL Class I 1,966 2,064 2,064‘ 2,064 ps
1.8-V HSTL Class I 1,208 1,268 1,460 1,720 ps
Altera Corporation 4–73
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Tables 4–109 and 4–110 show the adder delays for the column and row
IOE programmable delays. These delays are controlled with the
Quartus II software logic options listed in the Parameter column.
Table 4–109. Stratix IOE Programmable Delays on Column Pins Note (1)
Parameter Setting -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
Decrease input delay
to internal cells Off 3,970 4,367 5,022 5,908 ps
Small 3,390 3,729 4,288 5,045 ps
Medium 2,810 3,091 3,554 4,181 ps
Large 224 235 270 318 ps
On 224 235 270 318 ps
Decrease input delay
to input register Off 3,900 4,290 4,933 5,804 ps
On 0000ps
Decrease input delay
to output register Off 1,240 1,364 1,568 1,845 ps
On 0000ps
Increase delay to
output pin Off 0000ps
On 397 417 417 417 ps
Increase delay to
output enable pin Off 0000ps
On 338 372 427 503 ps
Increase output clock
enable delay Off 0000ps
Small 540 594 683 804 ps
Large 1,016 1,118 1,285 1,512 ps
On 1,016 1,118 1,285 1,512 ps
Increase input clock
enable delay Off 0000ps
Small 540 594 683 804 ps
Large 1,016 1,118 1,285 1,512 ps
On 1,016 1,118 1,285 1,512 ps
Increase output
enable clock enable
delay
Off 0000ps
Small 540 594 683 804 ps
Large 1,016 1,118 1,285 1,512 ps
On 1,016 1,118 1,285 1,512 ps
Increase tZX delay to
output pin Off 0000ps
On 2,199 2,309 2,309 2,309 ps
4–74 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Table 4–110. Stratix IOE Programmable Delays on Row Pins Note (1)
Parameter Setting -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Max Min Max Min Max Min Max
Decrease input delay
to internal cells Off 3,970 4,367 5,022 5,908 ps
Small 3,390 3,729 4,288 5,045 ps
Medium 2,810 3,091 3,554 4,181 ps
Large 173 181 208 245 ps
On 173 181 208 245 ps
Decrease input delay
to input register Off 3,900 4,290 4,933 5,804 ps
On 0000ps
Decrease input delay
to output register Off 1,240 1,364 1,568 1,845 ps
On 0000ps
Increase delay to
output pin Off 0000ps
On 397 417 417 417 ps
Increase delay to
output enable pin Off 0000ps
On 348 383 441 518 ps
Increase output clock
enable delay Off 0000ps
Small 180 198 227 267 ps
Large 260 286 328 386 ps
On 260 286 328 386 ps
Increase input clock
enable delay Off 0000ps
Small 180 198 227 267 ps
Large 260 286 328 386 ps
On 260 286 328 386 ps
Increase output
enable clock enable
delay
Off 0000ps
Small 540 594 683 804 ps
Large 1,016 1,118 1,285 1,512 ps
On 1,016 1,118 1,285 1,512 ps
Increase tZX delay to
output pin Off 0000ps
On 1,993 2,092 2,092 2,092 ps
Note to Table 4–109 and Table 4–110:
(1) The delay chain delays vary for different device densities. These timing values only apply to EP1S30 and EP1S40
devices. Reference the timing information reported by the Quartus II software for other devices.
Altera Corporation 4–75
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
The scaling factors for column output pin timing in Tables 4–111 to 4–113
are shown in units of time per pF unit of capacitance (ps/pF). Add this
delay to the tCO or combinatorial timing path for output or bidir ectional
pins in addition to the I/O adder del ays shown in Tables 4–103 through
4–108 and the IOE programm able delays in Tables 4–109 and 4–110.
Table 4–111. Output Delay Adder for Loading on LVTTL/LVCMOS Output Buffers Note (1)
Conditions Output Pin Adder Delay (ps/pF)
Parameter Value 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL LVCMOS
Drive Strength
24mA 15 – – - 8
16mA 25 18 – – –
12mA 30 25 25 – 15
8mA 50 35 40 35 20
4mA 60 – – 80 30
2mA – 75 120 160 60
Note to Table 4–111:
(1) The timing information in this table is preliminary.
Table 4–112. Output Delay Adder for Loading on SSTL/HSTL Output Buffe rs Note (1)
Conditions Output Pin Adder Delay (ps/pF)
SSTL-3 SSTL-2 SSTL-1.8 1.5-V HSTL
Class I
Class II 25 25 25 25
25 20 25 20
Note to Table 4–112:
(1) The timing information in this table is preliminary.
Table 4–113. Output Delay Adder for Loading on GTL+/GTL/CTT/PCI Output Buffers Note (1)
Conditions Output Pin Adder Delay (ps/pF)
Parameter Value GTL+ GTL CTT PCI AGP
VCCIO Voltage
Level 3.3V 18 18 25 20 20
2.5V 15 18 - - -
Note to Table 4–113:
(1) The timing information in this table is preliminary.
4–76 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Maximum Input & Output Clock Rates
Tables 4–114 through 4–119 show the maximum input clock rate for
column and ro w pins in Stratix devic es.
T able 4–114. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12]
Pins in Flip-Chip Packages (Part 1 of 2)
I/O Standard -5 Speed
Grade -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
LVTTL 422 422 390 390 MHz
2.5 V 422 422 390 390 MHz
1.8 V 422 422 390 390 MHz
1.5 V 422 422 390 390 MHz
LVCMOS 422 422 390 390 MHz
GTL 300 250 200 200 MHz
GTL+ 300 250 200 200 MHz
SSTL-3 Class I 400 350 300 300 MHz
SSTL-3 Class II 400 350 300 300 MHz
SSTL-2 Class I 400 350 300 300 MHz
SSTL-2 Class II 400 350 300 300 MHz
SSTL-18 Class I 400 350 300 300 MHz
SSTL-18 Class II 400 350 300 300 MHz
1.5-V HSTL Class I 400 350 300 300 MHz
1.5-V HSTL Class II 400 350 300 300 MHz
1.8-V HSTL Class I 400 350 300 300 MHz
1.8-V HSTL Class II 400 350 300 300 MHz
3.3-V PCI 422 422 390 390 MHz
3.3-V PCI-X 1.0 422 422 390 390 MHz
Compact PCI 422 422 390 390 MHz
AGP 1×422 422 390 390 MHz
AGP 2×422 422 390 390 MHz
CTT 300 250 200 200 MHz
Differential 1.5-V HSTL
C1 400 350 300 300 MHz
LVPECL (1) 645 645 622 622 MHz
PCML (1) 300 275 275 275 MHz
Altera Corporation 4–77
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
LVDS (1) 645 645 622 622 MHz
HyperTransport
technology (1) 500 500 450 450 MHz
Table 4–115. Stratix Maximum Input Clock Ra te for CLK[0, 2, 9, 11] Pins &
FPLL[10..7]CLK Pins in Flip-Chip Packages
I/O Standard -5 Speed
Grade -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
LVTTL 422 422 390 390 MHz
2.5 V 422 422 390 390 MHz
1.8 V 422 422 390 390 MHz
1.5 V 422 422 390 390 MHz
LVCMOS 422 422 390 390 MHz
GTL+ 300 250 200 200 MHz
SSTL-3 Class I 400 350 300 300 MHz
SSTL-3 Class II 400 350 300 300 MHz
SSTL-2 Class I 400 350 300 300 MHz
SSTL-2 Class II 400 350 300 300 MHz
SSTL-18 Class I 400 350 300 300 MHz
SSTL-18 Class II 400 350 300 300 MHz
1.5-V HSTL Class I 400 350 300 300 MHz
1.8-V HSTL Class I 400 350 300 300 MHz
CTT 300 250 200 200 MHz
Differential 1.5-V HSTL
C1 400 350 300 300 MHz
LVPECL (1) 717 717 640 640 MHz
PCML (1) 400 375 350 350 MHz
LVDS (1) 717 717 640 640 MHz
HyperTransport
technology (1) 717 717 640 640 MHz
T able 4–114. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12]
Pins in Flip-Chip Packages (Part 2 of 2)
I/O Standard -5 Speed
Grade -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
4–78 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Table 4–116. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in
Flip-Chip Packages
I/O Standard -5 Speed
Grade -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
LVTTL 422 422 390 390 MHz
2.5 V 422 422 390 390 MHz
1.8 V 422 422 390 390 MHz
1.5 V 422 422 390 390 MHz
LVCMOS 422 422 390 390 MHz
GTL+ 300 250 200 200 MHz
SSTL-3 Class I 400 350 300 300 MHz
SSTL-3 Class II 400 350 300 300 MHz
SSTL-2 Class I 400 350 300 300 MHz
SSTL-2 Class II 400 350 300 300 MHz
SSTL-18 Class I 400 350 300 300 MHz
SSTL-18 Class II 400 350 300 300 MHz
1.5-V HSTL Class I 400 350 300 300 MHz
1.8-V HSTL Class I 400 350 300 300 MHz
CTT 300 250 200 200 MHz
Differential 1.5-V HSTL
C1 400 350 300 300 MHz
LVPECL (1) 645 645 640 640 MHz
PCML (1) 300 275 275 275 MHz
LVDS (1) 645 645 640 640 MHz
HyperTransport
technology (1) 500 500 450 450 MHz
T able 4–117. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12]
Pins in Wire-Bond Packages (Part 1 of 2)
I/O Standard -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
LVTTL 422 390 390 MHz
2.5 V 422 390 390 MHz
1.8 V 422 390 390 MHz
1.5 V 422 390 390 MHz
LVCMOS 422 390 390 MHz
GTL 250 200 200 MHz
Altera Corporation 4–79
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
GTL+ 250 200 200 MHz
SSTL-3 Class I 300 250 250 MHz
SSTL-3 Class II 300 250 250 MHz
SSTL-2 Class I 300 250 250 MHz
SSTL-2 Class II 300 250 250 MHz
SSTL-18 Class I 300 250 250 MHz
SSTL-18 Class II 300 250 250 MHz
1.5-V HSTL Class I 300 180 180 MHz
1.5-V HSTL Class II 300 180 180 MHz
1.8-V HSTL Class I 300 180 180 MHz
1.8-V HSTL Class II 300 180 180 MHz
3.3-V PCI 422 390 390 MHz
3.3-V PCI-X 1.0 422 390 390 MHz
Compact PCI 422 390 390 MHz
AGP 1×422 390 390 MHz
AGP 2×422 390 390 MHz
CTT 250 180 180 MHz
Differential 1.5-V HSTL
C1 300 180 180 MHz
LVPECL (1) 422 400 400 MHz
PCML (1) 215 200 200 MHz
LVDS (1) 422 400 400 MHz
HyperTransport
technology (1) 422 400 400 MHz
Table 4–118. Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins &
FPLL[10..7]CLK Pins in Wire-Bond Packages (Part 1 of 2)
I/O Standard -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
LVTTL 422 390 390 MHz
2.5 V 422 390 390 MHz
1.8 V 422 390 390 MHz
1.5 V 422 390 390 MHz
T able 4–117. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12]
Pins in Wire-Bond Packages (Part 2 of 2)
I/O Standard -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
4–80 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
LVCMOS 422 390 390 MHz
GTL+ 250 200 200 MHz
SSTL-3 Class I 350 300 300 MHz
SSTL-3 Class II 350 300 300 MHz
SSTL-2 Class I 350 300 300 MHz
SSTL-2 Class II 350 300 300 MHz
SSTL-18 Class I 350 300 300 MHz
SSTL-18 Class II 350 300 300 MHz
1.5-V HSTL Class I 350 300 300 MHz
1.8-V HSTL Class I 350 300 300 MHz
CTT 250 200 200 MHz
Differential 1.5-V HSTL
C1 350 300 300 MHz
LVPECL (1) 717 640 640 MHz
PCML (1) 375 350 350 MHz
LVDS (1) 717 640 640 MHz
HyperTransport
technology (1) 717 640 640 MHz
Table 4–119. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in
Wire-Bond Packages (Part 1 of 2)
I/O Standard -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
LVTTL 422 390 390 MHz
2.5 V 422 390 390 MHz
1.8 V 422 390 390 MHz
1.5 V 422 390 390 MHz
LVCMOS 422 390 390 MHz
GTL+ 250 200 200 MHz
SSTL-3 Class I 350 300 300 MHz
SSTL-3 Class II 350 300 300 MHz
SSTL-2 Class I 350 300 300 MHz
SSTL-2 Class II 350 300 300 MHz
Table 4–118. Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins &
FPLL[10..7]CLK Pins in Wire-Bond Packages (Part 2 of 2)
I/O Standard -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
Altera Corporation 4–81
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Tables 4–120 through 4–123 show the maximum output clock rate for
column and ro w pins in Stratix devic es.
SSTL-18 Class I 350 300 300 MHz
SSTL-18 Class II 350 300 300 MHz
1.5-V HSTL Class I 350 300 300 MHz
1.8-V HSTL Class I 350 300 300 MHz
CTT 250 200 200 MHz
Differential 1.5-V HSTL
C1 350 300 300 MHz
LVPECL (1) 645 622 622 MHz
PCML (1) 275 275 275 MHz
LVDS (1) 645 622 622 MHz
HyperTransport
technology (1) 500 450 450 MHz
Note to Tables 4–114 through 4–119:
(1) These parameters are only available on row I/O pins.
Table 4–120. Stratix Maximum Output Clock Rate for PLL[ 5, 6, 11, 12] Pins
in Flip-Chip Packages (Part 1 of 2)
I/O Standard -5 Speed
Grade -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
LVTTL 350 300 250 250 MHz
2.5 V 350 300 300 300 MHz
1.8 V 250 250 250 250 MHz
1.5 V 225 200 200 200 MHz
LVCMOS 350 300 250 250 MHz
GTL 200 167 125 125 MHz
GTL+ 200 167 125 125 MHz
SSTL-3 Class I 200 167 167 133 MHz
SSTL-3 Class II 200 167 167 133 MHz
SSTL-2 Class I (3) 200 200 167 167 MHz
SSTL-2 Class I (4) 200 200 167 167 MHz
SSTL-2 Class I (5) 150 134 134 134 MHz
Table 4–119. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in
Wire-Bond Packages (Part 2 of 2)
I/O Standard -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
4–82 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
SSTL-2 Class II (3) 200 200 167 167 MHz
SSTL-2 Class II (4) 200 200 167 167 MHz
SSTL-2 Class II (5) 150 134 134 134 MHz
SSTL-18 Class I 150 133 133 133 MHz
SSTL-18 Class II 150 133 133 133 MHz
1.5-V HSTL Class I 250 225 200 200 MHz
1.5-V HSTL Class II 225 200 200 200 MHz
1.8-V HSTL Class I 250 225 200 200 MHz
1.8-V HSTL Class II 225 200 200 200 MHz
3.3-V PCI 350 300 250 250 MHz
3.3-V PCI-X 1.0 350 300 250 250 MHz
Compact PCI 350 300 250 250 MHz
AGP 1×350 300 250 250 MHz
AGP 2×350 300 250 250 MHz
CTT 200 200 200 200 MHz
Differential 1.5-V HSTL
C1 225 200 200 200 MHz
Differential 1.8-V HSTL
Class I 250 225 200 200 MHz
Differential 1.8-V HSTL
Class II 225 200 200 200 MHz
Differential SSTL-2 (6) 200 200 167 167 MHz
LVPECL (2) 500 500 500 500 MHz
PCML (2) 350 350 350 350 MHz
LVDS (2) 500 500 500 500 MHz
HyperTransport
technology (2) 350 350 350 350 MHz
Table 4–120. Stratix Maximum Output Clock Rate for PLL[ 5, 6, 11, 12] Pins
in Flip-Chip Packages (Part 2 of 2)
I/O Standard -5 Speed
Grade -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
Altera Corporation 4–83
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
T ab le 4–121. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1,
2, 3, 4] Pins in Flip-Chip Packages
I/O Standard -5 Speed
Grade -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
LVTTL 400 350 300 300 MHz
2.5 V 400 350 300 300 MHz
1.8 V 400 350 300 300 MHz
1.5 V 350 300 300 300 MHz
LVCMOS 400 350 300 300 MHz
GTL 200 167 125 125 MHz
GTL+ 200 167 125 125 MHz
SSTL-3 Class I 167 150 133 133 MHz
SSTL-3 Class II 167 150 133 133 MHz
SSTL-2 Class I 150 133 133 133 MHz
SSTL-2 Class II 150 133 133 133 MHz
SSTL-18 Class I 150 133 133 133 MHz
SSTL-18 Class II 150 133 133 133 MHz
1.5-V HSTL Class I 250 225 200 200 MHz
1.5-V HSTL Class II 225 225 200 200 MHz
1.8-V HSTL Class I 250 225 200 200 MHz
1.8-V HSTL Class II 225 225 200 200 MHz
3.3-V PCI 250 225 200 200 MHz
3.3-V PCI-X 1.0 225 225 200 200 MHz
Compact PCI 400 350 300 300 MHz
AGP 1×400 350 300 300 MHz
AGP 2×400 350 300 300 MHz
CTT 300 250 200 200 MHz
LVPECL (2) 717 717 500 500 MHz
PCML (2) 420 420 420 420 MHz
LVDS (2) 717 717 500 500 MHz
HyperTransport
technology (2) 420 420 420 420 MHz
4–84 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
Table 4–122. Stratix Maximum Output Clock Rate for PLL[5, 6, 11 , 12] Pins
in Wire-Bond Packages (Part 1 of 2)
I/O Standard -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
LVTTL 175 150 150 MHz
2.5 V 175 150 150 MHz
1.8 V 175 150 150 MHz
1.5 V 175 150 150 MHz
LVCMOS 175 150 150 MHz
GTL 125 100 100 MHz
GTL+ 125 100 100 MHz
SSTL-3 Class I 110 90 90 MHz
SSTL-3 Class II 133 125 125 MHz
SSTL-2 Class I 166 133 133 MHz
SSTL-2 Class II 133 100 100 MHz
SSTL-18 Class I 110 100 100 MHz
SSTL-18 Class II 110 100 100 MHz
1.5-V HSTL Class I 167 167 167 MHz
1.5-V HSTL Class II 167 133 133 MHz
1.8-V HSTL Class I 167 167 167 MHz
1.8-V HSTL Class II 167 133 133 MHz
3.3-V PCI 167 167 167 MHz
3.3-V PCI-X 1.0 167 133 133 MHz
Compact PCI 175 150 150 MHz
AGP 1×175 150 150 MHz
AGP 2×175 150 150 MHz
CTT 125 100 100 MHz
Differential 1.5-V HSTL
C1 167 133 133 MHz
Differential 1.8-V HSTL
Class I 167 167 167 MHz
Differential 1.8-V HSTL
Class II 167 133 133 MHz
Differential SSTL-2 (1) 110 100 100 MHz
LVPECL (2) 311 275 275 MHz
PCML (2) 250 200 200 MHz
Altera Corporation 4–85
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
LVDS (2) 311 275 275 MHz
HyperTransport
technology (2) 311 275 275 MHz
T able 4–123. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1,
2, 3, 4] Pins in Wire-Bond Packages (Part 1 of 2)
I/O Standard -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
LVTTL 200 175 175 MHz
2.5 V 200 175 175 MHz
1.8 V 200 175 175 MHz
1.5 V 200 175 175 MHz
LVCMOS 200 175 175 MHz
GTL 125 100 100 MHz
GTL+ 125 100 100 MHz
SSTL-3 Class I 110 90 90 MHz
SSTL-3 Class II 150 133 133 MHz
SSTL-2 Class I 90 80 80 MHz
SSTL-2 Class II 110 100 100 MHz
SSTL-18 Class I 110 100 100 MHz
SSTL-18 Class II 110 100 100 MHz
1.5-V HSTL Class I 225 200 200 MHz
1.5-V HSTL Class II 200 167 167 MHz
1.8-V HSTL Class I 225 200 200 MHz
1.8-V HSTL Class II 200 167 167 MHz
3.3-V PCI 200 175 175 MHz
3.3-V PCI-X 1.0 200 175 175 MHz
Compact PCI 200 175 175 MHz
AGP 1×200 175 175 MHz
AGP 2×200 175 175 MHz
CTT 125 100 100 MHz
LVPECL (2) 311 270 270 MHz
PCML (2) 400 311 311 MHz
Table 4–122. Stratix Maximum Output Clock Rate for PLL[5, 6, 11 , 12] Pins
in Wire-Bond Packages (Part 2 of 2)
I/O Standard -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
4–86 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
Timing Model
LVDS (2) 400 311 311 MHz
HyperTransport
technology (2) 420 400 400 MHz
Notes to Tables 4–120 through 4–123:
(1) Differential SSTL-2 outputs are only available on column clock pins.
(2) These parameters are only available on row I/O pins.
(3) SSTL-2 in maximum drive strength condition. See Table 4–101 on page 4–62 for
more information on exact loading conditions for each I/O standard.
(4) SSTL-2 in minimum drive strength with ≤ 10pF output load condition.
(5) SSTL-2 in minimum drive strength with > 10pF output load condition.
(6) Differential SSTL-2 outputs are only supported on column clock pins.
T able 4–123. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1,
2, 3, 4] Pins in Wire-Bond Packages (Part 2 of 2)
I/O Standard -6 Speed
Grade -7 Speed
Grade -8 Speed
Grade Unit
Altera Corporation 4–87
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
High-Speed I/O
Specification Table 4–124 provides high-speed timing specifications definitions.
Table 4–124. High-Speed Ti ming Specifications & Terminology
High-Speed Timing Specification Terminology
tCHigh-speed receiver/transmitter input and output clock period.
fHSCLK High-speed receiver/transmitter input and output clock frequency.
tRISE Low-to-high transmission time.
tFALL High-to-low transmission time.
Timing unit interval (TUI) The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = tC/w).
fHSDR Maximum LVDS data transfer rate (fHSDR = 1/TUI).
Channel-to-channel skew (TCCS) The timing difference between the fastest and slowest output edges,
including tCO variation and clock sk ew . The cloc k is included in the TCCS
measurement.
Sampling window (SW) The period of time during which the data must be valid to be captured
correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
SW = tSW (max) – tSW (min).
Input jitter (peak-to-peak) Peak-to-peak input jitter on high-speed PLLs.
Output jitter (peak-to-peak) Peak-to-peak output jitter on high-speed PLLs.
tDUTY Duty cycle on high-speed transmitter output clock.
tLOCK Lock time for high-speed transmitter and receiver PLLs.
J Deserialization factor (width of internal data bus).
W PLL multiplication factor.
4–88 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
High-Speed I/O Specification
Tables 4–125 and 4–126 show the high- speed I/O timing f or Stratix devices.
Table 4–125. High-Speed I/O Specifications for Flip-Chip Packages (Part 1 of 4) Notes (1), (2)
Symbol Conditions -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
fHSCLK (Clock
frequency)
(LVDS,
LVPECL,
HyperTransport
technology)
fHSCLK = fHSDR /
W
W = 4 to 30
(Serdes used) 10 210 10 210 10 156 10 115.5 MHz
W = 2 (Serdes
bypass) 50 231 50 231 50 231 50 231 MHz
W = 2 (Serdes
used) 150 420 150 420 150 312 150 231 MHz
W = 1 (Serdes
bypass) 100 462 100 462 100 462 100 462 MHz
W = 1 (Serdes
used) 300 717 300 717 300 624 300 462 MHz
fHSDR Device
operation
(LVDS,
LVPECL,
HyperTransport
technology)
J = 10 300 840 300 840 3 00 640 300 462 Mbps
J = 8 300 840 300 840 300 640 300 462 Mbps
J = 7 300 840 300 840 300 640 300 462 Mbps
J = 4 300 840 300 840 300 640 300 462 Mbps
J = 2 100 462 100 462 100 640 100 462 Mbps
J = 1 (LVDS
and LVPECL
only)
100 462 100 462 100 640 100 462 Mbps
Altera Corporation 4–89
January 2006 Stratix Device Handbook, Volume 1
High-Speed I/O Specification
fHSCLK (Clock
frequency)
(PCML)
fHSCLK = fHSDR /
W
W = 4 to 30
(Serdes used) 10 100 10 100 10 77.75 10 77.75 MHz
W = 2 (Serdes
bypass) 50 200 50 200 50 150 50 150 MHz
W = 2 (Serdes
used) 150 200 150 200 150 155.5 150 155.5 MHz
W = 1 (Serdes
bypass) 100 250 100 250 100 200 100 200 MHz
W = 1 (Serdes
used) 300 400 300 400 300 311 300 311 MHz
fHSDR Device
operation
(PCML)
J = 10 300 400 300 400 3 00 311 300 311 Mbps
J = 8 300 400 300 400 300 311 300 311 Mbps
J = 7 300 400 300 400 300 311 300 311 Mbps
J = 4 300 400 300 400 300 311 300 311 Mbps
J = 2 100 400 100 400 100 300 100 300 Mbps
J = 1 100 250 100 250 100 200 100 200 Mbps
TCCS All 200 200 300 300 ps
Table 4–125. High-Speed I/O Specifications for Flip-Chip Packages (Part 2 of 4) Notes (1), (2)
Symbol Conditions -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
4–90 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
High-Speed I/O Specification
SW PCML (J = 4, 7,
8, 10) 750 750 800 800 ps
PCML (J= 2) 900 900 1,200 1,200 ps
PCML (J= 1) 1,500 1,500 1,700 1,700 ps
LVDS and
LVPECL (J=1) 500 500 550 550 ps
LVDS,
LVPECL,
HyperTransport
technology
(J= 2 through
10)
440 440 500 500 ps
Input jitter
tolerance
(peak-to-peak)
All 250 250 250 250 ps
Output jitter
(peak-to-peak) All 160 160 200 200 ps
Output tRISE LVDS 80 110 120 80 110 120 80 110 120 80 110 120 ps
HyperTransport
technology 110 170 200 110 170 200 120 170 200 120 170 200 ps
LVPECL 90 130 150 90 130 150 100 135 150 100 135 150 ps
PCML 80 110 135 80 110 135 80 110 135 80 110 135 ps
Output tFALL LVDS 80 110 120 80 110 120 80 110 120 80 110 120 ps
HyperTransport
technology 110 170 200 110 170 200 110 170 200 110 170 200 ps
LVPECL 90 130 160 90 130 160 100 135 160 100 135 160 ps
PCML 105 140 175 105 140 175 110 145 175 110 145 175 ps
Table 4–125. High-Speed I/O Specifications for Flip-Chip Packages (Part 3 of 4) Notes (1), (2)
Symbol Conditions -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Altera Corporation 4–91
January 2006 Stratix Device Handbook, Volume 1
High-Speed I/O Specification
tDUTY LVDS (J=2
through 10) 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 %
LVDS (J =1)
and LVPECL,
PCML,
HyperTransport
technology
45 50 55 45 50 55 45 50 55 45 50 55 %
tLOCK All 100 100 100 100 μs
Notes to Table 4–125:
(1) When J = 4, 7, 8, and 10, the SERDES block is used.
(2) When J = 2 or J = 1, the SERDES is bypassed.
Table 4–125. High-Speed I/O Specifications for Flip-Chip Packages (Part 4 of 4) Notes (1), (2)
Symbol Conditions -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
4–92 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
High-Speed I/O Specification
Table 4–126. High-Speed I/O Specifications for Wire-Bond Packages (Part 1 of 2)
Symbol Conditions -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK (Clock
frequency)
(LVDS,LVPECL,
HyperTransport
technology)
fHSCLK = fHSDR / W
W = 4 to 30 (Serdes used) 10 156 10 115.5 10 115.5 MHz
W = 2 (Serdes bypass) 50 231 50 231 50 231 MHz
W = 2 (Serdes used) 150 312 150 231 150 231 MHz
W = 1 (Serdes bypass) 100 311 100 270 100 270 MHz
W = 1 (Serdes used) 300 624 300 462 300 462 MHz
fHSDR Device oper ation,
(LVDS,LVPECL,
HyperTransport
technology)
J = 10 300 624 300 462 300 462 Mbps
J = 8 300 624 300 462 300 46 2 Mbps
J = 7 300 624 300 462 300 46 2 Mbps
J = 4 300 624 300 462 300 46 2 Mbps
J = 2 100 462 100 462 100 46 2 Mbps
J = 1 (LVDS and LVPECL
only) 100 311 100 270 100 270 Mbps
fHSCLK (Clock
frequency)
(PCML)
fHSCLK = fHSDR / W
W = 4 to 30 (Serdes used) 10 77.75 MHz
W = 2 (Serdes bypass) 50 150 50 77.5 50 77.5 MHz
W = 2 (Serdes used) 150 155.5 MHz
W = 1 (Serdes bypass) 100 200 100 155 100 155 MHz
W = 1 (Serdes used) 300 311 MHz
Device operation,
fHSDR
(PCML)
J = 10 300 311 Mbps
J = 8 300 311 Mbps
J = 7 300 311 Mbps
J = 4 300 311 Mbps
J = 2 100 300 100 155 100 15 5 Mbps
J = 1 100 200 100 155 100 15 5 Mbps
TCCS All 400 400 400 ps
Altera Corporation 4–93
January 2006 Stratix Device Handbook, Volume 1
High-Speed I/O Specification
SW PCML (J = 4, 7, 8, 10) only 800 800 800 ps
PCML (J = 2) only 1,200 1,200 1,200 ps
PCML (J = 1) only 1,700 1,700 1,700 ps
LVDS and LVPECL (J = 1)
only 550 550 550 ps
LVDS, LVPECL,
HyperTransport technology
(J = 2 through 10) only
500 500 500 ps
Input jitter tolerance
(peak-to-peak) All 250 250 250 ps
Output jitter (peak-to-
peak) All 200 200 200 ps
Output tRISE LVDS 80 110 120 80 110 120 80 110 120 ps
HyperTransport technology 120 170 200 120 170 200 120 170 200 ps
LVPECL 100 135 150 100 135 150 100 135 150 ps
PCML 80 110 135 80 110 135 80 110 135 ps
Output tFALL LVDS 80 110 120 80 110 120 80 110 120 ps
HyperTransport 110 170 200 110 170 200 110 170 200 ps
LVPECL 100 135 160 100 135 160 100 135 160 ps
PCML 110 145 175 110 145 175 110 145 175 ps
tDUTY LVDS (J = 2 through10) only 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 %
LVDS (J =1) and LVPECL,
PCML, HyperTransport
technology
45 50 55 45 50 55 45 50 55 %
tLOCK All 100 100 100 μs
Table 4–126. High-Speed I/O Specifications for Wire-Bond Packages (Part 2 of 2)
Symbol Conditions -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Typ Max Min Typ Max Min Typ Max
4–94 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
PLL Specifications
PLL
Specifications Tables 4–127 through 4–129 describe the Stratix dev ice enhanced PL L
specifications.
Table 4–127. Enhanced PLL Specifications for -5 Speed Grades (Part 1 of 2)
Symbol Parameter Min Typ Max Unit
fIN Input clock frequency 3
(1), (2) 684 MHz
fINPFD Input frequency to PFD 3 420 MHz
fINDUTY Input clock duty cycle 40 60 %
fEINDUTY External feedback clock input duty
cycle 40 60 %
tINJITTER Input clock period jitter ±200 (3) ps
tEINJITTER External feedback clock period jitter ±200 (3) ps
tFCOMP External feedback clock
compensation time (4) 6ns
fOUT Output frequency for internal global
or regional clock 0.3 500 MHz
fOUT_EXT Output frequency for external clock
(3) 0.3 526 MHz
tOUTDUTY Duty cycle for external clock output
(when set to 50%)45 55 %
tJITTER P eriod jitter for e xternal clock output
(6) ±100 ps for >200-MHz outclk
±20 mUI for <200-MHz outclk ps or
mUI
tCONFIG5,6 Time required to reconfigure the
scan chains for PLLs 5 and 6 289/fSCANCLK
tCONFIG11,12 Time required to reconfigure the
scan chains for PLLs 11 and 12 193/fSCANCLK
tSCANCLK scanclk frequency (5) 22 MHz
tDLOCK Time required to lock dynamically
(after switchover or reconfiguring
any non-post-scale
counters/delays) (7)
100 μs
tLOCK Time required to lock from end of
device configuration 10 400 μs
fVCO PLL internal VCO operating range 300 800 (8) MHz
tLSKEW Clock skew between two external
clock outputs driven by the same
counter
±50 ps
Altera Corporation 4–95
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
tSKEW Clock skew between two external
clock outputs driv en b y the diff erent
counters with the same settings
±75 ps
fSS Spread spectrum modulation
frequency 30 150 kHz
% spread Percentage spread for spread
spectrum frequency (10) 0.4 0.5 0.6 %
tARESET Minimum pulse width on areset
signal 10 ns
tARESET_RECON
FIG Minimum pulse width on the
areset signal when using PLL
reconfiguration. Reset the PLL after
scandataout goes high.
500 ns
Table 4–128. Enhanced PLL Specifications for -6 Speed Grades (Part 1 of 2)
Symbol Parameter Min Typ Max Unit
fIN Input clock frequency 3
(1), (2) 650 MHz
fINPFD Input frequency to PFD 3 420 MHz
fINDUTY Input clock duty cycle 40 60 %
fEINDUTY External feedback clock input duty
cycle 40 60 %
tINJITTER Input clock period jitter ±200 (3) ps
tEINJITTER External feedback clock period jitter ±200 (3) ps
tFCOMP External feedback clock compensation
time (4) 6ns
fOUT Output frequency for internal global or
regional clock 0.3 450 MHz
fOUT_EXT Output frequency for external clock (3) 0.3 500 MHz
tOUTDUTY Duty cycle for external clock output
(when set to 50%)45 55 %
tJITTER Period jitter for external clock output
(6) ±100 ps for >200-MHz outclk
±20 mUI for <200-MHz outclk ps or
mUI
tCONFIG5,6 Time required to reconfigure the scan
chains for PLLs 5 and 6 289/fSCANCLK
tCONFIG11,12 Time required to reconfigure the scan
chains for PLLs 11 and 12 193/fSCANCLK
Table 4–127. Enhanced PLL Specifications for -5 Speed Grades (Part 2 of 2)
Symbol Parameter Min Typ Max Unit
4–96 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
PLL Specifications
tSCANCLK scanclk frequency (5) 22 MHz
tDLOCK Time required to lock dynamically
(after switchover or reconfiguring any
non-post-scale counters/delays) (7)
(11)
(9) 100 μs
tLOCK Time required to lock from end of
device configuration (11) 10 400 μs
fVCO PLL internal VCO operating range 300 800 (8) MHz
tLSKEW Clock skew between two external
clock outputs driven by the same
counter
±50 ps
tSKEW Clock skew between two external
clock outputs driven by the different
counters with the same settings
±75 ps
fSS Spread spectrum modulation
frequency 30 150 kHz
% spread Percentage spread for spread
spectrum frequency (10) 0.4 0.5 0.6 %
tARESET Minimum pulse width on areset
signal 10 ns
Table 4–129. Enhanced PLL Specifications for -7 Speed Grade (Part 1 of 2)
Symbol Parameter Min Typ Max Unit
fIN Input clock frequency 3
(1), (2) 565 MHz
fINPFD Input frequency to PFD 3 420 MHz
fINDUTY Input clock duty cycle 40 60 %
fEINDUTY External feedback clock input duty
cycle 40 60 %
tINJITTER Input clock period jitter ±200 (3) ps
tEINJITTER External feedback clock period jitter ±200 (3) ps
tFCOMP External feedback clock
compensation time (4) 6ns
fOUT Output frequency for internal global
or regional clock 0.3 420 MHz
fOUT_EXT Output frequency for external clock
(3) 0.3 434 MHz
Table 4–128. Enhanced PLL Specifications for -6 Speed Grades (Part 2 of 2)
Symbol Parameter Min Typ Max Unit
Altera Corporation 4–97
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
tOUTDUTY Duty cycle for external clock output
(when set to 50%)45 55 %
tJITTER Period jitter for external clock output
(6) ±100 ps for >200-MHz outclk
±20 mUI for <200-MHz outclk ps or
mUI
tCONFIG5,6 Time required to reconfigure the
scan chains for PLLs 5 and 6 289/fSCANCLK
tCONFIG11,12 Time required to reconfigure the
scan chains for PLLs 11 and 12 193/fSCANCLK
tSCANCLK scanclk frequency (5) 22 MHz
tDLOCK Time required to lock dynamically
(after switchover or reconfiguring any
non-post-scale counters/delays) (7)
(11)
(9) 100 μs
tLOCK Time required to lock from end of
device configuration (11) 10 400 μs
fVCO PLL internal VCO operating range 300 600 (8) MHz
tLSKEW Clock skew between two external
clock outputs driven by the same
counter
±50 ps
tSKEW Clock skew between two external
clock outputs driven by the different
counters with the same settings
±75 ps
fSS Spread spectrum modulation
frequency 30 150 kHz
% spread Percentage spread for spread
spectrum frequency (10) 0.5 0.6 %
tARESET Minimum pulse width on areset
signal 10 ns
Table 4–130. Enhanced PLL Specifications for -8 Speed Grade (Part 1 of 3)
Symbol Parameter Min Typ Max Unit
fIN Input clock frequency 3
(1), (2) 480 MHz
fINPFD Input frequency to PFD 3 420 MHz
fINDUTY Input clock duty cycle 40 60 %
fEINDUTY External feedback clock input duty
cycle 40 60 %
tINJITTER Input clock period jitter ±200 (3) ps
Table 4–129. Enhanced PLL Specifications for -7 Speed Grade (Part 2 of 2)
Symbol Parameter Min Typ Max Unit
4–98 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
PLL Specifications
tEINJITTER External feedback clock period jitter ±200 (3) ps
tFCOMP External feedback clock
compensation time (4) 6ns
fOUT Output frequency for internal global
or regional clock 0.3 357 MHz
fOUT_EXT Output frequency for external clock
(3) 0.3 369 MHz
tOUTDUTY Duty cycle for external clock output
(when set to 50%)45 55 %
tJITTER Period jitter for e xternal clock output
(6) ±100 ps for >200-MHz outclk
±20 mUI for <200-MHz outclk ps or
mUI
tCONFIG5,6 Time required to reconfigure the
scan chains for PLLs 5 and 6 289/fSCANCLK
tCONFIG11,12 Time required to reconfigure the
scan chains for PLLs 11 and 12 193/fSCANCLK
tSCANCLK scanclk frequency (5) 22 MHz
tDLOCK Time required to lock dynamically
(after switchover or reconfiguring
any non-post-scale counters/delays)
(7) (11)
(9) 100 μs
tLOCK Time required to lock from end of
device configuration (11) 10 400 μs
fVCO PLL internal VCO operating range 300 600 (8) MHz
Table 4–130. Enhanced PLL Specifications for -8 Speed Grade (Part 2 of 3)
Symbol Parameter Min Typ Max Unit
Altera Corporation 4–99
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
tLSKEW Clock skew between two external
clock outputs driven by the same
counter
±50 ps
tSKEW Clock skew between two external
clock outputs driven by the different
counters with the same settings
±75 ps
fSS Spread spectrum modulation
frequency 30 150 kHz
% spread Percentage spread for spread
spectrum frequency (10) 0.5 0.6 %
tARESET Minimum pulse width on areset
signal 10 ns
Notes to Tables 4–127 through 4–130:
(1) The minimum input clock frequency to the PFD (fIN/N) must be at least 3 MHz for Stratix device enhanced PLLs.
(2) Use this equation (fOUT = fIN * ml(n × post-scale counter)) in conjunction with the specified fINPFD and fVCO ranges
to determine the allowed PLL settings.
(3) See “Maximum Input & Output Clock Rates” on page 4–76.
(4) tFCOMP can also equal 50% of the input clock period multiplied by the pre-scale divider n (whichever is less).
(5) This parameter is timing analyzed by the Quartus II software because the scanclk and scandata ports can be
driven by the logic array.
(6) Actual jitter performance may vary based on the system configuration.
(7) Total required time to r econfigure and lock is equal to tDLOCK + tCONFIG. If only post-scale counters and delays are
changed, then tDLOCK is equal to 0.
(8) When using the spread-spectrum fe ature, the minimum VCO frequency is 500 MHz. The maximum VCO
frequency is determined by the speed grade selected.
(9) Lock time is a function of PLL configuration and may be significantly faster depending on bandwidth settings or
feedback counter change inc rement .
(10) Exact, user-controllable value depends on the PL L settings.
(1 1) The LOCK cir cuit on Stratix PLLs does not work for industrial devices below -20C unless the PFD frequency > 200
MHz. See the Stratix FPGA Errata Sheet for more information on the PLL.
Table 4–130. Enhanced PLL Specifications for -8 Speed Grade (Part 3 of 3)
Symbol Parameter Min Typ Max Unit
4–100 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
PLL Specifications
Tables 4–131 through 4–133 describe the Stratix dev ic e fast PLL
specifications.
Table 4–131. Fast PLL Specifications for -5 & -6 Speed Grade Devices
Symbol Parameter Min Max Unit
fIN CLKIN frequency (1), (2), (3) 10 717 MHz
fINPFD Input frequency to PFD 10 500 MHz
fOUT Output frequency for internal global or
regional clock (3) 9.375 420 MHz
fOUT_DIFFIO Output frequency for external clock
driven out on a differential I/O data
channel (2)
(5) (5)
fVCO VCO operating frequency 300 1,000 MHz
tINDUTY CLKIN duty cycle 40 60 %
tINJITTER Period jitter for CLKIN pin ±200 ps
tDUTY Duty cycle fo r DFFIO 1× CLKOUT pin (6) 45 55 %
tJITTER Period jitter for DIFFIO clock out (6) (5) ps
tLOCK Time required for PLL to acquire lock 10 100 μs
m Multiplication factors for m counter (6) 1 32 Integer
l0, l1, g0 Multiplication factors for l0, l1, and g0
counter (7), (8) 1 32 Integer
tARESET Minimum pulse width on areset
signal 10 ns
Table 4–132. Fast PLL Specifications for -7 Speed Grades (Part 1 of 2)
Symbol Parameter Min Max Unit
fIN CLKIN frequency (1), (3) 10 640 MHz
fINPFD Input frequency to PFD 10 500 MHz
fOUT Output frequency for internal global or
regional clock (4) 9.375 420 MHz
fOUT_DIFFIO Output frequency for external clock
driven out on a differential I/O data
channel
(5) (5) MHz
fVCO VCO operating frequency 300 700 MHz
tINDUTY CLKIN duty cycle 40 60 %
tINJITTER Period jitter for CLKIN pin ±200 ps
tDUTY Duty cycle f or DFFIO 1× CLKOUT pin (6) 45 55 %
Altera Corporation 4–101
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
tJITTER Period jitter for DIFFIO clock out (6) (5) ps
tLOCK Time required for PLL to acquire lock 10 100 μs
m Multiplication factors for m counter (7) 1 32 Integer
l0, l1, g0 Multiplication factors for l0, l1, and g0
counter (7), (8) 1 32 Integer
tARESET Minimum pulse width on areset
signal 10 ns
Table 4–133. Fast PLL Specifications for -8 Speed Grades (Part 1 of 2)
Symbol Parameter Min Max Unit
fIN CLKIN frequency (1), (3) 10 460 MHz
fINPFD Input frequency to PFD 10 500 MHz
fOUT Output frequency for internal global or
regional clock (4) 9.375 420 MHz
fOUT_DIFFIO Output frequency for external clock
driven out on a differential I/O data
channel
(5) (5) MHz
fVCO VCO operating frequency 300 700 MHz
tINDUTY CLKIN duty cycle 40 60 %
tINJITTER Period jitter for CLKIN pin ±200 ps
tDUTY Duty cycle f or DFFIO 1× CLKOUT pin (6) 45 55 %
tJITTER Period jitter for DIFFIO clock out (6) (5) ps
tLOCK Time required for PLL to acquire lock 10 100 μs
m Multiplication factors for m counter (7) 1 32 Integer
l0, l1, g0 Multiplication factors for l0, l1, and g0
counter (7), (8) 1 32 Integer
Table 4–132. Fast PLL Specifications for -7 Speed Grades (Part 2 of 2)
Symbol Parameter Min Max Unit
4–102 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
DLL Specifications
DLL
Specifications Table 4–134 reports the jitter for the DLL in the DQS phase shift refer ence
circuit.
fFor more information on DLL jitter, see the DDR SRAM section in the
Stratix Architecture chapter of the Stratix Device Handbook, Volume 1.
Table 4–135 lists the Stratix DLL low frequency limit for full phase shift
across all PVT conditions. The Stratix DLL can be used below these
frequenci es, but it will not achieve the full phase shift request ed across all
tARESET Minimum pulse width on areset
signal 10 ns
Notes to Tables 4–131 through 4–133:
(1) See “Maximum Input & Output Clock Rates” on page 4–76.
(2) PLLs 7, 8, 9, and 10 in the EP1S80 device support up to 717-MHz input and output.
(3) Use this equation (fOUT = fIN * ml(n × post-scale counter)) in conjunction with the specified fINPFD and fVCO
ranges to determine the allowed PLL settings.
(4) When using the SERDES, high-speed differential I/O mode supports a maximum output frequency of 210 MHz
to the global or regional clocks (that is, the maximum data rate 840 Mbps divided by the smallest SERDES J factor
of 4).
(5) Refer to the section “High-Speed I/O Specification” on page 4–87 for more information.
(6) This parameter is for high-speed differential I/O mode only.
(7) These counters have a maximum of 32 if programmed for 50/50 duty cycle. Otherwise, they have a maximum
of 16.
(8) High-speed differential I/O mode supports W = 1 to 16 and J = 4, 7, 8, or 10.
Table 4–133. Fast PLL Specifications for -8 Speed Grades (Part 2 of 2)
Symbol Parameter Min Max Unit
Table 4–134. DLL Jitter for DQS Phase Shift Reference Circuit
Frequency (MHz) DLL Jitter (ps)
197 to 200 ± 100
160 to 196 ± 300
100 to 159 ± 500
Altera Corporation 4–103
January 2006 Stratix Device Handbook, Volume 1
DC & Switching Characteristics
process and operating conditions. Run the timing analyzer in the
Quartus II software at the fast and slow operating conditions to see the
phase shift range that is achieved below these frequencies.
Table 4–135. Stratix DLL Low Frequency Limit for Full Phase Shift
Phase Shift Minimum Frequency for
Full Phase Shift Unit
72° 119 MHz
90° 149 MHz
4–104 Altera Corporation
Stratix Device Handbook, Volume 1 January 2006
DLL Specifications
Altera Corporation 5–1
September 2004
5. Reference & Ordering
Information
Software Stratix® devices are supported by the Altera® Quartus®II design
software, which pr ovides a comprehensive environment for system-on-a-
programmable-chip (SOPC) design. The Quartus II software includes
HDL and schemat ic design entry, compilation and logic synthesis, full
simulation and advanced timing analysis, SignalTap®II logic analyzer,
and device configuration. See the Design Software Selector Guide for more
details on the Quartus II software featur es.
The Quartus II software supports the Windows XP/2000/NT/98, Sun
Solaris, Linux Red Hat v7.1 and HP-UX operating systems. It also
supports seamless integration with industry-leading EDA tools through
the NativeLink® interface.
Device Pin-Outs Stratix device pin-outs can be found on the Altera web site
(www.altera.com).
Ordering
Information Figure 5–1 describes the ordering codes for Stratix devices. For more
information on a specific package, see the Package Inform ation for Stratix
Devices chapter.
S51005-2.1
5–2 Altera Corporation
Stratix Device Handbook, Volume 1 September 2004
Ordering Information
Figure 5–1. Stratix Device Packaging Ordering Information
Device Type
Package Type
5, 6, or 7, with 5 being the fastest
Number of pins for a particular BGA or FineLine BGA package
ES:
B:
F: Ball-grid array (BGA)
FineLine BGA
EP1S: Stratix
10
20
25
30
40
60
80 C:
I: Commercial temperature (t
J
= 0
˚
C to 85
˚
C)
Industrial temperature (t
J
= -40
˚
C to 100
˚
C)
Optional SuffixFamily Signature
Operating Temperature
Speed Grade
Pin Count
Engineering sample
7EP1S 80C1508FES
Indicates specific device options or
shipment method.
Altera Corporation Index–1
Index
A
Accumulator 2–63
Adder/Output Blocks 2–61
Adder/Subtractor
2–63
Accumulator
2–63
AGP 1x Specifications 4–13
AGP 2x Specifications 4–13
Architecture 2–1
36 x 36 Multiply Mode 2–66
addnsub Signal 2–8
Block Diagram 2–2
Bus Hold 2–121
Byte Alig nme n t 2–140
Carry-Select Chain 2–11
Clear & Prese t Logic Control 2–13
Combined Resources 2–78
Dedicated Circuitry 2–137
Device Resources 2–3
Device Routing Scheme 2–20
Digital Signal Pr ocessing Block 2–52
Direct Link Connection 2–5
Dynamic Arithmetic Mode 2–10
in LE 2–11
Four-Multipliers
Adder Mode 2–68
Functional Description 2–1
LAB
Interconnects 2–4
Logic Array Blocks 2–3
Structure 2–4
LE Operating Modes 2–8
Logic Elements 2–6
Modes of Oper a tion 2–64
Multiplier Size & Configurations per DSP
block 2–70
Multiply-Accumulator Mode 2–67
MultiTrack Interconnect 2–14
Normal Mode 2–9
in LE 2–9
Open-Drain Output 2–120
Power Sequencing & Hot Socketing 2–140
Programmable Drive Strength 2–119
Programmable Pull -Up Resistor 2–122
Simple Multiplie r Mo de 2–64
Single-Port Mode 2–51
Slew-Rate Control 2–120
Two-Multipliers
Adder Mode 2–67
Adder Mode Implementing Complex
Multiply 2–68
C
Class I Specifications 4–11, 4–12
Class II Specifications 4–11, 4–12, 4–13
Clocks
Clock Feedback 2–96
Clock Multiplication & Division 2–88, 2–101
Clock Switchover
2–88
Delay 2–97
EP1S10, EP1S20 & EP1S25
Device I/O Clock Groups
2–80
EP1S25, EP1S20 & EP1S10 Device Fast Clock
Pin Connections to Fast Regional
Clocks 2–77
EP1S30 Device Fast Regional Clock Pin Con-
nections to Fast Regional Clocks 2–78
EP1S30, EP1S40, EP1S60, EP1S80
Device I/O Clock Groups
2–81
External Clock
Inputs 2–102
Outputs 2–92, 2–103
Outputs for Enhanced PLLs 11 & 12 2–95
Outputs for PLLs 5 & 6 2–93
Fast Regional Clock External I/O Timing
Parameters 4–34
Fast Regional Clock Network 2–76
Index–2 Altera Corporation
Stratix Device Handbook, Volume 1
Global & Hierarchical Clocking 2–73
Global & Regional Clock Connections
from Side Pins & Fast PLL Outputs 2–85
from Top Clock Pins & Enhanced PLL
Outputs 2–86
Global Clock External I/O Timing
Parameters 4–35
Global Clock Network 2–74
Global Clocking 2–75
Independent Clock Mode 2–44
Input/Output
Clock Mode
2–46
Simple Dual-Port Mode 2–48
True Dual-Port Mode 2–47
Maximum Input & Output Clock Rates 4–76
Maximum Input Cloc k Ra te
for CLK
(0, 2, 9, 11) Pins in
Flip-Chip
Packages 4–77
Wire-Bond
Packages 4–79
(1, 3, 8, 10) Pins in
Flip-Chip
Packages 4–78
Wire-Bond
Packages 4–80
(7..4) & CLK(15..12) Pins in
Flip-Chip
Packages 4–76
Wire-Bond
Packages 4–78
Maximum Output Clock Rate
for PLL(1, 2, 3, 4) Pins in
Flip-Chip
Packages 4–83
Wire-Bond
Packages 4–85
(5, 6, 11, 12) Pins in
Flip-Chip
Packages 4–81
Wire-Bond
Packages 4–84
Phase & Delay Shifting 2–96
Phase Delay 2–96
PLL Clock Networks 2–73
Read/Write Clock Mode
2–49
in Simple Dual-Port Mode 2–50
Regional Clock 2–75
External I/O Timing Parameters 4–34
Regional Clock Bus 2–79
Regional Clock Network 2–75
Spread-Spectrum Clocking 2–98
Configuration 3–5
32-Bit IDCODE 3–3
and Testing 3–1
Data Sources for Configuration 3–7
Local Update Mode 3–12
Local Update Transition Diagram 3–12
Operating Modes 3–5
Partial Reconfiguration 3–7
Remote Update 3–8
Remote Update Transition Diagram 3–11
Schemes 3–7
SignalTap II Embedded Log ic Analy zer 3–5
Stratix FPGAs with JRunner 3–7
Control Signals 2–104
D
DC Switching
Absolute Ma ximum Ratings 4–1
Bus Hold Parameters 4–16
Capacitance 4–17
DC & Switching Characteristics 4–1
External Timing Parameters 4–33
Operating Conditions 4–1
Performance 4–20
Power Consumption 4–17
Recommended Operating Condi t ions 4–1
DDR
Double-Data Rate I/O Pins 2–111
Device Features
EP1S10, EP1S20, EP1S25, EP1S30, 1–3
EP1S40, EP1S60, EP1S80, 1–3
Altera Corporation Index–3
Stratix Device Handbook, Volume 1
Differential HSTL Specifications 4–15
DSP
Block Diagram
Configuration
for 18 x 18-Bit 2–55
for 9 x 9-Bit 2–56
Block Interconnect Interface 2–71
Block Interface 2–70
Block Signal Sources & Destin ations 2–73
Blocks
Arranged in Columns 2–53
in Stratix Devices 2–54
Input Register Modes 2–60
Input Registers 2–58
Multiplier
2–60
Block 2–57
Signed Representation 2–60
Sub-Block 2–57
Sub-Blocks Using Input Shift Register
Connections 2–59
Pipeline/Post Multiply Register 2–61
E
EP1S10 Devices
Column Pin
Fast Regional Clock External I/O Timing
Parameters 4–36
Global Clock External I/O Timing
Parameters 4–37
Regional Clock External I/O Timing
Parameters 4–36
Row Pin
Fast Regional Clock External I/O Timing
Parameters 4–37
Global Clock External I/O Timing
Parameters 4–38
Regional Clock External I/O Timing
Parameters 4–38
EP1S20 Devices
Column Pin
Fast Regional Clock External I/O Timing
Parameters 4–39
Global Clock External I/O Timing
Parameters 4–40
Regional Clock External I/O Timing
Parameters 4–39
Row Pin
Fast Regional Clock External I/O Timing
Parameters 4–40
Global Clock External I/O Timing
Parameters 4–41
Regional Clock External I/O Timing
Parameters 4–41
EP1S25 Devices
Column Pin
Fast Regional Clock External I/O Timing
Parameters 4–42
Global Clock External I/O Timing
Parameters 4–43
Regional Clock External I/O Timing
Parameters 4–42
Row Pin
Fast Regional Clock External I/O Timing
Parameters 4–43
Global Clock External I/O Timing
Parameters 4–44
Regional Clock External I/O Timing
Parameters 4–44
EP1S30 Devices
Column Pin
Fast Regional Clock External I/O Timing
Parameters 4–45
Global Clock External I/O Timing
Parameters 4–45
Regional Clock External I/O Timing
Parameters 4–45
Row Pin
Fast Regional Clock External I/O Timing
Parameters 4–46
Global Clock External I/O Timing
Parameters 4–47
Regional Clock External I/O Timing
Parameters 4–47
EP1S40 Devices
Column Pin
Fast Regional Clock External I/O Timing
Parameters 4–48
Global Clock External I/O Timing
Parameters 4–49
Regional Clock External I/O Timing
Parameters 4–48
Row Pin
Index–4 Altera Corporation
Stratix Device Handbook, Volume 1
Fast Regional Clock External I/O Timing
Parameters 4–49
Global Clock External I/O Timing
Parameters 4–50
Regional Clock External I/O Timing
Parameters 4–50
EP1S60 Devices
Column Pin
Fast Regional Clock External I/O Timing
Parameters 4–51
Global Clock External I/O Timing
Parameters 4–52
Regional Clock External I/O Timing
Parameters 4–51
M-RAM
Interface Locations 2–38
Row Pin
Fast Regional Clock External I/O Timing
Parameters 4–52
Global Clock External I/O Timing
Parameters 4–53
Regional Clock External I/O Timing
Parameters 4–53
EP1S80 Devices
Column Pin
Fast Regional Clock External I/O Timing
Parameters 4–54
Global Clock External I/O Timing
Parameters 4–55
Regional Clock External I/O Timing
Parameters 4–54
Global Clock External I/O Timing
Parameters 4–56
Row Pin
Fast Regional Clock External I/O Timing
Parameters 4–55
Regional Clock External I/O Timing
Parameters 4–56
H
HSTL
Class I Specifications 4–14, 4–15
Class II Specifications 4–14, 4–15
I
I/O
Standards
1.5-V 4–14, 4–15
I/O Specifications 4–4
1.8-V I/O Specifications 4–4
2.5-V I/O Specifications 4–3
3.3-V 4–13
LVDS I/O Specificatio ns 4–6
PCI Specifications 4–9
PCML Specifications 4–8
Advanced I/O Standard Suppo rt 2–122
Column I/O Block Connection to the
Interconnect 2–107
Column Pin
Input Delay Adders 4–66
Control Signal Selection per IOE 2–109
CTT I/O Specifications 4–16
Differential LVDS Input On-Chip
Termination 2–128
External I/O Delay Parameters 4–66
GTL+ I/O Specifications 4–10
High-Speed Differential I/O
Support 2–130
HyperTransport Technology
Specifications 4–9
I/O Banks 2–125
I/O Structure 2–104
I/O Support by Bank 2–126
IOE Structure 2–105
LVCMOS Specifications 4–3
LVDS Performance on Fast PLL
Input 2–103
LVPECL Specificati on s 4–8
LVTTL Specifications 4–3
MultiVolt I/O Interface 2–129
MultiVolt I/O Support 2–130
Output Delay Adders for Fast Slew Rate
on Column Pins 4–68
Output Delay Adders for Fast Slew Rate
on Row Pins 4–69
Output Delay Adders for Slow Slew Rate
on Column Pins 4–70
Package Options & I/O Pin Counts 1–4
Receiver Input Waveforms fo r Differential
Altera Corporation Index–5
Stratix Device Handbook, Volume 1
I/O Standards 4–5
Row I/O Block Connection to the
Interconnect 2–106
Row Pin
Input Delay Adders 4–67
Signal Path through the I/O Block 2–108
SSTL-18 4–11
SSTL-2 4–12
SSTL-3 4–12, 4–13
Stratix IOE in Bidirectional I/O
Configuration 2–110
Supported I/O Standards 2–123
Transmitter Output Waveforms for Differ-
ential I/O Standards 4–6
Interconnect
C4 Connections 2–18
DSP Block Interface to Interconnect 2–72
Left-Facing M-RAM to Interconnect
Interface 2–40
LUT Chain Register Chain
Interconnects 2–17
M-RAM
Column Unit Interface to
Interconnect 2–42
Row Unit Interface to Interconnect 2–41
R4 Connections 2–15
IOE
Internal Timing Microparameters 4–29
J
JTAG
Boundary-Scan
Register Length 3–3
Support 3–1
Stratix JTAG
Instructions 3–2
Waveforms 3–4
L
LAB
Control Signals 2–5
Wide Control Signals 2–6
LUT
Chain & Register Chain 2–8
M
Memory Architecture
Byte Enable for M4K
RAM Block
2–32
Byte Enable for M-RAM
Block 2–35
External RAM Interfacing 2–115
M4K
Block Internal Timing
Microparameter
Descriptions 4–24
Microparameters 4–31
RAM Block
2–30
Configurations (Simple Dual-
Port) 2–31
Configurations (True Dual-
Port) 2–31
Control Signals 2–33
LAB Row Interface 2–33
M512
Block Internal Timing
Microparameter
Descriptions 4–24
Microparameters 4–30
RAM Block
Architecture 2–27
Configurations (Simple Dual-Port
RAM) 2–27
Control Signals 2–29
LAB Row Interface 2–30
Memory Block Size 2–26
Memory Modes 2–21
M-RAM
Block 2–34
Configurations (Simple Dual-
Port) 2–34
Configurations (True Dual-
Port) 2–35
Block Contro l Signals 2–37
Block Internal Timing
Microparameter
Descriptions 4–25
Combined Byte Selection for x144
Index–6 Altera Corporation
Stratix Device Handbook, Volume 1
Mode 2–36
Row & Column Interface Unit
Signals 2–43
Parity Bit Support 2–24
Shift Register
Memory Configuration 2–26
Support 2–25
Simple Dual-Port & Single-Port Memory
Configurations 2–23
Stratix IOE in DDR Input I/O
Configuration 2–112
Stratix IOE in DDR Output I/O
Configuration 2–114
TriMatrix Memory 2–21
True Dual-Port Memory
Configuration 2–22
O
Ordering Information 5–1
Device Pin-Outs 5–1
Packaging Ordering Information 5–2
Reference & Ordering Information 5–1
Output Registers 2–64
Output Selection Multiplexer 2–64
P
Packaging
BGA Package Sizes 1–4
Device Speed Grades 1–5
FineLine BGA Package Sizes 1–5
PCI-X 1.0 Specifications 4–10
Phase Shifting 2–103
PLL
Advanced Clear & Enable Control 2–98
Dynamically Programmable Counters & De-
lays in Stratix Device Enhanced
PLLs 2–91
Enhanced
Fast PLLs 2–81
Fast PLL 2–100
Channel Layout EP1S10, EP1S20 or
EP1S25 Devices 2–138
Channel Layout EP1S30 to EP1S80
Devices 2–139
Port I/O Standards 2–102
I/O Standards Supported for Enhanced PLL
Pins 2–94
Lock Detect & Programmable Gated
Locked 2–98
PLL Locations 2–84
Programmable Bandwid t h 2–91
Programmable Delay Chain 2–111
Programmable Duty Cycle 2–98
Reconfiguration 2–90
T
Testing
Temperature Sensing Diode 3–13
Electrical Characteristics 3–14
External 3–14
Temperature vs. Temperature-Sensing Diode
Voltage 3–15
Timing
DSP
Block Internal Timing
Microparameter
Descriptions 4–23
Microparameters 4–29
Dual-Port RAM Timing Microparameter
Waveform 4–27
External Timi ng in Stratix Devices 4–33
High-Speed I/O Timing 4–87
High-Speed Timing Specifications &
Terminology 4–87
Internal Parameters 4–22
IOE Internal Timing Microparameter
Descriptions 4–22
LE Internal Timing Microparameters 4–28
Logic Elements Internal Timing Microparam-
eter Descriptions 4–22
Model 4–19
PLL Timing 4–94
Preliminary & Final 4–19
Stratix Device Timing Model Stat us 4–19
Stratix JTAG
Timing Parameters & Values 3–4
TriMatrix Memory
TriMatrix Memory Features 2–21
1–30 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Enhanced PLLs
With down-spread modulation, the pe ak of the modulated waveform is
the actual target frequency. Therefore , the system neve r exceeds the
maximum clock speed. To maintain r eliable communication, the entire
system/subsystem should use the Stratix or Stratix GX device as the clock
source. Communication co uld fail if the Stratix or Stratix GX logic array
is clocked by the spread-spectrum clock, but the data it receives from
another device is not.
Since spr ead sp ec trum affects the m counter values, all spread-spectrum
PLL outputs are af fected. Therefore, if only one spread-spectrum signal is
needed, the clock signal should use a separate PLL without other outputs
from that PLL.
No special considerations are needed when using spread spectrum with
the clock switchover featur e. This is because the clock swi tchover featur e
does not affect the m and n counter values, which are the counter values
that are switching when using spread spectrum.
PLL Reconfiguration
fSee AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX
Devices for information on PLL reconfiguration.
Enhanced PLL Pins
Table 1–9 shows the physical pins and their purpose for the Enhanced
PLLs. For inclk port connections to pins see “Clocking” on page 1–39.
Table 1–9. Enhanced PLL Pins (Part 1 of 2)
Pin Description
CLK4p/n Single-ended or differential pins that can drive the inclk port for PLL 6.
CLK5p/n Single-ended or differential pins that can drive the inclk port for PLL 6.
CLK6p/n Single-ended or differential pins that can drive the inclk port for PLL 12.
CLK7p/n Single-ended or differential pins that can drive the inclk port for PLL 12.
CLK12p/n Single-ended or differential pins that can drive the inclk port for PLL 11.
CLK13p/n Single-ended or differential pins that can drive the inclk port for PLL 11.
CLK14p/n Single-ended or differential pins that can drive the inclk port for PLL 5.
CLK15p/n Single-ended or differential pins that can drive the inclk port for PLL 5.
PLL5_FBp/n Single-ended or differential pins that can drive the fbin port for PLL 5.
PLL6_FBp/n Single-ended or differential pins that can drive the fbin port for PLL 6.
PLLENABLE Dedicated input pin that drives the pllena port of all or a set of PLLs. If you do not
use this pin, connect it to ground.
Altera Corporation 1–31
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
Fast PLLs Stratix devices contain up to eight fast PLLs and Stratix GX devices
contain up to four fast PLLs. Bot h de vic e PLLs have high-speed
differential I/O interface ability along with general-purpose features.
Figure 1–17 shows a diagram of the fast PLL. This section discusses the
PLL5_OUT[3..0]p/n Single-ended or differential pins driven by extclk[3..0] ports from PLL 5.
PLL6_OUT[3..0]p/n Single-ended or differential pins driven by extclk[3..0] ports from PLL 6.
PLL11_OUT, CLK13n Single-ended output pin driven by clk0 port fro m PLL 11.
PLL12_OUT, CLK6n Single-ended output pin driven by clk0 port from PLL 12.
VCCA_PLL5 Analog power for PLL 5. Connect this pin to 1.5 V, even if the PLL is not used.
VCCG_PLL5 Guard ring power for PLL 5. Connect this pin to 1.5 V, even if the PLL is not used.
GNDA_PLL5 Analog ground for PLL 5. You can connect this pin to the GND plane on the board.
GNDG_PLL5 Guard ring ground for PLL 5. You can connect this pin to the GND plane on the board.
VCCA_PLL6 Analog power for PLL 6. Connect this pin to 1.5 V, even if the PLL is not used.
VCCG_PLL6 Guard ring power for PLL 6. Connect this pin to 1.5 V, even if the PLL is not used.
GNDA_PLL6 Analog ground for PLL 6. You can connect this pin to the GND plane on the board.
GNDG_PLL6 Guard ring ground for PLL 6. You can connect this pin to the GND plane on the board.
VCCA_PLL11 Analog power for PLL 11. Connect this pin to 1.5 V, even if the PLL is not used.
VCCG_PLL11 Guard ring power for PLL 11. Connect this pin to 1.5 V, even if the PLL is not used.
GNDA_PLL11 Analog ground for PLL 11. You can connect this pin to the GND plane on the board.
GNDG_PLL11 Guard ring ground for PLL 11.You can connect this pin to the GND plane on the board.
VCCA_PLL12 Analog power for PLL 12. Connect this pin to 1.5 V, even if the PLL is not used.
VCCG_PLL12 Guard ring power for PLL 12. Connect this pin to 1.5 V, even if the PLL is not used.
GNDA_PLL12 Analog ground for PLL 12. You can connect this pin to the GND plane on the board.
GNDG_PLL12 Guard ring ground for PLL 12. You can connect this pin to the GND plane on the board.
VCC_PLL5_OUTA External clock output VCCIO power for PLL5_OUT0p, PLL5_OUT0n, PLL5_OUT1p,
and PLL5_OUT1n outputs from PLL 5.
VCC_PLL5_OUTB External clock output VCCIO power for PLL5_OUT2p, PLL5_OUT2n, PLL5_OUT3p,
and PLL5_OUT3n outputs from PLL 5.
VCC_PLL6_OUTA External clock output VCCIO power for PLL5_OUT0p, PLL5_OUT0n, PLL5_OUT1p,
and PLL5_OUT1n outputs from PLL 6.
VCC_PLL6_OUTB External clock output VCCIO power for PLL5_OUT2p, PLL5_OUT2n, PLL5_OUT3p,
and PLL5_OUT3n outputs from PLL 6.
Table 1–9. Enhanced PLL Pins (Part 2 of 2)
Pin Description
1–32 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Fast PLLs
general purpose abilities of the Fast PLL. For information on the high-
speed differ ential I/O interface capabilities, see the High-Speed Differential
I/O Interfaces in Stratix Devices chapter.
Figure 1–17. Stratix & Stratix GX Fast PLL Block Diagram
Notes to Figure 1–17:
(1) The global or regional clock input can be driven by an output from another PLL or any dedicated CLK or FCLK pin.
It cannot be driven by internally-generated global signals.
(2) In high-speed differential I/O support mode, this high-s peed PLL clock feeds the SERDES. Stratix and Stratix GX
devices only support one rate of data transfer per fast PLL in high-speed diff erential I/O support mode.
(3) This signal is a high-speed differ ential I/O support SERDES control signal.
Charge
Pump VCO ÷g0
8
Clock
Input PFD
÷l1
÷l0
÷m
Loop
Filter
Phase
Frequency
Detector
VCO Phase Selection
Selectable at each PLL
Output Port
Post-Scale
Counters
Global or
regional clock
Global or
regional clock
Global or
regional clock
diffioclk2 (2)
diffioclk1 (2)
txload_en (3)
rxload_en (3)
Global or
regional clock
(1)
Altera Corporation 1–33
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
Figure 1–18 shows all possi b le ports related to fast PLL s.
Figure 1–18. Fast PLL Ports & Physical Destinations
Notes to Figure 1–18:
(1) This input pin is shared by all enhanced and fast PLLs.
(2) This input pin is either single-ended or differential.
Tables 1–10 and 1–11 show the description of all fast PLL ports.
clk[2..0]
locked
pllena
inclk0
areset
pfdena
Fast PLL Signals
(1)
(2)
Physical Pin
Signal Driven by Internal Logic
Signal Driven to Internal Logic
Internal Clock Signal
Table 1–10. Fast PLL Input Signals
Name Description Source Destination
inclk1 Reference clock input to PLL Pin PFD
pllena Enable pin for enabling or disabling all or a set of
PLLs – active high Pin PLL control signal
areset Signal used to reset the PLL which re-
synchronizes all the counter outputs⎯active high Logic array PLL control signal
pfdena Enables the up/down outputs from the phase-
frequency detector⎯active high Logic array PFD
Table 1–11. Fast PLL Output Signals
Name Description Source Destination
clk[2..0] PLL outputs driving regional or global clock PLL counter Internal clock
locked Lock output from lock detect circuit⎯active high PLL lock
detect Logic array
1–34 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Fast PLLs
Clock Multiplication & Division
Stratix and Stratix GX device fast PLLs provide clock synthesis for PLL
output ports using m/(post scaler) scaling factors. The input clock is
multiplie d by the m feedback factor. Each output port has a unique post
scale counter to divide down the high-frequency VCO. There is one
multiply counter, m, per fast PLL with a range of 1 to 32. There are three
post-scale counters (g0, l0, and l1) for the regional and global clock output
ports. All post-scale co unters range from 1 to 32. If the des ign us es a
high-speed serial interface, you can set the output counter to 1 to allow
the high-speed VCO frequency to drive the SERDES.
External Clock Outputs
Each fast PLL supports differential or single-ended outputs for source-
synchronous transmitters or for general-purpose external clocks. Ther e
are no dedicated external clock outp ut pins. The fast PLL global or
regional outputs can drive any I/O pin as an external clock output pin.
The I/O standards supported by any particular bank determines what
standards ar e possible for an external clock output driven by the fast PLL
in that bank. See the Selectable I/O Standards in Stratix & Stratix GX Devices
chapter in the Stratix Device Handbook, Volume 2 or the Stratix GX Device
Handbook, Volume 2 for output standard support.
Table 1–12 shows the I/O standards supported by fast PLL input pins.
Table 1–12. Fast PLL Port I/O Standards (Part 1 of 2)
I/O Standard Input
INCLK PLLENABLE
LVTTL vv
LVCMOS vv
2.5 V v
1.8 V v
1.5 V v
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL v
PCML v
LVDS v
HyperTransport technology v
Differential HSTL v
Altera Corporation 1–35
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
Phase Shifting
Stratix and Stratix GX device fast PLLs have advanced clock shift ability
to provide programmable phase shift. These parameters are set in the
Quartus II software.
The Quartus II software automatically sets the phase taps and counter
settings according to the phase shift entry. Enter a desired phase shift and
the Quartus II software automatically sets the closest set ting achievable.
This type of phase shift is not reconfigurable during system operation.
You can enter a phase shift (in degrees or time units) for each PLL cl ock
output port or for all outputs together in one shift. Y ou can perform phase
shifting in time units with a resolu tion range of 1 25 to 416.66 ps to create
a function of freque ncy input and the multiplication and division factors
(that is, it is a function of the VCO period), with the finest step being equal
to an eighth (×0.125) of the VCO period. Each clock output counter can
choose a different phase of the VCO period from up to eight taps for
individual fine-s te p se le c t ion. Also, each clock output counter can use a
unique initial count setting to achieve individual coarse shift selection in
steps of one VCO period. The combination of coarse and grain shifts
allows phase shifting for the entire input clock period.
Differential SSTL
3.3-V GTL
3.3-V GTL+ v
1.5-V HSTL Class I v
1.5-V HSTL Class II
1.8-V HSTL Class I v
1.8-V HSTL Class II
SSTL-18 Class I v
SSTL-18 Class II
SSTL-2 Class I v
SSTL-2 Class II v
SSTL-3 Class I v
SSTL-3 Class II v
AGP (1× and 2×)
CTT v
Table 1–12. Fast PLL Port I/O Standards (Part 2 of 2)
I/O Standard Input
INCLK PLLENABLE
1–36 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Fast PLLs
The equation to determine the pr ecision of phase in degr ees is: 45°÷post-
scale counter value. Therefore, the maximum step size is 45°, and smaller
steps are possible depending on the multiplication and division ratio
necessary on the output counter port.
This type of phase shift provides the highest precision since it is the least
sensitive to process, supply, and temperature variation.
Programmable Duty Cycle
The programmable duty cycle allows the fast PLL to generate clock
outputs with a variable duty cycle. Th is feature is supported on each fast
PLL post-scale counter . g0, l0, and l1 all support programmable duty. You
use a low- and high-time count setting for the post-scale counters to set
the duty cycle.
The Quartus II software uses the frequency input and multiply /d iv ide
rate desired to select the post-scale counter, which determines the
possible choices for each duty cycle. The precision of the duty cycle is
determined by the post-scale coun te r value chosen on an output. The
precision is defined by 50% divided by the post-s cale coun ter value . The
closest value to 100% is not achievable for a given counter value. For
example, if the g0 counter is 10, then steps of 5% are possible for duty
cycle choices between 5 to 90%.
If the device uses external feedback, you must set the duty cycle for the
counter driving off the device to 50%.
Control Signals
The lock output indicates a stable clock output signal in phase with the
refer ence clock. Unlike enhanced PL Ls, fast PLLs do not have a lock filter
counter.
The pllenable pin is a dedicated pin that enables/disables both PLLs.
When the pllenable pin is low, the clock output ports are driven by
GND and all the PLLs go out of lock. When the pllenable pin goes high
again, the PLLs relock and resynchronize to the input clocks. You can
choose which PLLs are controlled by the pllenable by connecting the
pllenable input port of the altpll megafunction to the common
pllenable input pin.
The areset signals are r eset/resynchronization inputs for each fast PLL.
The Stratix and Stratix GX devices can drive these input signals from an
input pin or from LEs. When driven high, the PLL counters reset, clearing
the PLL output and placing the PLL ou t of lock. The VCO sets back to its
nominal setting (~700 MHz). When driven low again, the PLL
Altera Corporation 1–37
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
resynchr onizes to its input clock as it relocks. If the target VCO frequency
is below this nominal frequency, then the output frequency starts at a
higher value then desired as it locks.
The pfdena signals control the PFD output with a pr ogrammable gate. If
you disable the PFD, the VCO operates at its last set value of control
voltage and frequ ency with some long-term drift to a lower frequency.
The system continues running when the PLL goes out of lock or the input
clock disables. By maintaining the last locked frequency, the system has
time to store its current settings before shutting down.
If the PLL loses lock for any reason (for example, because of excessive
inclk jitter, clock switchover, PLL reconfiguration, or power supply
noise), the PLL must be reset with the areset signal to guarantee correct
phase relationship between the PLL output clocks. If the phase
relationship between the input clock and the output clock and between
differ ent output clocks fr om the PLL is not important in your d esign, it is
not necessary to re set the PLL.
Pins
Table 1–13 shows the physical pins and their purpose for the Fast PLLs.
For inclk port connections to pins see “Clocking” on page 1–39.
Table 1–13. Fast PLL Pins (Part 1 of 3)
Pin Description
CLK0p/n Single-ended or differential pins that can drive the inclk port for PLL 1 or 7.
CLK1p/n Single-ended or differential pins that can drive the inclk port for PLL 1.
CLK2p/n Single-ended or differential pins that can drive the inclk port for PLL 2 or 8.
CLK3p/n Single-ended or differential pins that can drive the inclk port for PLL 2.
CLK8p/n Single-ended or differential pins that can drive the inclk port for PLL 3 or 9. (1)
CLK9p/n Single-ended or differential pins that can drive the inclk port for PLL 3. (1)
CLK10p/n Single-ended or differential pins that can drive the inclk port for PLL 4 or 10. (1)
CLK11p/n Single-ended or differential pins that can drive the inclk port for PLL 4. (1)
FPLL7CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 7.
FPLL8CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 8.
FPLL9CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 9. (1)
FPLL10CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 10. (1)
PLLENABLE Dedicated input pin that drives the pllena port of all or a set of PLLs. If y ou do not
use this pin, connect it to ground.
VCCA_PLL1 Analog power for PLL 1. Connect this pin to 1.5 V, even if the PLL is not used.
1–38 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Fast PLLs
VCCG_PLL1 Guard ring power f or PLL 1. Connect this pin to 1.5 V, ev en if the PLL is not used.
GNDA_PLL1 Analog ground f or PLL 1. You can connect this pin to the GND plane on the board.
GNDG_PLL1 Guard ring ground for PLL 1. You can connect this pin to the GND plane on the
board.
VCCA_PLL2 Analog power for PLL 2. Connect this pin to 1.5 V, even if the PLL is not used.
VCCG_PLL2 Guard ring power for PLL 2. Connect this pin to1.5 V, ev en if the PLL is not used.
GNDA_PLL2 Analog ground f or PLL 2. You can connect this pin to the GND plane on the board.
GNDG_PLL2 Guard ring ground for PLL 2. You can connect this pin to the GND plane on the
board.
VCCA_PLL3 Analog power f or PLL 3. Connect this pin to 1.5 V, ev en if the PLL is not used. (1)
VCCG_PLL3 Guard ring power for PLL 3. Connect this pin to 1.5 V, even if the PLL is not
used. (1)
GNDA_PLL3 Analog ground for PLL 3. You can connect this pin to the GND plane on the
board. (1)
GNDG_PLL3 Guard ring ground for PLL 3. You can connect this pin to the GND plane on the
board. (1)
VCCA_PLL4 Analog power f or PLL 4. Connect this pin to 1.5 V, ev en if the PLL is not used. (1)
VCCG_PLL4 Guard ring power for PLL 4. Connect this pin to 1.5 V, even if the PLL is not
used. (1)
GNDA_PLL4 Analog ground for PLL 4. You can connect this pin to the GND plane on the
board. (1)
GNDG_PLL4 Guard ring ground for PLL 4. You can connect this pin to the GND plane on the
board. (1)
VCCA_PLL7 Analog power for PLL 7. Connect this pin to 1.5 V, even if the PLL is not used.
VCCG_PLL7 Guard ring power f or PLL 7. Connect this pin to 1.5 V, ev en if the PLL is not used.
GNDA_PLL7 Analog ground f or PLL 7. You can connect this pin to the GND plane on the board.
GNDG_PLL7 Guard ring ground for PLL 7. You can connect this pin to the GND plane on the
board.
VCCA_PLL8 Analog power for PLL 8. Connect this pin to 1.5 V, even if the PLL is not used.
VCCG_PLL8 Guard ring power f or PLL 8. Connect this pin to 1.5 V, ev en if the PLL is not used.
GNDA_PLL8 Analog ground f or PLL 8. You can connect this pin to the GND plane on the board.
GNDG_PLL8 Guard ring ground for PLL 8. You can connect this pin to the GND plane on the
board.
VCCA_PLL9 Analog power f or PLL 9. Connect this pin to 1.5 V, ev en if the PLL is not used. (1)
VCCG_PLL9 Guard ring power for PLL 9. Connect this pin to 1.5 V, even if the PLL is not
used. (1)
Table 1–13. Fast PLL Pins (Part 2 of 3)
Pin Description
Altera Corporation 1–39
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
Clocking Stratix and Stratix GX devices provide a hierarchical clock stru cture and
multiple PLLs with advanced featur es. The large number of clocking
reso urces in combination with the clock synthesi s precision provided by
enhanced and fast PLLs provides a complete clock management solution.
Global & Hierarchical Clocking
Stratix and Stratix GX devices provide 16 dedicated global clock
networks, 16 regional clock networks (4 per device quadrant), and
8 dedicated fast regional clock networks. These clocks are or ganized into
a hierarchical clock structure that allows for up to 22 clocks per device
region with low skew and de lay. This hierarchical clocking scheme
provides up to 48 unique clock domains within Stratix and Stratix GX
devices.
There are 16 dedicated clock pins (CLK[15..0]) on Stratix devices and
12 dedicated clock pins (CLK[11..0]) on Stratix GX devices to drive
either the global or regional clock networks. Four clock pins drive each
side of the Stratix device, as shown in Figures 1–19 and 1–20. On Stratix
GX devices, four cl ock pins drive the top, left, and bott om sides of the
device. The clocks on the right side of the device are not available for
general-purpose PLLs. Enhanced and fast PLL outputs can also drive the
global and regional clock networks.
GNDA_PLL9 Analog ground for PLL 9. You can connect this pin to the GND plane on the
board. (1)
GNDG_PLL9 Guard ring ground for PLL 9. You can connect this pin to the GND plane on the
board. (1)
VCCA_PLL10 Analog power for PLL 10. Connect this pin to 1.5 V, even if the PLL is not
used. (1)
VCCG_PLL10 Guard ring power for PLL 10. Connect this pin to 1.5 V, even if the PLL is not
used. (1)
GNDA_PLL10 Analog ground for PLL 10. Connect this pin to the GND plane on the board. (1)
GNDG_PLL10 Guard ring ground for PLL 10. You can connect this pin to the GND plane on the
board. (1)
Note to Table 1–13:
(1) PLLs 3, 4, 9, and 10 are not av ailable on Strati x GX devices for general-purpose configuration. These PLLs are part
of the HSSI block. See AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices for more
information.
Table 1–13. Fast PLL Pins (Part 3 of 3)
Pin Description
1–40 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Clocking
Global Clock Network
These clocks drive thro ughout the entire device, feeding all device
quadrants. All resources within the device—IO Es, LEs, DSP blocks, and
all memory blocks—can use the global clock networks as clock source s .
These reso urces can also be us ed for control signals, su ch as clock enables
and synchronous or asynchronous clears fed from the external pin.
Internal logic can also driv e the global clock networks for internally
generated global clocks and asynchronou s c lears, clock enables, or other
control signals with large fanout. Figure 1–19 shows the 16 dedicated CLK
pins driving global clock networks.
Figure 1–19. Global Clocking
Regional Clock Network
There are four regional clo ck networks within each quadrant of the
Stratix or Stratix GX dev ic e that are driven by the same dedicated
CLK[15..0] input pins or from PLL outputs. Fr om a top view of the
silicon, RCLK[0..3] are in the top-left quadrant, RCLK[8..11] are in
the top-right quadrant, RCLK[4..7] are in the bottom-left quadrant, and
Global Clock [15..0]
CLK[15..12]
CLK[3..0]
CLK[7..4]
CLK[11..8]
Global Clock [15..0]
Altera Corporation 1–41
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
RCLK[12..15] are in the bottom-right quadrant. The regional clock
networks only pertain to the quadrant they drive into. The r egional clock
networks provide the lowest clock delay and skew for logic contained
within a single quadrant. RCLK clock networks cannot be driven by
internal logic. The CLK clock pins symmetrically drive the RCLK networks
within a particular quadrant, as shown in Figure 1–20. See Figures 1–21
and 1–22 for RCLK connections from PLLs and CLK pins.
Figure 1–20. Regional Clocks
Clock Input Connections
Two CLK pins drive each enhanced PLL. You can use either one or both
pins for clock switc ho ver inputs into the PLL. Either pin can be the
primary clock source for clock switchover, which is co ntrolled in the
Quartus II software. Enhanced PLLs 5 and 6 also have feedback input
pins as shown in Table 1–14.
RCLK[1..0]
RCLK[4..5]
RCLK[6..7] RCLK[12..13]
RCLK[2..3]RCLK[11..10]
RCLK[14..15]
RCLK[9..8]
CLK[15..12]
CLK[3..0]
CLK[7..4]
CLK[11..8]
Regional Clocks Only Drive a Device
Quadrant from Specified CLK Pins or
PLLs within that Quadrant
1–42 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Clocking
Input clocks for fast PLLs 1, 2, 3, and 4 come from CLK pins. Stratix GX
devices use PL Ls 3 and 4 in the HSSI block only. A multiplexer chooses
one of two possible CLK pins to drive each PLL. This multiplexer is not a
clock switcho ver mu ltiplexer and is only use d for cloc k input
connectivity.
Either a FPLLCLK input pin or a CLK pin can drive the fast PLLs in the
corners (7, 8, 9, and 10) when used for general purpose. CLK pins cannot
drive these fast PLLs in high-speed differential I/O mode. PLLs 9 and 10
are used for the HSSI block in Stratix GX devices and are not available.
Table 1–14 shows which PLLs are available for each Stratix device and
which input clock pin drives which PLLs.
Table 1–14. Stratix Clock Input Sources For Enhanced & Fast PLLs (Part 1 of 2)
Clock Input
Pins
All Stratix Devices EP1S30, EP1S40, EP1S60 &
EP1S80 Devices Only
EP1S40 (3),
EP1S60 &
EP1S80
Devices Only
PLL 1
(1) PLL 2
(1) PLL 3
(1) PLL 4
(1) PLL 5
(2) PLL 6
(2) PLL 7
(1) PLL 8
(1) PLL 9
(1) PLL
10 (1) PLL
11 (2) PLL
12 (2)
CLK0p/n vv
CLK1p/n v
CLK2p/n vv
CLK3p/n v
CLK4p/n v
CLK5p/n v
CLK6p/n v
CLK7p/n v
CLK8p/n vv
CLK9p/n v
CLK10p/n vv
CLK11p/n v
CLK12p/n v
CLK13p/n v
CLK14p/n v
CLK15p/n v
Altera Corporation 1–43
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
Clock Output Connections
Enhanced PLLs have outputs for two regional clock outputs and four
global outputs. Ther e is line sharing between clock pins, global and
regional clock networks and all PLL outputs. Check Tables 1–15 and 1–16
and Figures 1–21 and 1–22 to make sure that the clocking scheme is valid.
The Quartus II software automatically maps to regional and global clocks
to avoid any restrictions. Enhanced PLLs 5 and 6 drive out to single-
ended pins as shown in Table 1–15. PLLs 11 and 12 drive out to single-
ended pins.
You can connect each fast PL L 1, 2, 3, or 4 outputs (g0, l0, and l1) to either
a global or a r egional clock. (PLLs 3 and 4 ar e not available on Stratix GX
devices.) Ther e is line sharing between clock pins, FPLLCLK pins, global
and regional clock networks and all PLL outputs. Check Figures 1–21 and
1–22 to make sure that the clocking is valid. The Quartus II soft ware
automatically maps to r egional and global clocks to avoid any
restrictions.
FPll7clk v
FPll8clk v
FPll9clk v
FPll10clk v
Clock Feedback Input Pins
Pll5_fbp/n v
Pll6_fbp/n v
Notes to Table 1–14:
(1) This is a fast PLL. The global or regional clocks in a fast PLL ’s quadrant can drive the fast PLL input. A pin or other
PLL must drive the global or regional source. The source cannot be driven by internally generated logic before
driving the fast PLL.
(2) This is an enhanced PLL.
(3) The EP1S40 device in the F780 package does not support PLLs 11 and 12.
Table 1–14. Stratix Clock Input Sources For Enhanced & Fast PLLs (Part 2 of 2)
Clock Input
Pins
All Stratix Devices EP1S30, EP1S40, EP1S60 &
EP1S80 Devices Only
EP1S40 (3),
EP1S60 &
EP1S80
Devices Only
PLL 1
(1) PLL 2
(1) PLL 3
(1) PLL 4
(1) PLL 5
(2) PLL 6
(2) PLL 7
(1) PLL 8
(1) PLL 9
(1) PLL
10 (1) PLL
11 (2) PLL
12 (2)
1–44 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Clocking
Table 1–15 shows the global and regional clocks that each PLL drives
outputs to for Stratix devices. Table 1–16 shows the global and regional
clock network each of the CLK and FPLLCLK pins drive when bypassing
the PLL.
Table 1–15. Stratix Global & Regional Clock Output Lin e Sharing for Enhanced & Fast PLLs (Part 1 of 2)
Clock
Network
All Devices EP1S30, EP1S40, EP1S60 &
EP1S80 Devices Only
EP1S40 (5),
EP1S60 &
EP1S80
Devices Only
PLL 1
(1) PLL 2
(1) PLL 3
(1) PLL 4
(1) PLL 5
(2) PLL 6
(2) PLL 7
(1) PLL 8
(1) PLL
9 (1) PLL
10 (1) PLL
11 (2) PLL
12 (2)
GCLK0 vv vv
GCLK1 vv vv
GCLK2 vv vv
GCLK3 vv vv
GCLK4 vv
GCLK5 vv
GCLK6 vv
GCLK7 vv
GCLK8 vv vv
GCLK9 vv vv
GCLK10 vv vv
GCLK11 vv vv
GCLK12 vv
GCLK13 vv
GCLK14 vv
GCLK15 vv
RCLK0 vv v
RCLK1 vv v
RCLK2 vv
RCLK3 vv
RCLK4 vv v
RCLK5 vv v
Altera Corporation 1–45
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
RCLK6 vv
RCLK7 vv
RCLK8 vv v
RCLK9 vv v
RCLK10 vv
RCLK11 vv
RCLK12 vv
RCLK13 vv
RCLK14 vv v
RCLK15 vv v
External Clock Output
PLL5_OUT
[3..0]p/n v
PLL6_OUT
[3..0]p/n v
PLL11_OUT
(3) v
PLL12_OUT
(4) v
Notes to Table 1–15:
(1) This is a fast PLL.
(2) This is an enhanced PLL.
(3) This pin is a tri-purpose pin; it can be an I/O pin, CLK13n, or used for PLL 11 output.
(4) This pin is a tri-purpose pin; it can be an I/O pin, CLK7n, or used for PLL 12 output.
(5) The EP1S40 device in the F780 package does not support PLLs 11 and 12.
Table 1–15. Stratix Global & Regional Clock Output Lin e Sharing for Enhanced & Fast PLLs (Part 2 of 2)
Clock
Network
All Devices EP1S30, EP1S40, EP1S60 &
EP1S80 Devices Only
EP1S40 (5),
EP1S60 &
EP1S80
Devices Only
PLL 1
(1) PLL 2
(1) PLL 3
(1) PLL 4
(1) PLL 5
(2) PLL 6
(2) PLL 7
(1) PLL 8
(1) PLL
9 (1) PLL
10 (1) PLL
11 (2) PLL
12 (2)
1–46 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Clocking
Table 1–16. Stratix CLK & FPLLCLK Input Pin Connections to Global & Regional Clock Networks Note (1)
Clock Network CLK Pins FPLLCLK (2)
012345678910111213141578910
GCLK0 vvv
GCLK1 vvv
GCLK2 vvv
GCLK3 vvv
GCLK4 v
GCLK5 v
GCLK6 v
GCLK7 v
GCLK8 vvv
GCLK9 vvv
GCLK10 vvv
GCLK11 vvv
GCLK12 v
GCLK13 v
GCLK14 v
GCLK15 v
RCLK0 vv
RCLK1 vv
RCLK2 vv
RCLK3 vv
RCLK4 v
RCLK5 v
RCLK6 v
RCLK7 v
RCLK8 vv
RCLK9 vv
RCLK10 vv
RCLK11 vv
RCLK12 v
Altera Corporation 1–47
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
The fast PLLs also drive high-speed SERDES clocks for diffe rential I/O
interfacing. For information on these FPLLCLK pins, see the High-Speed
Differential I/O Interfaces in Stratix Devices chapter.
Figure 1–21 shows the global and regional clock input and output
connections from the enhance d. Figure 1–21 shows gr aphically the sam e
information as Tables 1–15 and 1–16 but with the added detail of whe re
each specific PLL output port drives to.
RCLK13 v
RCLK14 v
RCLK15 v
Notes to Table 1–16:
(1) The CLK and FPLLCLK pins cannot drive.
(2) The FPLLCLK pin is only available in EP1S80, EP1S60, EP1S40, and EP1S30 devices.
Table 1–16. Stratix CLK & FPLLCLK Input Pin Connections to Global & Regional Clock Networks Note (1)
Clock Network CLK Pins FPLLCLK (2)
012345678910111213141578910
1–48 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Clocking
Figure 1–21. Global & Regional Clock Connections from Side Clock Pins & Fast PLL Outputs
Notes to Figures 1–21:
(1) The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A dedicated pin or other PLL
must drive the global or regional source. The source cannot be driven by internally generated logic before driving
the fast PLL.
(2) PLLs 3, 4, 9, and 10 are used for the HSSI block in Stratix GX devices and are not available for this use.
When using a fast PLL to compensate for clock delays to drive logic on
the chip, the clock delay from the input pin to the clock input port of the
PLL is compensated only if the clock is fed by the dedicated input pin
closest to the PLL. If the fast PLL gets its input clock from a global or
regional clock or from another dedicated clock pin, which does not
directly feed the fast PLL, the clock signal is first r oute d onto a global
clock network. The signal then drives into the PLL. In this case, the clock
delay is not fully compensated and the delay compensation is equal to the
clock delay from the dedicated clock pin closest to the PLL to the clock
input port of the PLL.
For example, if you use CLK0 to feed PLL 7, the input clock path delay is
not fully compensated, but if FPLL7CLK feeds PLL 7, the input clock path
delay is fully compe ns ated.
Figure 1–22 shows the global and regional clock input and output
connections from the fast PLLs. Figure 1–22 shows graphically the same
information as Tables 1–15 and 1–16 but with the added detail of whe re
each specific PLL output port drives to.
2
CLK0
CLK1
CLK2
CLK3
G0
FPLL7CLK
G1 G2 G3
RCLK0
RCLK1
RCLK4
RCLK5
G10
G11
G8
G9 RCLK9
RCLK8
RCLK15
RCLK14
Global
Clocks
Regional
Clocks
PLL 7 l0
l1
g0
PLL 1
PLL 2
FPLL8CLK
PLL 8
2
CLK10
CLK11
CLK8
CLK9
FPLL10CL
K
PLL 10
PLL 4
PLL 3
FPLL9CLK
PLL 9
Regional
Clocks
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
Altera Corporation 1–49
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
Figure 1–22. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs
Notes to Figures 1–22:
(1) CLK4, CLK6, CLK12, and CLK14 feed the corresponding PLL’s inclk0 port.
(2) CLK5, CLK7, CLK13, and CLK15 feed the corresponding PLL’s inclk1 port.
G12
G13
G14
G15
RCLK10
RCLK11
RCLK2
RCLK3
G7
G6
G5
G4
RCLK13
RCLK12
RCLK7
RCLK6
PLL 12
L0 L1 G0 G1 G2 G3
CLK7
CLK6
CLK5
CLK4
PLL 6
G0 G1 G2 G3 L0 L1
PLL 11
L0 L1 G0 G1 G2 G3
CLK13
CLK12
CLK14
CLK15
PLL 5
G0 G1 G2 G3 L0 L1
E[0..3]
PLL12_OUT
PLL6_OUT[3..0]
PLL11_OUT
PLL5_OUT[3..0]
PLL5_FB
PLL6_FB
Global
Clocks
Regional
Clocks
Regional
Clocks
(1)
(2)
(1)
(2)
(2)
(2)(1)
(1)
1–50 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Board Layout
Board Layout The enhanced and fast PLL circuits in Stratix and Stratix GX devices
contain analog components embedded in a digital device. These analog
components have separate power and ground pins to minimize noise
generated by the digital components. Both Stratix and Stratix GX
enhanced and fast PLLs use separate VCC and ground pins to isolate
circuitry and improve noise resistance.
VCCA & GNDA
Each enhanced and fast PLL uses separate VCC and ground pin pairs for
their analog circuitry. The analog circuit power and ground pin for each
PLL is calle d PLL<PLL number>_VCCA and PLL<PLL number>_GNDA.
Connect the VCCA power pin to a 1.5-V power supply, even if you do not
use the PLL. Isolate the power connected to VCCA from the power to the
rest of the Stratix and Stratix GX device or any other digital device on the
board. You can use one of three different methods of isolating the VCCA
pin: separate VCCA power planes, a partitioned VCCA island within the
VCCINT plane, and thick VCCA traces.
Separate VCCA Po wer Plane
A mixed signal system is already partitioned into analog and digital
sections, each with its own powe r pl anes on the board. To isolate the
VCCA pin using a separate VCCA power plane, connect the VCCA pin to the
analog 1.5-V power plane.
Partitioned VCCA Island with in VCCINT Plane
Fully digital systems do not have a separate analog power plane on the
board. Because it is expensive to add new planes to the boar d , yo u can
create islands for VCCA_PLL. Figure 1–23 shows an example board layout
with an analog power island. The dielectric boundary that creates the
island should be 25 mils thick. Figure 1–23 shows a partitioned plane
within VCCINT for VCCA.
Altera Corporation 1–51
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
Figure 1–23. VCCINT Plane Partitioned for VCCA Island
Thick VCCA Trace
Because of board constraints, you might not be able to partition a VCCA
island. Instead, run a thick trace from the power supply to each VCCA pin.
The traces should be at least 20 mils thick.
In each of these three cases, you should filter each VCCA pin with a
decoupling cir cuit shown in Figure 1–24. Place a ferrite bead that exhibit s
high impedance at frequencies of 50 MHz or higher and a 10-μF tantalum
parallel capacitor where the power enters the board. Decouple each VCCA
pin with a 0.1-μF and 0.001-μF parallel combination of ceramic capacitors
located as close as possi ble to the Str at ix or Strati x GX device. You can
connect the GNDA pins directly to the same gr ound plane as the device’s
digital ground.
1–52 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Board Layout
Figure 1–24. PLL Power Schematic for Stratix or Stratix GX PLLs
VCCG & GNDG
The guard ring power and ground pins are called
PLL<PLL number>_VCCG and PLL<PLL number>_GNDG. The guard ring
isolates the PLL circuit from the rest of the device. Connect these guard
ring VCCG pins to the quietest digital supply on the board. In most
systems, this is the digital 1 .5-V supply su pplied to the device's VCCINT
pins. Connect the VCCG pins to a power supply even if you do not use the
PLL. You can connect the GNDG pins directly to the same gr ound plane as
the device’s digital ground. See Figure 1–24.
0.1 μF 0.001 μF
10 μF
Ferrite
Bead 1.5-V Suppl
y
Stratix Device
PLL<PLL number>_VCCA
PLL<PLL number>_GNDA
PLL<PLL number>_VCCG
PLL<PLL number>_GNDG
Repeat for Each PLL
Power and Ground Set
VCCINT
Altera Corporation 1–53
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
External Clock Output Power
Enhanced PLLs 5 and 6 also have iso lated power pins for their dedicated
external clock outputs (VCC_PLL5_OUTA and VCC_PLL5_OUTB, or
VCC_PLL6_OUTA and VCC_PLL6_OUTB, respectively). PLLs 5 and 6 both
have two banks of outputs. Each bank is powered by a unique output
power, OUTA or OUTB, as illustrated in Figure 1–25. These outputs can by
powered by 3.3, 2.5, 1.8, or 1.5 V depending on the I/O standard for the
clock output in the A or B groups.
1–54 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Board Layout
Figure 1–25. External Clock Output Pin Association to Output Power Note (1)
Note to Figure 1–25:
(1) These pins apply to PLL 5. The figure for PLL 6 is similar , except that the pin names
begin with the prefix PLL6 instead of PLL5.
PLL5_OUT0p
VCC_PLL5_OUTA
PLL5_OUT0n
PLL5_OUT0p
PLL5_OUT0n
PLL5_OUT2p
VCC_PLL5_OUTB
PLL5_OUT2n
PLL5_OUT3p
PLL5_OUT3n
Altera Corporation 1–55
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
Filter each isolated power pin with a decoupling circuit shown in
Figure 1–26. Decouple the isolated power pins with a 0.1-μF and a
0.001-μF par allel combination of ceramic capacitors located as close as
possible to the Stratix device.
Figure 1–26. Stratix PLL External Clock Output Power Ball Connections
Note (1)
Note to Figure 1–26:
(1) Figure 1–26 also applies to VCC_PLL6_OUTA/B.
VCC_PLL5_OUTA
VCCIO
Supply
Stratix Device
VCC_PLL5_OUTB
0.1 μF 0.001 μF
0.1 μF 0.001 μF
1–56 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Conclusion
Guidelines
Use the following guidelines for optimal jitter performance on the
external clock outputs from enhanced PLLs 5 and 6. If all outputs are
running at the same frequency, these guidelines are not necessary to
improve performance.
■When driving two or more clock outputs from PLL 5 or 6, separate
the outputs into the two groups shown in Figure 1–24. For example,
if you are driving 100- a nd 200-MHz clock outputs off -chip from PLL
5, place one output on PLL5_OUT0p (pow ered by VCC_PLL5_OUTA)
and the other output on PLL5_OUT2p (powered by
VCC_PLL5_OUTB). Since the output buffers ar e powered by dif ferent
pins, they are less susceptibl e to bimodal jitter. Bimodal jitter is a
deterministic jitter not caused by the PLL but rather by coincident
edges of clock outputs that are multiple s of each other.
■Use phase shift to ensure edges are not coincide nt on all the clock
outputs.
■Use phase shift to skew clock edges with respect to each other for
best jitter performance.
1Delay shift (time delay elements) are no longer supported
in Stratix PLLs. Use the phase shift feature to implement the
desired time shift.
■If you cannot drive multiple clocks of different frequencies and
phase shifts or isolate banks, yo u should contr ol the drive capability
on the lower frequency clock. Reducing how much current the
output buffer has to supply can r educe the no ise. Minimize
capacitive load on the slower frequency output and configure the
output buffer to dri ve slow slew rate and lower current str ength. The
higher frequency output should have an improved performance , but
this may degrade the performance of your lower frequency clock
output.
Conclusion Stratix and Stratix GX device enhanced PLLs provide you with complete
contro l of you r cloc k s and sy stem timing. These PLLs are capa ble of
offering flexible system level clock management that was previously only
available in discrete PLL devices. The embedded PLLs meet and exceed
the features of fered by these high-end discrete devices, reducing the need
for other timing devices in the system.
Altera Corporation Section II–1
Section II. M emory
This section provides information on the TriMatrix™ Embedded Memory
blocks internal to Stratix® dev ice s and the supported external memory
interfaces.
It contains the following chapters:
■Chapter 2, TriMatrix Embedded Memory Blocks in
Stratix & Stratix GX Devices
■Chapter 3, External Memory Interfaces in Stratix & Stratix GX
Devices
The QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices
chapter is removed in this version of the Stratix Device Handbook. The
information is available in AN 349: Interfacing QDR SRAM with Stratix and
Stratix GX Devices.
Revision History The table below shows the rev ision hist ory for Chapters 2 and 3.
Chapter Date/Version Changes Made Comments
2 July 2005, v3.3 ●Updated “Implementing True Dual-Port Mode” section.
January 2005,
v3.2 ●Minor technical content update.
September
2004, v3.1 ●Updated Note 1 in Figure 2–12 on page 2–22.
●Updated description about using two different clocks in a
dual-port RAM on page 2–27.
●Deleted description of M-RAM block and document
references on page 2–27.
April 2004, v3.0 ●Synchronous occurrences are renamed to pipelined.
●Pseudo-synchronous occurrences are renamed flow-
through.
●Added AND gate to Figure 2–12.
July 2003, v2.0 ●Updated performance specification for TriMatrix memory
in Table 2-1.
●Added addressing example for a RAM that is using
mixed-width mode, page 2-9.
●Added Note 1 to Tables 2-9 and 2-10, Note 3 to Figure 2-
11, and Note 2 to Figures 2-12 and 2-13.
Section II–2 Altera Corporation
Memory Stratix Device Handbook, Volume 2
3 June 2006, v3.3 ●Changed the name of the chapter from External Memory
Interfaces to External Memory Interfaces in Stratix &
Stratix GX Devices to reflect its shared status between
those device handbooks.
●Added cross reference regarding frequency limits for 72
and 90° phase shift for DQS.
July 2005, v3.2 ●Updated mathematical symbols in Table 3–3.
●Updated “DQS Phase-Shift Circuitry” section.
September
2004, v3.1 ●Moved Figure 8 to become Figure 1, “Example of Where
a DQS Signal is Center-Aligned in the IOE” on page 3–3.
●Updated Table 3–1 on page 3–10, updated Note 4. Note
4, 5, and 6, are now Note 5, 6, and 7, respectively.
●Updated Table 3–2 on page 3–10.
●Updated Table 3–3 on page 3–13.
●Updated Note on page 3–14.
●Mov ed the “External Memory Standards” on page 3–1 to
follow the Introduction section.
●Moved “Conclusion” on page 3–27 to end of chapter.
April 2004, v3.0 ●Chapter renamed Chapter 3, External Memory Interfaces
in Stratix & Stratix GX Devices.
●Table 3–1: DDR SDRAM - side banks row added, ZBT
SRAM row updated.
●Added Tables 3–2 and 3–4.
●DQSn pins removed (page 3-5)
●Deleted “QDR SRAM Interfacing” figure.
●Replaced “tZX & tXZ Timing Diagram.”
November 2003,
v2.1 ●Removed support for series and parallel on-chip
termination.
July 2003, v2.0 ●altddio_bidir function is used for DQS in versions before
Quartus II 3.0. (page 3-2)
●Updated naming convention f or DQS pins on page 3-9 to
match pin tables.
●Clarified input clock to PLL must come from an external
input pin on page 3-12.
Chapter Date/Version Changes Made Comments
Altera Corporation 2–1
July 2005
2. TriMatrix Embedded
Memory Blocks in
Stratix & Stratix GX Devices
Introduction Stratix® and Stratix GX devices feature the TriMatrix™ memory
structure, composed of thr e e sizes of embedded RAM blocks. TriMatrix
memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and 512-Kbit
M-RAM blocks, each of which is configurable to support a wide range of
features. Offering up to 10 Mbits of RAM and up to 12 terabits per se cond
of device memory bandwidth, the TriMatrix memory structure makes the
Stratix and Stratix GX families ideal for memory-intensive applications.
TriMatrix
Memory TriMatrix memory structures can implement a wide variety of comple x
memory functions. For example, use the small M512 blocks for first-in
first-out (FIFO) functions and clock domain buffering where memory
bandwidth is critical. The M4K blocks are an ideal size for applications
requiring medium-sized memory, such as asynchronous transfer mode
(ATM) cell pr ocessing. M-RAM blocks enhance programmable logic
device (PLD) memo ry capabilities for large buf f ering applic ations, such
as internet protocol (IP) packet buffering and system cache.
TriM atrix memory blocks support various memo ry con f igurations,
including single -port, simple dual-port, true dual-port (also known as
bidir ec t ional dual-port), shift-register, ROM, and FIFO mode. The
TriMatrix memory architecture also includes advanced features and
capabilities, such as by te enable support, parity-bit support, and mixed-
port width support. This chapter describes the various T riMatrix memory
modes and features.
Table 2–1 summarizes the features supported by the three sizes of
TriM atrix memory.
fFor more information on selecting which memory block to use, see
AN 207: TriMatrix Memory Selection Using the Quartus II Software.
S52003-3.3
2–2 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
TriMatrix Memory
Table 2–1. Summary of TriMatrix Memory Features
Feature M512 Block M4K Block M-RAM Block
Performance 319 MHz 290 MHz 287 MHz
Total RAM bits (including parity bits) 576 4,608 589,824
Configurations 512 ×1
256 ×2
128 ×4
64 ×8
64 ×9
32 ×16
32 ×18
4K ×1
2K ×2
1K ×4
512 ×8
512 ×9
256 ×16
256 ×18
128 ×32
128 ×36
64K ×8
64K ×9
32K ×16
32K ×18
16K ×32
16K ×36
8K ×64
8K ×72
4K ×128
4K ×144
Parity bits vvv
Byte enable vv
Single-por t memory vvv
Simple dual-port memory vvv
True dual-port memory vv
Embedded shift register vv
ROM vv
FIFO buffer vvv
Simple dual-port mixed width support vvv
True dual-port mixed width support vv
Memory initialization file (.mif)vv
Mixed-clock mode vvv
Power-up condition Outputs cleared Outputs cleared Outputs unknown
Register clears Input and output
registers (1) Input and output
registers (2) Output registers
Same-port read-during-write New data available at
positive clock edge New data available at
positive clock edge New data available at
positive clock edge
Mixed-port read-during-write Outputs set to
unknown or old data Outputs set to
unknown or old data Unknown output
Notes to Table 2–1:
(1) The rden register on the M512 memory block does not have a clear port.
(2) On the M4K block, asserting the clear port of the rden and byte enable registers drives the output of these registers
high.
Altera Corporation 2–3
July 2005 Stratix Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
The extremely high memory bandwi dth of the Stratix and Stratix GX
device families is a result of increased memory capacity and speed.
Table 2–2 shows the memory capacity for TriMatrix memory blocks in
each Stratix devi ce. Table 2–3 shows the memory capacity for TriMatrix
memory blocks in each Stratix GX device.
Clear Signals
When applied to input registers, the asynchronous clear signal for the
TriMatrix embedded memory immediately clears the input registers.
However , the output of the memory block does not show the effects until
the next clock edge. When applied to output r egist ers, the asynchronous
clear signal clears the output registers and the effects are seen
immediately.
Parity Bit Support
The memory blocks support a parity bit for each byte. Parity bits are in
addition to the amount of memory in each RAM blo ck. For example, the
M512 block has 576 bits, 64 of which are optionally used for parity bit
Table 2–2. TriMatrix Memory Distribution in Stratix Devices
Device M512
Columns/Blocks M4K
Columns/Blocks M-RAM
Blocks Total RAM Bits
EP1S10 4 / 94 2 / 60 1 920,448
EP1S20 6 / 194 2 / 82 2 1,669,248
EP1S25 6 / 224 3 / 138 2 1,944,576
EP1S30 7 / 295 3 / 171 4 3,317,184
EP1S40 8 / 384 3 / 183 4 3,423,744
EP1S60 10 / 574 4 / 292 6 5,215,104
EP1S80 11 / 767 4 / 364 9 7,427,520
Table 2–3. TriMatrix Memory Distribution in Stratix GX Devices
Device M512
Columns/Blocks M4K
Columns/Blocks M-RAM
Blocks Total RAM Bits
EP1SGX10 4 / 94 2 / 60 1 920,448
EP1SGX25 6 / 224 3 / 138 2 1,944,576
EP1SGX40 8 / 384 3 / 183 4 3,423,744
2–4 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
TriMatrix Memory
storage. The parity bit, along with logic implemented in logic elements
(LEs), can implement parity checking for error detection to ensure data
integrity. Parity-size data wor ds ca n also stor e user-specified contr ol bi ts.
Byte Enable Support
In the M4K and M-RAM blocks, byte enable s can mask the input data so
that only specific bytes of data ar e written. The unwritten bytes r etain the
previous written value. The write enable signals (wren), in conjunction
with the byte enable signals (byteena), controls the RAM block’s write
operations. The default value for the byteena signals is high (enabled),
in which case writing is controlled only by the wren signals.
Asserting the clear port of the byte enable registers drives the byte enable
signals to their default high level.
M4K Blocks
M4K blocks support byte writes when the write port has a data width of
16, 18, 32, or 36 bits. Table 2–4 summarizes the byte selection .
Table 2–4. Byte Enable for M4K Blocks Notes (1), (2)
byteena datain ×18 datain ×36
[0] = 1 [8..0] [8..0]
[1] = 1 [17..9] [17..9]
[2] = 1 – [26..18]
[3] = 1 – [35..27]
Notes to Table 2–4:
(1) Any combination of byte enables is possible.
(2) Byte enables can be used in the same manner with 8-bit words, i.e., in ×16 and ×32
modes.
Altera Corporation 2–5
July 2005 Stratix Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
M-RAM Blocks
M-RAM blocks support byte enables for the ×16, ×18, ×32, ×36, ×64, and
×72 modes. In the ×128 or ×144 simple dual-port mode, the two sets of
byteena signals (byteena_a and byteena_b) comb ine to form the
necessary 16 byte enables. Tables 2–5 and 2–6 summarize the byte
selection.
Table 2–5. Byte Enable for M-RAM Blocks Notes (1), (2)
byteena datain ×18 datain ×36 datain ×72
[0] = 1 [8..0] [8..0] [8..0]
[1] = 1 [17..9] [17..9] [17..9]
[2] = 1 – [26..18] [26..18]
[3] = 1 – [35..27] [35..27]
[4] = 1 – – [44..36]
[5] = 1 – – [53..45]
[6] = 1 – – [62..54]
[7] = 1 – – [71..63]
Notes to Table 2–5:
(1) Any combination of byte enables is possible.
(2) Byte enables can be used in the same manner with 8-bit words , that is, in ×16, ×32,
and ×64 modes.
Table 2–6. M-RAM Combined Byte Selection for ×144 Mode (Part 1 of 2),
Notes (1), (2)
byteena_a datain ×144
[0] = 1 [8..0]
[1] = 1 [17..9]
[2] = 1 [26..18]
[3] = 1 [35..27]
[4] = 1 [44..36]
[5] = 1 [53..45]
[6] = 1 [62..54]
[7] = 1 [71..63]
[8] = 1 [80..72]
[9] = 1 [89..81]
[10] = 1 [98..90]
[11] = 1 [107..99]
2–6 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
TriMatrix Memory
Byte Enable Functional Waveform
Figure 2–1 shows how both the wren and the byteena signals co ntrol
the write operations of the RAM.
Figure 2–1. Byte Enable Functional Waveform Note (1)
Note to Figure 2–1:
(1) For more information on simulation output when a read-during-write occurs at the same address location, see
“Read-During-Write Operation at the Same Address” on page 2–25.
[12] = 1 [116..108]
[13] = 1 [125..117]
[14] = 1 [134..126]
[15] = 1 [143..135]
Notes to Table 2–6:
(1) Any combination of byte enables is possible.
(2) Byte enables can be used in the same manner with 8-bit words, i.e., in ×16, ×32,
×64, and ×128 modes.
Table 2–6. M-RAM Combined Byte Selection for ×144 Mode (Part 2 of 2),
Notes (1), (2)
byteena_a datain ×144
inclock
wren
address
data_in
asynch_data_out
an
XXXX
a0 a1 a2 a0 a1 a2
doutn ABXX XXCD ABCD ABFF FFCD
ABCD
byteena XX 10 01 11
XXXX
XX
ABCD
ABCDFFFF
FFFF
FFFF
ABFF
FFCD
contents at a0
contents at a1
contents at a2
Altera Corporation 2–7
July 2005 Stratix Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Using TriMatrix
Memory The TriMatrix memory blocks include input registers that synchronize
writes and output r egisters to pipeline designs and improve system
performance. All TriMatrix memory blocks are pipelined, meaning that
all inputs are registered, but outputs are either registered or
combinatorial. TriMatrix memory can emulate a flow-through memory
by using combinatorial outputs.
fFor more information, see AN 210: Converting Memory from Asynchr onous
to Synchronous for Stratix & Stratix GX Designs.
Depending on the TriMatrix memory block type, the memory can have
various modes, including:
■Single-port
■Simple dual-port
■True dual -port (bidirectional dual-port)
■Shift-register
■ROM
■FIFO
Implementing Single-Port Mode
Single-port mode supports non-simultaneous reads and writes.
Figure 2–2 shows the single-port memory configuration for TriMatrix
memory. All memory block types support the single-port mode.
Figure 2–2. Single-Port Memory Note (1)
Note to Figure 2–2:
(1) Two single-port memory blocks can be implemented in a single M4K block.
M4K memory blocks can also be divided in half and us ed for two
independent single-port RAM blocks. The Altera Quartus II software
automatically uses this single-port memory pa cking when running low
on memory resources. To force two single-port memories into one M4K
block, first ensure that e ach of the two independent RAM blocks is equal
to or less than half the size of the M4K block. Second, assign both single-
port RAMs to the same M4K block.
data[ ]
address[ ]
wren
inclock
inclocken
inaclr
q[ ]
outclock
outclocken
outaclr
2–8 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Using TriMatrix Memory
In the single-port RAM configuration, the outputs can only be in
read- dur ing-write m ode, which means that during the write operation,
data written to the RAM flows thr o ugh to the RAM outputs. When the
output registers are bypassed, the new data is available on the rising edge
of the same clock cycle it was written on. For more information about
read- during-write mode, see “Read-During-Write Operation at the Same
Address” on page 2–25.
Figure 2–3 shows timing waveforms for read and write operations in
single-port mode.
Figure 2–3. Single-Port Timing Waveforms
Implementing Simple Dual-Port Mode
Simple dual-port memory supports a simultaneou s read and write.
Figure 2–4 shows the simple dual-port memory configuration for
TriM atrix memory. All memory block types support this configuration.
Figure 2–4. Simple Dual-Port Memory Note (1)
Note to Figure 2–4:
(1) Simple dual-port RAM suppo rts read/write clo ck mode in addition to the
input/output clock mode shown.
in clock
wren
address
data_in
synch_data_out
an-1
din-1 din din4 din5
a6
din6
an a0 a1 a2 a3 a4 a5
asynch_data_out
din-2 din-1 din dout0 dout1 dout2 dout3 din4
din-1 din dout0 dout1 dout2 dout3 din4 din5
data[ ]
wraddress[ ]
wren
inclock
inclocken
inaclr
rdaddress[ ]
rden
q[ ]
outclock
outclocken
outaclr
Dual-Port Memory
Altera Corporation 2–9
July 2005 Stratix Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
TriM atrix memory supports mixed-width config urations , allowing
differ ent read and write port widths. When using mixed-width mode, the
LSB is written to or r ead from first. For exa mple, take a RAM that is set up
in mixed-width mode with write data width ×8 and read data width ×2.
If a binary 00000001 is written to write dress 0, the following is r ead out
of the ×2 output side:
Tables 2–7 to 2–9 show the mixed width configurations for the M512,
M4K, and M-RAM blocks, respectively.
Read Address ×2 data
00 01(LSB of ×8 data)
01 00
10 00
11 00(MSB of ×8 data)
Table 2–7. M512 Block Mixed-Width Configurations (Simple Dual-Port Mode)
Read Port Write Port
512 × 1 256 × 2 128 × 4 64 × 8 32 × 16 64 × 9 32 × 18
512 × 1 vvvvv
256 × 2vvvvv
128 × 4 vvv v
64 × 8 vv v
32 × 16 vvv v
64 × 9 v
32 × 18 v
Table 2–8. M4K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2)
Read Port Write Port
4K × 12K × 21K × 4 512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 128 × 36
4K × 1 vvv v v v
2K × 2 vvv v v v
1K × 4 vvv v v v
512 × 8 vvv v v v
256 × 16 vvv v v v
2–10 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Using TriMatrix Memory
M512 blocks support serializer and deserializer (SERDES) applications.
By using the mixed-width s upport in combinat ion with d ouble data rate
(DDR) I/O standards, the block can function as a SERDES to support low-
speed serial I/O standards using global or regional clocks.
fFor more information on Stratix device I/O structure see the Stratix
Device Family Data Sheet section of the Stratix Device Handbook, Volume 1.
For more information on Stratix GX device I/O structure see the
Stratix GX Device Family Data Sheet section of the Stratix GX Device
Handbook, Volume 1.
In simple dual-port mode, the M512 and M4K blocks have one write
enable and one read enable signal. The M512 does not support a clear port
on the rden register. On the M4K block, asserting the clear port of the
rden register drives rden high, which allows the read operation to occur .
When the read enable is deactivated, the current dat a is retained at the
output ports. If the r ead enable is activa ted during a write operation with
the same addr ess location selected, the simple dual-port RAM output is
either unknown or can be set to output the old data stor ed at the memory
address. For mor e information, see “Read-During-Write Operation at the
Same Address” on page 2–25.
128 × 32 vvv v v v
512 × 9 vv v
256 × 18 vv v
128 × 36 vv v
Table 2–9. M-RAM Block Mixed-Width Configurations (Simple Dual-Port Mode)
Read Port Write Port
64K × 932K × 18 16K × 36 8K × 72 4K × 144
64K × 9 vvvv
32K × 18 vvvv
16K × 36 vvvv
8K × 72 vvvv
4K × 144 v
Table 2–8. M4K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2)
Read Port Write Port
4K × 12K × 21K × 4 512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 128 × 36
Altera Corporation 2–11
July 2005 Stratix Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
M-RAM blocks have one write enable signal in simple dual-port mode. To
perform a write operation, the write enable is held high. The M-RAM
block is always enabled for r ead operation. If the read address and the
write address select the same address location during a write operation,
the M-RAM block output is unknown.
Figure 2–5 shows timing waveforms for read and write operations in
simple dual-port mode.
Figure 2–5. Simple Dual-Port Timing Waveforms Note (1)
Note to Figure 2–5:
(1) The rden signal is not available in the M-RAM block. A M-RAM block in simple dual-port mode is always reading
out the data stored at the current read address location.
Implementing True Dual-Port Mode
M4K and M-RAM blocks offer a tr ue dual-port mode to support any
combination of two-port operations: two reads, two write s, or one read
and one write at two different clock frequencies. Figure 2–6 shows the
true dual-port memory configuration for TriMatrix memory.
wrclock
wren
wraddress
data_in
synch_data_out
an-1 an a0 a1 a2 a3 a4 a5
din-1 din din4 din5
rdclock
a6
din6
asynch_data_out
rden
rdaddress bn b0 b1 b2 b3
doutn-2 doutn-1 doutn
doutn-1 doutn dout0
dout0
2–12 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Using TriMatrix Memory
Figure 2–6. True Dual-Port Memory Note (1)
Note to Figure 2–6:
(1) True dual-port memory supports input/output clock mode in addition to the
independent clock mode shown.
The widest bit conf iguration of the M4K and M-RAM b locks in true dual-
port mode is 256 × 16-bit (× 18-bit with parity) and 8K × 64-bit (×72-bit
with parity), respectively. The 128 × 32-bit (× 36-bit with parity)
configuration of the M4K block and the 4K × 128-bit (× 144-bit with parity)
configuration of the M-RAM block are unavailable because the number of
output drivers is equi valent to the maximum bit width of the respective
memory block. Because true dual-port RAM has outputs on two ports,
the maximum width of the true dual-port RAM equals half of the total
number of output drivers. Tables 2–10 and 2–11 list the possibl e M4K
RAM block and M-RAM block configurations, respectively.
dataA[ ]
addressA[ ]
wrenA
clockA
clockenA
qA[ ]
aclrA
dataB[ ]
addressB[ ]
wrenB
clockB
clockenB
qB[ ]
aclrB
AB
Table 2–10. M4K Block Mixed-Port Width Configurations (True Dual-Port)
Port A Port B
4K × 12K × 21K × 4 512 × 8 256 × 16 512 × 9 256 × 18
4K × 1 vvvvv
2K × 2 vvvvv
1K × 4 vvvvv
512 × 8 vvvvv
256 × 16 vvvvv
512 × 9 vv
256 × 18 vv
Altera Corporation 2–13
July 2005 Stratix Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
In true dual-port configuration, the RA M outputs can only be configur ed
for read-during-write mode. This means that during write operation,
data being written to the A or B port of the RAM flows through to the A
or B outputs, respectively. When the output registers are bypassed, the
new data is available on the rising edge of the same clock cycle it was
written on. For waveforms and information on mixed-port read-during-
write mode, see “Read-During-Write Operatio n at the Same Address” on
page 2–25.
Potential write contentions must be resolved external to the RAM because
writing to the same address location at both ports results in unknown
data storage at that location. Data is written on the rising edge of the write
clock for the M-RAM block. For a valid write operation to the same
address of the M-RAM block, the rising edge of the write clock for port A
must occur following the maximum write cycle time interval after the
rising edge of the write clock for port B. Since data is written into the
M512 and M4K blocks at the falling edge of the write clock, the rising
edge of the write clock for port A should occur following half of the
maximum write cycle time interval after the falling edge of the write clock
for port B. If this timing is not met, the data stored in that particular
address is invalid.
fSee the Stratix Device Family Data Sheet section of the Stratix Device
Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of
the Stratix GX Device Handbook, Volume 1 for the maximum synchronous
write cycle time.
Figure 2–7 shows tr ue dual-port timing waveforms for write operation at
port A and read operation at port B.
T able 2–11. M-RAM Block Mixed-Port Width Configurations (T rue Dual-Port)
Port A Port B
64K × 9 32K × 18 16K × 36 8K × 72
64K × 9 vvvv
32K × 18 vvvv
16K × 36 vvvv
8K × 72 vvvv
2–14 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Using TriMatrix Memory
Figure 2–7. True Dual-Port Timing Waveforms
Implementing Shift-Register Mode
Embedded memory block configurations can implement shif t registers
for digital signal pr oc essing (DSP) applications, such as fi ni te im pu lse
response (FIR) filters, pseudo-random number generators, multi-channel
filtering, and auto-correlation and cross-correlation functions. These and
other DSP appl ications require loc a l data storage, traditionally
implemented with standard flip-flops that can quickly consume man y
logic cells for lar g e shift registers. A more efficient alternative is to use
embedded memory as a shift register block, which save s logic cell and
routing resources and pr ov ides a more efficient implementation.
The size of a (w×m×n) shift register is determined by the input data
width (w), the length of the taps (m), and the number of taps (n). The size
of a (w×m×n) shift regi ster mus t be less than or eq ual to the maximum
number of memory bits in the respective block: 576 bits for the M512
block and 4,608 bits for the M4K block. In addition, the size of w×n must
be less than or equal to the maximum width of the respective block: 18
bits for the M512 block and 36 bits for the M4K block. If a larger shift
register is required, the memory blocks can be cascaded together.
1M-RAM blocks do not support the shift-r egister mode.
A_clk
A_wren
A_address
A_data_in
B_synch_data_out
an-1 an a0 a1 a2 a3 a4 a5
din-1 din din4 din5
B_clk
a6
din6
B_asynch_data_out
B_wren
B_address bn b0 b1 b2 b3
doutn-2 doutn-1 doutn
doutn-1 doutn dout0
A_synch_data_out
A_asynch_data_out
dout0
dout1
dout1
dout2
din-2 din-1 din dout0 dout1 dout2 dout3 din4
din-1 din dout0 dout1 dout2 dout3 din4 din5
Altera Corporation 2–15
July 2005 Stratix Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Data is written into each address location at the falling edge of the clock
and read fr om the address at the rising edge of the clock. The shift-register
mode logic automatically controls the positive and negative edge
clocking to shift the data in one clock cycle. Figure 2–8 shows the
TriMatrix memory block in the shift-register mode.
Figure 2–8. Shift-Register Memory Configuration
Implementing ROM Mode
The M512 and the M4K blocks support ROM mode. Use a memory
initialization file (.mif) to ini tialize the ROM content s of M512 and M4K
blocks. The M-RAM block does not support ROM mode.
All Stratix memory configurations must have synchronous inputs;
therefor e, the address line s of the ROM are r egistered. The outputs can be
registered or combinatorial. The ROM read operation is identical to the
read operation in the single-port RAM configuration.
m-Bit Shift Register
w w
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
ww
ww
ww
w × m × n Shift Register
n Numbe
r
of Taps
2–16 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Clock Modes
Implementing FIFO Buffers
While the small M512 memory blocks are ideal for designs with many
shallow FIFO buffers, all three memory sizes support FIFO mode.
All memory configurations have synchronous input s; however, the FIFO
buffer outputs are always combinatorial. Simultaneous read and write
from an empty FIFO is not supported.
Clock Modes Depending on the TriMatrix memory mode, independent, input/output,
read/write, and/or single-port clock modes are available. Table 2–12
shows the clock modes supported by the TriMatrix memory modes.
Independent Clock Mode
The TriMatrix memory blocks can implement independent clock mode
for true dual-port memory. In this mode, a separate clock is available for
each port (A and B). Clock A controls all registers on the port A side,
while clock B controls all registers on the port B side. Each port also
supports independent clock enables and asynchronous clear signals for
port A and B regi sters. Figure 2–9 shows a TriMatrix memory block in
independent clock mode.
Table 2–12. TriMatrix Memory Clock Modes
Clocking Mode True-Dual Port
Mode Simple Dual-
Port Mode Single-Port
Mode
Independent v
Input/output vv
Read/write v
Single-port v
Altera Corporation 2–17
July 2005 Stratix Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Figure 2–9. Independent Clock Mode Note (1), (2)
Note to Figure 2–9:
(1) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
(2) All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have
asynchronous clear ports on their output registers only.
8
D
ENA Q
D
ENA
Q
D
ENA
Q
dataA[ ]
addressA[ ]
Memory Block
256 ´ 16 (2)
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
Data In
Address A
Write/Read
Enable
Data Out
Data In
Address B
Write/Read
Enable
Data Out
clkenA
clockA
D
ENA Q
wrenA
8 LAB Row Clocks
qA[ ]
8dataB[ ]
addressB[ ]
clkenB
clockB
wrenB
qB[ ]
ENA
AB
ENA
DQ
D
ENA Q
byteenaA[ ] Byte Enable A Byte Enable B byteenaB[ ]
ENA
DQ
ENA
DQ
ENA
DQ
DQ
Write
Pulse
Generator
Write
Pulse
Generator
2–18 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Clock Modes
Input/Output Clock Mode
The TriMatrix memory blocks can implement input/output clock mode
for true and simple dual-port memory. On each of the two ports, A and B,
one clock controls all registers for input s into the memory block: data
input, wren, and address. The other clock controls the block’s data output
registers. Each memory block port also supports independent clock
enables and asynchronous clear signals for input and output r egisters.
Figures 2–10 and 2–11 show the memory block in input/output clock
mode for true and simple dual-port modes, respectively.
Altera Corporation 2–19
July 2005 Stratix Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Figure 2–10. Input/Output Clock Mode in True Dual-Port Mode Note (1)
Note to Figure 2–10:
(1) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
8
D
ENA Q
D
ENA
Q
D
ENA
Q
dataA[ ]
addressA[ ]
Memory Block
256 × 16 (2)
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Data In
Address A
Write/Read
Enable
Data Out
Data In
Address B
Write/Read
Enable
Data Out
clkenA
clockA
D
ENA Q
wrenA
8 LAB Row Clocks
qA[ ]
8
dataB[ ]
addressB[ ]
clkenB
clockB
wrenB
qB[ ]
ENA
AB
ENA
DQ
ENA
DQ
ENA
DQ
DQ
D
ENA Q
byteenaA[ ] Byte Enable A Byte Enable B byteenaB[ ]
ENA
DQ
Write
Pulse
Generator
Write
Pulse
Generator
2–20 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Clock Modes
All re gi sters shown have asynchronous clear ports, except when using
the M-RAM. M-RAM blocks have asynchronous clear ports on their
output registers only.
Figure 2–11. Input/Output Clock Mode in Simple Dual-Port Mode Notes (1), (2), (3), (4)
Notes to Figure 2–11:
(1) The rden signal is not available in the M-RAM block. A M-RAM block in simple dual-port mode is always reading
out the data stored at the current read address location.
(2) For more information on the MultiTrack™ inter connect, see the Strat ix Device Family Data Sheet section of the Stratix
Device Handbook, Volume 1 or the St ratix GX Device Family Data Sheet section of the Stratix GX Device Handbook,
Volume 1.
(3) All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have
asynchronous clear ports on their output registers only.
(4) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
8
D
ENA Q
D
ENA Q
D
ENA Q
D
ENA Q
D
ENA Q
data[ ]
D
ENA Q
wraddress[ ]
address[ ]
Memory Block
256 ´ 16
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
Data In
Read Address
Write Address
Write Enable
Read Enable
Data Out
outclken
inclken
wrclock
rdclock
wren
rden
8 LAB Row
Clocks
To MultiTrac
k
Interconnect
D
ENA Q
byteena[ ] Byte Enable
Write
Pulse
Generator
Altera Corporation 2–21
July 2005 Stratix Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Read/Write Clock Mode
The TriMatrix memory blocks can implement read/write clock mode for
simple dual-port memory. This mode can use up to two clocks. The write
clock controls the block’s data inputs, wraddress, and wren. The read
clock controls the data output, rdaddress, and rden. The memory
blocks support independent clock enables for each clock and
asynchronous clear signals for the read- and write-side registers.
Figure 2–12 shows a memory block in read/write clock mode.
2–22 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Clock Modes
Figure 2–12. Read/Write Clock Mode in Simple Dual-Port Mode Notes (1), (2), (3)
Notes to Figure 2–12:
(1) For more information on the MultiTrack interconnect, see the Stratix Device Family Data Sheet section of the Stratix
Device Handbook, Volume 1 or the St ratix GX Device Family Data Sheet section of the Stratix GX Device Handbook,
Volume 1.
(2) All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have
asynchronous clear ports on their output registers only.
(3) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
8D
ENA Q
D
ENA Q
D
ENA Q
D
ENA Q
D
ENA Q
data[ ]
D
ENA Q
wraddress[ ]
address[ ]
Memory Block
256 × 16
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Data In
Read Address
Write Address
Write Enable
Read Enable
Data Out
rdclocken
wrclocken
wrclock
rdclock
wren
rden
8 LAB Row
Clocks
To MultiTrac
k
Interconnect
D
ENA Q
byteena[ ] Byte Enable
Write
Pulse
Generator
Read
Pulse
Generator
Altera Corporation 2–23
July 2005 Stratix Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Single-Port Mode
The TriMatrix memory blocks can implement single-port clock mode for
single-port memory mode. Single-port mode is used when simultaneous
reads and writes are not required. See Figure 2–13. A single block in a
memory block can support up to two single-port mode RAM blocks in
M4K blocks.
Figure 2–13. Single-Port Mode Notes (1), (2), (3)
Notes to Figure 2–13:
(1) For more information on the MultiTrack interconnect, see the Stratix Device Famil y Data Sheet secti on of th e Stratix
Device Handbook, Volume 1 or the Stra ti x GX Device Family Dat a She e t section of the Stratix GX Device Handbook,
Volume 1.
(2) All registers shown have asynchronous clear ports, except when using the M-RAM. M-RAM blocks have
asynchronous clear ports on their output registers only.
(3) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
Designing With
TriMatrix
Memory
When instantiating TriMatrix memory you must understand the various
features that set it apart fr om other memo ry ar chitectur es. The following
sections describe some of the important attribute s and functio nality of
TriM atrix memory.
8
D
ENA Q
D
ENA Q
D
ENA Q
D
ENA Q
data[ ]
address[ ]
RAM/ROM
256 × 16
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Data In
Address
Write Enable
Data Out
outclken
inclken
inclock
outclock
Write
Pulse
Generator
wren
8 LAB Row
Clocks
To MultiTrac
k
Interconnect
2–24 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Designing With TriMatrix Memory
fFor information on the difference between APEX-style memory and
TriMatrix memory, see the Transition ing APEX Designs to Stratix Devices
chapter.
Selecting TriMatrix Memory Blocks
The Quartus II software automatically partitions user-defined memory
into embedded memory blocks using the most efficient size
combinations. The memory can also be manually assigned to a specific
block size or a mixture of block sizes. Table 2–1 on page 2–2 is a guide for
selecting a TriMatrix memory block size based on supported features.
1Violating the setup or hold time on the address registe rs could
corrupt the memory contents. This applies to both r ead and
write operations.
fFor more information on selecting which memory block to use, see
AN 207: TriMatrix Memory Selection Using the Quartus II Software.
1Violating the setup or hold time on the address registe rs could
corrupt the memory contents. This applies to both r ead and
write operations.
Pipeline & Flow-Through Modes
TriMatrix memory architecture implements synchronous (pipelined)
RAM by regist ering both the input and output signals to the RAM block.
All TriMatrix memory inputs are r egistered providing synchr onous write
cycles. In synchronous operation, RAM generates its own self-tim ed
strobe write enable (wren) signal derived from the global or regional
clock. In contrast, a circuit using asynchronous RAM must generate the
RAM wren sig nal while ensuring its data and ad dress signals meet setup
and hold time specifications relative to the wren signal. The output
regis ters can be by pass ed.
In an asynchronous memory neither the input nor the output is
registered. While Stratix and Stratix GX devices do not support
asynchronous memory, they do support a flow-through read where the
output data is available during the clock cycle when the read address is
driven into it. Flow-through r eading is possible in the simple and true
dual-port modes of the M512 and M4K blocks by clocking the read enable
and read a ddress registers on the negative clock edge and bypassing t he
output registers.
fFor more information, see AN 210: Converting Memory from Asynchr onous
to Synchronous for Stratix & Stratix GX Devices.
Altera Corporation 2–25
July 2005 Stratix Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Power-up Conditions & Memory Initialization
Upon power-up, T riMatrix memory is in an idle state. The M512 and M4K
block outputs always power-up to zer o, regar dless of whether the output
registers ar e used or bypassed. Even if a memory initialization file is used
to pre-load the contents of the RAM block, the outputs still power-up
cleared. Fo r example, if add ress 0 is pre-initialized to FF, the M512 and
M4K blocks power-up with the output at 00.
M-RAM blocks do not support memory in itialization files; therefore, they
cannot be pre-loaded with data upon power-up. M-RAM blocks
combinatorial outputs and memory controls always power-up to an
unknown state. If M-RAM block outputs are registered, the registers
po wer-up cleared. The unde fined output appears one clock cy cl e la ter.
The output r emai ns undef ined until a re ad operation is performed on an
address that has been written to.
Read-During-
Write Operation
at the Same
Address
The following two sections describe the functionality of the va rious RAM
configurations when readi ng from an address during a write operation at
that same address. There are two types of read-during-write operations:
same-port and mixed-port. Figure 2–14 illust rates the difference in data
flow between same-port and mixed-port read-during-write.
Figure 2–14. Read-During-Write Data Flow
Same-Port Read-During-Wr ite Mode
For read-during-write operation of a single-port RAM or the same port of
a true dual-port RAM, the new data is available on the rising edge o f the
same clock cycle it was written on. This behavior i s v alid on all memory-
block sizes. See Figure 2–15 for a sample functional waveform.
Port A
data in Port B
data in
Port B
data out
Port A
data out
Same-port
data flow
Mixed-port
data flow
2–26 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Read-During-Write Operation at the Same Address
When using byte enables in true dual-port RAM mode, the outputs for
the masked bytes on the same port are unknown. (See Figure 2–1 on
page 2–6.) The non-masked bytes are read out as shown in Figure 2–15.
Figure 2–15. Same-Port Read-During-Write Functionality Note (1)
Note to Figure 2–15:
(1) Outputs are not registered.
Mixed-Port Read-During-Write Mode
This mode is used when a RAM in simple or true dual-port mode has one
port reading and the other port writ ing to the same addr ess location with
the same clock.
The READ_DURING_WRITE_MODE_MIXED_PORTS parameter for M512
and M4K memory blocks determines whether to output the old data at
the address or a “don’t car e” value. Setting this parameter to OLD_DATA
outputs the old data at that address. Setting this parameter to DONT_CARE
outputs a “don’t care” or unknown value. See Figures 2–16 and 2–17 for
sample functional wave forms showing this operation. These figures
assume that the outputs are not registered.
The DONT_CARE setting allows memory implementation in any TriMatrix
memory block. The OLD_DATA setting restricts memory implementation
to only M512 or M4K memory blocks. Selecting DONT_CARE gives the
compiler mor e flexibili ty when placing memory functi ons into TriMatrix
memory.
inclock
data_in
wren
data_out A
BA
Old
Altera Corporation 2–27
July 2005 Stratix Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Figure 2–16. Mixed-Port Read-During-Write: OLD_DATA
For mixed-port read-during-write operation of the same addr ess location
of a M-RAM block, the RAM outputs are unknown, as shown in
Figure 2–17.
Figure 2–17. Mixed-Port Read-During-Write: DONT_CARE
Mixed-port read-during-write is not supported when two different clocks
are used in a dual-port RAM. The output value wi ll be unknown during
a mixed-port r ead -du r ing-write operation.
Conclusion TriMatrix memory, an enhanced RAM architecture with extremely high
memory bandwidth in Stratix and Stratix GX devices, gives advanced
control of memory applications with features such as byte enables, parity
bit storage, and shift-register mode, as well as mixed-port width support
and true dual-port mode.
inclock
Port A
data_in
Port A
wren
Port B
data_out
AB
AOld
Port B
wren
B
Address Q
addressA and
addressB
inclock
Port A
data_in
Port A
wren
Port B
data_out
AB
BUnknown
Port B
wren
Address Q
addressA and
addressB
2–28 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Conclusion
Altera Corporation 3–1
June 2006
3. External Memory
Interfaces in Stratix &
Stratix GX Devices
Introduction Stratix® and Strati x GX devi ces su pport a broad range of external
memory interfaces such as double data rate (DDR) SDRAM, RLDRAM II,
quad data rate (QDR) SRAM, QDRII S RAM, zero bus turnaround (ZBT)
SRAM, and single data rate (SDR) SDRAM. The dedicated phase-shift
circuitry allows the Stratix a nd Stratix GX devices to interface at twice the
system clock speed with an external memory (up to 200 MHz/400 Mbps).
Typical I/O architectu res transmit a single data word on each positive
clock edge and are limi ted to the as sociated clock speed using this
protocol. To achieve a 400-megabits per second (Mbps) transfer rate, a
SDR system requires a 400-MHz clock. Many new applications have
introduced a DDR I/O architecture as an alternative to SDR architectures.
While SDR architectur es capture data on one edge of a clock, the DDR
architectures captures data on both the rising and falling edges of the
clock, doubling the throughput for a given clock frequency and
accelerating performance. For example, a 200-MHz clock can capture a
400-Mbps data stream, enhancing system performance and simplifying
board design.
Most current memory architectures use a DDR I/O interface. These DDR
memory standards cover a broad range of applications for embedded
proce ss or system s, im ag e processing, storage, communications, and
networking. This chapter describes the hardwar e features in Stratix and
Stratix GX devices that facilitate the high-spee d memory interfacing for
each memory standard. It then briefly explains how each memory
standard uses the features of the Stratix and Stratix GX devices.
fYou can use this document with AN 329: ZBT SRAM Controller Reference
Design for Stratix & Stratix GX Devices, AN 342: Interfacing DDR SDRAM
with Stratix & Stratix GX Devices, and AN 349: QDR SRAM Controller
Reference Design for Stratix & Stratix GX Devices.
External
Memory
Standards
The following sections provide an overvie w on using the Stratix and
Stratix GX device external memory interfacing featur es.
DDR SDRAM
DDR SDRAM is a memory architecture that transmits and receives data
at twice the clock speed of traditional SDR archite ctu res. These devices
transfer data on both the rising and falling edge of the clock signal.
S52008-3.3
3–2 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
External Memory Standards
Interface Pins
DDR devices use interf ace pins inc lu di n g data, data str obe, clock,
command, and address pins. Data is sent and captured at twice the clock
rate by transferring data on both the positive and negative edge of a clock.
The commands and add resses only use one active edge of a clock.
Connect the memory device’s DQ and DQS pins to the DQ and DQS pins,
respectively, as listed in the Stratix and Stratix GX devices pin table. DDR
SDRAM also uses active-high data mask pins for writes. You can conne ct
DM pins to any of the I/O pins in the same bank as the DQ pins of the
FPGA. There is one DM pin per DQS/DQ group.
DDR SDRAM ×16 devices use two DQS pins, and each DQS pin is
associated with eight DQ pins. However, this is not the same as the
×16 mode in Stratix and Stratix GX devices. To support a ×16 DDR
SDRAM, you need to configure the Stratix and Stratix GX FPGAs to use
two sets of DQ pins in ×8 mode. Similarly if your ×32 memory device uses
four DQS pins wher e each DQS pin is associated with eight DQ pins, you
need to configure the Stratix and Stratix GX FPGA to use four sets of pins
in ×8 mode.
You can also use any I/O pins in banks 1, 2, 5, or 6 to interface with
DDR SDRAM devices. These banks do not have dedicated circuitry,
though.
You can also use any of the user I/O pins for commands and addresses to
the DDR SDRAM.
fFor more information, see AN 342: Interfacing DDR SDRAM with Stratix
& Stratix GX Devices.
If the DDR SDRAM device supports ECC, the design uses a DQS/DQ
group for ECC pins. You can use any of the user I/O pins for commands
and addresses.
Because of the symmetrical setup and hold time for the command and
address pins at the memory, you might need to generate these signals
from the system clock’s negative edge.
The clocks to the SDRAM device are called CK and CK#. Use any of the
user I/O pins via the DDR registers to generate the CK and CK# signals
to meet the DDR SDRAM tDQSS requirement. The memory device’s tDQSS
requires that the DQS signal’s positive edge write operations must be
within 25% of the positive edge of the DDR SDRAM clock input. Using
user I/O pins for CK and CK# ensures that any PVT variations seen by
the DQS signal are tracked by these pins, too.
Altera Corporation 3–3
June 2006 Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
Read & Write Operations
When reading from the DDR SDRAM, the DQS signal coming into the
Stratix and Stratix GX device is edge-aligned with the DQ pins. The
dedicated circuitry c enter-aligns the DQS signal with respect to the DQ
signals and the shifted DQS bus drives the clock input of the DDR input
registers. The DDR input registers bri ng the da t a from the DQ signals to
the device. The system clock clocks the DQS output enable and output
paths. The -90° shifted clock clocks the DQ output enable and output
paths. Figure 3–1 shows an example of the DQ and DQS relationship
during a burst-of-two read. It shows wher e the DQS signal is
center-aligned in the IOE.
Figure 3–1. Example of Where a DQS Signal is Center-Aligned in the IOE
When writing to the DDR SDRAM, the DQS signal must be center-
aligned with the DQ pins. Two PLL outputs are needed to generate the
DQS signal and to clock the DQ pins. The DQS are clocked by the 0°
phase-shift PLL output, while the DQ pins are clocke d by the -90° phase-
shifted PLL output. Figure 3–2 shows the DQS and DQ relationship
during a DDR SDRAM burst-of-two write.
Figure 3–2. DQ & DQS Relationship During a Burst-of-Two Write
DQS at DQ
IOE registers
DQS at
FPGA Pin
DQ at DQ
IOE registers
DQ at
FPGA Pin
Pin to register
delay
Pin to register
delay
90 degree shift
Preamble Postamble
DQS at
FPGA Pin
DQ at
FPGA Pin
3–4 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
External Memory Standards
Figure 3–3 shows DDR SDRAM interfacing from the I/O through the
dedicated circ uitry to the logic array. When the DQS pin acts as an input
stro be, the dedicated circuitry shifts the incoming DQS pin by either 72°
or 90° and clocks the DDR input registers. Because of the DDR input
registers architecture in Stratix and Stratix GX devices, the shifted DQS
signal must be inverted. The DDR registers outputs are sent to two LE
registers to be synchronized with the system clock.
fRefer to the DC & Switching Chara c teri stics chapter in volume 1 of the
Stratix Device Handbook for frequency limits regarding the 72 and 90°
phase shift for DQS.
Figure 3–3. DDR SDRAM Interfacing
fFor more information on DDR SDRAM specifications, see JEDEC
standard publications JESD79C from www.jedec.org, or see
AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices.
RLDRAM II
RLDRAM II provides fast random access as well as high bandwidth and
high density, making this memory technology ideal for high-speed
network and communication data storage applications. The fast random
access speeds in RLDRAM II devices make them a viable alternative to
SRAM devices at a lower cost. Additionally, RLDRAM II devices have
minimal latency to support designs that require fast response times.
User logic/
GND 2
OE
PLL − 90˚
DQS
Adjacent LAB LEs
DQS Bus
Resynchronizing
Global Clock
Compensated
Delay Shift
DDR
OE
Registers
DDR
Output
Registers
2
OE DDR
OE
Registers
DDR
Output
Registers
DQ
I/O Elements &
Periphery
DDR
Input
Registers
LE
Register
LE
Register
Δ t
2
Altera Corporation 3–5
June 2006 Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
Interface Pins
RLDRAM II devices use interface pins such as data, clock, command, and
address pins. There ar e tw o types o f RLDRAM II memory: common I/O
(CIO) and separate I/O (SIO). The data pins in RLDRAM II CIO device
are bidirectional while the data pins in a RLDRAM II SIO device are
uni-directional. Instead of bidirectional data strobes, RLDRAM II uses
differ ential free-ru nning read and write clocks to accompany the data. As
in DDR SDRAM, data is sent and captur ed at twice the clock rate by
transferring data on both the positive and negative edge of a clock. The
commands and addresses still only use one active edge of a clock.
If the data pins are bidirectional, connect them to the Stratix and
Stratix GX device DQ pins. If the data pins are uni-directional, connect
the RLDRAM II device Q ports to the Stratix and Stratix GX device DQ
pins and connect the D ports to any user I/O pins in I/O banks 3, 4, 7, and
8. RLDRAM II also uses active-high data mask pins for writes. You can
connect DM pins to any of the I/O pins in the same bank as the DQ pins
of the FPGA. When interfacing with SIO devices, connect the DM pins to
any of the I/O pins in the same bank as the D pins. There is one DM pin
per DQS/DQ group.
Connect the read clock pins (QK) to Stratix and Stratix GX device DQS
pins. You must configure the DQS signals as bidirectional pins. However ,
since QK pins are output-only pins fr om the memory, RLDRAM memory
interfacing in Stratix and Stratix GX devices requir es that you gr ound the
DQS and DQSn pin output enables. The Stratix and Stratix GX devices
use the shifted QK signal from the DQS logic block to capture dat a. You
can leave the QK# signal of the RLDRAM II device unconnected.
RLDRAM II devices have both input clocks (CK and CK#) and write
clocks (DK and DK#). Use the external clock buffer to generate CK, CK#,
DK, and DK# to meet the CK, CK#, DK, and DK# skew requirements from
the RLDRAM II device. If you are interfacing with multiple RLDRAM II
devices, perform IBIS simulations to analyze the loading effects on the
clock pair.
You can use any of the us er I/O pins for commands and addresses.
RLDRAM II also offers QVLD pins to indicate the read data availability.
Connect the QVLD pins to the Stratix and Stratix GX device DQVLD pins,
listed in the pin table.
Read & Write Operations
When reading from the RLDRAM II device, data is sent edge-aligned
with the read clock QK or QK# signal. When writing to the RLDRAM II
device, data must be center-aligned with the write clock (DK or DK#
signal). The Stratix and Stratix GX device RLDRAM II interface uses the
3–6 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
External Memory Standards
same scheme as in DDR SDRAM interfaces wher eby the dedicated
circuitry is used during reads to center-align the data and the read clock
inside the FPGA and the PLL center-aligns the data and write clock
outputs. The data and clock relationship for read s and writes in
RLDRAM II is similar to those in DDR SDRAM as already depicted in
Figure 3–1 on page 3–3 and Figure 3–3 on page 3–4.
QDR & QDRII SRAM
QDR SRAM provides independent read and write ports that eliminate
the need for bus turnaround. The me mo ry uses two sets of clo cks: K and
Kn for write access, and optional C and Cn for read accesses, where Kn
and Cn are the inverse of the K and C clocks, respectively. You can use
differ ential HSTL I/O pins to drive the QDR SRAM clock into t he Stratix
and Stratix GX devices. The separate write data and read data ports
permit a transfer rate up to four words on every cycle thr ough the DDR
circuitry. Stratix and Stratix GX devices su pport both burst-of-two and
burst-of-four QDR SRAM architectur es, with clock cycles up to 167 MHz
using the 1.5-V HSTL Class I or Class II I/O standard. Figure 3–4 shows
the block diagram for QDR SRAM burst-of-two architecture.
Figure 3–4. QDR SRAM Block Diagram for Burst-of-Two Architecture
QDRII SRAM is a second generation of QDR SRAM devices. It can
transfer four words per clock cycle, fulfilling the requirements facing
next-generation communications system designers. QDRII SRAM
devices provide concurrent reads and writes, zero latency, and increased
data throughput. Stratix and Stratix GX devices support Q DRII SRAM at
speeds up to 200 MHz since the timing requirements for QDRII SRAM
are no t as strict as QDR SRAM.
256K × 18
Memory
Array
256K × 18
Memory
Array Read
Port RPSn
Q
Write
Port
WPSn
D
A
18
18 Data
Control
Logic
K, Kn
18
36
BWSn
V
REF
C, Cn
2
2
Data
36
Discrete QDR SRAM Device
Altera Corporation 3–7
June 2006 Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
Interface Pins
QDR and QDRII SRAM uses two separate, uni-directional data ports for
read and write operations, enabling quad data-rate data transfer. Both
QDR and QDRII SRAM use shared address lines for reads and writes.
Stratix and Stratix GX devices ut ilize dedicated DDR I/O circuitry for the
input and output data bus and the K and Kn output clock signal s.
Both QDR and QDRII SRAM burst-of-two devices sample the read
address on the rising edge of the K clock and sample the write address on
the rising edge of the Kn clock while QDR and QDRII SRAM burst-of-
four devices sample both read and write addresses on the K clock's rising
edge. You can use any of the Stratix and Stratix GX device user I/O pins
in I/O banks 3, 4, 7, and 8 for the D write data ports, commands, and
addresses.
QDR SRAM uses the following clock signals: input clocks K and Kn and
output clocks C and Cn. In addition to the aforementioned two pairs of
clocks, QDRII SRAM also uses echo clocks CQ and CQn. Clocks Cn, Kn,
and CQn are logical complements of clocks C, K, and CQ respectively.
Clocks C, Cn, K, and Kn are inputs to the QDRII SRAM while clocks CQ
and CQn are outputs fro m the QDRII SRAM. Stratix and Stratix GX
devices use single-clock mode for single-device QDR and QDRII SRAM
interfacing where the K and Kn are used for both read and write
operations, and the C and Cn clocks ar e unused. Use both C or Cn and K
or Kn clocks when interfacing with a bank of multiple QDRII SRAM
devices with a single controller.
You can generate C, Cn, K, and Kn clocks using any of the I/O r egisters
in I/O banks 3, 4, 7, or 8 via the DDR registers. Due to strict skew
requir ements between K and Kn signals, use adjacent pins to generate the
clock pair. Surround the pair with buf fer pins tied to VCC and gr ound for
better noise immunity from other signals.
In general, all output signals to the QDR and QDRII SRAM should use the
top and bottom banks (I/O banks 3, 4, 7, or 8). You can place the input
signals from the QDR and QDRII SRAM in any I/O banks.
Read & Write Operations
Figure 3–5 shows the data and clock relationships in QDRII SRAM
devices at the memory pins during reads. QDR and QDRII SRAM devices
send data within a tCO time after each rising edge of the input clock C or
Cn in multi-clock mode, or the input clock K or Kn in single clock mode.
Data is valid until tDOH time, after each rising edge of the C or Cn in multi-
3–8 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
External Memory Standards
clock mode, or K or Kn in single clock mode. The edge-aligned CQ and
CQn clocks accompany the read data for data capture in Stratix and
Stratix GX devices.
Figure 3–5. Data & Clock Relationship During a QDRII SRAM Read Note (1)
Notes to Figure 3–5:
(1) The timing parameter nomenclature is based on the Cypress QDRII SRAM data sheet for CY7C1313V18.
(2) CO is the data clock-to-out time and tDOH is the data output hold time between burst.
(3) tCLZ and tCHZ are bus turn-on and turn-off times respectively.
(4) tCQD is the skew between CQn and data edges.
(5) tCQQO and tCQOH are skew between the C or Cn (or K or Kn in single-clock mode) and the CQ or CQn clocks.
When writing to QDRII SRAM devices, data is generated by the write
clock, while the K clock is 90° shifted from the write clock, creating a
center-aligned arrangement.
fGo to www.qdrsram.com for the QDR SRAM and QDRII SRAM
specifications. For more information on QDR and QDRII SRAM
interfaces in Stratix and Stratix GX devices, see AN 349: QDR SRAM
Controller Reference Design for Stratix & Stratix GX Devices.
ZBT SRAM
ZBT SRAM eliminate dead bus cycles when turning a bidirectional bus
around between reads and writes or between writes and reads. ZBT
allows for 100% bus utilization because ZBT SRAM can be read or written
on every clock cycle. Bus contention can occur when shifting from a write
cycle to a read cycle or vice versa with no idl e cy cles in between.
ZBT SRAM allows small amounts of bus contention. To avoid bus
contention, the output clock-to-low-impedance time (t ZX) must be greater
QA QA + 1 QA + 2 QA + 3
C/K
Cn/Kn
CQ
CQn
Q
t
CO (2)
t
CO (2)
t
CLZ (3)
t
CCQO (5)
t
CQOH (5)
t
CQD (4)
t
CQD (4)
t
DOH (2)
t
CHZ (3)
Altera Corporation 3–9
June 2006 Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
than the clock-to-high-impedance time (tXZ). Stratix and Stratix GX device
I/O pins can interface with ZBT SRAM devices at up t o 200 MHz and can
meet ZBT tCO and tSU timing requirements by contro lling phase delay in
clocks to the OE or output and input registers using an enhanced PLL.
Figure 3–6 shows a flow-through ZBT SRAM operation where A1 and A3
are read addresses and A2 and A4 are write addresses. For pipelined
ZBT SRAM operation, data is delayed by another clock cycle. Stratix and
Stratix GX devices support up to 200-MHz ZBT SRAM operation using
the 2.5-V or 3.3-V LVTTL I/O standard.
Figure 3–6. tZX & tXZ Timing Diagram
Interface Pins
ZBT SRAM uses one system clock input for all clocking purposes. Only
the rising edge of this clock is used, since ZBT SRAM uses a single data
rate scheme. The data bus, DQ, is bidirectional. There are three contro l
signals to the ZBT SRAM: RW_N, BW_N, and ADV_LD_N. You can use any
of the Stratix and Stratix GX device user I/O pins to interface to the
ZBT SRAM device.
fFor more information on ZBT SRAM Interfaces in Stratix devices, see
AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX
Devices.
ZBT Bus Sharing
Device t
ZX
t
XZ
t
ZX
A1 A2 A3 A4
Q(A1) Q(A3)
D(A3)
clock
addr
dataout
datain
wren
3–10 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
DDR Memory Support Over view
DDR Memor y
Support
Overview
Table 3–1 shows the external RAM support in Stratix EP1S10 through
EP1S40 devices and all Stratix GX devices. Table 3–2 shows the external
RAM support in Stratix EP1S60 and EP1S80 devices.
Table 3–1. External RAM Support in Stratix EP1S10 through EP1S40 & All Stratix GX Devices
DDR Memor y Type I/O
Standard
Maximum Clock Rate (MHz)
-5 Speed
Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Flip-Chip Flip-Chip Wire-
Bond Flip-
Chip Wire-
Bond Flip-
Chip Wire-
Bond
DDR SDRAM (1),
(2) SSTL-2 200 167 133 133 100 100 100
DDR SDRAM - side
banks (2), (3), (4) SSTL-2 150 133 110 133 100 100 100
RLDRAM II (4) 1.8-V HSTL 200 (5) (5) (5) (5) (5) (5)
QDR SRAM (6) 1.5-V HSTL 167 167 133 133 100 100 100
QDRII SRAM (6) 1.5-V HSTL 200 167 133 133 100 100 100
ZBT SRAM (7) LVTTL 200 200 200 167 167 133 133
Notes to Table 3–1:
(1) These maximum clock rates apply if the Stratix device uses DQS phase-shift circuitry to interface with DDR
SDRAM. DQS phase-shift circuitry is only available on the top and bottom I/O banks (I/O banks 3, 4, 7, and 8).
(2) For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices.
(3) DDR SDRAM is supported on the Stratix device side I/O bank s (I/O banks 1, 2, 5, and 6) without dedicated DQS
phase-shift circuitry. The read DQS signal is ignored in this mode.
(4) These performance specifications are preliminary.
(5) This device does not support RLDRAM II.
(6) For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Ref e rence Design for Stratix &
Stratix GX Devices.
(7) For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix and Stratix GX
Devices.
Table 3–2. External RAM Support in Stratix EP1S60 & EP1S80 (Part 1 of 2)
DDR Memory T y pe I/O Standard Maximum Clock Rate (MHz)
-5 Speed Grade -6 Speed Grade -7 Speed Grade
DDR SDRAM (1), (2) SSTL-2 167 167 133
DDR SDRAM - side banks (2), (3) SSTL-2 150 133 133
QDR SRAM (4) 1.5-V HSTL 133 133 133
QDRII SRAM (4) 1.5-V HSTL 167 167 133
Altera Corporation 3–11
June 2006 Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
Stratix and Stratix GX devices support the data strobe or r ead clock signal
(DQS) used in DDR SDRAM, and RLDRAM II devices. DQS signals are
associated with a gr oup of data (DQ) pins.
Stratix and Stratix GX devices contain dedicated cir cu it ry to shift the
incoming DQS signals by 0°, 72°, and 90°. The DQS phase-shift circuitry
uses a frequency re ference to dynamically generate control signals for the
delay chains in each of the DQS pins, allowing it to compensate for
process, vol tage, and temperature (PVT) variations. The dedicated
circuitry also creates consistent marg ins that meet your data sam pling
window requirements.
fRefer to the DC & Switching Chara c teri stics chapter in volume 1 of the
Stratix Device Handbook for frequency limits regarding the 72 and 90°
phase shift for DQS.
In addition to the DQS dedicated phase-shift cir cuitry, every I/O element
(IOE) in Stratix and Stratix GX devices contains six registers and one latch
to achieve DDR operation. Ther e is also a programmable delay chain in
the IOE that can help reduce contention when interfacing with ZBT
SRAM devices.
DDR Memory Interface Pins
Stratix and Stratix GX devices use data (DQ), data strobe (DQS), and clock
pins to interface with DDR SDRAM and RLDRAM II devices. This section
explains the pins used in the DDR SDRAM and RLDRAM II interfaces.
For QDR, QDRII, and ZBT SRAM interfaces, see the “External Memory
Standards” section.
ZBT SRAM (5) LVTTL 200 200 167
Notes to Table 3–2:
(1) These maximum clock rates apply if the Stratix device uses DQS phase-shift circuitry to interface with DDR
SDRAM. DQS phase-shift circuitry is only available on the top and bottom I/O banks (I/O banks 3, 4, 7, and 8).
(2) For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices.
(3) DDR SDRAM is supported on the side banks (I/O banks 1, 2, 5, and 6) with no dedicated DQS phase-shift circuitry.
The read DQS signal is ignored in this mode.
(4) For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Ref e rence Design for Stratix &
Stratix GX Devices.
(5) For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix and Stratix GX
Devices.
Table 3–2. External RAM Support in Stratix EP1S60 & EP1S80 (Part 2 of 2)
DDR Memory T y pe I/O Standard Maximum Clock Rate (MHz)
-5 Speed Grade -6 Speed Grade -7 Speed Grade
3–12 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
DDR Memory Support Over view
Figure 3–7 shows the DQ and DQS pins in ×8 mode.
Figure 3–7. Stratix & Stratix GX Device DQ & DQS Groups in × 8 Mode
Note to Figure 3–7:
(1) There are at least eight DQ pins per group.
Data & Data Strobe Pins
Stratix and Strat ix GX data pins for the DDR memory interfaces are called
DQ pins. The Stratix and Stratix GX device I/O banks at the top (I/O
banks 3 and 4) and the bottom (I/O banks 7 and 8) of the dev ice support
DDR SDRAM and RLDRAM II up to 200 MHz. These pins support DQS
signals with DQ bus modes of ×8, ×16, or ×32. Stratix and Stratix GX
devices can support either bidirectional data strobes or uni-directional
read clocks. Depending on the external memory interface, either the
memory device's read data strobes or read clocks feed the DQS pins.
For ×8 mode, there are up to 20 groups of programmable DQS and DQ
pins—10 groups in I/O b anks 3 and 4 and 10 groups in I/O banks 7 and 8
(see Table 3–3). Each group consists of one DQS pin and a set of eight DQ
pins.
For ×16 mode, th ere are up to eight groups of programmable DQS and
DQ pins—four groups in I/O banks 3 and 4, and four groups in I/O
banks 7 and 8. The EP1S20 device supports seven ×16 mode groups. The
EP1S10 device does not support ×16 mode. All other devices support the
full eight groups. See Table 3–3. Each group consists of one DQS and 16
DQ pins. In ×16 mode, DQS1T, DQS3T, DQS6T, and DQS8T pins on the top
side of the device, and DQS1B, DQS3B, DQS6B, and DQS8B pins on the
DQ Pins
(
1
)
DQS Pin
Top or Bottom I/O Bank
Altera Corporation 3–13
June 2006 Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
bottom side of the device are dedicated DQS pins. The DQS2T, DQS7T,
DQS2B, and DQS7B pins are dedicated DQS pins for ×32 mode, and each
group consists of one DQS and 32 DQ pins.
Table 3–3. DQS & DQ Bus Mode Support Note (1)
Device Package Number of ×8
Groups Number of ×16
Groups Number of ×32
Groups
EP1S10 672-pin BGA
672-pin FineLine BGA®12 (2) 00
484-pin FineLine BGA
780-pin FineLine BGA 16 (3) 04
EP1S20 484-pin FineLine BGA 18 (4) 7 (5) 4
672-pin BGA
672-pin FineLine BGA 16 (3) 7 (5) 4
780-pin FineLine BGA 20 7 (5) 4
EP1S25 672-pin BGA
672-pin FineLine BGA 16 (3) 84
780-pin FineLine BGA
1,020-pin FineLine BGA 20 8 4
EP1S30 956-pin BGA
780-pin FineLine BGA
1,020-pin FineLine BGA
20 8 4
EP1S40 956-pin BGA
1,020-pin FineLine BGA
1,508-pin FineLine BGA
20 8 4
EP1S60 956-pin BGA
1,020-pin FineLine BGA
1,508-pin FineLine BGA
20 8 4
EP1S80 956-pin BGA
1,508-pin FineLine BGA
1,923-pin FineLine BGA
20 8 4
Notes to Table 3–3:
(1) For VREF guidelines, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix Device
Handbook, Volume 2 or the Stratix GX Handbook, Volume 2.
(2) These packages have six groups in I/O banks 3 and 4 and six groups in I/O banks 7 and 8.
(3) These packages have eight groups in I/O banks 3 and 4 and eight groups in I/O banks 7 and 8.
(4) This package has nine groups in I/O banks 3 and 4 and nine groups in I/O banks 7 and 8.
(5) These packages have three groups in I/O banks 3 and 4 and four groups in I/O banks 7 and 8.
3–14 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
DDR Memory Support Over view
The DQS pins ar e marked in the Strat ix and Stratix GX device pin table as
DQS[9..0]T or DQS[9..0]B, wher e T stands for top and B for bottom.
The corresponding DQ pins are marked as DQ[9..0]T[7..0], where
[9..0] indicates which DQS group the pins belong to. The numbering
scheme starts from right to left on the package bottom view. When not
used as DQ or DQS pins, these pins are available as user I/O pins.
You can also create a design in a mode other than the ×8, ×16, or ×32
mode. The Quartus®II softwar e uses the next larger mode with the
unused DQ pins available as regular use I/O pins. For example, if you
create a design for ×9 mode for an RLDRAM II interface (nine DQ pins
driven by one DQS pin), the Quartus II software implements a ×16 mode
with seven DQ pins unconnected to the DQS bus. These seven unused
DQ pins can be used as re gular I/O pins.
1On the top and bottom side of the device, the DQ and DQS pins
must be configur ed as bidirectional DDR pins to enable the DQS
phase-shift circuitry. If you only want to use the DQ and/or
DQS pins as inputs, you need to set the output enable of the DQ
and/or DQS pins to ground. Use the altdqs and altdq
megafunctions to configure the DQ S and DQ pins, r espectively.
However, you should use the Altera® IP Toolbench to create the
data path for your memory interfaces.
Stratix and Stratix GX device side I/O banks (I/O banks 1, 2, 5, and 6)
support SDR SDRAM, ZBT SRAM, QDR SRAM, QDRII SRAM, and DDR
SDRAM interfaces and can use any of th e user I/O pins in these banks for
the interface. Since these I/O banks do not have any dedicated circuitry
for memory interfacing, they can support DDR SDRAM up to 150 MHz
in -5 speed grade devices. However, these I/O banks do not support the
HSTL-18 Class II I/O standard, which is required to interface with
RLDRAM II.
Clock Pins
You can use any of the DDR I/O registers in the to p or bottom bank of the
device (I/O banks 3, 4, 7, or 8) to generate clocks to the memory device.
You can also use any of the DDR I/O registers in the side I/O banks 1, 2,
5, or 6 to generate clocks for DDR SDRAM interfaces on the side I/O
banks (not using the DQS circuitry).
Altera Corporation 3–15
June 2006 Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
Command & Address Pins
You can use any of the user I/O pins in the top or bottom bank of the
device (I/O banks 3, 4, 7, or 8) for commands and addresses. For DDR
SDRAM, you can also use any of the user I/O pins in the side I/O banks
1, 2, 5, or 6, regardless of whether you use the DQS phase-shift circuitry
or not.
Other Pins (Parity, DM, ECC & QVLD Pins)
You can use any of the DQ pi ns for the parity pins in Stratix and
Stratix GX devices. However, this may mean that you are using the next
larger DQS/DQ mode. For example, if you need a parity bit for each byte
of data, you are actually going to have nine DQ pins per DQS pin. The
Quartus II software then implements a ×16 mode, with the seven unused
DQ pins available as user I/O pins.
The data mask (DM) pins are only required when writing to
DDR SDRAM and RLDRAM II devices. A low signal on the DM pins
indicates that the write is valid. If the DM signal is high, the memory
masks the DQ si gnals. You can use any of the I/O pins in the same bank
as the DQ pins for the DM signals. Each group of DQS and DQ signals
requires a DM pin. The DDR register, clocked by the –90° shifted clock,
creates the DM signals, similar to DQ output signals.
Some DDR SDRAM devices support error correction coding (ECC),
which is a method of detecting and automatically correcting errors in
data transmission. Connect the DDR ECC pins to a Stratix and Stratix GX
device DQS/DQ gro up. In 72-bit DDR SDRAM, there are eight ECC pins
in addition to the 64 data pins. The memory controller needs extra logic
to encode and decode the ECC data.
QVLD pins are used in RLDRAM II interfacing to indi cate the read data
availability. There is one QVLD pin per RLDRAM II device. A high on
QVLD indicates that the memory is outputting the data requested.
Similar to DQ inputs, t his signal is edge-aligned with the RLDRAM I I
read clocks, QK and Q K#, and is sent half a clock cycle before data starts
coming out of the memory. You can connect QVLD pins to any of the I/O
pins in the same bank as the DQ pins for the QVLD signals.
DQS Phase-Shift Circuitry
Two single phase-shifting reference circuits are located on the top and
bottom of the Stratix and Stratix GX devices. Each circ uit is driven by a
system reference clock that is of the same frequency as the DQS signal.
Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the
device and clock pins CLK[7..4]p feed the phase-shift circuitry on the
3–16 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
DDR Memory Support Over view
bottom of the device. The phase-shift circuitry cannot be fed from other
sourc es such as the LE or the PLL internal output clocks. This phase-shift
circuitry is used for DDR SDRAM and RLDRA M II interface s. For best
performance, turn off the input r e ference clock to the DQS phase-shift
circuitry when reading fr om the DDR SDRAM or RLDRAM II. This is to
avoid any DLL jitter incorrectly shif ting the DQS signal while the FPGA
is capturing data.
1The I/O pins in I/O banks 1, 2, 5, and 6 can interface with the
DDR SDRAM at up to 150 MHz. See AN 342: Interfacing DDR
SDRAM with Stratix & Stratix GX Devices.
A compensated delay element on each DQS pin allows for either a 90° or
a 72° phase shift, which automatically centers input DQS signals with the
data valid window of their corresponding DQ data signals. The DQS
signals drive a local DQ S bus within t he top and bottom I/O banks. This
DQS bus is an additional resource to the I/O clocks and clocks DQ input
registers with the DQS signal.
fRefer to the DC & Switching Chara c teri stics chapter in volume 1 of the
Stratix Device Handbook for frequency limits regarding the 72 and 90°
phase shift for DQS.
The phase-shifting reference circuit on the top of the device controls the
compensated delay elements for al l 10 DQS pins located at the top of the
device. The phase-shifting reference circuit on the bottom of the device
contro ls the com pensated delay element s for all 10 DQS pins located on
the bottom of the device. All 10 delay elements (DQS signals) on either the
top or bottom of the device shift by the same degree amount. For
example, all 10 DQS pins on the top of the device can be shifted by 90° and
all 10 DQS pins on the bottom of the device can be shifted by 72°. The
refer ence circuit r equires a maximum of 256 system r eference clock cycles
to set the correct phase on the DQS delay elements.
1This applies only to the initia l phase calculation. Altera
recommends that you enable the DLL during the refresh cycle of
the DDR SDRAM. Enabling the DLL for the duration of the
minimum refresh time is sufficient for recalculating the phase
shift.
Figure 3–8 shows the phase-shift reference cir cuit contr ol of each DQS
delay shift on the top of the device. This same cir cuit is duplicate d on the
bottom of the device.
Altera Corporation 3–17
June 2006 Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
Figure 3–8. DQS & DQSn Pins & the DQS Phase-Shift Circuitry Note (1)
Notes to Figure 3–8:
(1) There are up to 10 DQS and DQSn pins available on the top or the bottom of the Stratix and Stratix GX devices.
(2) Clock pins CLK[15..12]p feed the phase-s hift circuit ry on the top of the dev ice and clock pins CLK[7..4]p feed
the phase circuitry on the bottom of the device. The reference clock can also be used in the logic array.
The phase-shift cir cuitry is only used during read transactions where the
DQS pins are acting as input clocks or strobes. The phase-shift circuitry
can shift the incoming DQS signal by 0°, 72°, and 90°. The shifted DQS
signal is then inverted and used as a clock or a str obe at the DQ IOE input
registers.
fRefer to the DC & Switching Chara c teri stics chapter in volume 1 of the
Stratix Device Handbook for frequency limits regarding the 72 and 90°
phase shift for DQS.
The DQS phase-shift circuitry is bypassed when 0° shift is chosen. The
routing delay between the pins and the IOE registers is matched with
high precision for bot h the DQ and DQS signal when the 72° or 90° phase
shift is used. With the 0° phase shift, the skew between DQ and the DQS
signals at the IOE register has been minimized. See Table 3–4 for the
Quartus II software reported number on the DQ and DQS path to the IOE
when the DQS is set to 0° phase shift.
DQS
Pin DQS
Pin DQS
Pin DQS
Pin DQS
Pin DQS
Pin DQS
Pin DQS
Pin DQS
Pin DQS
Pin
Phase Shift
Reference
Circuit
Δ t Δ t Δ t Δ t Δ t Δ t Δ t Δ t Δ t Δ t
DQS Bus
Compensated
Delay Elemen
t
CLK[15..12](2)
Table 3–4. Quartus II Reported Number on the DQS Path to the
IOE Note (1)
Speed Grade DQ2IOE DQS2IOE Unit
-5 0.908 1.008 ns
-6 0.956 1.061 ns
-7 1.098 1.281 ns
3–18 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
DDR Memory Support Over view
To generate the correct phase shift, you must pr ovide a clock signal of the
same frequency as the DQS signal to the DQS phase-shift circuitry. Any
of the CLK[15..12]p clock pins can feed the phase circuitry on the top
of the device (I/O banks 3 and 4) and any of the CLK[7..4]p clock pins
can feed the phase circuitry on the bottom of the device (I/O banks 7
and 8). Both the top and bottom phase-shift circuits need unique clock
pins for the reference clock. You cannot use any internal clock sour ces to
feed the phase-shift circ uitry, but you can route internal clock sources
off-chip and then back into one of the allowable clock input pins.
DLL
The DQS phase-shift circuitry uses a DLL to dynamically measure the
clock period needed by the DQS pin (see Figure 3–9). The DQS
phase-shift circuitry then uses the clock period to generate the corr ect
phase shift. The DLL in the Stratix and Stratix GX devices DQS phase-
shift circuitry ca n operate between 100 and 200 MHz. The phase-shift
circuitry needs a maximum of 256 clock cycles to calculate the correct
phase shift. Data sent during these clock cycles may not be properly
captured.
1You can still use the DQS phase-shift cir cuitry for DDR SDRAM
interfaces that ar e less than 100 MHz. The DQ S signal is shifted
by about 2.5 ns. This shifted DQS signal is not in the center of the
DQ signals, but it is shifted enough to capture the corr ect data in
this low-frequency application.
-8 1.293 1.635 ns
Note to Table 3–4:
(1) These are reported by Quartus II version 4.0. Check the latest version of the
Quartus II software for the most current information.
Table 3–4. Quartus II Reported Number on the DQS Path to the
IOE Note (1)
Speed Grade DQ2IOE DQS2IOE Unit
Altera Corporation 3–19
June 2006 Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
Figure 3–9. Simplified Diagram of the DQS Phase-Shift Circuitry
The input r efer ence clock goes into the DLL to a chain of delay elements.
The phase comparator compares the signal coming out of the end of the
delay element chain to the input reference clock. The phase comparat or
then issues the upndn signal to the up/down counter. This signal
increments or decrements a six-bit delay setting (control signals to DQS
pins) that increases or decreases the delay through the del ay element
chain to bring the input refer ence clock and the signals co ming out of the
delay elem ent chain in phas e.
The shifted DQS signal then goes to the DQS bus to clock the IOE input
registers of the DQ pins. It cannot go into the logic array for other
purposes.
For external memory interfaces that use a bidirectional read strobe like
DDR SDRAM, the DQS signal is low before going to or coming from a
high-impedance state (see Figure 3–1 on page 3–3). The state where DQS
is low just after a high-impedance state is called the preamble and the
state where DQS is low just before it returns to high-impedance state is
called the postamble. Ther e are preamble and postamble specifications
for both read and write operat ions in DDR SDRAM. To ensure data is not
lost when there is noise on the DQS line at the end of a read postamble
time, you need to add soft postamble cir cuitry to disab le the clocks at the
DQ IOE registers.
fFor more information, the DQS Pos tam ble soft logic is described in
AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. The
Altera DDR SDRAM controlle r MegaCore® generates this logic as
open-source code.
Phase
Comparator Up/Down
Counter
Delay Chains
Input
Reference
Clock
Control Signals
to DQS Pins
6
3–20 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
DDR Memory Support Over view
DDR Registers
Each Stratix and Stratix GX IOE contains six registers and one latch. Two
registers and a latch ar e used for input , two registers ar e used for output,
and two registers are used for output enable control. The second output
enable register provides the write pr eamble for the DQS strobe in the
DDR external memory interfaces. This negative-edge output enable
register extends the high-impedance st ate of the pin by a half cl ock cycle
to provide the external me mory's DQS preamble time specification.
Figure 3–10 shows the six registers and the latch in the Stratix and
Stratix GX IOE and Figure 3–11 shows how the second OE register
extends the DQS high impedance state by half a clock cycle during a write
operation.
Altera Corporation 3–21
June 2006 Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
Figure 3–10. Bidirectional DDR I/O Path in Stratix & Stratix GX Devices Note (1)
Notes to Figure 3–10:
(1) All control signals can be inverted at the IOE. No programmable delay chains are shown in this diagram.
(2) The OE signal is active low, but the Quartus II software implements this as active high and autom atically ad ds an
inverter before input to th e AOE register during compilation.
(3) The AOE register generates the enable signal for general-purpose DDR I/O applications.
(4) This select line is to choose whether the OE signal should be delayed by half-a-clock cycle.
(5) The BOE register generates the delayed enable signal for the write strobes and write clock for memory interfaces.
(6) The tristate enable is active low by default. You can design it to be active high. The combinational control path for
the tristate is not shown in this diagram.
(7) You can also have combinational output to the I/O pin; this path is not shown in the diagram.
DQ
DFF
DQ ENA DQ
DFF
Input Register BI
Input Register AI
Latch C
DQ
DFF
DQ
DFF
0
1
Output Register AO
Output Register BO
DQ
DFF
DQ
DFF
OR2
TRI I/O Pin (7)
OE Register BOE
OE Register AOE
Logic Array
dataout_l
dataout_h
outclock
datain_h
datain_l
OE
inclock
neg_reg_out
I
0
(5)
(4)
(6)
(3)
combout
1
(2)
LatchTCHLA
3–22 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
DDR Memory Support Over view
Figure 3–11. Extending the OE Disable by Half-a-Clock Cycle for a Write Transaction Note (1)
Note to Figure 3–11:
(1) The waveform reflects the software simulation result. The OE signal is an active low on the device. However, the
Quartus II software implements this signal as an active high and automatically adds an inverter before the AOE
register D input.
Figures 3–12 and 3–13 summarize t he IOE registers used f or the DQ a nd
DQS signals.
D0
D0 D2
D1
D1 D3
D2 D3
Preamble Postamble
System clock
(outclock for DQS)
OE for DQS
(from logic array)
datain_h
(from logic array)
datain_l
(from logic array)
OE for DQ
(from logic array)
Write Clock
(outclock for DQ,
−90° phase shifted
from System Clock)
DQS
DQ
Delay
by Half
a Clock
Cycle
90˚
Altera Corporation 3–23
June 2006 Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
Figure 3–12. DQ Configuration in Stratix & Stratix GX IOE Note (1)
Notes to Figure 3–12:
(1) You can use the altdq megafunction to generate the DQ signals.
(2) The OE signal is active low, but the Quartus II software implements this as active hi gh and automatically adds an
inverter before the OE register AOE during compilation.
(3) The outclock signal is phase shifted –90° from the system clock.
(4) The shifted DQS signal must be inverted before going to the IOE. The inversion is automatic if you use the altdq
megafunction to generate the DQ signals.
DQ
DFF
DQ
LATCH
ENA DQ
DFF
Input Register AI
Input Register BI
Latch C
DQ
DFF
DQ
DFF
0
1
DQ
DFF
TRI DQ Pin
OE Register AOE
Output Register AO
Output Register BO
Logic Array
Latch
dataout_l
dataout_h
outclock
(3)
datain_h
datain_l
OE
inclock (from DQS bus)
neg_reg_out
I
(4)
(2)
3–24 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
DDR Memory Support Over view
Figure 3–13. DQS Configuration in Stratix & Stratix GX IOE Note (1)
Notes to Figure 3–13:
(1) You can use the altdqs megafunction to generate the DQS signals.
(2) The OE signal is active low, but the Quartus II software implements this as active high and autom atically ad ds an
inverter before OE register AOE during compilation.
(3) The select line can be chosen in the altdqs MegaWizard Plug-In Manager.
(4) The datain_l and datain_h pins are usually connected to VCC and ground, respec tively.
(5) DQS postamble handling is not shown in this diagram. For mor e inf ormation , see AN 342: Interfacing DDR SDRAM
with Stratix & Stratix GX Devices.
(6) This undelayed DQS signal goes to the LE for the soft postamble circuitry.
(7) You must invert this signal before it reaches the DQ IOE. This signal is automatically inverted if you use the altdq
megafunction to generate the DQ signals. Connect this port to the inclock port in the altdq megafunction.
(8) DQS phase-shift circuitry is only available on DQS pins.
DQ
DFF
DQ
DFF
0
1
Output Register B
O
Output Register A
O
OE Register B
OE
OE Register A
OE
DQ
DFF
DQ
DFF
OR2
TRI DQS Pin
(5
)
Logic Array
system clock
datain_l
(4)
datain_h
(3)
OE
(3)
combout
(7)
(2)
0
1
DQS Phase
Shift Circuitry
(8)
undelayed DQS
(6)
Altera Corporation 3–25
June 2006 Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
The Stratix and Stratix GX DDR IOE structure requires you to invert the
incoming DQS signal by using a NOT gate to ensure proper data transfer .
The altdq megafunction automatically adds the inverter when it
generates the DQ signals. As shown in Figure 3–10, the inclock signal's
rising edge clocks the AI register, inclock signal's f a lling edge clocks
the BI register, and latch CI is opened when inclock is one. In a DDR
memory read operation, the last data c oincides with DQS being low. If
you do not invert the DQS pin, you do not get this last data because the
latch does not open until the next rising ed ge of the DQS signal. T he NOT
gate is inserted automatically if the altdg megafunction is used;
otherwise you need to add the NOT gate manually.
Figure 3–14 shows waveforms of the circuit shown in Figure 3–12. The
second set of waveforms in Figure 3–14 shows what happens if the
shifted DQS signal is not inverted; the last data, Dn, does not get latched
into the logic array as DQS goes to tristate after the r e ad postamble time.
The third set of wavef orms in Figure 3–14 shows a pr oper r ead operation
with the DQS signal inverted after the 90° shift; the last data Dn does get
latched. In this case the outputs of register AI and latch CI, which
correspond to dataout_h and dataout_l ports, are now switched
because of the DQS inversion.
3–26 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
DDR Memory Support Over view
Figure 3–14. DQ Captures with Non-Inverted & Inverted Shifted DQS
DQ at the pin
DQS shifted
by 90˚
Output of register A1
(dataout_h)
Output of latch C1
(dataout_l)
Output of register B1
DQS inverted and
shifted by 90˚
Output of register A1
(dataout_h)
Output of latch C1
(dataout_l)
Output of register B1
DQS at the pin
Shifted DQS Signal is Not Inverted
Shifted DQS Signal is Inverted
DQ & DQS Signals
D
n
− 1
D
n
− 2
D
n
− 2
D
n
− 2
D
n
− 1
D
n
D
n
D
n
− 3 D
n
− 1
D
n
− 1 D
n
Altera Corporation 3–27
June 2006 Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
PLL
When using the Stratix and Stratix GX top and bottom I/O banks (I/O
banks 3, 4, 7, or 8) to interface with a DDR memory, at least one PLL with
two output s is needed to ge nerate the sy st em clock and the write clock.
The system clock generates the DQS write signals, comma nd s, and
addresses. The write clock is –90° shifted from the system clock and
generates the DQ signals during writes.
When using the Stratix and Stratix GX side I/O banks 1, 2, 5, or 6 to
interface with DDR SDRAM devices, two PLLs may be needed per I/O
bank for best performance. The side I/O banks do not have dedicated
circuitry, so one PLL captures data from the DDR SDRAM and another
PLL generates the write signals, comm ands, and addresses to the
DDR SDRAM device. Stratix and Stratix GX devices side I/O banks can
support DDR SDRAM up to 1 50 MH z .
fFor more information, see AN 342: Interfacing DDR SDRAM with Stratix
& Stratix GX Devices.
Conclusion Stratix and Stratix GX devices support SDR SDRAM, DDR SDRAM,
RLDRAM II, QDR SDRAM, QDRII SRAM, and ZBT SRAM external
memories. Stratix and Stratix GX devices feature high-speed interfaces
that transfer data between external memory devices at up to
200 MHz/400 Mbps. Phase-shift circuitry in the Stratix and Stratix GX
devices allows you to ensur e that clock edges are pr operly aligned.
3–28 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Conclusion
Altera Corporation Section III–1
Section III. I/O Standards
This section provides information on Stratix® single-ended, voltage-
referenced, and differential I/O standards.
It contains the following chapters:
■Chapter 4, Selectable I/O Standards in Stratix & Stratix GX Devices
■Chapter 5, High-Speed Differential I/O Interfaces in Stratix Devices
Revision History The table below shows the rev ision hist ory for Chapters 4 and 5.
Chapter Date/Version Change s Made Comments
4 June 2006, v3.4 ●Updated “AC Hot Socketing Specification” section.
July 2005, v3.3 ●Updated “Non-Voltage-Referenced Standards” section.
●Minor change to Table 4–6.
January 2005,
v3.2 ●Updated content throughout.
Section III–2 Altera Corporation
I/O Standards Stratix Device Handbook, Volume 2
September 2004,
v3.1 ●Table 4–1 on page 4–1: renamed table, updated tabl e, and
added Note 1.
●Deleted Figure named “1.5-V Differential HSTL Class II
Termination.”
●Updated text describing “SSTL-18 Class I & II - EIA/JEDEC
Preliminary Standard JC42.3” on page 4–11.
●Updated HyperTransport data rates on page 4–17.
●Changed HyperTransport device speed from 800 MHz to
400 MHz on page 4–17.
●Added four rows to Table 4–2 on page 4–18: 1.5-
V HSTL Class I, 1.8-V HSTL Class I, 1.5-V HSTL Class II,
and 1.8-V HSTL Class II.
●Changed title of Table 4–3 on page 4–21.
●Updated Table 4–4 on page 4–22 .
●Updated Figure 4–20 on page 4–29.
●Added description of which clock pins support differential
on-chip termination on page 4–30.
●Updated description of flip-chip packages on page 4–31.
●Changed title of Figure 4–21 on page 4–31.
●Updated milliamps for non-thermally enhanced cavity up
and non-thermally enhanced FineLine BGA packages on
page 4–35.
●Updated equation for FineLine BGA package on
page 4–35.
●Updated milliamps in non-thermally enhanced cavity up and
non-thermally enhanced FineLine BGA packages
onpage 4–37.
April 2004, v3.0 ●Updated notes to Figure 4–18.
●New information added to the “Hot Socketing” section.
●New information added to the “Differential Pad Placement
Guidelines” section.
Nov ember 2003,
v2.2 ●Removed support for series and parallel on-chip
termination.
●Updated Figure 4–22.
October 2003,
v2.1 ●Added the Output Enable Group Logic Option in Quartus II
and Toggle Rate Logic Option in Quartus II sections.
●Updated notes to Table 4–10.
July 2003, v2.0 ●Renamed impedance matching to series termination
throughout Chapter.
●Removed wide range specs for LVTTL and LVCMOS
standards pages 4-3 to 4-5.
●Relaxed restriction of input pins next to differential pins for
flipchip packages (pages 4-20, 4-35, and 4-36).
●Added Drive Strength section on page 4-26.
●Removed text “for 10 ns or less” from AC Hot socketing
specification on page 4-27.
●Added Series Termination column to Table 4-9.
Chapter Date/Version Change s Made Comments
Altera Corporation Section III–3
I/O Standards
5 July 2005, v3.2 Updated Table 5–14 on page 5–58.
September 2004,
v3.1 ●Updated Note 3 in Table 5–10 on page 5–54.
●Updated Table 5–7 on page 5–34 .
●Updated Table 5–8 on page 5–36 .
●Updated description of “RD Differential Termination” on
page 5–46.
●Updated Note 5 in Table 5–14 on page 5–58.
●Updated Notes 2, 5, and 7 in Table 5–11 on page 5–56
through Table 5–14 on page 5–58.
●Added new text about spanning two I/O banks on
page 5–60.
April 2004, v3.0 ●Updated notes for Figure 5–17.
●Updated Table 5–7, 5–8, and 5–10.
●“Data Alignment with Clock” section, last sentence: change
made from 90 degrees to 180 degrees.
Nov ember 2003,
v2.2 ●Removed support for series and parallel on-chip
termination.
●Updated the number of channels per PLL in Tables 5-10
through 5-14.
October 2003,
v2.1 ●Added -8 speed grade de vice inf ormation, including Tables
5-7 and 5-8.
July 2003, v2.0 ●Format changes throughout Chapter.
●Relaxed restriction of input pins next to differential pins for
flip chip packages in Figure 5-1, Note 5.
●Wire bond package performance specification for “high”
speed channels was increased to 624 Mbps from 462 Mbps
throughout Chapter.
●Updated high-speed I/O specification for J=2 in Tables 5-7
and 5-8.
●Updated Tables 5-10 to 5-14 to reflect PLL cross-bank
support for high-speed differential channels at full speed.
●Increased maximum output clock frequency to 462 to 500
MHz on page 5-66.
Chapter Date/Version Change s Made Comments
Section III–4 Altera Corporation
I/O Standards Stratix Device Handbook, Volume 2
Altera Corporation 4–1
June 2006
4. Selectable I/O Standards
in Stratix &
Stratix GX Devices
Introduction The prolif eration of I/O standar ds and the need for higher I/O
performance have made it cri t ical that devices have flexible I/O
capabilities. Stratix® and Stratix GX programm able logic devices (PLDs )
feature programmable I/O pins that support a wide range of industry
I/O standards, permitting increased design flexibility. These I/O
capabilities enable fast time-to-market and high-performance solutions to
meet the demands of comple x system designs. Additionally, Stratix and
Stratix GX devices simplify system board design and make it easy to
connect to microprocessors, periph erals , memories, gate arrays,
programmable logic circuits, and standard logic functions.
This chapter provid es gui de lines for using one or more industry I/O
standards in Stratix and Stratix GX devices, including:
■Stratix and Stratix GX I/O standards
■High-speed interfaces
■Stratix and Stratix GX I/O banks
■Programmable current drive strength
■Hot socketing
■Differential on-chip termination
■I/O pad placement guidelines
■Quartus® II software support
Stratix & Stratix
GX I/O
Standards
Stratix and Stratix GX devices support a wide range of industry I/O
standards as shown in the Stratix Device Family Data Sheet section in the
Stratix Device Handbook, Volume 1 and the Stratix GX Device Family Data
Sheet sec tion of the Stratix GX Device Handbook, Volume 1. Several
applications that use these I/O standards are listed in Table 4–1.
Table 4–1. I/O Standard Applications & Performance (Part 1 of 2) Note (1)
I/O Standard Application Performance
3.3-V LVTTL/LVCMOS General purpose 350 MHz
2.5-V LVTTL/LVCMOS General purpose 350 MHz
1.8-V LVTTL/LVCMOS General purpose 250 MHz
1.5-V LVCMOS General purpose 225 MHz
PCI/CompactPCI PC/embedded systems 66 MHz
S52004-3.4
4–2 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Stratix & Stratix GX I/O Standards
3.3-V Low Voltage Transistor-Transistor Logic (LVTTL) -
EIA/JEDEC Standard JESD8-B
The 3.3-V LVTTL I/O standard is a general-purpose, single-ended
standard used for 3.3-V applications. The LVTTL standard defines the DC
interface parameters for digital circuits operating from a 3.0-V or 3.3-V
power supply and driving or being driven by LVTTL-compatible dev ices.
The LVTTL input standard specifies a wider input voltage range of
–0.5 V ≤VI≤3.8 V. Altera allows an input voltage range of –0.5 V ≤VI≤4.1
V. The L VTTL standard does not require input reference voltages or board
terminations.
Stratix and Stratix GX devi ces su pport both input and output levels for
3.3-V LVTTL operation.
PCI-X 1.0 PC/embedded systems 133 MHz
AGP 1× and 2×Graphics processors 66 to 133 MHz
SSTL-3 Class I and II SDRAM 167 MHz
SSTL-2 Class I and II DDR I SDRAM 160 to 400 Mbps
HSTL Class I QDR SRAM/SRAM/CSIX 150 to 225 MHz
HSTL Class II QDR SRAM/SRAM/CSIX 150 to 250 MHz
Differential HSTL Clock interfaces 150 to 225 MHz
GTL Backplane driver 200 MHz
GTL+ Pentium processor interface 133 to 200 MHz
LVDS Communications 840 Mbps
HyperTransport
technology Motherboard interfaces 800 Mbps
LVPECL PHY interface 840 Mbps
PCML Communications 840 Mbps
Differential SSTL-2 DDR I SDRAM 160 to 400 Mbps
CTT Back planes and bus interf aces 200 MHz
Note to Table 4–1:
(1) These performance values ar e dependent on device speed grade, package type
(flip-chip or wirebond) and location of I/Os (top/bottom or left/right). See the
DC & Switching Characteristics chapter of the Stratix Device Handbook, Volume 1.
Table 4–1. I/O Standard Applications & Performance (Part 2 of 2) Note (1)
I/O Standard Application Performance
Altera Corporation 4–3
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
3.3-V LVCMOS - EIA/JEDEC Standard JESD8-B
The 3.3-V low voltage complementary metal oxide semiconductor
(LVCMOS) I/O standard is a general-purpose, single-ended standard
used for 3.3-V applications. The LVCMOS standard defines the DC
interface parameters for digital circuits operating from a 3.0-V or 3.3-V
power supply and driving or being driven by LVCMOS-compatible
devices.
The LVCMOS standard specifies the same input v oltage r equir ements as
LVTTL (–0.5 V ≤VI≤3.8 V). The output buffer drives to the rail to me et the
minimum high-level output voltage requirements. The 3.3-V I/O
standard does not r equire input refere nce voltages or board terminations.
Stratix and Stratix GX devi ces su pport both input and output levels for
3.3-V LVCMOS operation.
2.5-V LVTTL Normal Voltage Range - EIA/JEDEC Standard
EIA/JESD8-5
The 2.5-V I/O standard is used for 2.5-V LVTTL applications. This
standard de fines the DC interfac e parameters for high-speed, low-
voltage, non-terminated digital circuits driving or being driven by other
2.5-V devices. The input and output voltage ranges are:
■The 2.5-V normal range input standards spe cify an input voltage
range of – 0.3 V ≤VI ≤3.0 V.
■The normal range minimum high-level output voltage requirement
(VOH) is 2.1 V.
Stratix and Stratix GX devi ces su pport both input and output levels for
2.5-V LVTTL operation.
2.5-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard
EIA/JESD8-5
The 2.5-V I/O standard is used for 2.5-V LVCMOS applications. This
standard de fines the DC interfac e parameters for high-speed, low-
voltage, non-terminated digital circuits driving or being driven by other
2.5-V parts. The input and output voltage ranges are:
■The 2.5-V normal range input standards spe cify an input voltage
range of – 0.5 V ≤VI ≤3.0 V.
■The normal range minimum VOH requirement is 2.1 V.
4–4 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Stratix & Stratix GX I/O Standards
Stratix and Stratix GX devi ces su pport both input and output levels for
2.5-V LVCMOS operation.
1.8-V LVTTL Normal Voltage Range - EIA/JEDEC Standard
EIA/JESD8-7
The 1.8-V I/O standard is used for 1.8-V LVTTL applications. This
standard de fines the DC interfac e parameters for high-speed, low-
voltage, non-terminated digital circuits driving or being driven by other
1.8-V parts. The input and output voltage ranges are:
■The 1.8-V normal range input standards spe cify an input voltage
range of – 0.5 V ≤VI ≤2.3 V.
■The normal range minimum VOH requirement is VCCIO –0.45 V.
Stratix and Stratix GX devi ces su pport both input and output levels for
1.8-V LVTTL operation.
1.8-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard
EIA/JESD8-7
The 1.8-V I/O standard is used for 1.8-V LVCMOS applications. This
standard de fines the DC interfac e parameters for high-speed, low-
voltage, non-terminated digital circuits driving or being driven by other
1.8-V devices. The input and output voltage ranges are:
■The 1.8-V normal range input standards spe cify an input voltage
range of – 0.5 V ≤VI ≤2.5 V.
■The normal range minimum VOH requirement is VCCIO –0.45 V.
Stratix and Stratix GX devi ces su pport both input and output levels for
1.8-V LVCMOS operation.
1.5-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard
JESD8-11
The 1.5-V I/O standard is used for 1.5-V applications. This standard
defines the DC interface parameters for high-speed, low-voltage, non-
terminated digita l circuits driving or being driven by other 1.5-V dev ices.
The input and output voltage ranges ar e:
■The 1.5-V normal range input standards spe cify an input voltage
range of – 0.5 V ≤VI ≤2.0 V.
■The normal range minimum VOH requirement is 1.05 V.
Altera Corporation 4–5
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
Stratix and Stratix GX devi ces su pport both input and output levels for
1.5-V LVCMOS operation.
1.5-V HSTL Class I & II - EIA/JEDEC Standard EIA/JESD8-6
The high-speed transceiver logic (HSTL) I/O standard is used for
applications designed to operate in the 0.0- to 1.5-V HSTL logic switching
range. This standar d defines single ended input and output specifications
for all HSTL-compliant digital integrated circuits . The single ended input
standard specifies an input voltage range of – 0.3 V ≤VI ≤VCCIO + 0.3 V.
Stratix and Stratix GX devices support both input and output levels
specified by the 1.5 - V HSTL I/O standard. The input clock is
implemented using dedicated differential input buffers. Two single-
ended output buffers ar e automatically programmed to have opposite
polarity so as to implement a differential output clock. Additionally, the
1.5-V HSTL I/O standard in Stratix and Stratix GX devices is compatible
with the 1.8-V HSTL I/O standard in APEXTM 20KE and APEX 20KC
devices becaus e the input and output vo ltage thr esholds ar e compatible .
See Figures 4–1 and 4–2. Stratix and Stratix GX devices support both
input and output levels with VREF and VTT.
Figure 4–1. HSTL Class I Te rmination
Figure 4–2. HSTL Class II Termination
Output Buffer
Input Buffer
VTT = 0.75 V
50 Ω
Z = 50 Ω
VREF = 0.75 V
Output Buffer
Input Buffer
V
TT
= 0.75 V
50 Ω
V
TT
= 0.75 V
50 ΩZ = 50 Ω
V
REF
= 0.75 V
4–6 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Stratix & Stratix GX I/O Standards
1.5-V Differential HSTL - EIA/JEDEC Standard EIA/JESD8-6
The differential HSTL I/O standard is used for applications designed to
operate in the 0.0- to 1.5-V HSTL lo gic switching range su ch as quad data
rate (QDR) memory clock interfaces. The differenti al HSTL specification
is the same as the single ended HSTL specification. The standard specifies
an input voltage range of – 0.3 V ≤VI ≤VCCIO + 0.3 V. Differe ntial HSTL
does not require an input reference voltage, howeve r, it does require a
50 Ωresistor termination resistor to VTT at the input buffer (see
Figure 4–3). Stratix and Stratix GX devices support both input and output
clock levels for 1.5-V differ ential HSTL. The input clock is implemented
using dedicated differenti al input buffer. Two single-ended output
buffers are automatically programmed to have opposite pola rity so as to
implement a differential output clock.
Figure 4–3. 1.5-V Differential HSTL Class I Termination
3.3-V PCI Local Bus - PCI Special Interest Group PCI Local Bus
Specification Rev. 2.3
The PCI local bus specification is used for applications that interface to
the PCI local bus, which provides a processor-independent data path
between highly integrated peripheral controller components, peripheral
add-in boards, and processor/memory systems. The conventional PCI
specification r evisio n 2.3 define s the PCI hardware environment
including the protocol, electrical, mechanical, and configuration
specifications for the PCI devices and expans ion boar ds . This standar d
requires 3.3-V VCCIO. Stratix and Stratix GX devices are fully compliant
with the 3.3-V PCI Local Bus Specificatio n Revisio n 2.3 and meet
64-bit/66-MHz operating frequency and timing r equirements. The 3.3-V
PCI standard does not require input reference voltages or board
terminations. Stratix and Stratix GX devices support both input and
output levels.
Differential
Transmitter Differential
Receiver
Z0 = 50 Ω
50 Ω50 Ω
Z0 = 50 Ω
VTT = 0.75 V VTT = 0.75 V
Altera Corporation 4–7
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
3.3-V PCI-X 1.0 Local Bus - PCI-SIG PCI-X Local Bus
Specification Revision 1.0a
The PCI-X 1.0 standard is used for applications that interface to the PCI
local bus. The standard enables the design of systems and dev ices that
operate at clock speeds up to 133 MHz, or 1 gigabit per second (Gbps) for
a 64-bit bus. The PCI-X 1.0 protocol enhancements enable devices to
operate much mor e efficiently, providing more usable bandwidth at any
clock frequency. By using the PCI-X 1.0 standard, devices can be designed
to meet PCI-X 1.0 requirements and operate as conventional 33- and
66-MHz PCI devices when installed in those systems. This standard
requires 3.3-V VCCIO. Stratix and Stratix GX devices are fully compliant
with the 3.3-V PCI-X Specification Revisio n 1.0a and meet the 133-MHz
operating frequency and timing requirements. The 3.3-V PCI standard
does not require input refer ence voltages or board terminations. Stratix
and Stratix GX devices support both input and output levels.
3.3-V Compact PCI Bus - PCI SIG PCI Local Bus Specification
Revision 2.3
The Compact PCI local bus specification is used for applications that
interface to the PCI local bus. It follows the PCI Local Bus Specification
Revision 2.3 plus additional requirements in PCI Industrial Computers
Manufacturing Group (PICMG) specifications PICMG 2.0 R3.0,
CompactPCI specification, and the hot swap requir ements in PICMG 2.1
R2.0, CompactPCI Hot Swap Specification. This standar d has similar
electrical requirements as LVTTL and requires 3.3-V VCCIO. Stratix and
Stratix GX devices are compliant with the Compact PCI electrical
requirements. The 3.3-V PCI standard does not requ ire input reference
voltages or boar d term inati ons. St ratix and Stratix GX devices support
both input and output levels.
3.3-V 1× AGP - Intel Corporation Accelerated Graphics Port
Interface Specification 2.0
The AGP interface is a platform bus specification that enables high-
performance graphics by providing a dedicated high-spee d port for the
movement of large blocks of 3-dimensional texture data between a PC's
graphics controller and system memory. The 1× AGP I/O standard is a
single-ended standard used for 3.3-V graphics applications. The 1× AGP
input standard specifies an input voltage range of
–0.5V≤VI≤VCCIO + 0.5 V. The 1× AGP standard does not require input
reference voltages or board terminat ions. Strati x and Stratix GX devices
support both input and output leve ls.
4–8 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Stratix & Stratix GX I/O Standards
3.3-V 2× AGP - Intel Corporation Accelerated Graphics Port
Interface Specification 2.0
The 2× AGP I/O standar d is a voltage-r eferenced, single- ended standard
used for 3.3-V graphics applications. The 2× AGP input standard
specifies an input voltage range of – 0.5V ≤VI ≤VCCIO + 0.5V. The 2× AGP
standard does not require board terminations. Stratix and Stratix GX
devices support both input and output levels.
GTL - EIA/JEDEC Standard EIA/JESD8-3
The GTL I/O standard is a low-level, high-speed back plane standard
used for a wide range of applications from ASICs and processors to
interface logic devices. The GTL standard defines the DC interface
parameters for digital circuits operating from power supplies of 2.5, 3.3,
and 5.0 V. The GTL standard is an open-drain standard, and Stratix and
Stratix GX devices support a 2.5- or 3.3-V VCCIO to meet this standard.
GTL requires a 0.8-V VREF and open-drain outputs with a 1.2-V VTT (see
Figure 4–4). Stratix and Stratix GX devices support both input and output
levels.
Figure 4–4. GTL Termination
GTL+
The GTL+ I/O standard is used for high-speed back plane drivers and
Pentium processor interfaces. The GTL+ standard defines the DC
interface parameters for digital circuits operating from power supplies of
2.5, 3.3, and 5.0 V. The GTL+ standard is an open-drain stand a rd, and
Stratix and Stratix GX devices support a 2.5- or 3.3-V VCCIO to meet this
standard. GTL+ requires a 1.0-V VREF and open-drain outputs with a
1.5-V VTT (see Figure 4–5). Stratix and Stratix GX devices support both
input and output levels.
Output Buffer
Input Buffe
r
VTT = 1.2 V
50 Ω
Z = 50 Ω
VREF = 0.8 V
VTT = 1.2 V
50 Ω
Altera Corporation 4–9
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
Figure 4–5. GTL+ Termination
CTT - EIA/JEDEC Standard JESD8-4
The CTT I/O standard is used for backplanes and memory bus interfaces.
The CTT standard defines the DC interface parameters for digital circuits
operating from 2.5- and 3.3-V power supplies. The CTT standard does not
require special circuitry to interface with LVTTL or LVCMOS devices
when the CTT driver is not terminated. The CTT standard requires a 1.5-V
VREF and a 1.5-V VTT (see Figure 4–6). Stratix and Stratix GX devices
support both input and output leve ls.
Figure 4–6. CTT Termination
SSTL-3 Class I & II - EIA/JEDEC Standard JESD8-8
The SSTL-3 I/O standard is a 3.3-V memo ry bus standard used for
applications such as high-speed SDRAM interfaces. This standard
defines the input and output specifications for devices that operate in the
SSTL-3 logic switching range of 0.0 to 3.3 V. The SSTL-3 standard specifies
an input voltage range of – 0.3 V ≤VI ≤VCCIO + 0.3 V. SSTL-3 requir es a 1.5-
V VREF and a 1.5-V VTT to which the series and termination resistors are
connected (see Figures 4–7 and 4–8). Stratix and Stratix GX devices
support both input and output leve ls.
Output Buffer
Input Buffe
r
V
TT
= 1.5 V
50 Ω
Z = 50 Ω
V
REF
= 1.0 V
V
TT
= 1.5 V
50 Ω
Output Buffer
Input Buffer
V
TT
= 1.5 V
50 Ω
Z = 50 Ω
V
REF
= 1.5 V
4–10 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Stratix & Stratix GX I/O Standards
Figure 4–7. SSTL-3 Class I Termination
Figure 4–8. SSTL-3 Class II Termination
SSTL-2 Class I & II - EIA/JEDEC Standard JESD8-9A
The SSTL-2 I/O standard is a 2.5-V memo ry bus standard used for
applications such as high-speed DDR SDRAM interfaces. This standard
defines the input and output specifications for devices that operate in the
SSTL-2 logic switching range of 0.0 to 2.5 V. This standard improves
operation in conditions where a bus must be isolated from large stubs.
The SSTL-2 standard specifies an input voltage range of
–0.3V≤VI≤VCCIO + 0.3 V. SSTL-2 requires a 1.25-V VREF and a 1.25-V
VTT to which the series and termination resistors are connected (see
Figures 4–9 and 4–10). Stratix and Stratix GX devices support both input
and output levels.
Figure 4–9. SSTL-2 Class I Termination
Output Buffer
Input Buffer
V
TT
= 1.5 V
50 Ω
25 ΩZ = 50 Ω
V
REF
= 1.5 V
Output Buffer
Input Buffer
V
TT
= 1.5 V
50 Ω
V
TT
= 1.5 V
50 Ω
25 ΩZ = 50 Ω
V
REF
= 1.5 V
Output Buffer
Input Buffer
V
TT
= 1.25 V
50 Ω
25 ΩZ = 50 Ω
V
REF
= 1.25 V
Altera Corporation 4–11
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
Figure 4–10. SSTL-2 Class II Termination
SSTL-18 Class I & II - EIA/JEDEC Preliminary Standard JC42.3
The SSTL-18 I/O standard is a 1.8-V memory bus standar d. This standard
is similar to SSTL-2 and defines inpu t a nd output specifications for
devices that are de signed to operate in the SSTL-18 logic switching range
0.0 to 1.8 V. SSTL-18 requires a 0.9-V VREF and a 0.9-V VTT to which the
series and termination resistors ar e connected. See Figures 4–11 and 4–12
for details on SSTL-18 Class I and II termination. Stratix and Stratix GX
devices support both input and output levels.
Figure 4–11. SSTL-18 Class I Termination
Figure 4–12. SSTL-18 Class II Termination
Differential SSTL-2 - EIA/JEDEC Standard JESD8-9A
The differential SSTL-2 I/O standard is a 2.5-V standar d used for
applications such as high-speed DDR SDRAM clo ck interfaces. This
standard supports differential signals in systems using the SSTL-2
Output Buffer
Input Buffer
V
TT
= 1.25 V
50 Ω
V
TT
= 1.25 V
50 Ω
25 ΩZ = 50 Ω
V
REF
= 1.25 V
Output Buffer
Input Buffer
V
TT
= 0.9 V
50 Ω
25 ΩZ = 50 Ω
V
REF
= 0.9 V
Output Buffer
Input Buffer
V
TT
= 0.9 V
50 Ω
V
TT
= 0.9 V
50 Ω
25 ΩZ = 50 Ω
V
REF
= 0.9 V
4–12 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Stratix & Stratix GX I/O Standards
standard and supplements the SSTL-2 standard for differential clocks.
The differential SSTL-2 standard specifies an input voltage range of
–0.3V≤VI≤VCCIO + 0.3 V. The differential SSTL-2 standard does not
requir e an input refer ence volta ge dif ferential . See Figure 4–13 for details
on differential SSTL-2 termination. Stratix and Stratix GX devices support
output clock levels for differential SSTL-2 Class II operation. The output
clock is implemented using two single-ended output buffers which are
programmed to have opposite polarity.
Figure 4–13. Differential SSTL-2 Class II Termination
LVDS - ANSI/TIA/EIA Standard ANSI/TIA/EIA-644
The LVDS I/O standard is a differential hi gh-speed, low-voltage swing,
low-power, general-purpose I/O interface standard requiring a 3.3-V
VCCIO. This standard is us ed in applications re quiring high-bandwidth
data transfer, backplane drivers, and clock distribution. The
ANSI/TIA/EIA-644 standard specifies LVDS transmitters and receivers
capable of operating at recommended maximum data signaling rates of
655 Mbps. However, devices can operate at slower speeds if needed, and
there is a theoretical maximum of 1.923 Gbps. Stratix and Stratix GX
devices meet the ANSI/TIA/EIA-644 standard.
Due to the low voltage swing of the LVDS I/O standard, the
electromagnetic i nterfer ence (EMI) effects ar e much smaller than CMOS,
TTL, and PECL. This low EMI make s LVDS ideal for applications with
low EMI requirements or noise immunity requirements. The LVDS
standard does not require an input r eference voltage, however, it does
requir e a 100 Ωtermination resistor between the two signals at the input
buffer. Stratix and St rat ix GX devices include an optional differential
LVDS termination resistor within the device using differential on-chip
termination. Stratix and Stratix GX devices support both input and
output levels.
Differential
Transmitter Differential
Receiver
Z0 = 50 Ω
50 Ω50 Ω
Z0 = 50 Ω
VTT = 1.25 V VTT = 1.25 V
50 Ω50 Ω
VTT = 1.25 V VTT = 1.25 V
25 Ω
25 Ω
Altera Corporation 4–13
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
fFor more information on the LVDS I/O standard in Strati x devices, see
the High-Speed Differential I/O Interfaces in Stra tix Devices chapter.
LVPECL
The LVPECL I/O standard is a differential interface standar d requiring a
3.3-V VCCIO. The standard is used in applications involving video
graphics, telecommunications, data communications, and clock
distribution. The high-speed, low-voltage swing LVPECL I/O standard
uses a positive power supply and is similar to LVDS, however, LVPECL
has a larger differential output voltage swing than LVDS. The LVPECL
standard does not requi re an input r eference voltage, but it does require
a 100-Ω termination resistor between the two signals at the input buf fer.
See Figures 4–14 and 4–15 for two alternate termination schemes for
LVPECL. Stratix and Stratix GX devices support both input and output
levels.
Figure 4–14. LVPECL DC Coupled Termination
Figure 4–15. LVPECL AC Coupled Termination
Pseudo Current Mode Logic (PCML)
The PCML I/O standard is a differential high-speed, low-power I/O
interface standard used in applic ations such as networking and
telecommunications. The standard requires a 3.3-V VCCIO. The PCML I/O
standard consumes less power than the LVPECL I/O standard. The
Output Buffer Input Buffer
100 Ω
Z = 50 Ω
Z = 50 Ω
Output Buffer
Input Buffe
r
100 Ω
Z = 50 Ω
Z = 50 Ω
VCCIO
VCCIO
R2 R2
R1 R1
10 to 100 nF
10 to 100 nF
4–14 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Stratix & Stratix GX I/O Standards
PCML standard is similar to LVPECL, but PCML has a reduced voltage
swing, which allows for a faster switching time and lower power
consumption. The PCML standard uses open drain outputs and requir es
a differential output signal. See Figure 4–16 for details on PCML
termination. Stratix and Stratix GX devices support both input and
output levels.
Additionally, Stratix GX devices support 1.5-V PCML as described in the
Stratix GX Device Handbook, Volume 1.
Figure 4–16. PCML Termination
HyperTransport Technology - HyperTransport Consortium
The HyperTransport technology I/O standard is a differential high-
speed, high-performance I/O interface standar d r equiring a 2.5-V VCCIO.
This standard is used in applications such as high-performance
networking, telecommunications, embedded systems, consumer
electronics, and Internet connectivity devices. The HyperTransport
technology I/O standard is a point-to-point standard in which each
HyperTransport technology bus consists of two point-to-point
unidirectional links. Each link is 2 to 32 bits. The HyperTransport
technology standard does not require an input reference voltage.
However, it does require a 100-Ωtermination resisto r between the two
signals at the input buffer. See Figure 4–17 for details on HyperTransport
technology termination. Stratix and Stratix GX devices support both
input and output levels.
Figure 4–17. HyperTr ansport Technology Termination
Output Buffer
Input Buffe
r
50 Ω50 ΩZ = 50 Ω
Z = 50 Ω
50 Ω50 Ω
V
TT
Output Buffer Input Buffer
100 Ω
Z = 50 Ω
Z = 50 Ω
Altera Corporation 4–15
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
fSee the Stratix Device Family Data Sheet section in the Stratix Device
Handbook, Volume 1; the Stratix GX Device Family Data Sheet section of the
Stratix GX Device Handbook, Volume 1; and the High-Speed Differential I/O
Interfaces in Stratix Devices chapter for more information on differential
I/O standards.
High-Speed
Interfaces In addition to current industry physical I/O standards, Stratix and
Stratix GX devices also support a variety of emerging high-speed
interfaces. This section pro vides an overview of these interfaces.
OIF-SPI4.2
This implementation agreement is widely used in the industry for
OC-192 and 10-Gbps multi-service system interfaces. SONET and SDH
are synchronous transmission systems over which data packets are
transferred. POS-PHY Level 4 is a standard interface for switches and
routers, and defines the operation between a physical layer (PHY) device
and link layer devices (ATM, Internet pr otocol, and Gigabit Ethernet) for
bandwidths of OC-192 ATM, POS, and 10-Gigabit Ethernet applications.
Some key POS-PHY Level 4 system features include:
■Large sel ection of POS-PHY Level 4-based P HYs
■Independent of data protocol
■Wid e industry support
■LVDS I/O standard to improve signal integrity
■Inband addressing/control
■Out of band flow control
■Scalable ar chite cture
■Over 622-Mbps operation
■Dynamic interface timing mode
POS-PHY Level 4 operates at a wide range of frequencies.
OIF-SFI4.1
This implementation agreement is widely used in the industry for
interfacing physical layer (PHY) to the serializer-deserializer (SERDES)
devices in OC-192 and 10 Gbps multi-service systems. Th e POS - PHY
Level 4 interface standard defines the SFI-4 standard. POS-PHY
Level 4: SFI-4 is a standardized 16-bit ×622-Mbps line-side interface for
10-Gbps applications. Internet LAN and WAN architectures use
telecommunication SONET protocols for data transferring data over the
PHY layer. SFI-4 interfaces between OC-192 SERDES and SONET
framers.
4–16 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
High-Speed Interfaces
10 Gigabit Ethernet Sixteen Bit Interface (XSBI) - IEEE Draft
Standard P802.3ae/D2.0
10 Gigabit Ethernet XSBI is an interface standard for LANs, metr opolitan
area networks (MANs), storage ar ea networks (SA Ns), and WANs.
10 Gigabit Ethernet XSBI provides ma ny fe a tures for efficient, effective
high-speed networking, including easy migration to higher performance
levels without disruption, lower cost of ownership inclu ding acquisition
and support versus other alternatives, familiar management tools and
common skills, abi lity to support new applications and data protoco ls,
flexibility in network desi gn, a nd multiple vendor sourcing and
interoperability.
Under the ISO Open Systems Interconnection (OSI) model, Ethernet is a
Layer 2 protocol. 10 Gigabit Et hernet XSBI uses the IEEE 802.3 Ethernet
media access control (MAC ) protocol, Ethernet frame format, and the
minimum/maximum frame size. An Ethernet PHY corresponding to OSI
layer 1 connects the media to the MAC layer that corresponds to OSI
layer 2. The PHY is divided into a physical media dependent (PMD)
element, such as optical transceiv ers, and a physical coding sub-layer
(PCS), which has coding and a serializer/mul tipl exor. This standard
defines two PHY types, including the LAN PHY and the WAN PHY,
which are disti nguis hed by the PCS. The 10 Gigabi t Ethernet XSB I
standard is a full-duplex technology standard that can increase the speed
and distance of Ethernet.
RapidIO Interconnect Specification Revision 1.1
The RapidIO interface is a communications standard used to connect
devices on a circuit boar d and circuit boar ds on a backplane. RapidIO is a
packet-switched interconnect standard designed for embedded systems
such as those used in networking and communications. The RapidIO
interface standard is a high-performance interconnect interface used for
transferring data and control information between microprocessors,
DSPs, system memory, communications and network processors, and
peripheral devices in a system.
RapidIO replaces existing peripheral bus and processor technologies
such as PCI. Some features of RapidIO include multiprocessing support,
an open standard, flexible topologies, higher bandwidth, low latency,
error management support in hardware, small silicon footprint, widely
available process and I/O technologies, and transparency to existing
applications and operating system software. The RapidIO standard
provides 10-Gbps device bandwidth using 8-bit-wide input and output
data ports. RapidIO uses LVDS technology, has the capability to be scaled
to multi-GHz frequencies, and featur es a 10-bit interface.
Altera Corporation 4–17
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
HyperTransport Technology - HyperTransport Consortium
The HyperTransport technology I/O standard is a differential
high-speed, high performance I/O interface standard developed for
communications and network ing chip-to-chip communications.
HyperTransport technology is used in applications such as high-
performance networking, telecommunications, embedded systems,
consumer electronics, and Internet connectivity devices. The
HyperTransport technology I/O standard is a point-to-point (one source
connected to exactly one destination) sta ndard that provides a high-
performance interconnect between integrated circuits in a system, such as
on a motherboard.
Stratix devices support HyperTransport technology at data rates up to
800 Mbps and 32 bits in each dir e ction. HyperTransport technology uses
an enhanced differential signaling technology to improve performance.
HyperTransport technology supports data widths of 2, 4, 8, 16, or 32 bits
in each direction. HyperTrans port tech nology in Stratix and Stratix GX
devices operates at multiple clock speeds up to 400 MHz.
UTOPIA Level 4 – ATM Forum Technical Committee Standard AF-
PHY-0144.001
The UTOPI A Level 4 frame-based interface standard allows device
manufactur ers and network developers to dev elop compone nts that can
operate at data rates up to 10 Gbps. This standard increases interface
speeds using LVDS I/O and advanced silicon technologies for fast data
transfers.
UTOPI A Le vel 4 provides new control techniques and a 32-, 16-, or 8-bit
LVDS bus, a symmetric transmit/receive bus structure for easier
application design and tes tability, nominal data rates of 10 Gbps, in-b and
control of cell delimiters and flow control to minimize pin count, source-
synchronous clocking, and supports variable length pack et sy stems.
UTOPIA Level 4 handles susta ined data rates for OC-192 and supports
ATM cells. UTOPIA Level 4 also supports interconnections a cross
motherboards, daughtercards, and backplane interfaces.
Stratix & Stratix
GX I/O Banks Stratix devices have eight I/O banks in addition to the four enhanced PLL
external clock output banks, as shown in Table 4–2 and Figure 4–18. I/O
banks 3, 4, 7, and 8 support all single-ended I/O standards. I/O banks 1,
2, 5, and 6 support differential HSTL (on input clocks), LVDS, LVPECL,
PCML, and Hyper Transport technology, as well as all single-ended I/O
standards except HSTL Class II, GTL, SSTL-18 Cl as s II, PCI/PCI-X 1.0,
and 1×/2× AGP. The four enhanced PLL external clock output banks
(I/O banks 9, 10, 11, and 12) support clock outputs all single-ended I/O
4–18 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Stratix & Stratix GX I/O Banks
standards in addition to differential SSTL-2 and HSTL (both on the output
clock only). Since Stratix devices support both non-voltage-referenced
and voltage-referenced I/O standards, there are different guidelines
when working with either separately or when working with both.
Table 4–2. I/O Standards Supported in Stratix I/O Banks (Part 1 of 2)
I/O Standard I/O Bank Enhanced PLL Externa l
Clock Output Banks
123456789101112
3.3-V LVTTL/LVCMOS vvvvvvvvvvvv
2.5-V LVTTL/LVCMOS vvvvvvvvvvvv
1.8-V LVTTL/LVCMOS vvvvvvvvvvvv
1.5-V LVCMOS vvvvvvvvvvvv
PCI/PCIX//Compact PCI vv vvvvvv
AGP 1×vv vvvvvv
AGP 2×vv vvvvvv
SSTL-3 Class I vvvvvvvvvvvv
SSTL-3 Class II vvvvvvvvvvvv
SSTL-2 Class I vvvvvvvvvvvv
SSTL-2 Class II vvvvvvvvvvvv
SSTL-18 Class I vvvvvvvvvvvv
SSTL-18 Class II vv vvvvvv
Differential SSTL-2
(output clocks) vvvv
HSTL Class I vvvvvvvvvvvv
1.5-V HSTL Class I vvvvvvvvvvvv
1.8-V HSTL Class I vvvvvvvvvvvv
HSTL Class II vv vvvvvv
1.5-V HSTL Class II vv vvvvvv
1.8-V HSTL Class II vv vvvvvv
Differential HSTL (input
clocks) vvvvvvvv
Differential HSTL (output
clocks) vvvv
GTL vv vvvvvv
Altera Corporation 4–19
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
GTL+ vvvvvvvvvvvv
CTT vvvvvvvvvvvv
LVDS vv(1) (1) vv(1) (1) (2) (2) (2) (2)
HyperTransport
technology vv(1) (1) vv(1) (1) (2) (2) (2) (2)
LVPECL vv(1) (1) vv(1) (1) (2) (2) (2) (2)
PCML vv(1) (1) vv(1) (1) (2) (2) (2) (2)
Notes to Table 4–2:
(1) This I/O standard is only supported on input clocks in this I/O bank.
(2) This I/O standard is only supported on output clocks in this I/O bank.
Table 4–2. I/O Standards Supported in Stratix I/O Banks (Part 2 of 2)
I/O Standard I/O Bank Enhanced PLL Externa l
Clock Output Banks
123456789101112
4–20 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Stratix & Stratix GX I/O Banks
Figure 4–18. Stratix I/O Banks Notes (1), (2), (3)
Notes to Figure 4–18:
(1) Figure 4–18 is a top view of the silicon die. This corresponds to a top-down view for non-flip-chip packages, but is
a reverse view for flip-chip packages.
(2) Figure 4–18 is a graphic representation only. See the pin list and the Quartus II software for exact locations.
(3) Banks 9 through 12 are enhanced PLL external clock output banks.
(4) If the high-speed differential I/O pins are not use d for high-speed differ ential signaling, they can support all of the
I/O standards except HSTL Class II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and A GP 1×/2×.
(5) For guidelines on placing single-ended I/O pads next to differ ential I/O pads, see “I/O Pad Placement Guidelines”
on page 4–30.
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
I/O Banks 3, 4, 9 & 10 Support
All Single-Ended I/O Standards
I/O Banks 7, 8, 11 & 12 Support
All Single-Ended I/O Standards
I/O Banks 1, 2, 5, and 6 Support All
Single-Ended I/O Standards Except
Differential HSTL Output Clocks,
Differential SSTL-2 Output Clocks,
HSTL Class II, GTL, SSTL-18 Class II,
PCI, PCI-X 1.0, and AGP 1×/2×
DQS9T DQS8T DQS7T DQS6T DQS5T DQS4T DQS3T DQS2T DQS1T DQS0T
PLL5
VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3 VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4
VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7
PLL6
DQS9B DQS8B DQS7B DQS6B DQS5B DQS4B DQS3B DQS2B DQS1B DQS0B
910
VREF1B2 VREF2B2 VREF3B2 VREF4B2VREF1B1 VREF2B1 VREF3B1 VREF4B1
VREF4B6 VREF3B6 VREF2B6 VREF1B6 VREF4B5 VREF3B5 VREF2B5 VREF1B5
Bank 5Bank 6
PLL3
PLL4PLL1
PLL2
Bank 1 Bank 2
Bank 3 Bank 4
11 12Bank 8 Bank 7
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
PLL7 PLL10
PLL8 PLL9
PLL12
PLL11
(5)
(5)
(5)
(5)
Altera Corporation 4–21
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
Tables 4–3 and 4–4 list the I/O standards that Stratix GX enhanced and
fast PLL pins support. Figure 4–19 shows the I/O standar ds that each
Stratix GX I/O bank supports.
Table 4–3. I/O Standards Supported in Stratix & Stratix GX Enhanced PLL Pins
I/O Standard Input Output
INCLK FBIN PLLENABLE EXTCLK
LVTTL vvvv
LVCMOS vvvv
2.5 V vv v
1.8 V vv v
1.5 V vv v
3.3-V PCI vv v
3.3-V PCI-X 1.0 vv v
LVPECL vv v
3.3-V PCML vv v
LVDS vv v
HyperTranspor t techno logy vv v
Differential HSTL vv
Differential SSTL v
3.3-V GTL vv v
3.3-V GTL+ vv v
1.5-V HSTL Class I vv v
1.5-V HSTL Class II vv v
SSTL-18 Class I vv v
SSTL-18 Class II vv v
SSTL-2 Class I vv v
SSTL-2 Class II vv v
SSTL-3 Class I vv v
SSTL-3 Class II vv v
AGP (1× and 2×)vv v
CTT vv v
4–22 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Stratix & Stratix GX I/O Banks
Table 4–4. I/O Standards Supported in Stratix & Stratix GX Fast PLL Pins
I/O Standard Input
INCLK PLLENABLE
LVTTL vv
LVCMOS vv
2.5 V v
1.8 V v
1.5 V v
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL v
3.3-V PCML v
LVDS v
HyperTransport technology v
Differential HSTL v
Differential SSTL
3.3-V GTL
3.3-V GTL+
1.5V HSTL Class I v
1.5V HSTL Class II
SSTL-18 Class I v
SSTL-18 Class II
SSTL-2 Class I v
SSTL-2 Class II v
SSTL-3 Class I v
SSTL-3 Class II v
AGP (1× and 2×)
CTT v
Altera Corporation 4–23
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
Figure 4–19. Stratix GX I/O Banks
There is some flexibility with the number of I/O standards each Stratix
I/O bank can simultaneously support. The following sec tio ns provide
guidelines for mixing non-voltage-referenced and voltage-referenced
I/O standards in Stratix devices.
I/O Banks 3, 4, 6 & 7 Support:
■ 3.3-, 2.5-, 1.8-V LVTTL
■ 3.3-V PCI, PCI-X 1.0
■ GTL
■ GTL+
■ AGP
■ CTT
■ SSTL-18 Class I and II
■ SSTL-2 Class I and II
■ SSTL-3 Class I and II
■ HSTL Class I and II
Individual
Power Bus
I/O Bank 3
I/O Bank 1
I/O Bank 2
I/O Banks 1 & 2 Support:
■ Differential I/O Standards
- True LVDS
- LVPECL
- 3.3-V PCML
- HyperTransport Technology
■ Single-Ended I/O Standard
- 3.3
-, 2.5
-, 1.8
-V LVTTL
- GTL+
- CTT
- SSTL-18 Class I
- SSTL-2 Class I and II
- SSTL-3 Class I and II
- 1.5
-, 1.8
-V HSTL Class I
I/O Bank 5
I/O Bank 5 Contains Transceiver Block
s
I/O Bank 4
I/O Bank 7 I/O Bank 6
4–24 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Stratix & Stratix GX I/O Banks
Non-Voltage-Referenced Standards
Each Stratix I/O bank has its own VCCIO pins and supports only one
VCCIO, either 1.5, 1.8, 2.5 or 3.3 V. A Strati x I/ O bank can simultaneously
support any number of input signals with different I/O standard
assignments, as shown in Table 4–5.
For output signals, a single I/O bank can only support non-voltage-
referenced output signals driving at the same voltage as VCCIO. A St ratix
I/O bank can only have one V CCIO value, so it can only drive out that one
value for non-voltage r efe r enced signa ls. For exampl e, an I/O bank with
a 2.5-V VCCIO setting can support 2.5-V LVTTL inpu ts and outputs,
HyperTransport technology inputs and outputs, and 3.3-V LVCMOS
inputs (not output or bidirectional pins).
1If the output buffer overdrives the input buffer, you must turn
on the Allow voltage overdrive for LVTTL/LVCMOS option in
the Quartus II software. To see this option, click the Device &
Pin Options button in the Device page of the Settings dialog
box (Assignments menu). Then click the Pin Placement tab in
the Device & Pin Options dialog box.
Voltage-Referenced Standards
To accommodate voltage-refere nced I/O standards, each Stratix I/O
bank supports multiple VREF pins feeding a common VREF bus. The
number of available VREF pins increases as device density increases. If
these pins are not used as VREF pins, they can not be used as generic I/O
pins.
Table 4–5. Acceptable Input Levels for LVTTL/LVCMOS
Bank VCCIO Acceptable Input Levels
3.3 V 2.5 V 1.8 V 1.5 V
3.3 V vv
2.5 V vv
1.8 V v (2) v (2) vv (1)
1.5 V v (2) v (2) vv
Notes to Table 4–5:
(1) Because the input signal will not drive to the rail, the input buffer does not
completely shut off, and the I/O current will be slightly higher than the default
value.
(2) These input values overdrive the input buffer, so the pin leakage current will be
slightly higher than the de fault value.
Altera Corporation 4–25
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
An I/O bank featuring single-ended or differential standards can support
voltage-refe r enced sta ndards as long as all voltage-referenced standards
use the same VREF setting. For example, although one I/O bank can
implement both SSTL-3 and SSTL-2 I/O standar ds, I/O pins using these
standards mu st be in di fferent banks since they requ ire different VREF
values
For voltage-refer enced inputs, the r eceiver compares the input vo ltage to
the voltage reference and does not take into account the VCCIO setting.
Therefore, the VCCIO setting is irrelevant for voltage referenced inputs.
Voltage-referenced bidirectional and output signals must be the same as
the I/O bank’s VCCIO voltage. For example, although you can place an
SSTL-2 input pin in any I/ O bank with a 1.25-V VREF level, you can only
place SSTL-2 output pins in an I/O bank with a 2.5-V VCCIO.
Mixing Voltage Referenced & Non-Voltage Referenced
Standards
Non-voltage referenced and voltage referenced pins can safely be mixed
in a bank by applying each of the rule-s ets indivi duall y. For example, on
I/O bank can support SSTL-3 inputs and 1.8-V LVCMOS inputs and
outputs with a 1.8-V VCCIO and a 1.5-V VREF. Similarly, an I/O bank can
support 1.5-V LVCMOS, 3.3-V LVTTL (inputs, but not outputs), and
HSTL I/O standards with a 1.5-V VCCIO and 0.75-V VREF.
For the voltage-referenced examples, see the “I/O Pad Placement
Guidelines” sect ion. For details on how the Quartus II software supports
I/O standards, see the “Quartus II Software Support”section.
4–26 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Drive Strength
Drive Strength Each I/O standard supported by Stratix and Stratix GX devices drives out
a minimum drive strength. When an I/O is configured as LVTTL or
LVCMOS I/O standards, you can specify the current drive strength, as
summarized in Table 4–7.
Standard Current Drive Strength
Each I/O standard supported by Stratix and Stratix GX devices drives out
a minimum drive strength. Table 4–6 summarizes the minimum driv e
strength of each I/O standard.
When the SSTL-2 Class I and II I/O standards ar e implemented on top or
bottom I/O pins, the drive strength is designed to be higher than the
drive strength of the buffer when implemented on side I/O pins. This
allows the top or bottom I/O pins to support 200-MHz operation with the
standard 35-pF load. At the same time, the current consumption when
using top or bottom I/O pins is higher than the side I/O pins. The high
current strength may not be necessary for certain applications where the
value of the load is le ss than the st andard test load (e.g., DDR interface).
The Quartus II software allows you to r educe the drive strength when the
I/O pins are used for the SSTL-2 Class I or Class II I/O standar d and
being implemented on the top or bottom I/O through the Current
Strength setting. Select the minimum strength for lower drive strength.
Table 4–6. Minimum Current Drive Strength of Each I/O Standard
I/O Standard Current Strength, IOL/IOH (mA)
GTL 40 (1)
GTL+ 34 (1)
SSTL-3 Class I 8
SSTL-3 Class II 16
SSTL-2 Class I 8.1
SSTL-2 Class II 16.4
SSTL-18 Class I 6.7
SSTL-18 Class II 13.4
1.5-V HSTL Class I 8
1.5-V HSTL Class II 16
CTT 8
AGP 1×IOL = 1.5, IOH = –0.5
Note to Table 4–6:
(1) Because this I/O standard uses an open drain buffer, this value refers to IOL.
Altera Corporation 4–27
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
Programmable Current Drive Strength
The Stratix and Stratix GX device I/O pins support various output
current drive settings as shown in Table 4–7. These programmable drive
stre ngth settings help decrease the ef fects of simultaneously switching
outputs (SSO) in conjun ction with reducing sy stem noise. The supported
settings ensure that the dev ice driver meets the IOH and IOL specifications
for the corresponding I/O standard.
These drive-strength set tings are pr ogrammable on a per-pin basis (for
output and bidirectional pins only) using the Quartus II software. To
modify the current str ength of a particular pin, see “Programmable Drive
Strength Settings” on page 4–40.
Hot Socketing Stratix devices support hot socketin g without any external components.
In a hot socketing situation, a device’s output buffers are turned off
during system power-up or power -d own. Stratix and Strat ix GX devices
support any power-up or power-down sequence (VCCIO and VCCINT) to
simplify designs . For mixed-voltage envir onments, you can drive signals
into the device before or during power-up or power-down without
damaging the device. Stratix and Stratix GX devices do not drive out until
the device is configured and has attained proper operating conditions.
Even though you can power up or down the VCCIO and VCCINT power
supplies in any sequence you should not power down any I/O bank(s)
that contains the configuration pins while leaving other I/O banks
powered on. For power up and power down, all supplies (VCCINT and all
VCCIO power planes) must be powered up and down within 100 ms of one
another. This prevents I/O pins from driving out.
Table 4–7. Programmable Drive Strength
I/O Standard IOH / IOL Current Strength Setting (mA)
3.3-V LVTTL 24 (1), 16, 12, 8, 4
3.3-V LVCMOS 24 (2), 12 (1), 8, 4, 2
2.5-V LVTTL/LVCMOS 16 (1), 12, 8, 2
1.8-V LVTTL/LVCMOS 12 (1), 8, 2
1.5-V LVCMOS 8 (1), 4, 2
Notes to Table 4–7:
(1) This is the Quartus II software default current setting.
(2) I/O banks 1, 2, 5, and 6 do not support this setting.
4–28 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
I/O Termination
You can power up or power down the VCCIO and VCCINT pins in any
sequence. The power supply ram p rates can range fr om 100 ns to 100 ms.
During hot socketing, the I/O pin capacitance is less than 15 pF and the
clock pin capacitance is less than 20 pF.
DC Hot Socketing Specification
The hot socketing DC specification is | IIOPIN | < 300 μA.
AC Hot Socketing Specification
The hot socketing AC specification is | IIOPIN | < 8 mA for 10 ns or less.
This specification takes into account the pin capacitance, but not board
trace and external loading capacitance. Additional capacitance for trace,
connector, and loading must be considered separately.
IIOPIN is the current at any user I/O pin on the device. The DC
specification applies when all VCC supplies to the device are stable in the
powered-up or powered-down conditions. For the AC specification, the
peak current duration because of power-up transients is 10 ns or less. For
more information, refer to the Hot-Socketing & Power-Sequencing Feature &
Testing for Altera Devices white paper.
I/O Termination Although single-ended, non-voltage-referenced I/O standard s do not
require termination, Altera recommends using external termination to
improve signal integrity where required.
The following I/O standards do not require termination:
■LVTTL
■LVCMOS
■2.5 V
■1.8 V
■1.5 V
■3.3-V PCI/Compact PCI
■3.3-V PCI-X 1.0
■3.3-V AGP 1×
Voltage-Referenced I/O Standards
Vo ltage-referenced I/ O standa rds requ ire both an in put ref erence
voltage, VREF, and a termination voltage, VTT. Off-chip termination on the
board should be used for series and parallel termination.
Altera Corporation 4–29
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
For more information on termination for voltage-referenced I/O
standards, see the Selectable I/O Standards in Stratix & Stratix GX Devices
chapter in the Stratix Device Handbook, Volume 2; or the Stratix GX De vice
Handbook, Volume 2.
Differential I/O Standards
Differential I/O standard s typically require a termination resistor
between the two signals at the receiver. The termination resistor must
match the differential load impedance of the bus. Stratix and Stratix GX
devices provide an optional differential termination on-chip r esistor
when using LVDS.
See the High-Speed Differential I/O Interfaces in Stratix Devices chapter for
more information on differential I/O standards and their interfaces.
For differential I/O standards, I/O banks support differential
termination when VCCIO equals 3.3 V.
Differential Termination (RD)
Stratix devices support differential on-chip termi na t ion for source-
synchr onou s LVDS signaling. The differential termination resistors are
adjacent to the differential input buffers on the device. This placement
eliminates stub effects, improving the signal integrity of the serial link.
Using diffe rential on-chip termination resis tors also sav es boa rd space.
Figure 4–20 shows the differential termination connections for Stratix and
Stratix GX devices.
Figure 4–20. Differential Termination
Z0
Z0
Stratix LVDS
Receiver Buffer with
Differential On-Chip Termination
RD
Differential
Transmitter
4–30 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
I/O Pad Placement Guidelines
Differential termination for Stratix devices is supported for the left and
right I/O banks. Differential termination for Stratix GX devices is
supported for the left, source-synchronous I/O bank. Some of the clock
input pins are in the top and bottom I/O banks, which do not support
differential termination. Clock pins CLK[1,3,8,10] support di fferential
on-chip termination. Clock pins CLK[0,2,9,1 1], CLK[4-7], and CLK[12-15]
do not support differential on-chip termination.
Transceiver Termination
Stratix GX devices feature built-in on-chip termination within the
transceiver at both the transmit and receive buffers. This termination
improves signal integrity and provides support for the 1.5-V PCML I/O
standard.
I/O Pad
Placement
Guidelines
This section provides pad placement guidelines for the programmable
I/O standards supported by Stratix and Stratix GX devices and includes
essential informati on for designing systems using the devices' selectable
I/O capabilities. These guidelines will reduce noise problems so that
FPGA devices can mai ntain an acceptable noise level on the line from the
VCCIO supply. Since Al tera FPGAs require that a separate VCCIO power
each bank, these noise issues do not have any effect when cr ossing bank
boundaries and these guidelines do not apply. Although pad placement
rules need not be considered between I/O banks, some r u les must be
considered if you ar e using a VREF signal in a PLLOUT bank. Note that the
signals in the PLLOUT banks share the VREF supply with neighboring I/O
banks and, therefore, must adhere to the VREF rules discussed in “VREF
Pad Placement Guidelines”.
Differential Pad Placement Guidelines
To avoid cross coupling and maintain an acceptable noise level on the
VCCIO supply, there ar e r estrictions on the placement of single-ended I/O
pads in relation to differential pads. Use the following guidelines for
placing single-ended pads with respect to differential pads in Stratix
devices. These guidelines apply for LVDS, HyperTransport technology,
LVPECL, and PCML I/O standards. The differential pad placement
guidelines do not apply for differential HSTL and differential SSTL
output clocks since each differential output clock is essentially
implemented using two single-ended output buffers. These rules do not
apply to differ ential HSTL input clocks either even though the dedicated
input buffers are used. Howeve r, both differential HSTL and differential
SSTL output standards must adhere to the single-ended (VREF) pad
placement restrictions discus sed in “VREF Pad Placement Guidelines”.
Altera Corporation 4–31
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
■For flip-chip packages, there are no restrictions for plac em ent o f
single-ended input si gnal s with respect to differential signals (see
Figure 4–21). For wire-bond pac kages, single ended input pads ma y
only be placed four or more pads away from a differential pad.
■Single-ended outputs and bidirectional pads may only be placed five
or more pads away from a differential pad (see Figure 4–21),
regardless of package type.
Figure 4–21. Legal Pin Placement Note (1)
Note to Figure 4–21:
(1) Input pads on a flip-chip packages have no restrictions.
VREF Pad Placement Guidelines
Restrictions on the placement of single-ended voltage-referenced I/O
pads with respect to VREF pads help maintain an acceptable noise level
on the VCCIO supply and to prevent output switching noise fr om shifting
the VREF rail. The following guidelines are for placing single-ended pads
in Stratix devices.
Input Pins
Each VREF pad supports a maximum of 40 input pads with up to 20 on
each side of the VREF pad.
Output Pins
When a voltage referenced input or bidirectional pad does not exist in a
bank, there is no limit to the number of output pads that can be
implemented in that bank. When a voltage referenced input exists, each
VREF pad supports 20 outputs for thermally enhanced FineLine BGA®
and thermally enhanced BGA cavity up packages or 15 outputs for Non-
thermally enhanced cavity up and non-ther mally enhanc ed
FineLine BGA packages.
Differential Pin
Wirebond
Input
Input, Output,
Bidirectional
Input, Output,
Bidirectional
Input
FlipChip
Input
4–32 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
I/O Pad Placement Guidelines
Bidirectional Pins
Bidirectional pads must satisfy input and out put guidelines
simultaneously. If the bidirectional pads ar e all controlled by the same OE
and there are no other outputs or voltage referenced inputs in the bank,
then there is no case wher e there is a voltage referenced input active at the
same time as an output. Therefore, the output limitation does not apply.
However, since the bidirectional pads are linked to the same OE, the
bidirectional pads act as inputs at the same time. Therefore, the input
limitation of 40 input pads (20 on each side of the VREF pad) applies.
If any of the bidirectional pads are controlled by differ ent output enables
(OE) and there are no othe r outputs or voltage referenced inputs in the
bank, then there may be a case where one group of bidirectional pads is
acting as inputs while another group is acting as outputs. In such cases,
apply the formulas shown in Table 4–8.
Consider a thermally enhanced FineLine BGA package with eight
bidirec tiona l pads contr olle d by OE1, eight bidir ecti onal pads contr oll ed
by OE2, and six bidirectio nal pads controlled by OE3. While this totals 22
bidir ectional pa ds, it is safely allowabl e because there would be a
maximum of 16 outputs per VREF pad possible assuming the worst case
where OE1 and OE2 are active and OE3 is inactiv e. This is partic ul arly
relevant in DDR SDRAM applic ations.
When at least one additional voltage referenced input and no other
outputs exist in the same VREF bank, then the bidirectional pad limitation
must simultaneously adhere to the input and output limitations. See the
following equation.
<Total number of bidirectional pads> + <T otal number of input pads> ≤ 40 (20 on
each side of the VREF pad)
Table 4–8. Input-Only Bidirectional Pin Limitation Formulas
Package Type Formula
Thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up <Total number of bidirectional pads> – <Total number of pads from the
smallest group of pads controlled by an OE> ≤ 20 (per VREF pad)
Non-thermally enhanced cavity up and
non-thermally enhanced FineLine BGA <Total number of bidirectional pads> – <Total number of pads from the
smallest group of pads controlled by an OE> ≤ 15 (per VREF pad).
Altera Corporation 4–33
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
The previous equation accounts for the input limitations, but yo u m ust
apply the appropriate equation from Table 4–9 to determine the output
limitations.
When at least one additional output exists but no voltage re ferenced
inputs exist, apply the appr opriate formula from Table 4–10.
When additional voltage refer enced inputs and other outputs exist in the
same VREF bank, then the bidirectional pad limitation must again
simultaneously adhere to the input and output limitations. See the
following equation.
<Total number of bidirectional pads> + <Total number of input pads> ≤40 (20 on
each side of the VREF pad)
Table 4–9. Bidirectional pad Limitation Formulas (Where VREF Inputs Exist)
Package Type Formula
Thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up <Total number of bidirectional pads> ≤ 20 (per VREF pad)
Non-thermally enhanced cavity up and
non-thermally enhanced FineLine BGA <Total number of bidirectional pads> ≤ 15 (per VREF pad)
Table 4–10. Bidirectional Pad Limitation Formulas (Where VREF Outputs Exist)
Package Type Formula
Thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up <Total number of bidirectional pads> + <Total number of additional
output pads> – <Total number of pads from the smallest group of pads
controlled by an OE> ≤ 20 (per VREF pad)
Non-thermally enhanced cavity up and
non-thermally enhanced FineLine BGA <Total number of bidirectional pads> + <Total number of additional
output pads> – <Total number of pads from the smallest group of pads
controlled by an OE> ≤ 15 (per VREF pad)
4–34 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
I/O Pad Placement Guidelines
The previous equation accounts for the input limitations, but yo u m ust
apply the appropriate equation from Table 4–9 to determine the output
limitations.
In addition to the pad placement guidelines, use the following guidelines
when working with VREF standards:
■Each bank can only have a single VCCIO voltage level and a single
VREF voltage level at a given time. Pins of differ ent I/O standards can
share the bank if they have compati ble VCCIO values (see Table 4–12
for more details).
■In all cases listed above, the Quartus II software generates an error
message for illegally placed pads.
Output Enable Group Logic Option in Quartus II
The Quartus II software can check a design to make sure that the pad
placement does not violate the rules mentioned above. When the
softwar e checks the design, if the design contains mor e bidirectiona l pins
than what is allowed, the Quartus II software returns a fitting err or . When
all the bidirectional pins are either input or output but not both (for
example, in a DDR memory interface), you can use the Output Enable
Group Logic option. Turning on this option directs the Quartus II Fitter
to view the specified nodes as an output enable group. This way, the Fitter
does not violate the requirements for the maximum number of pins
driving out of a VREF bank when a voltaged-referenced input pin or
bidir ec tional pin is present.
In a design that implements DDR memory interface w ith dq, dqs and dm
pins utilized, there are two ways to enable the above logic options. You
can enable the logic options through the Assignment Editor or by adding
the following assignments to your proje ct’ s ES F file:
OPTIONS_FOR_INDIVIDUAL_NODES_ONLY
{dq : OUTPUT_ENABLE_GROUP 1;
dqs: OUTPUT_ENABLE_GROUP 1;
Table 4–11. Bidirectional Pad Limitation Formulas (Multiple VREF Inputs & Outputs)
Package Type Formula
Thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up <Total number of bidirectional pads> + <Total number of additional
output pads> ≤ 20 (per VREF pad)
non-thermally enhanced cavity up and
non-thermally enhanced FineLine BGA <Total number of bidirectional pads> + <Total number of additional
output pads> ≤ 15 (per VREF pad)
Altera Corporation 4–35
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
dm : OUTPUT_ENABLE_GROUP 1;
}
As a result, the Quartus II Fitter does not count the bidirectional pin
potential outputs, and the number of VREF bank outputs remains in the
legal range.
Toggle Rate Logic Option in Quartus II
You should specify the pin’s output toggling rate in order to perform a
stricter pad placement ch ec k in the Quartus II software. Specify the
frequency at which a pin toggles in the Quartus II Assignment Editor.
This option is useful for adjusting the pin toggle rate in order to place
them closer to dif ferential pins. The option directs the Quartus II Fitter
toggle-rate checking while allowing you to place a single-ended pin
closer to a differential pin.
DC Guidelines
V ariables affecting the DC current draw include package type and desired
termination methods. This section pr ovide s information on each of these
variables and also shows how to calculate the DC current for pin
placement.
1The Quartus II software automatically takes these variables into
account during compilation.
For any 10 consecutive output pads in an I/O bank, Altera recommends
a maximum current of 200 mA for thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up packages and 164 mA for
non-thermally enhanced cavity up and non-thermally enhanced FineLine
BGA packages. The following equation shows the current density
limitation equation for thermally enhanced FineLine BGA and thermally
enhanced BGA cavity up packages:
The following equation shows the current density lim itation equation for
non-thermally enhanced cavity up and non-thermally en hanced
FineLine BGA packages:
Σ
pin + 9
pin
Ipin < 200 mA
4–36 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
I/O Pad Placement Guidelines
Table 4–12 shows the DC current specification pe r pin for each I/O
standard. I/O standards not shown in the table do not exceed these
current limitations.
fFor more information on Altera device packaging, see the Package
Information for Stratix Devi ces chapter in the Stratix Device Handbook,
Volume 2.
Table 4–12. I/O Standard DC Specification Note (1)
Pin I/O Standard IPIN (mA)
3.3-V VCCIO 2.5-V VCCIO 1.5-V VCCIO
GTL 40 40 -
GTL+ 34 34 -
SSTL-3 Class I 8 - -
SSTL-3 Class II 16 - -
CTT 8 - -
SSTL-2 Class I - 8.1 -
SSTL-2 Class II - 16.4 -
HSTL Class I - - 8
HSTL Class II - - 16
Note to Table 4–12:
(1) The current rating on a VREF pin is less than 10μA.
Σ
pin + 9
pin
Ipin < 164 mA
Altera Corporation 4–37
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
Figure 4–22. Current Draw Limitation Guidelines
Any 10 consecutive I/O pads cannot exceed 200 mA in thermally
enhanced FineLine BGA and thermally enhanced BGA cavity up
packages or 164 mA in non-thermally enhanced cavity up and non-
thermally enhanced FineLine BGA packages.
For example, consider a case where a group of 10 consecutive pads are
configured as follows for a the rmally enhanced FineLine BGA and
thermally enhanced BGA cavity up package:
■Number of SSTL-3 Class I output pads = 3
■Number of GTL+ output pads = 4
■The rest of the surrounding I/O pads in the consecutive group of 10
are unused
In this case, the total current draw for these 10 consecutive I/O pads
would be:
(# of SSTL-3 Class I pads × 8 mA) +
(# of GTL+ output pads × 34 mA) = (3 × 8 mA) + (4 × 34 mA) = 160 mA
In the above example, the total current draw for all 10 consecutive I/O
pads is less than 200 mA.
GND
VCC
I/O Pin Sequence
of an I/O Bank
Any 10 Consecutive I/O Pins,
4–38 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Power Source of Various I/O Standards
Power Source of
Various I/O
Standards
For Stratix and Stratix GX devices, the I/O standards are powered by
different power sources. To determine which source powers the input
buffers, see Table 4–13. All output buffers are power ed by V CCIO.
Quartus II
Software
Support
You specify which programmable I/O standards to use for Stratix and
Stratix GX devices with the Quartus II software. This section describes
Quartus II implementation, placement, and assignment gui delines,
including
■Compiler Settings
■Device & Pin Options
■Assign Pins
■Programmable Driv e Strength Settings
■I/O Banks in the Floorplan View
■Auto Placement & Verification
Compiler Settings
You make Compiler settings in the Compiler Settings dialog box
(Processing menu). Click the Chips & Devices tab to specify the device
family, specific device, package, pin count, and speed grade to use for
your design.
Table 4–13. The Relationships Between Various I/O St andards and the
Power Sources
I/O Standard Power Source
2.5V/3.3V LVTTL VCCIO
PCI/PCI-X 1.0 VCCIO
AGP VCCIO
1.5V/1.8V VCCIO
GTL VCCINT
GTL+ VCCINT
SSTL VCCINT
HSTL VCCINT
CTT VCCINT
LVDS VCCINT
LVPECL VCCINT
PCML VCCINT
HyperTransport VCCINT
Altera Corporation 4–39
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
Device & Pin Options
Click Device & Pin Options in the Compiler Settings dialog box to
access the I/O pin settings. For example, in the Voltage tab you can sele ct
a default I/O standard for all pins for the targeted device. I/O pins that
do not have a specific I/O standard assignment de fault this standard.
Click OK when you are done setting I/O pin options to return to the
Compiler Settings dialog box.
Assign Pins
Click Assign Pins in the Compiler Settings dialog box to view the
device’s pin sett ings and pin assignments (see Figure 4–23). Y ou can view
the pin settings under Available Pins & Existing Assignments. The
listing does not include VREF pins because t h ey are dedicated pins. The
information for each pin includes:
■Number
■Name
■I/O Bank
■I/O Standard
■Type (e.g., row or column I/O and differential or control)
■SignalProbe Source Name
■Enabled (that is, whether SignalProbe routing is enabled or disabled
■Status
Figure 4–23. Assign Pins
4–40 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Quartus II Software Support
When you assign an I/O standard that requir es a refer ence voltage to an
I/O pin, the Quartus II software automatically assigns VREF pins. See t he
Quartus II Help for instructions on how to use an I/O standard for a pin.
Programmable Drive Strength Settings
To make programmable drive strength settings, perform the following
steps:
1. In the Tools menu, choose Assignment Organizer.
2. Choose the Edit specific entity & node settings for: setting, then
select the output or bidir ectional pin to specify the current strength
for.
3. In the Assignment Categories dialog box, select Options for
Individual Nodes Only.
4. Select Click here to add a new assignme nt.
5. In the Assignment dialog box, set the Name field to Current
Strength and set the Setting field to the desired, allowable value.
6. Click Add.
7. Click Apply, then OK.
I/O Banks in the Floorplan View
You can view the arrangement of the device I/O banks in the Floorplan
View (V iew menu) as shown in Figure 4–24. You can assign multiple I/O
standards to the I/O pins in any given I/O bank as long as the VCCIO of
the standards is the same. Pins that belong to the same I/O bank must use
the same VCCIO signal.
Each device I/O pin belongs to a specific, numbered I/O bank. The
Quartus II software color co des the I/O bank to which each I/O pin and
VCCIO pin belong. Turn on the Show I/O Banks option to display the I/O
bank color and the bank numbers for each pin.
Altera Corporation 4–41
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
Figure 4–24. Floorplan View Window
Auto Placement & Verification of Selectable I/O Standards
The Quartus II software automatically verifies the pla cement fo r all I/O
and VREF pins and performs the following actions.
■Automatically places I/O pins of dif ferent VREF standards without
pin assignments in separate I/O banks and enables the VREF pins of
these I/O banks.
■Verifies that voltage-referenced I/O pins r equ iri ng different VREF
levels are not placed in the same bank.
■Reports an err or message if the curr ent limit is exceeded for a Stratix
or Stratix GX power bank, as determined by the equation
documented in “DC Guidelines” on page 4–35.
■Reserves the unused high-speed differential I/O channels and
regular user I/O pins in the high-speed differ ential I/O banks when
any of the high-speed differential I/O channels are bei ng used.
■Automatically assigns VREF pins and I/O pins such that the current
requirements are met and I/O standards ar e placed properly.
4–42 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Conclusion
Conclusion Stratix and Stratix GX devices provide the I/O capabilities to allow you
to work with current and emerging I/O standards and requirements.
Today’ s complex designs de mand increased fle xi b il ity to work with the
wide variety of available I/O standards and to simplify board design.
With Stratix and Stratix GX device features, su ch as hot soc k eting and
differential on-chip termination, you can reduce board design interface
costs and increase your development flexibi li t y.
More
Information For more inform ati on, see the following sources:
■The Stratix Device Family Data Sheet section in the Stratix Device
Handbook, Volume 1
■The Stratix GX Device Family Data Sheet section of the Stratix GX
Device Handbook, Volume 1
■The High-Speed Differential I/O Interfaces in Stra tix Devices chapter
■AN 224: High-Speed Board Layout Guidelines
References For more information, see the following references:
■Stub Series Terminated Logic for 2.5-V (SSTL-2), JESD8-9B,
Electronic Industries Association, December 2000.
■High-Speed Transceiver Logic (HSTL) – A 1.5-V Output Buffer
Supply Voltage Based Interface Standard for Digital Integrated
Circuits, EIA/JESD8-6, Electronic Industries Association, August
1995.
■1.5-V +/- 0.1 V (Normal Range) and 0.9 V – 1.6 V (Wide Range)
Power Supply Voltage and Interface Standard for Non-terminated
Digital Integrated Circuits, JESD8-11, Electronic Industries
Association, October 2000.
■1.8-V +/- 0.15 V (Normal Range) and 1.2 V – 1.95 V (Wide Range)
Power Supply Voltage and Interface Standard for Non-terminated
Digital Integrated Circuits, JESD8-7, Electronic Industries
Association, February 1997.
■Center-Tap-Terminated (CTT) Low-Level, High-Speed Interface
Standard for Digital Integrated Circuits, JESD8-9A, Electronic
Industries Association, November 1993.
■2.5-V +/- 0.2V (Normal Range) and 1.8-V to 2.7V (Wide Range)
Power Supply Voltage and Interface Standard for Non-terminated
Digital Integrated Circuits, JESD8-5, Electronic Industries
Association, October 1995.
■Interface Standard for Nominal 3V/ 3.3-V Supply Digital Integrated
Circuits, JESD8-B, Electr onic Industries Association, September 1999.
■Gunning Transceiver Logic (GTL) Low-Level, High-Speed Interface
Standard for Digital Integrated Circuits, JESD8-3, Electronic
Industries Association, November 1993.
Altera Corporation 4–43
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
■Accelerated Graphics Port Interface Specification 2.0, Intel
Corporation.
■Stub Series T erminated Logic for 1.8-V (SSTL-18), Preliminary JC42.3,
Electronic Industries Association.
■PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group,
December 1998.
■PCI-X Local Bus Speci fication, Revision 1.0a, PCI Special Interest
Group.
■UTOPIA Level 4, AF-PHY-0144.001, ATM Technical Committee.
■POS-PHY Level 4: SPI-4, OIF-SPI4-02.0, Optical Internetworking
Forum.
■POS-PHY Level 4: SFI-4, OIF-SFI4-01.0, Optical Internetworking
Forum.
■Electrical Characteristics of Low Voltage Differential Signaling
(LVDS) Interface Circuits, ANSI/TIA/EIA-644, American National
Standards Institute/Telecommunications Industry/Electronic
Industries Association, October 1995.
4–44 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
References
Altera Corporation 5–1
July 2005
5. High-Speed Differential I/O
Interfaces in Stratix Devices
Introduction To achieve high data transfer rates, Stratix® devices support True-
LVDSTM differ ential I/O interfaces which have dedicated
serializer/deserializer (SERDES) circuitry for each differential I/O pair.
Stratix SERDES circuitry transmits and receives up to 840 megabits per
second (Mbps) per channel. The differential I/O interfaces in Stratix
devices support many high-speed I/O standards, such as LVDS,
LVPECL, PCML, and HyperTransportTM technology. Stratix device high-
speed modules are designed to provide solutions for many leading
protocols such as SPI-4 Phase 2, SFI-4, 10G Ethernet XSBI, RapidIO,
HyperTransport technology, and UTOPIA-4.
The SERDES transmitter is designed to serialize 4-, 7-, 8-, or 10-bit wide
words and transmit them across either a cable or printed circ uit board
(PCB). The SERDES receiver takes the serialized data and reconstructs the
bits into a 4-, 7-, 8-, or 10-bit-wide parallel wor d. The SERDES contains the
necessary high-frequ ency circuitry, multiplexer, demultiplexer, clock,
and data manipulation circuitry. You can use double data rate I/O
(DDRIO) circuitry to transm it or receive differential data in by-one (×1)
or by-two (×2) modes.
1Contact Altera Applications for more information on other B
values that the Stratix devices support and using ×7-mode in the
Quartus®II software. Stratix devices currently only support
B= 1 and B = 7 in ×7 mode.
This chapter describes the high-speed differe nt ial I/O capabilities of
Stratix programmable logic devices (PLDs) and provides guidelines for
their optimal use. You should use this document in conjunction with the
Stratix Device Family Data Sheet section of the Stratix Device Handbook,
Volume 1. Consid eration of the critical issues of controlled impe dance of
traces and connectors, dif ferential routing, termination techniques, and
DC balance gets the best performance from the device. Therefore, an
elementary knowledge of high-speed clock-forwarding techniques is also
helpful.
Stratix I/O Banks Stratix devices contain eight I/ O banks, as shown in Figure 5–1. The two
I/O banks on each side contain circuitry to support high-speed LVDS,
LVPECL, PCML, HSTL Class I an d II, SSTL-2 Class I and II, and
HyperTransport inputs and outputs.
S52005-3.2
5–2 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Stratix I/O Banks
Figure 5–1. Stratix I/O Banks Notes (1), (2), (3)
Notes to Figure 5–1:
(1) Figure 5–1 is a top view of the Stratix silicon die, which corresponds to a top-down view of non-flip- chip packages
and a bottom-up view of flip-chip packages.
(2) Figure 5–1 is a graphic representation only. See the pin list and the Quartus II software for exact locations.
(3) Banks 9 through 12 are enhanced PLL external clock output banks.
(4) If the high-speed differential I/O pins are not use d for high-speed differ ential signaling, they can support all of the
I/O standards except HSTL Class I and II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and AGP 1×/2×.
(5) See “Differential Pad Placement Gu idelines” on page 4–30. You can only place single-ended output/bidirectional
pads five or more pads away from a differ ential pad. Use the Show Pads view in the Quartus II Floorplan Editor to
locate these pads. The Quartus II software gives an error message for illegal output or bidirectional pin placement
next to a high-speed differential I/O pin.
Stratix Differential I/O Standards
Stratix devices provide a multi-protocol interface that allows
communication between a variety of I/O standards, including LVDS,
HyperTransport technology, LVPECL, PCML, HSTL Class I and II, and
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
I/O Banks 3, 4, 9 & 10 Support
All Single-Ended I/O Standards
I/O Banks 7, 8, 11 & 12 Support
All Single-Ended I/O Standards
I/O Banks 1, 2, 5, and 6 Support All
Single-Ended I/O Standards Except
Differential HSTL Output Clocks,
Differential SSTL-2 Output Clocks,
HSTL Class II, GTL, SSTL-18 Class II,
PCI, PCI-X 1.0, and AGP 1×/2×
DQS9T DQS8T DQS7T DQS6T DQS5T DQS4T DQS3T DQS2T DQS1T DQS0T
PLL5
VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3 VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4
VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7
PLL6
DQS9B DQS8B DQS7B DQS6B DQS5B DQS4B DQS3B DQS2B DQS1B DQS0B
910
VREF1B2 VREF2B2 VREF3B2 VREF4B2VREF1B1 VREF2B1 VREF3B1 VREF4B1
VREF4B6 VREF3B6 VREF2B6 VREF1B6 VREF4B5 VREF3B5 VREF2B5 VREF1B5
Bank 5Bank 6
PLL3
PLL4PLL1
PLL2
Bank 1 Bank 2
Bank 3 Bank 4
11 12Bank 8 Bank 7
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
LVDS, LVPECL, 3.3-V PCML,
and HyperTransport I/O Block
and Regular I/O Pins (4)
PLL7 PLL10
PLL8 PLL9
PLL12
PLL11
(5)
(5)
(5)
(5)
Altera Corporation 5–3
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
SSTL-2 Class I and II. This feature makes the Stratix device family ideal
for applications that require multiple I/O standards, such as a protocol
translator.
fFor more information on termination for Stratix I/O standards, see
“Differential I/O Termination” on page 5–46.
Figure 5–2 compares the voltage levels between differential I/O
standards supported in all the Stratix devices.
Figure 5–2. Differential I/O Standards Supported by Stratix Devices
PCML
3.3 V
3.0 V
2.1 V
1.4 V
1.0 V
0.9 V
0.3 V
1.7 V
0.0
1.0
2.0
3.0
4.0
LVPECL
LVDS
Hyper-
Transport
Technology
Voltage
(V)
5–4 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Stratix I/O Banks
LVDS
The LVDS I/O standard is a differential hi gh-speed, low-voltage swing,
low-power, general-purpose I/O interface standard requiring a 3.3-V
VCCIO. This standard is us ed in applications re quiring high-bandwidth
data transfer, backplane drivers, and clock distribution. The
ANSI/TIA/EIA-644 standard specifies LVDS transmitters and receivers
capable of operating at recommended maximum data signaling rates of
655 Mbps. However, devices can operate at slower speeds if needed, and
there is a theoretical maximum of 1.923 Gbps. Stratix devices meet the
ANSI/TIA/EIA-644 standard.
Due to the low voltage swing of the LVDS I/O standard, the
electromagnetic i nterfer ence (EMI) effects ar e much smaller than CMOS,
transistor-to-transistor logic (TTL), and PECL. This low EMI makes LVDS
ideal for applicatio ns with low EMI requirements or noise immunity
requirements. The LVDS standard specifies a differential output voltage
range of 0.25 V ×VOD ≤0.45 V. The LVDS standard does not requir e an
input reference voltage, however, it does require a 100-Ω termination
resistor betwee n the two signal s a t the input buffer. Stratix devices
include an optional differential termination resistor within the device. See
Section I, Stratix Device Family Data Sheet of the Stratix Device Handbook,
Volume 1 for the LVDS parameters.
HyperTransport Technology
The HyperTransport technology I/O standard is a differential high-
speed, high-performance I/O int erface standard requiring a 2.5-V
VCCIO. This standard is used in applications such as high-performance
networking, telecommunications, embedded systems, consumer
electronics, and Internet connectivity devices. The HyperTransport
technology I/O standard is a point-to-point standard in which each
HyperTransport technology bus consists of two point-to-point
unidir ecti onal links. Eac h link is 2 to 32 bits. See the Stratix Device Family
Data Sheet section of the Stratix Device Handbook, Volume 1 for the
HyperTransport parameters.
LVPECL
The LVPECL I/O standard is a differential interface standar d requiring a
3.3-V VCCIO. The standard is used in applications involving video
graphics, telecommunications, data communications, and clock
distribution. The high-speed, low-voltage swing LVPECL I/O standard
uses a positive power supply and is similar to LVDS, however, LVPECL
has a larger differential output voltage swi ng than LVDS. See the Stratix
Device Family Data Sheet section of the Stratix Device Handbook, Volume 1
for the LVPECL signaling characteristics.
Altera Corporation 5–5
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
PCML
The PCML I/O standard is a differential high-speed, low-power I/O
interface standard used in applic ations such as networking and
telecommunications. The standard requires a 3.3-V VCCIO. The PCML I/O
standard achieves better performance and consumes less power than the
LVPECL I/O st andard. The PCML standard is similar to LVPECL, but
PCML has a reduced voltage swing, which allows for a faster switching
time and lower power consumption.See the Stratix Device Family Data
Sheet section of the Stratix Device Handbook, Volume 1 for the PCML
signaling characteristics.
Differential HSTL (Class I & II)
The differential HSTL I/O standard is used for applications designed to
operate in the 0.0- to 1.5-V HSTL lo gic switching range su ch as quad data
rate (QDR) memory clock interfaces. The differenti al HSTL specification
is the same as the single ended HSTL specification. The standard specifies
an input voltage range of – 0.3 V ≤VI ≤VCCIO + 0.3 V. The differ ential
HSTL I/O standar d is only available on the input and output clocks. See
the Stratix Device Family Data Sheet secti on of the Strat ix Device Handbook,
Volume 1 for the HSTL signaling characteristics
Differential SSTL-2 (Class I & II)
The differential SSTL-2 I/O standard is a 2.5-V memory bus standar d
used for applications such as high-speed double data rate (DDR) SDRAM
interfaces. This standard defines the input and output specifications for
devices that operate in the SSTL-2 logic switching range of 0.0 to 2.5 V.
This standard improves operation in conditions where a bus must be
isolated fr om larg e stubs. The SSTL-2 s tandard s pecifies an input voltage
range of – 0.3 V ≤VI≤VCCIO + 0.3 V. Stratix devices support both input
and output levels. The differ ential SSTL-2 I/ O standar d is only available
on output clocks. See the Stratix Device Family Data Sheet section of the
Stratix Device Handbook, Volume 1 for the SSTL-2 signaling characteristics.
Stratix Differential I/O Pin Location
The differential I/O pins are located on the I/O banks on the right and
left side of the Stratix device. Table 5–1 shows the location of the Stratix
device high-speed dif fer ential I/O buf fers. When the I/O pins in the I/ O
banks that support differ ential I/O standards are not used for high-speed
5–6 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Principles of SERDES Operation
signaling, you can configure them as any of the other supported I/O
standar ds . DDRIO capabilities are detailed in “SERDES Bypass DDR
Differential Signaling” on page 5–42.
Principles of
SERDES
Operation
Stratix devices support source-synchronous differ ential signaling up to
840 Mbps. Serial data is transmitted and received along with a low-
frequency clock. The PLL can multiply the incoming low-frequency clock
by a factor of 1 to 10. T he SERDES factor J can be 4, 7, 8, or 10 and do es not
have to equal the clock multiplication value. ×1 and ×2 operation is also
possible by bypassing the SE RDES; it is explained in “SERDES Bypass
DDR Differential Interface Review” on page 5–42.
On the receiver side, the high-fr equency clock generated by the PLL shifts
the serial data through a shift register (also called deserializer). The
parallel data is clocked out to the logic array synchronized with the low-
frequency clock. On the transmitter si de, the parallel data fr om the logic
array is first clocked into a parallel-in, serial-out shift register
synchroniz ed with the low-frequency clock and then transmitted out by
the output buffers.
There are four dedicated fast PLLs in EP1S10 to EP1S25 devices, and eight
in EP1S30 to EP1S80 devices. These PLLs ar e used for the SERDES
operations as well as general-purpose use.
The differential channe ls and the high-speed PLL layout in Stratix
devices are described in the “Differential I/O Interface & Fast PLLs”
section on page 5–16.
Table 5–1. I/O Pin Locations on Each Side of Stratix Devices
Device Side (1) Differential Input Differential Output DDRIO
Left vvv
Right vvv
Top v
Bottom v
Note to Table 5–1:
(1) Device sides are relative t o pin A1 in the upper le ft corner of the device (to p view
of the package).
Altera Corporation 5–7
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Stratix Differential I/O Receiver Operation
You can confi gure any of the Stratix differential input channels as a
receiver channel (see Figure 5–3). The differential receiver deserializes
the incoming high-speed data. The input shift register continu ously
clocks the incoming data on the negative t ransition of the high-frequency
clock generated by the PLL clock (×W).
The data in the serial shift register is shifted into a parallel r egister by the
RXLOADEN signal generated by the fast PLL counter circ uitry on the third
falling edge of the high-frequency clock. However, you can select which
falling edge of the high frequency clock loads the data into the parallel
register, using the data-realignment circuit. For more information on the
data-realignment circuit, see “Data Realignment Principles of Operation”
on page 5–25.
In normal mode, the enable signal RXLOADEN loads the parallel data into
the next parallel register on the second rising edge of the low-frequency
clock. You can also load data to the parallel register through the
TXLOADEN signal when using the data-realignment circ uit.
Figure 5–3 shows the block diagram of a single SERDES receiver channel.
Figure 5–4 shows the timing relationship between the data and clocks in
Stratix devices in ×10 mode. W is the low-frequency multiplier and J is
data paralleliz ation division factor.
5–8 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Principles of SERDES Operation
Figure 5–3. Stratix High-Speed Interface Deserialized in ×10 Mode
Notes to Figure 5–3:
(1) W = 1, 2, 4, 7, 8, or 10.
J = 4, 7, 8, or 10.
W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, the device uses DDRIO registers.
(2) This figure does not show additional circuitry for clock or data manipulation.
Figure 5–4. Receiver Timing Diagram
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
Stratix
Logic Array
Receiver Circuit
Serial Shift
Registers Parallel
Registers Parallel
Registers
Fast
PLL (2)
RXIN+
RXIN−
RXCLKIN+
RXCLKIN−
×
W
×
W
/
J (1)
RXLOADEN
TXLOADEN
RXLOADEN
Internal ×1 clock
Internal ×10 clock
Receiver
data input n – 1 n – 0 9 8 7 6 5 4 3 2 1 0
RXLOADEN
Internal ×1 clock
Internal ×10 clock
Receiver
data input n – 1 n – 0 9 8 7 6 5 4 3 2 1 0
Altera Corporation 5–9
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Stratix Differential I/O Transmitter Operation
You can confi gure any of the Stratix differential output channels as a
transmitter channel. The differential transmitter is used to serialize
outbound parallel data.
The logic array se nds parallel data to the SERDES transmitter circuit
when the TXLOADEN signal is asserted. This signal is generated by the
high-speed counter circuitry of the logi c ar ray low-frequenc y clock’s
rising edge. The data is then transferr ed from the parallel r egister into the
serial shift register by the TXLOADEN signal on the third rising edge of the
high-frequency clock.
Figure 5–5 shows the block diagram of a single SERDES transmitter
channel and Figure 5–6 shows the timing relationship between the data
and clocks in Stratix devices in ×10 mode. W is the low-frequency
multiplier and J is the data parallelization division factor.
Figure 5–5. Stratix High-Speed Interface Serialized in ×10 Mode
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Stratix
Logic Array
Transmitter Circuit
Parallel
Register Serial
Register
Fast
PLL
TXOUT+
TXOUT−
×
W
TXLOADEN
5–10 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Principles of SERDES Operation
Figure 5–6. Transmitter Timing Diagram
Transmitter Clock Output
Different applications and protocols call for various clocking schemes.
Some applications require you to center-align the rising or falling clock
edge with the data. Other applications require a divide version of the
transmitted clock, or the clock and data to be at the same high-speed
frequency. The Stratix device transmitter clock output is versatile and
easily programmed for all such applications.
Stratix dev ices transmit data usin g the source-synchr onous scheme,
where the clock is transmitted along with the serialized data to the
receiving device . Un like APEXTM 20KE and APEX II devices, Stratix
devices do not have a fixed transm itter clock output pin. The Altera®
Quartus II software generates the transmitter clock output by using a fast
clock to drive a transmitter dataout channel. Therefore, you can place
the transmitter clock pair close to the data channels, r educing clock-to -
data skew and incr easing system mar gins. This approach is more flexible,
as any channel can driv e a clock, not just s pec ially designated cl ock pins.
Divided-Down Transmitter Clock Output
You can divide down the high-fr equency clock by 2, 4, 8, or 10, depending
on the system requir ements. The various options allow Stratix devices to
accommodate many different types of pr otocols. The divided-down clock
is generated by an additional transmitting data channel.
TXLOADEN
Internal ×1 clock
Internal ×10 clock
Receiver
data input n – 1 n – 0 9 8 7 6 5 4 3 2 1 0
Altera Corporation 5–11
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Table 5–2 shows the divided-down versio n of the high-frequency clock
and the selected serialization factor J (described in pervious sections). The
Quartus II software automatically generates the data input to the
additional transmitter data channel.
Center-Aligned Transmitter Clock Output
A negative-edge-triggered D flipflop (DFF) register is located between
the serial register of each data channel and its output buffer, as show in
Figure 5–7. The negative-edge-triggered DFF register is used when
center-aligned data is r equir ed. For center alignment, the DFF only shifts
the output from the channel used as the transmitter clock out. The
transmitter data channels bypass the negative-edge DFF. When you use
the DFF register, the data is transmitted at the negative edge of the
multiplied clock. This de lays the transmitted clock output re lative to the
data channels by half the multiplied clock cycle. This is used for
HyperTransport technology, but can also be used for any interface
requiring center alignment.
Table 5–2. Differential Transmitter Output Clock Division
J Data Input Output Clock Divided By (1)
41010 2
40011 4
810101010 2
800110011 4
811000011 8
10 1010101010 2
10 1110000011 10
Note to Table 5–2:
(1) This value is usually referred to as B.
5–12 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Principles of SERDES Operation
Figure 5–7. Stratix Programm able Transmitter Clock
SDR Transmitter Clock Output
You can route the high-f requency clock internally generated by the PLL
out as a transmitter clock output on any of the differential channels. The
high-frequency clock output allows Stratix devices to support
applications that requir e a 1-to-1 relationship between the clock and data.
The path of the high-speed clock is shown in Figure 5–8. A programmable
inverter allows you to drive the signal out on either the negative edge of
the clock or 180º out of phase with the str eaming data.
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Stratix
Logic Array
Transmitter Circuit
Parallel
Register Serial
Register
Fast
PLL
TXOUT+
TXOUT−
×
W
TXLOADEN
Altera Corporation 5–13
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–8. High-Speed 1-to-1 Transmitter Clock Output
Note to Figure 5–8:
(1) This figure does not show additional circuitry for clock or data manipulation.
Using SERDES
to Implement
DDR
Some designs require a 2-to-1 data-to-clock ratio. These systems are
usually based on Rapid I/O, SPI-4 Phase 2 (POS_PHY Level 4), or
HyperTransport interfaces, and support various data rates. Stratix
devices meet this requirement for such applications by providing a
variable clock division factor. The SERDES clock division factor is set to 2
for double data rate (DDR).
An additional differential channel (as de scribed in “Transmitter Clock
Output” on page 5–10) is automatically configured to produce the
transmitter clock output signal with half the frequency of the data.
For example, when a system is required to transmit 6.4 Gbps with a
2-to-1 clock-to-data ratio, program the SERDES with eight high-speed
channels running at 800 Mbps each. When you set the output clock
division factor (2 for this example), the Quartus II software automatica lly
assigns a ninth channel as the transmitter clock output. You can edge- or
center-align the transmitte r clock by selecting the default PLL phase or
selecting the negative-edge transmitter clock output. On the receiver side,
the clock signal is connected to the receiver PLL's cloc k .
The multiplication factor W is also calculated automatically. The data rate
divides by the input clock frequency to calculate the W factor. The
deserialization factor (J) may be 4, 7, 8, or 10.
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Stratix
Logic Array
Transmitter Circuit
Parallel
Register Serial
Register
Fast
PLL (1)
TXOUT+
TXOUT−
×
W
TXLOADEN
Inverter
5–14 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Using SERDES to Implement SDR
Figure 5–9 shows a DDR clock-to-data timing r elationship with the clock
center-aligned with respect to data. Figure 5–10 shows the connection
between the receiver and transmitter circuits.
Figure 5–9. DDR Clock-to-Data Relationship
Figure 5–10. DDR Receiver & Transmitter Circuit Connection
Using SERDES
to Implement
SDR
Stratix devices support systems based on s ingl e data rate (SDR)
operations applications by allowing you to directly transmit out the
multiplied clock (as described in “SDR Transmitter Clock Output” on
page 5–12). These systems are usually based on Utopia-4, SFI-4, or XSBI
interfaces, and support various data rates.
An additional differ ential channel is automatically configured to produce
the transmitter clock output signal and is transmitted along with the data.
For example, when a system is required to transmit 10 Gbps with a 1-to-
1 clock-to-data ratio, program the SERDES with sixteen high-speed
channels running at 624 Mbps each. The Quartus II software
XX B0 A0 B1 A1 B2 A2 B3 A3
inclock
DDR
Serial-to-Parallel
Register Parallel
Register
rx_d[0] Channel
08Parallel-to-Serial
Register
Parallel
Register tx_d[0]
Channel
0
8
Serial-to-Parallel
Register Parallel
Register
rx_d[15] Channel
15 8Parallel-to-Serial
Register
Parallel
Register
Channel
15 txclk_out
8
Parallel-to-Serial
Register
Parallel
Register
8
LVDS PLL
LVDS PLL
txloaden
rxloadena
input clock ×
W
input clock ×
W
txclk_in
100 MHz
800 Mbps
Channel
16 txclk_out
400 MHz
Stratix
Logic
Array
Stratix SERDES DDR TransmitterStratix SERDES DDR Receiver
data rate = 800 Mbps
data rate = 800 Mbps
rxclk
400 MHz
÷2
Altera Corporation 5–15
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
automatically assigns a seventeenth channel as the transmitter clock
output. You can edge- or center-align the transmitter clock output by
selecting the default PLL phase or selecting the 90° phase of the PLL
output. On the receiver side, the clock signal is connected to the receiver
PLL's clock input, and you can assign identical clock-to-data alignment.
The multiplication factor W is calculated automatically. The data rate is
dividing by the input clock frequency to calculate the W factor. The
deserialization factor J may be 4, 7, 8, or 10.
Figure 5–11 shows an SDR clock-to-data timing relationship, with clock
center aligned with respect to data. Figure 5–12 shows the connection
between the receiver and transmitter circuits.
Figure 5–11. SDR Clock-to-Data Relationship
Figure 5–12. SDR Receiver & Transmitter Circuit Connection
XX B0 B1 B2 B3
inclock
SDR
Serial-to-Parallel
Register Parallel
Register
rx_d[0] Channel
08Parallel-to-Serial
Register
Parallel
Register tx_d[0]
Channel
0
8
Serial-to-Parallel
Register Parallel
Register
rx_d[15] Channel
15 8Parallel-to-Serial
Register
Parallel
Register tx_d[15]
Channel
15
txclk_out
Channel
16
8
LVDS PLL LVDS PLL
txloaden
rxloaden input clock ×
W
input clock ×
W
txclk_in
624 MHz
624 MHz
Stratix
Logic
Array
Stratix SERDES SDR TransmitterStratix SERDES SDR Receiver
data rate = 624 Mbps
data rate = 624 Mbps
rxclk
624 MHz
5–16 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Differential I/O Interface & Fast PLLs
Differential I/O
Interface & Fast
PLLs
Stratix devices provide 16 dedicated global clocks, 8 dedicated fast
regional I/O pins, and up to 16 regional clocks (four per device quadrant)
that are fed from the dedicated global clock pins or PLL outputs. The 16
dedicated global clocks are driven either by global clock input pins that
support all I/O standards or from enhanced and fast PLL outputs.
Stratix devices use the fast PLLs to implement clock multiplication and
division to support the SERDES circuitry. The input clock is either
multiplie d by the W fee dback factor and/or divided by the J factor. The
resulting clocks ar e distributed to SERDES, loc al, or global clock lines.
Fast PLLs ar e placed in the center of the left and right sides for EP1S10 to
EP1S25 devices. For EP1S30 to EP1S80 devi ces, fast PLLs ar e placed in the
center of the left and r ight sides, as well as the device corners (see
Figure 5–13). These fast PLLs drive a dedicated clock network to the
SERDES in the r ows above and bel ow or top and bott om of the device as
shown in Figure 5–13.
Altera Corporation 5–17
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–13. Stratix Fast PLL Positions & Clock Naming Convention Note (1)
Notes to Figure 5–13:
(1) Dedicated clock input pins on the right and left sides do not support PCI or PCI-X 1.0.
(2) PLLs 7, 8, 9, and 10 are not available on the EP1S30 device in the 780-pin FineLine BGA® package.
FPLLCLK0 FPLLCLK3
FPLLCLK2
CLK[11..8]
FPLLCLK1
CLK[3..0]
7
1
2
8
10
4
3
9
115
126
CLK[7..4]
CLK[15..12]
PLLs
5–18 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Differential I/O Interface & Fast PLLs
Clock Input & Fast PLL Output Relationship
Table 5–3 summarizes the PLL interface to the input clocks and the enable
signal (ENA). Table 5–4 summarizes the clock networks each fast PLL can
connect to across all Stratix family device s.
Table 5–3. Fast PLL Clock Inputs (Including Feedback Clocks) & Enables Note (1)
Input Pin All Stratix Devices EP1S30 to EP1S80 Devices Only
PLL 1 PLL 2 PLL 3 PLL 4 PLL 7 PLL 8 PLL 9 PLL 10
CLK0 (2) vv (3)
CLK1 v
CLK2 (2) vv (3)
CLK3 v
CLK4
CLK5
CLK6
CLK7
CLK8 vv (3)
CLK9 (2) v
CLK10 vv (3)
CLK11 (2) v
CLK12
CLK13
CLK14
CLK15
ENA vvvvvvvv
FPLL7CLK v
FPLL8CLK v
FPLL9CLK v
FPLL10CLK v
Notes to Table 5–3:
(1) PLLs 5, 6, 11, and 12 are not fast PLLs.
(2) Clock pins CLK0, CLK2, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential on-chip
termination.
(3) Either a FPLLCLK pin or a CLK pin can drive the corner fast PLLs (PLL7, PLL8, PLL9, and PLL10) when used for
general purpose. CLK pins cannot drive these fast PLLs in high-speed differential I/O mode.
Altera Corporation 5–19
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Table 5–4. Fast PLL Relationship with Stratix Clock Networks (Part 1 of 2) Notes (1), (2)
Output Signal All Stratix Devices EP1S30 to EP1S80 Devices Only
PLL 1 PLL 2 PLL 3 PLL 4 PLL 7 PLL 8 PLL 9 PLL 10
GCLK0 v
GCLK1 v
GCLK2 v
GCLK3 v
GCLK4 v
GCLK9 v
GCLK10 v
GCLK11 v
RCLK1 vv v
RCLK2 vv v
RCLK3 vv v
RCLK4 vv v
RCLK9 vv v
RCLK10 vv v
RCLK11 vv v
RCLK12 vv v
DIFFIOCLK1 v
DIFFIOCLK2 v
DIFFIOCLK3 v
DIFFIOCLK4 v
DIFFIOCLK5 v
DIFFIOCLK6 v
DIFFIOCLK7 v
DIFFIOCLK8 v
DIFFIOCLK9 v
DIFFIOCLK10 v
DIFFIOCLK11 v
DIFFIOCLK12 v
DIFFIOCLK13 v
5–20 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Differential I/O Interface & Fast PLLs
Fast PLL Specifications
You can drive the fast PLLs by an external pin or any one of the sectional
clocks [21..0]. You can connect the clock input directly to local or global
clock lines, as shown in Figure 5–14. You cannot use the sectional-cloc k
inputs to the fast PLL’s input multiplexer for the re cei ver PLL. You can
only use the sectional clock inputs in the transmitter only mode or as a
general purpose PLL.
DIFFIOCLK14 v
DIFFIOCLK15 v
DIFFIOCLK16 v
Notes to Table 5–4:
(1) PLLs 5, 6, 11, and 12 are not fast PLLs.
(2) The input clock for PLLs used to clock receiver the rx_inclock port on the altlvds_rx megafunction must be
driven by a dedicated clock pin (CLK[3..0] and CLK[8..11]) or the corner pins that clock the corner PLLs
(FPLL[10..7]CLK).
Table 5–4. Fast PLL Relationship with Stratix Clock Networks (Part 2 of 2) Notes (1), (2)
Output Signal All Stratix Devices EP1S30 to EP1S80 Devices Only
PLL 1 PLL 2 PLL 3 PLL 4 PLL 7 PLL 8 PLL 9 PLL 10
Altera Corporation 5–21
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–14. Fast PLL Block Diagram
Notes to Figure 5–14:
(1) In high-speed differentia l I/O mode, the high-speed PLL clock feeds the SERDES. Stratix devices only support one
rate of data transfer per fast PLL in high-speed differential I/O mode.
(2) Control signal for high-speed differential I/O SERDES.
You can multiply the input clock by a factor of 1 to 16. The multiplied
clock is used for high-speed serialization or deserialization oper ations .
Fast PLL specificatio ns are shown in the Stratix Device Family Data Sheet
section of the Stratix Device Handbook, Volume 1. The voltage controlled
oscillators (VCOs) are designed to op erate within the fr equency range of
300 to 840 MHz, to provide data rates of up to 840 Mbps.
High-Speed Phase Adjust
There are eight phases of the multiplied clock at the PLL output, each
delayed by 45° from the previous clock and synchronized with the
original clock. The three multiplexers (shown in Figure 5–14) select one of
the delayed, m ultiplied clocks . The PL L output d rives t he thr ee co unters
k, v, and l. You can program the three individual post scale counters ( k, v,
and l) independently for division ratio or phase. The selected PLL output
is used for the serialization or deserialization process in SERDES.
Charge
Pump
VCO
÷
l
8
Clock Input Phase
Frequency
Detector
÷
v
÷
k
÷
m
Loop
Filter
VCO Phase Selection
Selectable at each PLL
Output Port
Post-Scale
Counters
Global or
regional clock
Regional clock
Regional clock
DIFFIOCLK2 (1
)
DIFFIOCLK1 (1
)
TXLOADEN (2)
RXLOADEN (2)
Global or
regional clock
rxclkin
5–22 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Differential I/O Interface & Fast PLLs
Counter Circuitry
The multiplied clocks bypass the counter taps k and v to dir ectly feed the
SERDES serial registers. These two taps also feed to the quadrant local
clock network and the dedicated RXLOADENA or TXLOADENA pins, as
shown in Figure 5–15. Both k and v are utilized simultaneously during the
data-realignment procedure. When the design does not use the data
realignment, both TXLOADEN and RXLOADEN pins use a single counter.
Figure 5–15. Fast PLL Connection to Logic Array
The Stratix device fast PLL has another GCLK connection for general-
purpose applications. The third tap l feeds the quadrant local clock as
well as the global clock network. You can use the l counter's multiplexer
for applications requ iring the devi ce to connec t the incoming clock
directly to the local or global clocks. You can program the multiplexer to
connect the RXCLKIN signal directly to the local or global clock lines.
Figure 5–15 shows the connection between the incoming clock, the l tap,
and the local or global clock lines.
The differential clock selection is made per differential bank. Since the
length of the clock tree limits the performance, each fast PLL should drive
only one differ ential bank.
÷
l
8÷
v
÷
k
VCO Phase Selection
Selectable at each PLL
Output Port
Regional clock
×1 CLK2 to logic array
or local clocks
×1 CLK1 to logic array
or local clocks
CLK1 SERDES
Circuitry
CLK2 SERDES
Circuitry
TXLOADEN
RXLOADEN
clkin
PLL Output
Clock
Distribution
Circuitry
Counter Circuitry
Post-Scale
Counters
Altera Corporation 5–23
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Fast PLL SERDES Channel Support
The Quartus II MegaWizard Plug-In Manager only allows you to
implement up to 20 r ece iver or 20 transmitter channels for eac h fast PLL.
These channels operate at up to 840 Mbps. For more information on
implementing more than 20 channels, see “Fast PLLs” on page 5–52. The
receiver and transmitter channels are interleaved such that each I/O bank
on the left and right side of the device has one receiver channel and one
transmitter channel per ro w. Figure 5–16 shows the fast PLL and channel
layout in EP1S10, EP1S20, and EP1S25 devices. Figure 5–17 shows the fast
PLL and channel layout in EP1S30 to EP1S80 devices .
fFor more the number of channe ls in each device, se e Tables 5–10 through
5–14.
Figure 5–16. Fast PLL & Channel Layout in EP1S10, EP1S20 & EP1S25 Devices Note (1)
Notes to Figure 5–16:
(1) Wire-bond packages only support up to 624 Mbps until characterization shows otherwise.
(2) See Tables 5–10 through 5–14 for the exact number of channels each package and device density supports.
(3) There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of
its bank quadrant (e.g., if PLL 2 clocks PLL 1’s channel region), those clocked channels support up to 840 Mbps.
Transmitter
Receiver
Transmitter
Receiver
CLKIN
CLKIN
Transmitter
Receiver
Transmitter
Receiver
CLKIN
CLKIN
Fast
PLL 1
Fast
PLL 2
(3)
Fast
PLL 4
Fast
PLL 3
(3)
Up to 20 Receiver and
Transmitter Channels (2)
Up to 20 Receiver and
Transmitter Channels (2)
Up to 20 Receiver and
Transmitter Channels (2)
Up to 20 Receiver and
Transmitter Channels (2)
5–24 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Differential I/O Interface & Fast PLLs
Figure 5–17. Fast PLL & Channel Layout in EP1S30 to EP1S80 Devices Note (1)
Notes to Figure 5–17:
(1) Wire-bond packages only support up to 624-Mbps until characterization shows otherwise.
(2) See Tables 5–10 through 5–14 for the exact number of channels each package and device density supports.
(3) There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of
its bank quadrant (e.g., if PLL 2 clocks PLL 1’s channel region), those clocked channels support up to 840 Mbps.
Transmitter
Receiver
Transmitter
Receiver
CLKIN
FPLL7CLK
Transmitter
Receiver
Transmitter
Receiver
CLKIN
FPLL10CLK
Transmitter
Receiver
Transmitter
Receiver
FPLL9CLK
CLKIN
Fast
PLL 7
Fast
PLL 1
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
Transmitter
Receiver
Transmitter
Receiver
FPLL8CLK
CLKIN Fast
PLL 2
Fast
PLL 8
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
Up to 20 Receiver and
20 Transmitter
Channels in 20 Rows (2)
(3) (3)
Fast
PLL 10
Fast
PLL 4
Fast
PLL 3
Fast
PLL 9
Altera Corporation 5–25
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Advanced Clear & Enabl e Contro l
There ar e several control signals for clearing and enabling PLLs and their
outputs. You can use these signals to control PL L resynchronization and
to gate PLL output clocks for low-power applications.
The PLLENABLE pin is a dedicated pin that enables and disables Stratix
device enhanced and fast PLLs. When the PLLENABLE pin is low, the
clock output ports are driven by GND and all the PLLs go out of lock.
When the PLLENABLE pin goes high again, the PLLs relock and
resynchronize to the input clocks.
The reset signals are reset/resynchronization inputs for each enhanced
PLL. Stratix devices can drive these inpu t signals from an input pin or
from LEs. When driven high, the PLL counters reset, clearing the PLL
output and placing the PLL out of lock. When driven low again, the PLL
resynchronizes to its input as it relocks.
Receiver Data
Realignment Most systems using serial differential I/O data transmission require a
certain data-realignment circuit. Stratix devices contain embedded data-
realignment circuitry. While normal I/O operation guarantees that data
is captured, it does not guarantee the parallelization boundary, as this
point is randomly determined based on the power-up of both
communicating devices. The data-realignment circuitry corrects for bit
misalignments by shifting, or delaying, data bits.
Data Realignment Principles of Operation
Stratix devices use a re al ignment and clock distri bution circuitry
(described in “Counter Circuitry” on page 5–22) for data realignment.
Set the in ternal rx_data_align node end high to assert the data-
realignment circuitry. When this node is switched fro m a low to a high
state, the realignment cir cuitry is activated and the data is delayed by one
bit. To ensure the rising edge of the rx_data_align node end is latched
into the PLL, the rx_data_align node end should stay high for at least
two low-frequency clock cycles .
An external circuit or an internal custom-made state machine using LEs
can generate the signal to pull the rx_data_align node end to a high
state.
When the data r ealignment c ircuitry is activated, it generates an internal
pulse Sync S1 or Sync S2 that disables one of the two counters used for the
SERDES operation (described in “Counter Cir cuitry” on page 5–22). One
counter is disabled for one high-frequency clock cycl e, delaying the
5–26 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Receiver Data Realignment
RXLOADEN signal and dropping the first incoming bit of the serial input
data stream located in the first serial register of the SERDES circuitry
(shown in Figure 5–3 on page 5–8).
Figure 5–18 shows the function-timing diagram of a Stratix SERDES in
normal ×8 mode, and Figure 5–19 shows the function-timing diagrams of
a Stratix SERDES when data realignment is used.
Figure 5–18. SERDE S Function Timing Diagram in Normal Operation
×8 clock
×1 clock
D7 D0 D1 D2
D2 D2 D2
D3 D4 D5 D6 D7 D0 D1 D2 D7 D0 D1 D2D3 D4 D5 D6
D3 D3 D3
D4 D4 D4
D5 D5 D5
D6 D6 D6
D7 D7 D7
D0 D0 D0
D1
PD7
Serial data
PD6
PD5
PD4
PD3
PD2
PD1
PD0 D1 D1
Altera Corporation 5–27
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–19. SERDE S Function Timing Diagram with Data-Realignment Operation
Generating the TXLOADEN Signal
The TXLOADEN signal controls the transfer of data between the SERDES
circuitry and the logic array when data realignment is used. To prevent
the interruption of the TXLOADEN signal during data r ealignment, both k
and v counter are used.
In normal operation the TXLOADEN signal is generated by the k cou nter.
However, during the data-realignment operation this signal is generated
by either counter. When the k counter is used for realignment, the
×8 clock
×1 clock
D7 D0 D1 D2
D2
D2 D2
D3 D4 D5 D6 D7 D0 D1 D2 D7 D0 D1 D2D3 D4 D5 D6
D3
D3 D3
D4
D4 D4
D5
D5 D5
D6
D6 D6
D7
D7 D7
D0
D0 D0
D1
PD7
Serial data
PD6
PD5
PD4
PD3
PD2
PD1
PD0
D1 D1
5–28 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Receiver Data Realignment
TXLOADEN signal is generated by the v counter, and when the v counter
is used for realignment, the TXLOADEN signal is generated by the k
counter, as shown in Figure 5–20.
Figure 5–20. Realignment Circuit TXLOADEN Signal Control Note (1)
Note to Figure 5–20:
(1) This figure does n ot show additional realignment circuitry.
Realignment Implementation
The realignment signal (SYNC) is used for data realignment and
reframing. An external pin (RX_DATA_ALIGN) or an internal signal
controls the rx_data_align node end. When the rx_data_align
node end is asserted high for at least two low-frequency clock cycles, the
RXLOADEN signal is delayed by one high-fr equency clock period and the
parallel bits shift by one bit. Figure 5–21 shows the timing relationship
between the high-fr equency clock, the RXLOADEN signal, and the parallel
data.
8
÷
v
÷
k
×1 CLK2 to logic array
×1 CLK1 to logic array
CLK1 LVDS
Circuitry
CLK2 LVDS
Circuitry
GCLK/LCLK
TXLOADEN
RXLOADEN
÷
l
PLL Output
Clock
Distribution
Circuitry
Counter Circuitry
Sync S1
Realignment CLK
Sync S2
Realignment CLK
SYNC
Data
Realignment
Circuit
Data
Realignment
Circuit
Altera Corporation 5–29
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–21. Realignment by rx_data_align Node End
A state machine can generate the realignment signal to control the
alignment procedure. Figure 5–22 shows the connection between the
realignment signal and the rx_data_align node end.
Figure 5–22. SYNC Signal Path to Realignment Circuit
To guarantee that the rx_data_align signal generated by a user state
machine is latched correctly by the counters, the user cir cuit must meet
certain requirements.
■The design must include an input synchronizing register to ensure
that data is synchronized to the ×1 clock.
10× clock
1× clock
SYNC
rxloaden
datain
receiver A
receiver B
67890123456789012345678901234
65 7890123456789012345678901234
0123456789 0123456789 1234567890 1234567890
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
Stratix Logic Array
Receiver Circuit
Parallel
Register Register
Array
×
W/J
×
1
TXLOADEN
Hold
Register
SYNC
Realignment
Circuit
SYNC Out
10 Pattern
Detection
State Machine
5–30 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Source-Synchronous Timing Budget
■After the pattern detection state ma chine, use another synchronizing
register to capture the generated SYNC signal and synchronize it to
the ×1 clock.
■Since the skew in the path from the output of this synchronizing
register to the PLL is undefined, the state machine must generate a
pulse that is high for two ×1 clock period s.
■Since the SYNC generator cir cuitry only gene rates a single fast clock
period pulse for each SYNC pulse, you cannot generate additional
SYNC pulses until the comparator signal is r eset low.
■T o guarantee the pattern detection state machine does not incorrectly
generate multiple SYNC pulses to shift a single bit, the state machine
must hold the SYNC signal low for at least three ×1 clock period s
between pulses.
Source-
Synchronous
Timing Budget
This section disc usses the timing budget , waveforms, and specifications
for source-synchronous signaling in Stratix devices. LVDS, LVPECL,
PCML, and HyperTransport I/O standards enable high-speed data
transmission. This high data-transmission rate results in better overall
system performance. To take advantage of fast system performance, you
must understand how to analyze timing for these high-speed signals.
Timing analysis for the differential block is different from traditional
synchronous timing analysis techniques.
Rather than focusing on clock-to-output and setup times, source-
synchronous timing analysis is based on the skew between the data and
the clock signals. High-speed differ en tial data transmission r equir es you
to use timing parameters provided by IC vendors and to consider board
skew, cable skew, and clock jitter. This section defines the source-
synchronous differ ential data orientation timing parameters, and timing
budget definitions for Stratix devices, and explains how to use these
timing parameters to determine a design's maximum performance.
Differential Data Orientation
There is a set relationship between an external clock and the incoming
data. For operation at 840 Mbps and W = 10, the external clock is
multiplied by 10 and phase-aligned by the PLL to coincide with the
sampling window of each data bit. The third falling edge of high-
frequency clock is used to strobe the incoming high-speed data.
Therefore, the first two bits belong to the previous cycle. Figure 5–23
shows the data bit orientation of the ×10 mode as defined in the
Quartus II software.
Altera Corporation 5–31
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–23. Bit Orientation in the Quartus II Software
Differential I/O Bit Position
Data synchronization is necessary for successful data transmission at
high frequencies. Figure 5–24 shows the data bit orientation for a receiver
channel operating in ×8 mode. Similar positioning exists for the most
significant bits (MSBs) and least significant bits (LSBs) after
deserialization, as listed in Table 5–5.
Figure 5–24. Bit Order for One Channel of Differential Data
n-1 n-0 9 8 7 6 5 4 3 2 1 0
10 LVDS Bits
MSB LSB
inclock/outclock
data in
high-frequency clock
inclock/outclock
Data in/
Data out D7 D6 D5 D4 D3 D2 D1 D0
Current CyclePrevious Cycle Next Cycle
Data in/
Data out 10010110
Current CyclePrevious Cycle Next Cycle
Example: Sending the Data 10010110
MSB LSB
MSB LSB
5–32 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Source-Synchronous Timing Budget
Table 5–5 shows the conventions for differential bit naming for
18 differential channels . Howe ver, the MSB and LSB are increased with
the number of channels used in a system.
Timing Definition
The specifications used to define hi gh-s peed timing are described in
Table 5–6.
Table 5–5. LVDS Bit Naming
Receiver Data Channel
Number
Internal 8-Bit Parallel Data
MSB Position LSB Position
170
2158
32316
43124
53932
64740
75548
86356
97164
10 79 72
11 87 80
12 95 88
13 103 96
14 111 104
15 119 112
16 127 120
17 135 128
18 143 136
Table 5–6. High-Speed Timing Specifications & Terminology (Part 1 of 2)
High-Speed Timing Specification Terminology
tCHigh-speed receiver/transmitter input and output clock period.
fHSCLK High-speed receiver/transmitter input and output clock frequency.
tRISE Low-to-high transmission time.
Altera Corporation 5–33
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
tFALL High-to-low transmission time.
Timing unit interval (TUI) The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = tC/w).
fHSDR Maximum LVDS data transfer rate (fHSDR = 1/TUI).
Channel-to-channel skew (TCCS) The timing difference between the fastest and slowest output edges,
including tCO variation and clock sk ew . The cloc k is included in the TCCS
measurement.
Sampling window (SW) The period of time during which the data must be valid in order f or you to
capture it correctly. The setup and hold times determine the ideal strobe
position within the sampling window.
SW = tSW (max) – tSW (min).
Input jitter (peak-to-peak) Peak-to-peak input jitter on high-speed PLLs.
Output jitter (peak-to-peak) Peak-to-peak output jitter on high-speed PLLs.
tDUTY Duty cycle on high-speed transmitter output clock.
tLOCK Lock time for high-speed transmitter and receiver PLLs.
Table 5–6. High-Speed Timing Specifications & Terminology (Part 2 of 2)
High-Speed Timing Specification Terminology
Altera Corporation 5–34
July 2005 Stratix Device Handbook, Volume 2
Source-Synchronous Timing Budget
Tables 5–7 and 5–8 show the high-speed I/O timing for Stratix devices
Table 5–7. High-Speed I/O Specifications for Flip-Chip Packages (Part 1 of 3) Notes (1), (2)
Symbol Conditions -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
fHSCLK (Clock
frequency)
(LVDS, LVPECL,
HyperTransport
technology)
fHSCLK = fHSDR / W
W = 4 to 30 10 210 10 210 10 156 10 115.5 MHz
W = 2 (Serdes
bypass) 50 231 50 231 50 231 50 231 MHz
W = 2 (Serdes used) 150 420 150 420 150 312 150 231 MHz
W = 1 (Serdes
bypass) 100 462 100 462 100 462 100 462 MHz
W = 1 (Serdes used) 300 717 300 717 300 624 300 462 MHz
fHSDR Device
operation
(LVDS, LVPECL,
HyperTransport
technology)
J = 10 300 840 300 840 300 640 300 462 Mbps
J = 8 300 840 300 840 300 640 300 462 Mbps
J = 7 300 840 300 840 300 640 300 462 Mbps
J = 4 300 840 300 840 300 640 300 462 Mbps
J = 2 100 462 100 462 100 640 100 462 Mbps
J = 1 (LVDS and
LVPECL only) 100 462 100 462 100 640 100 462 Mbps
fHSCLK (Clock
frequency)
(PCML)
fHSCLK = fHSDR / W
W = 4 to 30 (Serdes
used) 10 100 10 100 10 77.75 10 77.75 MHz
W = 2 (Serdes
bypass) 50 200 50 200 50 150 50 150 MHz
W = 2 (Serdes used) 150 200 150 200 150 155.5 150 155.5 MHz
W = 1 (Serdes
bypass) 100 250 100 250 100 200 100 200 MHz
W = 1 (Serdes used) 300 400 300 400 300 311 300 311 MHz
Altera Corporation 5–35
July 2005 Stratix Device Handbook, Volume 2
Source-Synchronous Timing Budget
fHSDR Device
operation (PCML) J = 10 300 400 300 400 300 311 300 311 Mbps
J = 8 300 400 300 400 300 311 300 311 Mbps
J = 7 300 400 300 400 300 311 300 311 Mbps
J = 4 300 400 300 400 300 311 300 311 Mbps
J = 2 100 400 100 400 100 300 100 300 Mbps
J = 1 100 250 100 250 100 200 100 200 Mbps
TCCS All 200 200 300 300 ps
SW PCML (J = 4, 7, 8,
10) 750 750 800 800 ps
PCML (J= 2) 900 900 1,200 1,200 ps
PCML (J= 1) 1,500 1,500 1,700 1,700 ps
LVDS and LVPECL
(J=1) 500 500 550 550 ps
LVDS, LVPECL,
HyperTransport
technology (J=2
through 10)
440 440 500 500 ps
Input jitter tolerance
(peak-to-peak) All 250 250 250 250 ps
Output jitter (peak-
to-peak) All 160 160 200 200 ps
Output tRISE LVDS 80 110 120 80 110 120 80 110 120 80 110 120 ps
HyperTransport
technology 110 170 200 110 170 200 120 170 200 120 170 200 ps
LVPECL 90 130 150 90 130 150 100 135 150 100 135 150 ps
PCML 80 110 135 80 110 135 80 110 135 80 110 135 ps
Table 5–7. High-Speed I/O Specifications for Flip-Chip Packages (Part 2 of 3) Notes (1), (2)
Symbol Conditions -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
5–36 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Source-Synchronous Timing Budget
Output tFALL LVDS 80 110 120 80 110 120 80 110 120 80 110 120 ps
HyperTransport
technology 110 170 200 110 170 200 110 170 200 110 170 200 ps
LVPECL 90 130 160 90 130 160 100 135 160 100 135 160 ps
PCML 105 140 175 105 140 175 110 145 175 110 145 175 ps
tDUTY LVDS (J= 2 through
10) 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 %
LVDS (J =1) and
LVPECL, PCML,
HyperTransport
technology
45 50 55 45 50 55 45 50 55 45 50 55 %
tLOCK All 100 100 100 100 μs
Notes to Table 5–7:
(1) When J = 4, 7, 8, and 10, the SERDES block is used.
(2) When J = 2 or J = 1, the SERDES is bypassed.
Table 5–8. High-Speed I/O Specifications for Wire-Bond Packages (Part 1 of 3)
Symbol Conditions -6 Sp eed Grade -7 Speed Grade -8 Speed Grade Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK (Clock frequency)
(LVDS,LVPECL, HyperTransport
technology)
fHSCLK = fHSDR / W
W = 4 to 30 (Serdes used) 10 156 10 115.5 10 115.5 MHz
W = 2 (Serdes bypass) 50 231 50 231 50 231 MHz
W = 2 (Serdes used) 150 312 150 231 150 231 MHz
W = 1 (Serdes bypass) 100 311 100 270 100 270 MHz
W = 1 (Serdes used) 300 624 300 462 300 462 MHz
Table 5–7. High-Speed I/O Specifications for Flip-Chip Packages (Part 3 of 3) Notes (1), (2)
Symbol Conditions -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Altera Corporation 5–37
July 2005 Stratix Device Handbook, Volume 2
Source-Synchronous Timing Budget
fHSDR Device operation,
(LVDS,LVPECL, HyperTransport
technology)
J = 10 300 624 300 462 300 462 Mbps
J = 8 300 624 300 462 300 462 Mbps
J = 7 300 624 300 462 300 462 Mbps
J = 4 300 624 300 462 300 462 Mbps
J = 2 100 462 100 462 100 462 Mbps
J = 1 (LVDS and LVPECL only) 100 311 100 270 100 270 Mbps
fHSCLK (Clock frequency)
(PCML)
fHSCLK = fHSDR / W
W = 4 to 30 (Serdes used) 10 77.75 MHz
W = 2 (Serdes bypass) 50 150 50 77.5 50 77.5 MHz
W = 2 (Serdes used) 150 155.5 MHz
W = 1 (Serdes bypass) 100 200 100 155 100 155 MHz
W = 1 (Serdes used) 300 311 MHz
Device operation, fHSDR
(PCML) J = 10 300 311 Mbps
J = 8 300 311 Mbps
J = 7 300 311 Mbps
J = 4 300 311 Mbps
J = 2 100 300 100 155 100 155 Mbps
J = 1 100 200 100 155 100 155 Mbps
TCCS All 400 400 400 ps
SW PCML (J = 4, 7, 8, 10) only 800 800 800 ps
PCML (J = 2) only 1,200 1,200 1,200 ps
PCML (J = 1) only 1,700 1,700 1,700 ps
LVDS and LVPECL (J = 1) only 550 550 550 ps
LVDS, LVPECL, HyperTransport
technology (J = 2 through 10) only 500 500 500 ps
Table 5–8. High-Speed I/O Specifications for Wire-Bond Packages (Part 2 of 3)
Symbol Conditions -6 Sp eed Grade -7 Speed Grade -8 Speed Grade Unit
Min Typ Max Min Typ Max Min Typ Max
Altera Corporation 5–38
July 2005 Stratix Device Handbook, Volume 2
Source-Synchronous Timing Budget
Input jitter tolerance (peak-to-
peak) All 250 250 250 ps
Output jitter (peak-to-peak) All 200 200 200 ps
Output tRISE LVDS 80 110 120 80 110 120 80 110 120 ps
HyperTransport technology 120 170 200 120 170 200 120 170 200 ps
LVPECL 100 135 150 100 135 150 100 135 150 ps
PCML 80 110 135 80 110 135 80 110 135 ps
Output tFALL LVDS 80 110 120 80 110 120 80 110 120 ps
HyperTransport 110 170 200 110 170 200 110 170 200 ps
LVPECL 100 135 160 100 135 160 100 135 160 ps
PCML 110 145 175 110 145 175 110 145 175 ps
tDUTY LVDS (J =2..10) only 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 %
LVDS (J =1) and LVPECL, PCML,
HyperTransport technology 45 50 55 45 50 55 45 50 55 %
tLOCK All 100 100 100 μs
Table 5–8. High-Speed I/O Specifications for Wire-Bond Packages (Part 3 of 3)
Symbol Conditions -6 Sp eed Grade -7 Speed Grade -8 Speed Grade Unit
Min Typ Max Min Typ Max Min Typ Max
Altera Corporation 5–39
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Input Timing Waveform
Figure 5–25 illustrates the essenti al operati ons and the timing
relationshi p between the clock cycle and the incoming serial data. For a
functional description of the SERDES, see “Principles of SERDES
Operation” on page 5–6.
Figure 5–25. Input Timing Waveform Note (1)
Note to Figure 5–25:
(1) The timing specifications are referenced at a 100-mV differential voltage.
Input Clock
(Differential
Signal)
Input Data
Previous Cycle Current Cycle Next
Cycle
bit 2 bit 3 bit 4 bit 5 bit 6 bit 7bit 0 bit 1
MSB LSB
tsw0 (min)
tsw1 (min)
tsw0 (max)
tsw2 (min)
tsw1 (max)
tsw3 (min)
tsw2 (max)
tsw4 (min)
tsw3 (max)
tsw5 (min)
tsw4 (max)
tsw6 (min)
tsw5 (max)
tsw6 (max)
tsw7 (min)
tsw7 (max)
5–40 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Source-Synchronous Timing Budget
Output Timing
The output timing waveform in Figure 5–26 illustrates the r elationship
between the output clock and the serial output data stream.
Figure 5–26. Output Timing Wavefo rm Note (1)
Note to Figure 5–26:
(1) The timing specifications are referenced at a 250-mV differential voltage.
Receiver Skew Margin
Change in syste m environment, such as temperature, media (cable,
connector, or PCB) loading effect, a receiver's inherent setup and hold,
and internal skew, reduces the sampling window for the receiver. The
timing margin between receiver’s clock input and the data input
sampling window is known as RSKM. Figure 5–27 illustrates the
relationship between the parameter an d the receiver’s sampling window.
Output Clock
(Differential
Signal)
Output Data
Previous Cycle Current Cycle Next
Cycle
bit 2 bit 3 bit 4 bit 5 bit 6 bit 7bit 0 bit 1
MSB LSB
TPPos0 (min)
TPPos1 (min)
TPPos0 (max)
TPPos2 (min)
TPPos1 (max)
TPPos3 (min)
TPPos2 (max)
TPPos4 (min)
TPPos3 (max)
TPPos5 (min)
TPPos4 (max)
TPPos6 (min)
TPPos5 (max)
TPPos6 (max)
TPPos7 (min)
TPPos7 (max)
Altera Corporation 5–41
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–27. Differential High-Speed Timing Diagram & Timing Budget
RSKM
TUI
Time Unit Interval (TUI)
RSKM
TCCS
TPPos (min)
Bit
n
Internal
Clock
Falling Edge
tSW (min)
Bit
n
tSW (max)
Bit
n
TPPos (max)
Bit
n
RSKM
TCCS
TSWBEGIN
TSWEND
Sampling
Window
TCCS
2
Receiver
Input Data
Transmitter
Output Data
Internal
Clock
Synchronization
External
Clock
Receiver
Input Clock
Internal
Clock
External
Input Clock
Timing Budget
Timing Diagram
Clock Placement
Sampling
Window (SW) RSKM
TCCS
TPPos (min)
Bit
n
+ 1
TPPos (max)
Bit
n
+ 1
5–42 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
SERDES Bypass DDR Differential Signaling
Switching Characteristics
Timing specifications for Stratix devices are listed in Tables 5–7 and 5–8.
You can also find Stratix device timing information in the Stratix Device
Family Data Sheet secti o n of th e Stratix Device Handbook, Volume 1.
Timing Ana lysis
Differ ential timing analysis is b ased on skew between dat a and the clock
signals. For static timing analysis, the timing characteristics of the
differential I/O standards are guaranteed by design and depend on the
frequency at which they are operated. Use the values in the Stratix Device
Family Data Sheet secti o n of th e Stratix Device Handbook, Volume 1 to
calculate system timing margins for various I/O protocols. For detailed
descriptions and implementations of these protocols, see the Altera web
site at www.altera.com.
SERDES Bypass
DDR Differential
Signaling
Each Stratix device hi gh-speed dif ferentia l I/O channel can transmit or
receive data in by-two (×2) mode at up to 624 Mbps using PLLs. These
pins do not require dedicated SERDES ci rcuitry and they imple me nt
serialization and deserialization with minim al logic.
SERDES Bypass DDR Differential Interface Review
Stratix devices use dedicated DDR circuitry to implement ×2 dif ferential
signaling. Although SDR circuitry samples data only at the positive edge
of the clock, DDR captures data on both the rising and falling edges for
twice the transfer rate of SDR. Stratix device shift registers, internal global
PLLs, and I/O cells can perform serial-to-parallel conversions on
incoming data and parallel-to-seria l conv ersion on outgoing data.
SERDES Clock Domains
The SERDES bypass differential signaling can use any of the many clock
domains available in Strati x devices. These clock domains fall into four
categories: global, regional, fast regional, and internally generated.
General-purpose PLLs generate the global clock domains. The fast PLLs
can generate additional global clocks domains. Each PLL features two
taps that directly drive two unique global clock networks. A dedicated
clock pin drives each general-purpose PLL. These clock lines are utilized
when designing for speeds up to 420 Mbps. Tables 5–3 and 5–4 on
page 5–19, respectively, show the available clocks in Stratix devices.
Altera Corporation 5–43
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
SERDES Bypass DDR Differential Signaling Receiver Operation
The SERDES bypass differential signaling receiver uses the Stratix device
DDR input circuitry to receiv e high-s peed serial data. The DDR input
circuitry consists of a pair of shift registers used to capture the high-speed
serial data, and a latch.
One register captures the data on the positive edge of the clock (generated
by PLL) and the other register captures the data on the negative edge of
the clock. Because the data captured on the negative edge is delayed by
one-half of the clock cycle, it is latched before it interf aces with the system
logic.
Figure 5–28 shows the DDR timing r elationship between the incoming
serial data and the clock. In this example, the inclock signal is running
at half the speed o f the incoming data. However, other combinations are
also possible. Figure 5–29 shows the DDR input and the other modules
used in a Flexible-LVDS receiver design to interface with the system logic.
Figure 5–28. ×2 Timing Relation between Incoming Serial Data & Clock
clock
datain
neg_reg_out
dataout_l
dataout_h
B0 A0 B1 A1 B2 A2 B3 A3
XX B0 B1 B2
XX B0 B1 B2
XX A0 A1 A2
B3
5–44 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
SERDES Bypass DDR Differential Signaling
Figure 5–29. ×2 Data Rate Receiver Channel with Deserialization Factor of 8
SERDES Bypass DDR Differential Signaling Transmitter
Operation
The ×2 differential signaling transmitter uses the Stratix device DDR
output circuitry to transmit high-speed serial data. The DDR output
circuitry consi sts of a pair of shift registers and a mult iplexer. The shift
registers capture t he parallel data on the clock’s rising edge (generate d by
the PLL), and a multiplexer transmits the data in sync with the clock.
Figure 5–30 shows the DDR timing relation between the parallel data and
the clock. In this example, the inclock signal is running at half the speed
of the data. However , other combinations are possible. Figure 5–31 shows
the DDR output and the other modules used in a ×2 transmitter design t o
interface with the system logic.
PLL
DFF
DFF
Shift
Register
Shift
Register
Stratix
Logic
Array
inclock
datain
Latch
Register
×4
×1
Clock
DDR IOE
D0, D2, D4, D6
D1, D3, D5, D7
Altera Corporation 5–45
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–30. ×2 Timing Relation between Parallel Data & Clock
Figure 5–31. ×2 Data Rate Transmitter Channel with Serialization Factor of 8
High-Speed
Interface Pin
Locations
Stratix high-speed interface pins are lo cated at the edge of the package to
limit the possible mismatch between a pair of high-speed signals. Stratix
devices have eight programmable I/ O banks. Figure 5–32 shows the I/O
pins and their location r elative to the package.
outclock
dataout
datain_l
datain_h
XX
XX
XX
A0 B0 A1 B1 A2 B2 A3
B0 B1 B2 B3
A0 A1 A2 A3
PLL
Stratix
Logic
Array
Shift
Register
Shift
Register
DFF
DFF
DDR IOE
inclock
dataout
D0, D2,
D4, D6
D1, D3,
D5, D7
×4
×1
×1
5–46 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Differential I/O Termin ation
Figure 5–32. Differential I/O Pin Locations
Differential I/O
Termination Stratix devices implement differential on-chip termination to reduce
reflections and maintain signal integrity. On-chip termination also
minimizes the number of external resistors required. This simplifies
board design and places the resistors closer to the pack age, elimina t ing
small stubs that can still lead to reflections.
RD Differential Termination
Stratix devices support differenti al on-chip termination for the LVDS I/O
standard. External termination is required on output pins for PCML
transmitters. HyperTransport, LVPECL, and LVDS receivers require
100 ohm termination at the input pins. Figure 5–33 shows the device with
differential termination for the LVDS I/O standard.
fFor more information on dif fer ential on-chip termination technology, see
the Selectable I/O Standards in Stratix & Stratix GX Devices chapter.
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
V
W
Y
AA
21 20 19 1817 16 15 14 13 9
10
11
12 86
75
4321
Differential I/O Pins
(LVDS, LVPECL,
PCML, HyperTransport
)
Differential I/O Pins
(LVDS, LVPECL,
PCML, HyperTransport)
Regular I/O Pins
Regular I/O Pins
Altera Corporation 5–47
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–33. LVDS Differential On-Chip Termination
HyperTransport & LVPECL Differential Termination
HyperTransport and LVPECL I/O standards ar e terminate d by an
external 100-Ω resistor on the input pin. Figure 5–34 shows the device
with differential termination for the HyperTranspor t or LVPECL I/O
standard.
Figure 5–34. HyperTransport & LVPECL Differential Termination
PCML Differential Termination
The PCML I/O technology is an alternative to the LVDS I/O technology,
and use an external voltage source (VTT), a pair of 100-Ω resistors on the
input side and a pair of 50-Ω resistors on the output side. Figure 5–35
shows the device with differential termination for PCML I/O standard.
R
D
LVDS Transmitter
LVDS Receiver with
On-Chi
p
100
-
Ω Termination
Z0 =
50
Ω
Z0 =
50
Ω
R
D
Differential
Transmitter Differential Receiver
Z
0
= 50 Ω
Z
0
= 50 Ω
5–48 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Differential I/O Termin ation
Figure 5–35. PCML Differential Termination
Differential HSTL Termination
The HSTL Class I and II I/O standar ds require a 0.75-V VREF and a 0.75-
V VTT. Figures 5–36 and 5–37 show the devic e with differential
termination for HSTL Class I and II I/O standard.
Figure 5–36. Differential HSTL Class I Termination
Differential
Transmitter Differential
Receiver
Z
0
= 50 Ω
50 Ω50 Ω50 Ω50 Ω
Z
0
= 50 Ω
VTT
Differential
Transmitter Differential
Receiver
Z0 = 50 Ω
50 Ω50 Ω
Z0 = 50 Ω
VTT = 0.75 V VTT = 0.75 V
Altera Corporation 5–49
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–37. Differential HSTL Class II Termination
Differential SSTL-2 Termination
The SSTL-2 Class I and II I/O standards require a 1.25-V VREF and a
1.25-V VTT. Figures 5–37 and 5–38 show the devic e with differential
termination for SSTL-2 Class I and II I/O standard.
Figure 5–38. Differential SSTL-2 Class I Termination
Differential
Transmitter Differential
Receiver
Z0 = 50 Ω
50 Ω50 Ω
Z0 = 50 Ω
VTT = 0.75 V VTT = 0.75 V
50 Ω50 Ω
VTT = 0.75 V VTT = 0.75 V
Differential
Transmitter Differential
Receiver
Z
0
= 50 Ω
50 Ω50 Ω
Z
0
= 50 Ω
V
TT
= 1.25 V V
TT
= 1.25 V
25 Ω
25 Ω
5–50 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Board Design Consideration
Figure 5–39. Differential SSTL-2 Class II Termination
Board Design
Consideration This section is a brief explanation of how to get the optimal performance
from the Stratix high-speed I/O block and ensure first-time success in
implementing a functional design with optimal signal quality. For mor e
information on detailed board layout recommendation and I/O pin
terminations see AN 224: High-Speed Board Layout Guidelines .
You mus t consi der the critic al issues of controlled impedance of traces
and connectors, differential routing, and termination techniques to get
the best performance from the IC. For more inf ormation, use this chapter
and the Stratix Device Family Data Sheet se ction of the Stratix Device
Handbook, Volume 1.
The Stratix high-speed module generates signals that travel over the
media at frequencies as high as 840 Mbps. Board designers should use the
following general guidelines:
■Baseboar d designs on contro lled diff erential im ped a nce. Calculate
and compare all parameters such as trace width, trace thickness, and
the distance between two differential traces.
■Place external reference resistors as close to receiver input pins as
possible.
■Use surface mount components.
■Avoid 90° or 45° corners.
■Use high-performance connectors such as HS-3 connectors for
backplane designs. High-performance connectors are provided by
Terady ne Corp (www.teradyne.com) or Tyco International Ltd.
(www.tyco.com).
■Design backplane and card traces so that trace impedance matches
the connector’s and/or the termination’s impedance.
■Keep equal number of vias for both signal traces.
Differential
Transmitter Differential
Receiver
Z0 = 50 Ω
50 Ω50 Ω
Z0 = 50 Ω
VTT = 1.25 V VTT = 1.25 V
50 Ω50 Ω
VTT = 1.25 V VTT = 1.25 V
25 Ω
25 Ω
Altera Corporation 5–51
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
■Create equal trace lengths to avoid skew between signals. Unequal
trace lengths also result in misplaced crossing points and system
margins as the TCCS value increases.
■Limit vias because they cause discontinuities.
■Use the common bypass capacitor values such as 0.001 µF, 0.01 µF,
and 0.1 µF to decouple the fast PLL power and ground planes.
■Keep switching TTL signals away from differential signals to avoid
possible noise coupling.
■Do not route TTL clock signals to areas under or above the
differential signals.
Software
Support This section provides information on using the Quartus II software to
create Stratix designs with LVDS transmitters or r eceivers. You can use
the altlvds megafunction in the Quartus II software to implement the
SERDES circuitry. You mu st bypass the SERDES circuitry in ×1 and ×2
mode designs and use the altddio megafunction to implement the
deserialization instead. You can use either the logic array or the M512
RAM blocks closest to the diff erential pins for deserialization in SERDES
bypass mode.
Differential Pins in Stratix
Stratix device differ enti al pins are located in I/O banks 1, 2, 5, and 6 (see
Figure 5–1 on page 5–2). Each bank has differential transmitter and
differential receiver pin pairs. You can use each differential transmitter
pin pair as either a dif ferential data pin pair or a dif ferential clock pin pair
because Stratix devices do not have dedicated LVDS tx_outclock pin
pairs. The differential receiver pin pairs can only function as differential
data pin pairs. You can use these differential pins as regular user I/O pins
when not used as differential pins. When using differential signaling in
an I/O bank, you cannot place non-differential output or bidirectional
pads within five I/O pads of either side of the dif fer ential pins to avoid a
decrease in performance on the LVDS signals.
You only need to make assignments to the positive pin of the pin-pair.
The Quartus II software automatically reserves and make s the sam e
assignment to the negative pin. If you do not assign any differential I/O
standard to the differential pins, the Quartus II software sets them as
LVDS differential pins during fitting, if the design uses the SERDES
circu itry. Additionally, if you bypass the SERDES circuitry, you can still
use the differential pins by assigning a differential I/O standard to the
pins in the Quartus II software. Howe ver, when you bypass the SERDES
circuitry in the ×1 and ×2 mode, you must assign the correct differential
I/O standard to the associated pins in the Assignment Organizer. For
more information on how to use the Assignment Organizer, see the
Quartus II On-Line Help.
5–52 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
Stratix devices can drive the PLL_LOCK signal to both output pins and
internal logic. As a result, you do not need a dedicated LOCK pin for your
PLLs. In addition, there is only one PLL_ENABLE pin that enab les all the
PLLs on the device, including the fast PLLs. You must use either the
LVTTL or LVCMOS I/O standard with this pin.
Table 5–9 displays the LVDS pins in Stratix devices.
Fast PLLs
Each fast PLL featur es a multiplexed input path fr om a global or r egional
clock net. A clock pin or an output from another PLL in the device can
drive the input path. The input clock for PLLs used to clock receiver the
rx_inclock port on the altlvds_rx megafunction must be driven by
a dedicated clock pin (CLK[3..0,8..11]) or the corner pins that clock the
corner PLLs (FPLL[10..7]CLK). EP1S10, EP1S20, and EP1S25 devices have
a total of four fast PLLs located in the center of both sides of the device
(see Figure 5–16 on page 5–23). EP1S30 and larger devices have two
additional fast PLLs per side at the top a nd bottom corners of the device.
As shown in Figure 5–17 on page 5–24, the corner fast PLL shares an I/O
bank with the closest center fast PLL (e.g., PLLs 1 and 7 share an I/O
bank). The maximum input clock frequency for enhanced PLLs is 684
MHz and 717 MHz for fast PLLs.
fFor more information on Strati x PLLs, see the General-Purpose PLLs in
Stratix & Stratix GX Devices chapter.
Table 5–9. LVDS Pin Names
Pin Names Functions
DIFFIO_TX#p Transmitter positive data or output clock pin
DIFFIO_TX#n Transmitter negative data or output clock pin
DIFFIO_RX#p Receiver positive data pin
DIFFIO_RX#n Receiver negative data pin
FPLLCLK#p Positive input clock pin to the corner fast PLLs (1), (2)
FPLLCLK#n Negative input clock pin to the corner fast PLLs (1), (2)
CLK#p Positive input clock pin (2)
CLK#n Negative input clock pin (2)
Notes to Table 5–9:
(1) The FPLLCLK pin-pair is only availa ble in EP1S30, EP1S40 , EP1S60, E P1S80
devices.
(2) Either a FPLLCLK pin or a CLK pin can drive the corner fast PLLs (PLL7, PLL8 ,
PLL9, and PLL10) wh en used for general purpo s e. CLK pins cannot drive these
fast PLLs in high-speed differential I/O mode.
Altera Corporation 5–53
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
One fast PLL can drive the 20 transmitter channels and 20 receiver
channels closest to it with data rates of up to 840 Mbps. Wire-bond
packages support a data rate of 624 Mbps. The corner fast PLLs in EP1S80
devices support data rates of up to 840 Mbps. See Tables 5–10 through
5–14 for the number of high-speed differential channels in a particular
Stratix device density and package.
Since the fast PLL drives the 20 closest differential channels, there are
coverage overlaps in the EP1S30 and larger devices that have two fast
PLLs per I/O bank. In these devices, either the center fast PLL or the
corner fast PLL can drive the differential channels in the middle of the
I/O bank.
Fast PLLs can drive more than 20 transmitter and 20 receiver channels
(see Tables 5–10 through 5–14 and Figures 5–16, and 5–17 for the number
of channels each PLL can drive). In addition, the center fast PLLs can
drive either one I/O bank or both I/O banks on the same side (left or
right) of the device, while the corner fast PLLs can only drive the
differential channels in its I/O bank. Neither fast PLL can drive the
differential channels in the opposite side of the device.
The center fast PLLs can only drive two I/O at 840 Mbps. For example,
EP1S20 device fast PL L 1 c an drive all 33 dif fe r enti al channels on its si de
(17 channels fr om I/O bank 2 and 16 channels from I/O bank 1) running
at 840 Mbps in 4× mode. When a center fast PLL drives the opposite bank
on the same side of the dev ice, the other ce nter fast PLL cannot drive any
differential channels on the device.
See Tables 5–10 through 5–14 for the maximum number of channels that
one fast PLL can drive. The number of channels is also listed in the
Quartus II software. The Quartus II software gives an error message if
you try to compile a design exceeding the maximum number of channels.
fAdditional high-speed DIFFIO pin information for Stratix devices is
available in Volume 3 of the Stratix Device Handbook.
5–54 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
Table 5–10 shows the number of channels and fast PLLs in EP1S10,
EP1S20, and EP1S25 devices. Tables 5–11 thr ough 5–14 show this
information for EP1S30, EP1S40, EP1S60, and EP1S80 devices.
Table 5–10. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 1 of 2) Note (1)
Device Package Transmitter/
Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs
PLL 1 PLL 2 PLL 3 PLL 4
EP1S10 484-pin FineLine BGA Transmitter
(2) 20 840 5 5 5 5
840 (3) 10 10 10 10
Receiver 20 840 5 5 5 5
840 (3) 10 10 10 10
672-pin FineLine BGA
672-pin BGA Transmitter
(2) 36 624 (4) 9999
624 (3) 18 18 18 18
Receiver 36 624 (4) 9999
624 (3) 18 18 18 18
780-pin FineLine BGA Transmitter
(2) 44 840 11 11 11 11
840 (3) 22 22 22 22
Receiver 44 840 11 11 11 11
840 (3) 22 22 22 22
EP1S20 484-pin FineLine BGA Transmitter
(2) 24 840 6 6 6 6
840 (3) 12 12 12 12
Receiver 20 840 5 5 5 5
840 (3) 10 10 10 10
672-pin FineLine BGA
672-pin BGA Transmitter
(2) 48 624 (4) 12 12 12 12
624 (3) 24 24 24 24
Receiver 50 624 (4) 13 12 12 13
624 (3) 25 25 25 25
780-pin FineLine BGA Transmitter
(2) 66 840 17 16 16 17
840 (3) 33 33 33 33
Receiver 66 840 17 16 16 17
840 (3) 33 33 33 33
Altera Corporation 5–55
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
EP1S25 672-pin FineLine BGA
672-pin BGA Transmitter
(2) 56 624 (4) 14 14 14 14
624 (3) 28 28 28 28
Receiver 58 624 (4) 14 15 15 14
624 (3) 29 29 29 29
780-pin FineLine BGA Transmitter
(2) 70 840 18 17 17 18
840 (3) 35 35 35 35
Receiver 66 840 17 16 16 17
840 (3) 33 33 33 33
1,020-pin FineLine
BGA Transmitter
(2) 78 840 19 20 20 19
840 (3) 39 39 39 39
Receiver 78 840 19 20 20 19
840 (3) 39 39 39 39
Notes to Table 5–10:
(1) The first row for each transmitter or receiver reports the number of channels driven directly by the PLL. The second
row below it shows the maximum channels a PLL can drive if cross bank ch annels are used fr om the adjacent center
PLL. For example, in the 484-pin FineLine BGA EP1S10 device, PLL 1 can drive a maximum of five channels at
840 Mbps or a maximum of 10 channels at 840 Mbps. The Quartus II software may also merge r eceiver and
transmitter PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive both the maximum
numbers of receiver and transmitter channels.
(2) The number of channels listed includes the transmitter clock output (tx_outclock) channel. If the design
requires a DDR clock, it can use an extra data channel.
(3) These channels span across two I/O banks per side of the device. When a center PLL clocks chann e ls in the
opposite bank on the same side of the device it is called cross-bank PLL support. Both center PLLs can clock cross-
bank channels simultaneously if, for example, PLL_1 is clocking all RX channels and PLL_2 i s clocking all TX
channels. You cannot have two adjacent PLLs simultan eously clock in g cross-bank RX channels or two adjacen t
PLLs simultaneously clocking TX channels. Cross-bank allows for all receiver channels on one side of the device to
be clocked on one clock while all transmitter channels on the devi ce are clocked on the other center PLL. Crossbank
PLLs are supported at full-speed, 840 Mbps. For wire-bond devices, the full-speed is 624 Mbps.
(4) These values show the channels available for each PLL without crossing another bank.
Table 5–10. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 2 of 2) Note (1)
Device Package Transmitter/
Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs
PLL 1 PLL 2 PLL 3 PLL 4
5–56 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
Table 5–11. EP1S30 Differential Channels Note (1)
Package Transmitter
/Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs Corner Fast PLLs (2), (3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
780-pin
FineLine
BGA
Transmitter
(4) 70 840 18 17 17 18 (6) (6) (6) (6)
840 (5) 35 35 35 35 (6) (6) (6) (6)
Receiver 66 840 17 16 16 17 (6) (6) (6) (6)
840 (5) 33 33 33 33 (6) (6) (6) (6)
956-pin
FineLine
BGA
Transmitter
(4) 80 (7) 840 19 20 20 19 20 20 20 20
840 (5) 39 39 39 39 20 20 20 20
Receiver 80 (7) 840 20 20 20 20 19 20 20 19
840 (5) 40 40 40 40 19 20 20 19
1,020-pin
FineLine
BGA
Transmitter
(4) 80 (2) (7) 840 19
(1) 20 20 19
(1) 20 20 20 20
840 (5),(8) 39
(1) 39
(1) 39
(1) 39
(1) 20 20 20 20
Receiver 80 (2) (7) 840 20 20 20 20 19 (1) 20 20 19 (1)
840 (5),(8) 40 40 40 40 19 (1) 20 20 19 (1)
Table 5–12. EP1S40 Differential Ch annels (Part 1 of 2) Note (1)
Package Transmitter
/Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs Corner Fast PLLs (2), (3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
780-pin
FineLine
BGA
Transmitter
(4) 68 840 18 16 16 18 (6) (6) (6) (6)
840 (5) 34 34 34 34 (6) (6) (6) (6)
Receiver 66 840 17 16 16 17 (6) (6) (6) (6)
840 (5) 33 33 33 33 (6) (6) (6) (6)
956-pin
FineLine
BGA
Transmitter
(4) 80 840 18 17 17 18 20 20 20 20
840 (5) 35 35 35 35 20 20 20 20
Receiver 80 840 20 20 20 20 18 17 17 18
840 (5) 40 40 40 40 18 17 17 18
Altera Corporation 5–57
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
1,020-pin
FineLine
BGA
Transmitter
(4) 80 (10)
(7) 840 18
(2) 17
(3) 17
(3) 18
(2) 20 20 20 20
840 (5),(8) 35
(5) 35
(5) 35
(5) 35
(5) 20 20 20 20
Receiver 80 (10)
(7) 840 20 20 20 20 18
(2) 17
(3) 17
(3) 18 (2)
840 (5),(8) 40 40 40 40 18
(2) 17
(3) 17
(3) 18 (2)
1,508-pin
FineLine
BGA
Transmitter
(4) 80 (10)
(7) 840 18
(2) 17
(3) 17
(3) 18
(2) 20 20 20 20
840 (5),(8) 35
(5) 35
(5) 35
(5) 35
(5) 20 20 20 20
Receiver 80 (10)
(7) 840 20 20 20 20 18
(2) 17
(3) 17
(3) 18 (2)
840 (5),(8) 40 40 40 40 18
(2) 17
(3) 17
(3) 18 (2)
Table 5–13. EP1S60 Differential Ch annels (Part 1 of 2) Note (1)
Package Transmitter
/Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs Corner Fast PLLs (2), (3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
956-pin
FineLine
BGA
Transmitter
(4) 80 840 12 10 10 12 20 20 20 20
840 (5),(8) 22 22 22 22 20 20 20 20
Receiver 80 840 20 20 20 20 12 10 10 12
840 (5),(8) 40 40 40 40 12 10 10 12
1,020-pin
FineLine
BGA
Transmitter
(4) 80 (12)
(7) 840 12
(2) 10
(4) 10
(4) 12
(2) 20 20 20 20
840 (5),(8) 22
(6) 22
(6) 22
(6) 22
(6) 20 20 20 20
Receiver 80 (10)
(7) 840 20 20 20 20 12
(8) 10
(10) 10
(10) 12 (8)
840 (5),(8) 40 40 40 40 12
(8) 10
(10) 10
(10) 12 (8)
Table 5–12. EP1S40 Differential Ch annels (Part 2 of 2) Note (1)
Package Transmitter
/Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs Corner Fast PLLs (2), (3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
5–58 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
1,508-pin
FineLine
BGA
Transmitter
(4) 80 (36)
(7) 840 12
(8) 10
(10) 10
(10) 12
(8) 20 20 20 20
840 (5),(8) 22
(18) 22
(18) 22
(18) 22
(18) 20 20 20 20
Receiver 80 (36)
(7) 840 20 20 20 20 12
(8) 10
(10) 10
(10) 12 (8)
840 (5),(8) 40 40 40 40 12
(8) 10
(10) 10
(10) 12 (8)
Table 5–14. EP1S80 Differential Ch annels (Part 1 of 2) Note (1)
Package Transmitter
/Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs Corner Fast PLLs (2)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
956-pin
FineLine
BGA
Transmitter
(4) 80 (40)
(7) 840 10 10 10 10 20 20 20 20
840 (5),(8) 20 20 20 20 20 20 20 20
Receiver 80 840 20 20 20 20 10 10 10 10
840 (5),(8) 40 40 40 40 10 10 10 10
1,020-pin
FineLine
BGA
Transmitter
(4) 80 (12)
(7) 840 10
(2) 10
(4) 10
(4) 10
(2) 20 20 20 20
840 (5),(8) 20
(6) 20
(6) 20
(6) 20
(6) 20 20 20 20
Receiver 80 (10)
(7) 840 20 20 20 20 10
(2) 10
(3) 10 (3) 10 (2)
840 (5),(8) 40 40 40 40 10
(2) 10
(3) 10 (3) 10 (2)
Table 5–13. EP1S60 Differential Ch annels (Part 2 of 2) Note (1)
Package Transmitter
/Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs Corner Fast PLLs (2), (3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
Altera Corporation 5–59
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
The Quartus II software ma y also merge transmitter and receiver PLLs
when a receiver block is driving a transmitter block if the Use Common
PLLs for Rx and Tx option is set for both modules. The Quartus II
software does not m erge the PLLs in multiple transmitter-only or
multiple receiver-only modules fed by the sa me clock.
1,508-pin
FineLine
BGA
Transmitter
(4) 80 (72)
(7) 840 10
(10) 10
(10) 10
(10) 10
(10) 20
(8) 20
(8) 20 (8) 20 (8)
840 (5),(8) 20
(20) 20
(20) 20
(20) 20
(20) 20
(8) 20
(8) 20 (8) 20 (8)
Receiver 80 (56)
(7) 840 20 20 20 20 10
(14) 10
(14) 10
(14) 10
(14)
840 (5),(8) 40 40 40 40 10
(14) 10
(14) 10
(14) 10
(14)
Notes to Tables 5–11 through 5–14.
(1) The first row for each transmitter or receiver reports the number of channels driven directly by the PLL. The second
row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center
PLL. For example, in the 780-pin FineLine BGA EP1S30 device, PLL 1 can drive a maximum of 18 transmitter
channels at 840 Mbps or a maximum of 35 transmitter channels at 840 Mbps. The Quartus II software may also
merge transmitter and receiver PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive
both the maximum numbers of receiver and transmitter channels.
(2) Some of the channels accessible by the center fast PLL and the channels accessible by the corner fast PLL overlap.
Therefor e, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and
4 with the number o f channels ac cessible by P LLs 7, 8, 9, and 10. For more information on which channels overlap,
see the Fast PLL to High-Speed I/O Connections section in the relevant device pin table available on the web
(www.altera.com).
(3) The corner fast PLLs in this device support a data rate of 840 Mbps for channels labeled “high” speed in the device
pin tables.
(4) The numbers of channels listed include the transmitter clock output (tx_outclock) channel. You can use an extra
data channel if you need a DDR clock .
(5) These channels span across two I/O banks per side of the device. When a center PLL clocks channels in the opposite
bank on the same side of the device it is called cross-bank PLL support. Both center PLLs can clock cross-bank
channels simultaneously if, for example, PLL_1 is clocking all receiver channels and PLL_2 is clocking all
transmitter channels. You cannot have two adjacent PLLs simultaneously clocking cross-bank receiver channels or
two adjacent PLLs simultaneously clocking transmitter channels. Cross-bank allows for all receiver channels on one
side of the device to be clocked on one clock while all transmitter channels on the device are clocked on the other
center PLL. Crossbank PLLs are supported at full-speed, 840 Mbps. For wire-bond devices, the full-speed is
624 Mbps.
(6) PLLs 7, 8, 9, and 10 are not available in this device.
(7) The number in parentheses is the number of slow-speed channels, guaranteed to operate at up to 462 Mbps. These
channels ar e independent of the high-speed differential channels. For the location of these channels, see the Fast
PLL to High-Speed I/O Connections section in the relevant device pin table available on the web (www.altera.com).
(8) See device pin-outs channels marked “high” speed are 840 Mbps and “low” speed channels are 462 MBps.
Table 5–14. EP1S80 Differential Ch annels (Part 2 of 2) Note (1)
Package Transmitter
/Receiver Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs Corner Fast PLLs (2)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
5–60 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
When you span two I/O banks using cross-bank support, you can route
only two load enable signals total between the plls. When you enable
rx_data_align, you use both rxloadena and txloadena of a PLL.
That leaves no loadena for the second PLL.
The only way you can use the rx_data_align is if one of the following
is true:
■The RX PLL is only clocking RX channels (no resources for TX)
■If all channels can fit in one I/O bank
LVDS Receiver Block
Yo u only need to enter the input clo ck frequency, deserialization factor,
and the input data rate to implement an LVDS receiver block. The
Quartus II software then automatically sets the clock boost (W) factor for
the receiver. In addition, you can also indicate the clock and data
alignment for the receiver or add the pll_enable, rx_data_align,
and rx_locked output ports. Table 5–15 explains the function of the
available ports in the LVDS receiver block.
Table 5–15. LVDS Receiver Ports
Port Name Direction Function Input Port
Source/Output Port
Destination
rx_in[number_of_channels - 1..0] Input Input data channel Pin
rx_inclock Input Ref erence input clock Pin or output from a PLL
rx_pll_enable Input Enables fast PLL Pin (1), (2), (3)
rx_data_align Input Control for the data
realignment circuitry Pin or logic array (1),
(3), (4)
rx_locked Output Fast PLL locked pin Pin or logic array (1), (3)
rx_out[Deserialization_factor *
number_of_channels -1..0] Output De-serialized data Logic array
rx_outclock Output Internal reference clock Logic array
Notes to Table 5–15:
(1) This is an optional port.
(2) Only one rx_pll_enable pin is necessary to enable all the PLLs in the device.
(3) This is a non-differential pin.
(4) See “Realignment Implementation” on page 5–28 for more information. For guaranteed performance and data
alignment, you must synchronize rx_data_align with rx_outclock.
Altera Corporation 5–61
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Use the altlvds MegaWizard Plug-In Manager to create an LVDS
receiver block. The following sections explain the parameters available in
the Plug-In Manager when creating an LVDS receiver block.
Page 3 of the altlvds_rx MegaWizard Plug-In Manager
On page 3 of the altlvds MegaWizard Plug-In Ma n a ger, you can
choose to create either an LVDS transmitter or receiver. Depending on
what you select, the MegaWizard Plug-In Mana ger provides you with
differ ent options. Figure 5–40 shows page 3 of the altlvds MegaW izard
Plug-In Manager with options for creating an LVDS receiver.
Figure 5–40. Page 3 of the altlvds_rx MegaWizard Plug-In Manager
Number of Channels
The What is the number of channels? parameter specifies the number of
receiver channels required and the width of rx_out port. To set a fast
PLL to drive over 20 channels, type the required number in the Quartus II
window instead of choosing a numb er from the dr op-down menu, which
only has selections of up to 20 channels.
5–62 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
Deserialization Factor
Use the What is the deserialization factor? parameter to specify the
number of bits per channel. The Stratix LVDS receiver supports 4, 7, 8,
and 10 for deserialization factor (J) values. Based on the factor specified,
the Quartus II software determines the mul tiplication and/or division
factor for the LVDS PLL to deserialize the data.
See Table 5–5 for the differ ential bit naming convention . The parallel data
for the nth channel spans from the MSB (rx_out bit [(J × n) – 1]) to the
LSB (rx_out bit [J × (n – 1)]), where J is the deserialization factor. The
total width of the r eceiver rx_out port is equal to the number of channels
multiplied by your deserialization fac tor.
Input Data Rate
The What is the inclock boost(W)? parameter sets the data rate coming
into the r eceiver and is usually the deserialization facto r (J) multiplied by
the inclock frequency. This parameter’s value must be larger than the
input clock frequency and has a maximum input data rate of 840 Mbps
for Stratix devices. You do not have to provide a value for the inclock
boost (W) when designing with Stratix devices because the Quartus II
software can calculate it automatically from this parameter and the clock
frequency or clock period.
The rx_outclock fre quency is (W/J) × input frequency. The parallel
data coming out of the receiver has the same frequency as the
rx_outclock port. The clock-to-data alignment of the parallel data
output from the r eceiv er depends on the What is the alignment of data
with respect to rx_inclock? parameter.
Data Alignment with Clock
The What is the alignment of data with respect to rx_inclock? parameter
adjusts the clock-to-data skew. For most applications, the data is source
synchronous to the clock. However, there are applications where you
must center-align the data with respe ct to the clock. You can use the What
is the alignment of data with respect to rx_inclock? parameter to align
the input data with respect to the rx_inclock port. The MegaWizard
Plug-In automatically calculates the phase for the fast PLL outputs from
the What is the alignment of data with respect to rx_inclock? parameter .
This parameter’s default value is EDGE_ALIGNED, and other value s
available from the pull-down menu are EDGE_ALIGNED,
CENTER_ALIGNED, 45_DEGREES, 135_DEGREES, 180_DEGREES,
225_DEGREES, 270_DEGREES, and 315_DEGREES. CENTER_ALIGNED
is the same as 90 degrees aligned and is useful for applications like
HyperTransport technology.
Altera Corporation 5–63
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Clock Frequency or Clock Period
The fields in the Specify the input clock rate by box specify the input
frequency or the period of the input clock going into the fast PLL. When
using the same input clock to feed a transmitter and receiver
simultaneously, the Quartus II software can us e one fast PLL for both t he
transmitter and receiver.
Page 4 of the altlvds_rx MegaWizard Plug-In Manager
This section describes the parameters found on page 4 of the
altlvds_rx MegaWizard Plug-In Manager (see Figure 5–41).
Figure 5–41. Page 4 of the altlvds_rx MegaWizard Plug-In Manager
5–64 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
Data Realignment
Check the Use the “rx_data_align” input port box within the Input Ports
box to add the rx_data_align output port and enable the data
realignment circuitry in Stratix SERDES. See “Receiver Data
Realignment” on page 5–25 for more information. If necessary, you can
create a state machine to send a pulse to the rx_data_align port to
realig n the data coming in the LVDS receiver. You need to assert the port
for at least two clock cycles to enable the data realignment circuitry. Go
to the Altera web site at www.altera.com for a sample design written in
Verilog HDL.
For guaranteed performance when using data realignment, check the
Add Extra registers for rx_data_align input box when using the
rx_data_align port. The Quartus II software places one
synchr onization re gi ster in the LE closest to the rx_data_align port.
Register Outputs
Check the Register outputs box to register the receiver’s output data. The
register acts as the module’s register boundary. If the module fed by the
receiver does not have a register boundary for the data, turn this option
on. The number of registers used is proportional to the deserialization
factor (J). The Quartus II software places the synchronization r egisters in
the LEs closest to the SERDES circuitry.
Use Common PLL for Both Transmitter & Receiver
Check the Use Common PLLs for Rx and Tx box to place both the LVDS
transmitter and the LVDS receiver in the same Stratix device I/O bank.
The Quartus II software allows the transmitter and receiver to share the
same fast PLL when they use the same input clock. Although you must
separate the transmitter and receiver modules in your design, the
Quartus II software merges the fast PLLs when appr opriate and give you
the following message:
Receiver fast PLL <lvds_rx PLL name> and transmitter fast PLL <lvds_tx
PLL name> are merged together
The Quartus II software provides the following message when it cannot
merge the fast PLLs for the LVDS transmitter and receiver pair in the
design:
Can't merge transmitter-only fast PLL <lvds_tx PLL name> and receiver-
only fast PLL <lvds_rx PLL name>
rx_outclock Resource
You can use either the global or regional clock for the rx_outclock
signal. If you select Auto in the Quartus II software, the tool uses any
available lines.
Altera Corporation 5–65
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
LVDS Transmitter Module
The Quartus II software calculates the inclock boost (W) factor for the
LVDS transmitter based on input data rate, input clock frequency, and
the deserialization factor. In addition to setting the data and clock
alignment, you can also set the outclock divide factor (B) for the
transmitter output clock and add the pll_enable, tx_locked, and
tx_coreclock ports. Table 5–16 explains the function of the available
ports in the LVDS transmitter block.
You can also use the altlvds MegaW izard Plug-In Manager to create an
LVDS transmitter block. The following sections explain the parameters
available in the Plug-In Manager when creating an LVDS transmitter
block.
Page 3 of the altlvds_tx MegaWizard Plug-In Manager
This section describes the parameters found on page 3 of the
altlvds_tx MegaWizard Plug-In Manager (see Figure 5–42).
Table 5–16. LVDS Transmitter Ports
Port Name Direction Function Input port
Source/Output port
Destination
tx_in[Deserialization_factor *
number_of_channels - 1..0] Input Input data Logic array
tx_inclock Input Reference input clock Pin or output clock
from a PLL
tx_pll_enable Input Fast PLL enable Pin (1), (2), (3)
tx_out[number_of_channels - 1..0] Output Serialized LVDS data
signal Pin
tx_outclock Output External reference clock Pin
tx_coreclock Output Internal reference clock Pin, logic array, or
input clock to a fast
PLL (1)
tx_locked Output Fast PLL locked pin Pin or logic array (1),
(2), (3)
Notes to Table 5–16:
(1) This is an optional port.
(2) Only one tx_pll_enable pin is necessary to enable all the PLLs in the device.
(3) This is a non-differential pin.
5–66 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
Figure 5–42. Page 3 of the Transmitter altlvds MegaWizard Plug-In Manager
Number of Channels
The What is the number of channels? parameter specifies the number of
transmitter channels required and the width of the tx_in port. You can
have more than 20 channels in a transmitter or receiver module by typing
in the required number instead of choosing a number from the drop
down menu, which only has selections of up to 20 channels.
Deserialization Factor
The What is the deserialization factor? parameter specifies the number
of bits per channel. The transmitter block support s deserialization factors
of 4, 7, 8, and 10. Based on the factor specified, the Quartus II software
determines the multiplicati on and/or division factor for the LVDS PLL in
orde r to serialize the data.
Table 5–5 on page 5–32 lists the differential bit naming convention. The
parallel data for the nth channel spans from the MSB ( rx_out bit
[(J×n) – 1]) to the LSB (rx_out bit [J × (n – 1)]), where J is t he
Altera Corporation 5–67
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
deserialization factor . The total width of the tx_in port of the transmitter
is equal to the number of channels multipl ied b y the deserialization
factor.
Outclock Divide Factor
The What is the Output data rate? parameter specifies the ratio of the
tx_outclock frequency compared to the data rate. The default value for
this parameter is the value of the deserialization factor parameter. The
tx_outclock fr equency is equal to [W/B] x input clock frequency.
There is also an optional tx_coreclock port which has the same
frequency as the [W/J]×input frequency.
The outclock divide factor is useful for applications that do not require
the data rate to be the same as the clock freque ncy. For example,
HyperTransport technology uses a half-clock data rate scheme where the
clock frequency is half the data rate. Table 5–17 shows the supported
outclock divide factor for a give n deserialization factor.
Output Data Rate
The What is the Output data rate parameter specifies the data rate out of
the fast PLL and determines the input clock boost/multiplication factor
needed for the transmitter. This parameter must be lar ger than the input
clock frequency and has a maximum rate o f 840 Mbps for Stratix de vices.
The input clock boost factor (W) is the output data rate divided by the
input clock frequency. The Stratix SERDES cir cuitry supports input clock
boost factors of 4, 7, 8, or 10. The maximum output dat a rate is 840 Mbps,
while the clock has a maximum output of 500 MHz.
Data Alignment with Clock
Use the What is the alignment of data with respect to tx_inclock?
parameter and the What is the alignment of tx_outclock? to align the
input and output data, respectively, with the clock. For most applications,
the data is edge-aligned with the clock. However, there are applications
where the data must be center-aligned with respect to the clock. With
Table 5–17. Deserialization Factor (J) vs. Outclock Divide Factor (B)
Deserialization Factor (J) Outclock Divide Factor (B)
4 1, 2, 4
71, 7(1)
8 1, 2, 4, 8
10 1, 2, 10
Note to Table 5–17:
(1) The clock does not have a 50% duty cycle when b=7 in x7 mode.
5–68 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
Stratix devices, you can align the input data with respect to the
tx_inclock port and align the output data with respect to the
tx_outclock port. The MegaWizard Plug-In Manag er uses the
alignment of input and output data to automatically calculate the phase
for the fast PLL outputs. Both of these parameters default to
EDGE_ALIGNED, and othe r values are CENTER_ALIGNED, 45_DEGREES,
135_DEGREES, 180_DEGREES, 225_DEGREES, 270_DEGREES, and
315_DEGREES. CENTER_ALIGNED is the same as 180 degrees aligned
and is required for the HyperTransport technology I/O standar d.
Clock Frequency & Clock Period
The fields in the Specify the input clock rate by box specify either the
frequency or the period of the input clock going into the fast PLL.
However, you cannot specify both. If your design uses the same input
clock to feed a transmitter and a receiver module simultaneously, the
Quartus II software can merge the fast PLLs for both t he transmitter and
receiver when the Use common PLLs for Tx & Rx option is turned on.
Page 4 of the altlvds_tx MegaWizard Plug-In Manager
This section describes the parameters found on page 4 of the
altlvds_tx MegaWizard Plug-In Manager (see Figure 5–43).
Altera Corporation 5–69
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–43. Page 4 of the Transmitter altlvds MegaWizard Plug-In Manager
Registered Inputs
Check the Register inputs box if the input data to the transmitter is not
registered just befor e it feeds the transmitter module. You can choose
either tx_clkin or tx_coreclk to clock the transmitter data
(tx_in[]) signal. This serves as the register boundary. The number of
registers used is proportional to the deseria lization factor (J). The
Quartus II software places the synchronization registers with the LEs in
the same row and closest to the SERDES circuitry.
Use Common PLL for Transmitter & Receiver
Check the Use Common PLLs for Rx and Tx box to place both the LVDS
transmitter and receiver in the same I/O bank in Stratix devices. The
Quartus II software also allows the transmitter and receiver to share the
PLL when the same input clock is used for both. Although you must
5–70 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
separate the transmitter and receiver in your design, the Quartus II
software merges the fast PLLs when appropriate and gives you the
following message:
Receiver fast PLL <lvds_ rx pll name> and transmitter fast PLL
<lvds_tx pll name> are merged together
The Quartus II software gives the following message when it cannot
merge the fast PLLs for the LVDS transmitter and receiver pair in the
design:
Can't merge transmitter-only fast PLL
<lvds_tx pll name> and receiver-only fast PLL
<lvds_rx pll name>
tx_outclock Re source
You can use either the global or regional clock for the tx_outclock
signal. If you select Auto in the Quartus II software, the tool uses any
available lines.
SERDES Bypass Mode
You can bypass the SERDES block if your data rate is less than 624 Mbps,
and you must bypass the SERDES block for the ×1 and ×2 L VDS modules.
Since you cannot route the fast PLL output to an output pin, you must
create additional DDR I/O circuitry for the transmitter clock output. To
create an ×J transmitter output clock, instantiate an alt_ddio
megafunction clocked by the ×J clock with datain_h connected to VCC
and datain_l connected to GND.
×1 Mode
For ×1 mode, you only need to specify the I/O standar d of the pins to tell
the Quartus II software that you are using differential signaling.
However, Altera recommends using the DDRIO circuitry when the input
or output data rate is higher than 231 Mbps. T he maximum output clock
frequency for ×1 mode is 420 MHz.
×2 Mode
You must use the DDRIO circuitry for ×2 mode. The Quartus II software
provides the altddio_in and altddio_out megafunctions to use for
×2 receiver and ×2 transmitter, respectively. The maximum data rate in
×2 mode is 624 Mbps. Figure 5–44 shows the schemat ic for using DDR
circuitry in ×2 mode.
Altera Corporation 5–71
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–44. LVDS x2 Mode Schematic Using DDR I/O Circuitry
The transmitter output clock requires extra DDR output circuitry that has
the input high and input low connected to VCC and GND r espectively. The
output clock frequency is the same as the input frequency of the DDR
output circuitry.
Other Modes
For other modes, you can still to use the DDR circuitry for better
frequency performance. You can use either the LEs or the M512 RAM
block for the deserialization.
M512 RAM Block as Serializer/Deserializer Interface
In addition to using the DDR circuitry and the M512 RAM block, you
need two extra counters per memory block to pr ovide the addr ess for the
memory: a fast counter powering up at 0 and a slow counter powering up
at 2. The M512 RAM block is configured as a simple dual-port memory
block, where the r ead enable and the write enable signal s are always tied
high. Figures 5–45 and 5–46 show the block diagram for the SERDES
bypass receiver and SERDES bypass transmitter, respectively.
datain[0]
inclock
dataout_h[0]
dataout_l[0]
DDIO In
datain_h[0]
datain_l[0]
outclock
dataout[0]
DDIO Out
datain_h[0]
datain_l[0]
outclock
dataout[0]
DDIO Out
inclock /1 clock1
/2 clock0
RX_PLL
Custom Logic
VCC
GND
RXp
RXn
rx_inclk
TXp
TXn
tx_outclk
5–72 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
Figure 5–45. SERDE S Bypass LVDS Receiver Using M512 RAM Block as the Deserializer
Figure 5–46. SERDE S Bypass LVDS Transmitter Using M512 RAM Block as Deserializer
datain[0]
inclock
dataout_h[0]
dataout_l[0]
DDIO In
datain[1..0]
waddr[7..0]
wclock
rclock
raddr[5..0]
dataout[7..0]
Simple Dual Port
RX_SESB
512 Bits
inclock ÷1 clock1
÷2 clock0
RX_PLL
RXp
RXn
rx_inclk
W-UpCounter
clock q[4..0]
R-UpCounter
clock q[2..0]
waddr[7..5]
Core data
Core clock
raddr[5..3]
datain[7..0]
waddr[5..0]
wclock
rclock
raddr[7..0]
dataout[7..0]
Simple Dual Port ×2×8
TX_SESB
512 Bits
inclock ÷1 clock1
×2 clock0
RX_PLL
datain_h[0]
datain_l[0]
outclock
datain_h[0]
datain_l[0]
outclock
dataout_h[0]
dataout_l[0]
DDIO Out
/1 clock1
/2 clock0
RX_PLL
core_clk
core_data
W-UpCounter
clock q[2..0]
R-UpCounter
clock q[5..0]
waddr[7..5]
raddr[5..3]
VCC
GND
TXp
TXn
tx_outclk
Altera Corporation 5–73
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
For the transmitter, the read counter is the fast coun ter and the write
counter is the slow counter. For the receiver, the write counter is the fast
counter and the read counter is the slow counter. Tables 5–18 and 5–19
provide the address counter configurations for the transmitter and the
receiver, respectively.
In different M512 memory configurations, the counter width is smaller
than the address width, so you must ground some of the most significant
address bits. Table 5–20 summarizes the address width, the counter
width, and the number of bits to be grounded.
Table 5–18. Address Counters for SERDES Bypass LVDS Receiver
M512 Mode Deserialization
Factor
Write Up-Counter
(Fast Counter) Read Up-Counter
(Slow Counter) Inval id Initial Cycles
Width Starts at Width Starts at Write Read
×2×4 4 4032126
×2×8 8 5032246
×4×16 8 5032246
×2×16 16 6032486
Table 5–19. Address Counters for SERDES Bypass LVDS Transmitter
M512 Mode Deserialization
Factor
Write Up-Counter
(Fast Counter) Read Up-Counter
(Slow Counter) Inval id Initial Cycles
Width Starts at Width Starts at Write Read
×2×4 4 403224
×2×8 8 503228
×4×16 8 503228
×2×16 16 6032216
Table 5–20. Address & Counter Width
M512 Mode Write Counter
Width Read Counter
Width Write Address
Width Read Address
Width
Number of Grounded Bits
Write Address R ead Address
×2×4 438744
×2×8 538633
×4×16637512
×2×16538532
5–74 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
Logic Array as Serializer/Deserializer Interface
The design can use the lpm_shift_reg megafunction instea d of a
simple dual port memory block to serialize/deserialize data. The r eceiver
requires an extra flip-flop clocked by the slow clock to latch on to the
deserialized data. The transmitter requires a counter to generate the
enable signal for the shift register to indicate the times to load and
serialize the data. Figures 5–47 and 5–48 show the schematic of the ×8
LVDS receiver and ×8 LVDS transmitter, respectively, with the logic
array performing the deserialization.
This scheme can also be used for APEX II and Mercury devic e flexi b le
LVDS solutions.
Figure 5–47. SERDE S Bypass LVDS Receiver with Logic Array as Deserializer
PLL DDR
Input
Shift
Register
Shift
Register
DFF[7..0]
Clock
Serial
data in
÷2 clock1
×4 clock0
data_l data[0, 2, 4, 6]
data[1, 3, 5, 7]
data_h
clock
clock
data
data
data[7..0]
Data to
logic array
rx_clk
D
Q
CLK
Altera Corporation 5–75
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–48. SERDE S Bypass LVDS Transmitter with Logic Array as Deserializer
Summary The Stratix device family of flexible, high-performance, high-density
PLDs delivers the performance and bandwidth necessary for complex
system-on-a-programmable-chip (SOP C) solutions. Stratix devices
support multiple I/O protocols to interface with other devices within the
system. Stra tix devices can easily implement processing-intensive data-
path functions that are received and transmitted at high speeds. The
Stratix family of devices combines a high-performance enhanced PLD
architecture with dedicated I/O circuitry in order to provide I/O
standard performances of up to 840 Mbps.
PLL
Counter
Shift
Register
Shift
Register
DDR
Output
Clock
×1 clock
×4 clock
data_h
data_l
Data[7..0]
clock
clock
data
data
load
load
Serial
data out
tx_clk
5–76 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Summary
Altera Corporation Section IV–1
Section IV. Digital Signal
Processing (DSP)
This section provides information for design and optimization of digital
signal processing (DSP) functions and arithmetic operations in the on-
chip DSP blocks.
It contains the following chapters:
■Chapter 6, DSP Blocks in Stratix & Stratix GX Devices
■Chapter 7, Implementing High Performance DSP Functions
in Stratix & Stratix GX Devices
Revision History The table below shows the rev ision hist ory for Chapters 6 and 7.
Chapter Date/Version Changes Made
6 July 2005, v2.2 ●Changed Stratix GX FPGA Family data sheet reference to
Stratix GX Device Handbook, Volume 1.
September 2004, v2.1 ●Updated “Software Support” on page 6–28.
●Deleted “Quartus II DSP Megafunctions” section. It was replaced by
the updated “Software Support” on page 6–28
●Replaced references to AN 193 and AN 194 with a new reference
on page 6–28.
July 2003, v2.0 ●Minor content change.
April 2003, v1.0 ●No new changes in Stratix Device Handbook v2.0.
7 September 2004, v1.1 ●Corrected spelling error.
April 2003, v1.0 ●No new changes in Stratix Device Handbook v2.0.
Section IV–2 Altera Corporation
Digital Signal Processing (DSP) Stratix Device Handbook, Volume 2
Altera Corporation 6–1
July 2005
6. DSP Blocks in Stratix &
Stratix GX Devices
Introduction Traditionally, designers had to make a trade-of f between the flexib ility of
off-the-shelf digital signal processors and the performance of custom-
built devices. Al tera® Stratix® and Stratix GX devi ces eliminate the need
for this trade-off by pr oviding exceptional performance combined with
the flexibility of programmable logic dev ic es (PL D s ) . Strati x and
Stratix GX devices have d edicated digital signal processing (DSP) blocks,
which have high-speed parallel processing capabilities, that are
optimized for DSP applications. DSP blocks are ideal for implementing
DSP applications that need high data throughput.
The most commonly used DSP functions are finite impulse response (FIR)
filters, complex FIR filters, infinite impulse response (IIR) filters, fast
Fourier transform (FFT) functions, discrete cosine transfor m (DCT)
functions, and correlators. These functions are the building blocks for
mor e com p lex sy stems such as wideband code d ivision multiple access
(W-CDMA) basestations, voice over Internet protocol (VoIP), and high-
definition television (HDTV).
Although these functions are complex, they all use similar building
blocks such as multiply-adders and multiply-accumulators. Stratix and
Stratix GX DSP blocks combine five arithm etic operations—
multiplication, addition, subtraction, accumulation, and summation—to
meet the requirements of complex functions and to provide improved
performance.
This chapter describes the Stratix and Stratix GX DSP blocks, and
explains how you can use them to implement high-performance DSP
functions. It addresses the following topics:
■Architecture
■Operational Modes
■Software Support
fSee the Stratix Device Family Data Sheet section of the Stratix Device
Handbook, Volume 1 and the Stratix GX Device Family Data Sheet section of
the Stra tix GX Device Handbook, Volume 1 for more information on Stratix
and Stratix GX devices, respectively.
S52006-2.2
6–2 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
DSP Block Overview
DSP Block
Overview Each Stratix and Stratix GX device has two columns of DSP blocks that
effici ently implement multiplication, multiply accumulate (MAC), and
filtering functions. Figure 6–1 shows one of the columns with
surrounding LAB rows. You can configure each DSP block to support:
■Eight 9 ×9 bit multipliers
■Four 18 ×18 bit multipliers
■One 36 ×36 bit multiplier
Figure 6–1. DSP Blocks Arranged in Columns
The multipliers can then feed an adder or an accumulator block,
depending on the DSP block operational mode. Additionally, you can use
the DSP block input registers as shift r egisters to implement applications
such as FIR filters efficiently. The number of DSP blocks per column
DSP Block
Column
8 LAB
Rows DSP Block
Altera Corporation 6–3
July 2005 Stratix Device Handbook, Volume 2
DSP Blocks in Stratix & Stratix GX Devices
increases with device density. Tables 6–1 and 6–2 describe the number of
DSP blocks in each Stratix and Stratix GX device, respectively, and the
multipliers that you can im plement.
Table 6–1. Number of DSP Blocks in Stratix Devices Note (1)
Device DSP Blocks 9 × 9 Multipliers 18 × 18 Multipliers 36 × 36 Multipliers
EP1S10 6 48 24 6
EP1S20 10 80 40 10
EP1S25 10 80 40 10
EP1S30 12 96 48 12
EP1S40 14 112 56 14
EP1S60 18 144 72 18
EP1S80 22 176 88 22
Table 6–2. Number of DSP Blocks in Stratix GX Devices Note (1)
Device DSP Blocks 9 × 9 Multipliers 18 × 18 Multipliers 36 × 36 Multipliers
EP1SGX10C 6 48 24 6
EP1SGX10D 6 48 24 6
EP1SGX25C 10 80 40 10
EP1SGX25D 10 80 40 10
EP1SGX25F 10 80 40 10
EP1SGX40D 14 112 56 14
EP1SGX40G 14 112 56 14
Note to Tables 6–1 and 6–2:
(1) Each device has either the number of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers shown.The total number of
multipliers for each device is not the sum of all the multipliers.
6–4 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
DSP Block Overview
Figure 6–2 shows the DSP block operating as an 18 ×18 multiplier.
Figure 6–2. DSP Block in 18 ×18 Mode
Adder/
Subtractor/
Accumulator
Adder/
Subtractor/
Accumulator
Adder
Multiplier Block Output
Register
PRN
CLRN
DQ
ENA
PRN
CLRN
DQ
ENA
PRN
CLRN
DQ
ENA
PRN
CLRN
DQ
ENA
PRN
CLRN
DQ
ENA
PRN
CLRN
DQ
ENA
PRN
CLRN
DQ
ENA
PRN
CLRN
DQ
ENA
PRN
CLRN
DQ
ENA
PRN
CLRN
DQ
ENA
PRN
CLRN
DQ
ENA
PRN
CLRN
DQ
ENA
Optional Serial Shift Register
Inputs from Previous
DSP Block
From the Row
Interface Block
Summation
Block
Pipeline
Register
Adder Output Block
Altera Corporation 6–5
July 2005 Stratix Device Handbook, Volume 2
DSP Blocks in Stratix & Stratix GX Devices
Architecture The DSP block consists of the following elements:
■A multiplier block
■An adder/subtractor/accumulator block
■A summation block
■An output interface
■Output registers
■Routing and control signals
Multiplier Block
Each multiplier block has inpu t registers, a multiplier stage, and a
pipeline register. See Figure 6–3.
Figure 6–3. Multiplier Block Architecture
CLRN
DQ
ENA
Data A
Data B
Data Out
to Adder
Blocks
shiftoutb shiftouta
shiftina
shiftinb
aclr[3..0]
clock[3..0]
ena[3..0]
signa
signb
CLRN
D Q
ENA
CLRN
DQ
ENA
6–6 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Architecture
Input Registers
Each operand feeds an input r egister or the multiplier directly. The DSP
block has the following signals (one of each controls every input and
output register):
■clock[3..0]
■ena[3..0]
■aclr[3..0]
The input registers feed the multiplier and drive two dedicated shift
output lines, shiftouta and shiftoutb. The shift outputs from one
multiplier block directly feed the adjacent multiplier block in the same
DSP block (or the next DSP block), as shown in Figure 6–4 on page 6–7, to
form a shift register chain. This chain can terminate in any block, i.e., you
can create any length of shift register chain up to 224 registers. A shift
register is useful in DSP applications such as FIR filters. When
implementing 9 ×9 and 18 ×18 multipliers, you do not need external
logic to cr eate the shift r e gister chain because the input shift r e gisters are
internal to the DSP block. This implementation greatly reduces the
required LE count and routing resources, and produces repeatable
timing.
Altera Corporation 6–7
July 2005 Stratix Device Handbook, Volume 2
DSP Blocks in Stratix & Stratix GX Devices
Figure 6–4. Shift Register Chain
CLRN
DQ
ENA
Data A
Data B
A[n] × B[n]
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
shiftouta
shiftoutb
A[n - 1] × B[n - 1]
CLRN
DQ
ENA
CLRN
D Q
ENA
CLRN
DQ
ENA
shiftouta
shiftoutb
A[n - 2] × B[n - 2]
CLRN
DQ
ENA
CLRN
DQ
ENA
DSP Block 0
DSP Block 1
shiftouta
shiftoutb
6–8 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Architecture
Multiplier Stage
The multiplier stage supports 9 ×9, 18 ×18, or 36 ×36 multiplication.
(The multiplier stage also su pport sm aller multipliers. See “Operational
Modes” on page 6–18 for details.) Based on the data width, a single DSP
block can perform many multiplications in parallel.
The multiplier operands can be signed or unsigned numbers. Two
signals, signa and signb, indicate the representation of the two
operands. For example, a logic 1 on the signa signal indicates that data
A is a signe d number; a logic 0 i ndicate s an uns igned num ber. The result
of the multiplication is signed if any one of the operands is a signed
number, as shown in Table 6–3.
The signa and signb signals affect the entire DSP block. Therefore, all
of the data A inputs fe eding the same DSP block must have the same sign
representation. Similarly, all of the data B inputs feeding the same DSP
block must have the same sign representation. The multiplier offers full
precision regardle ss of the sign representation.
1By default, the Altera Quartus® II sof tware sets the multiplie r to
perform unsigned multiplication when the signa and signb
signals are not used.
Pipeline Registers
The output from the multiplier can feed a pipeline register or be
bypassed. You can use pipeline registers for any multiplier size;
pipelining is useful for increasing the DSP block performance,
particularly when using subsequent adder stages.
1In the DSP block, pipelining improves the performance of
36 ×36 multipliers. For 18 ×18 multipliers and smaller,
pipelining adds latency but do es not im prove performance.
Table 6–3. Multiplier Signed Representation
Data A Data B Result
Unsigned Unsigned Unsigned
Unsigned Signed Signed
Signed Unsigned Signed
Signed Signed Signed
Altera Corporation 6–9
July 2005 Stratix Device Handbook, Volume 2
DSP Blocks in Stratix & Stratix GX Devices
Adder/Output Block
The adder/output block has the following elements (See Figure 6–5 on
page 6–10):
■An adder/subtractor/accumulator block
■A summation block
■An output select multiplexer
■Output registers
You can configure the adder/output block as:
■A pure output interface
■An accumulator
■A simple one-level adder
■A two-level adder with dynamic addition/subtraction control on the
first-level adde r
■The final stage of a 36-bit multiplier
The output select multiplexer sets the output of the DSP block. You can
register the adde r/ output bloc k’s output using the output registers.
1You cannot use the adder/output block independently of the
multiplier.
6–10 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Architecture
Figure 6–5. Adder/Output Block
Adder/Subtractor/Accumulator Block
The adder/subtractor/accumulator is the first level of the adder/output
block. You can configure the block as an accumulator or as an
adder/subtractor.
Accumulator
When the adder/subtractor/accumulator is configured as an
accumulator, the output of the adder/output block feeds back to the
accumulator as shown in Figure 6–5. You can use the
Adder/
Subtractor/
Accumulator 0
Adder
Result A
Result B
Result C
Result D
addnsub1
accum_sload0
addnsub3
signa
signb
accum_sload1
Accumulator Feedback
Accumulator Feedback
overflow0
Adder/
Subtractor/
Accumulator 1
Output Select
Multiplexer
Output
Registers
overflow1
Altera Corporation 6–11
July 2005 Stratix Device Handbook, Volume 2
DSP Blocks in Stratix & Stratix GX Devices
accum_sload[1..0] signals to clear the accumulator asynchronously.
This action is not the same as resetti ng the output reg isters. You can clear
the accumulation and begin a new one without losing any clock cycles.
The overflow signal goes high on the positive edge of the clock when
the accumulator overflows or underflows. In the next clock cycle,
however , the overflow signal r esets to zero even though an overflow (or
underflow) occurred in the previous clock cycle. Use a latch to preserve
the overflow condition indefinitely (until the latch is cleared).
Adder/Subtractor
The addnsub[1..0] signals select addition or subtraction: high for
addition and low for subtraction. You can control the addnsub[1..0]
signals using external logic; therefore, the first-level block can switch
from an adder to a subtractor dynamically, simply by changing the
addnsub[1..0] signals. If the first stage is configured as a subtractor,
the output is A - B and C - D.
The adder/subtractor also uses two signals, signa and signb, like the
multiplier block. These signals indicate the sign representation of both
operands together. You can register the signals with a latency of 1 or 2
clock cycles.
Summation Block
The output from the adder/subtractor feeds to an optional summation
block, which is an adder block that sums the outputs of the
adder/subtractor. The summation block is important in applications
such as FIR filters.
Output Select Multiplexer
The outputs from the various elements of the adder/output block are
routed through an output select multiplexer. Based on the DSP block
operational mode, the outputs of the multiplier block,
adder/subtractor/accumulator, or summation block feed straight to the
output, bypassing the remaining blocks in the DSP block.
1The output select multiplier configuration is configured
automatically by software.
Output Registers
You can use the output registers to r egister the DSP block output . Like the
input registers, the output registers are contro lled by the four
clock[3..0], aclr[3..0], and ena[3..0] signals. You can use the
output registers in any DSP block operational mode.
6–12 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Architecture
1The output registers form part of the accumulator in the
multiply-accumulate mode.
Routing Structure & Control Signals
This section de sc ribes the interface between the DSP blocks and the row
interface blocks. It also describes how the DSP block generates control
signals and how the signals route from the row interface to the DSP block.
DSP Block Interface
The DSP blocks are organized in columns, which provides efficient
horizontal communication between the blocks and the column-based
memory blocks. The DSP block communicates with other parts of the
device through an input and output interface. Each DSP block, including
the input and output interface, is 8 logic array blocks (LABs) long.
The DSP block and row interface blocks consist of eight blocks that
connect to eight adjacent LAB rows on the left and right. Each of the eight
blocks has two regions: right and left, one per row. The DSP block
receives 144 data input signals and 18 control signals for a total of
162 input signals. This block drives out 144 data output signals; 2 of the
data signals can be used as overflow signa ls (overflow). Figure 6–6
provides an overview of the DSP block and its interface to adjacent LABs.
Figure 6–6. DSP Block Interface to Adjacent LABs
Input Interface
The DSP block input interface has 162 inpu t signals f rom adjacent LABs;
18 data signals per row and 18 control signals per block.
Output Interface
The DSP block output interface drives 144 outputs to adjacent LABs, 18
signals per row from 8 rows.
144
8 LAB
Rows Row
Interfaces
0 through 7 DSP
Block
8 LAB
Rows
DSP Block & Row Interface
144
18
Data
Control
162
DSP Block
Input Interface DSP Block
Output Interface
Altera Corporation 6–13
July 2005 Stratix Device Handbook, Volume 2
DSP Blocks in Stratix & Stratix GX Devices
Because the DSP block outputs communicate horizontally, and because
each DSP block row has more outputs than an LAB (18 from the DSP
block compared to 10 from an LAB), the DSP block has double the
number of row channel drivers compared to an LAB. The DSP block has
the same number of row channels, but the row channe ls ar e stagger ed as
if there were two LABs within each block. The DSP blocks have the same
number of column channels as LABs because DSP blocks communicate
primarily through row channels.
Row Interface Block
Each row interface block connects to the DSP block row structure with
21 signals. Because each DSP block has eight row interface blocks, this
block receives 162 signals from the eight row interfaces. Of the
162 signals, 144 are data inputs and 18 are control signals. Figure 6–7 on
page 6–14 shows one row block within the DSP block.
6–14 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Architecture
Figure 6–7. DSP Row Interface Block
Control Signals in the Row Interface Block
The DSP block has a set of input registers, a pipeline register, and an
output register. Each register is grouped in banks that share the same
clock and clear resources:
■1- to 9-bit banks for the input register
■1- to 18-bit banks for the pipeline register
■18 bits for the output register
LAB LAB
Row Interface
Block
DSP Block
Row Structure
10
[17..0][17..0]
DSP Block to
LAB Row Interface
Block Interconnect Region
18 Inputs per Row 18 Outputs per Row
R4 and R8 Interconnects
C
4 and
C8
Int
e
r
co
nn
ec
t
s
Dir
ec
tLink Int
e
r
co
nn
ect
f
rom Ad
j
acent LA
B
Nine DirectLink Outputs
to Adjacent LABs
DirectLink Interconnect
from Adjacent LAB
1818
9
10
3
Control
9
18
Altera Corporation 6–15
July 2005 Stratix Device Handbook, Volume 2
DSP Blocks in Stratix & Stratix GX Devices
The row interface block generates the control signals and routes them to
the DSP block. Each DSP block has 18 control signals:
■Four clock signals (clock[3..0]), which ar e available to each bank
of DSP blocks
■Four clear signals (aclr[3..0]), which are available to each bank
of DSP blocks
■Four clock enable signals (ena[3..0]), which the whole DSP block
can use
■signa and signb, which ar e specifi c to each DSP block
■addnsub[1..0] signals
■accum_sload[1..0] signals
The signa, signb, and addnsub[1..0], accum_sload[1..0]
signals have independent clocks and clears and can be registered
individually. When each 18 ×18 multiplie r in the DSP block sp lits in half
to two 9 ×9 multipliers, each 9 ×9 multiplier has independent control
signals. Figure 6–8 shows the DSP block row interf ace and shows how it
generates the data and control signals.
Figure 6–8. DSP Block Row Interface
DSP Row 1
DSP Row 2
DSP Row 3
DSP Row 4
DSP Row 5
DSP Row 6
DSP Row 7
DSP Row 8
DSP Block
Row Interface
Input
Registers DSP
Block
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
DSP Row
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
DSP Row
21 Signals for
Data to Input
Register
DSP Row
Unit Control
Block
3
30 Local
Interconnect
Signals
LAB
Row
Clocks
Detail of
1 DSP Row
6–16 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Architecture
The DSP block interface generates the clock signals fro m LAB row cl ocks
or the local interco nnec t. The clear signals are generated from the local
interconnect s within each DSP bloc k row interface or from LAB row
clocks. The four clock enable signals are generated from the 30 local
interc onnects from the sam e LAB rows tha t generate the cloc k signals.
The clock enable is pair ed with the clock because the enable logic is
implemented at the interface. Figure 6–9 shows the signal distri bution
within the row interface block.
Figure 6–9. DSP Block Row Interface Signal Distribution
18 × 18
Multiplier
A1
B1
18
18
18
18
Row 1
Row 2
18 × 18
Multiplier
A4
B4
18
18
18
18
Row 7
Row 8
4
4
4
18
clock[3..0]
aclr[3..0]
ena[3..0]
data[17..0]
Input
Registers
18-Bit Data Routed
from 30 Local
Interconnects
Four Clock Enable
Signals Routed from
30 Local Interconnects
Four Clear Signals
Routed from 30 Local
Interconnects or LAB
Row Clock
Four Clock Signals
Routed from LAB
Row Clock or Local
Interconnect
Altera Corporation 6–17
July 2005 Stratix Device Handbook, Volume 2
DSP Blocks in Stratix & Stratix GX Devices
Each row block provides 18 bits of data to the multiplier (i.e., one of the
operands to the multiplier), which are routed thr ough the 30 local
interconnects within each DSP r ow interface block. Any signal in the
device can be the sour ce of the 18-bit multiplier data, by connecting to the
local row in terconnect throu gh any row o r column.
Each contr ol signal routes thr ough one of the eight rows of the DSP block.
Table 6–4 shows the 18 control signals and the row to which each one
routes.
Input/Output Data Interface Routing
The 30 local inter c onnects generate the 18 inputs to the row inte rface
blocks. The 21 outputs of the r ow interface block are the inputs to the DSP
row block (see Figure 6–7 on page 6–14 ).
Table 6–4. Control Signals in DSP Block
Signal Name Row Description
signa 1 DSP block-wide signed and unsigned control signals for all multipliers.
The multiplier outputs are unsigned only if both signa and signb are
low.
signb 6
addnsub1 3 Controls addition or subtraction of the two one-level adders. The
addnsub0 signal controls the top two one-lev el adders; the addnsub1
signal controls the bottom two one-level adders. A high indicates
addition; a low indicates subtraction.
addnsub3 7
accum_sload0 2 Resets the feedback input to the accumulator. The signal
asynchronously clears the accum ulator and allows new accumulation to
begin without losing any clock cycles. The accum_sload0 controls the
top two one-le vel adders , and the accum_sload1 controls the bottom
two one-level adders. A low is for normal accumulation operations and
a high is for zeroing the accumulator.
accum_sload1 7
clock0 3 DSP block-wide clock signals.
clock1 4
clock2 5
clock3 6
aclr0 1 DSP block-wide clear signals.
aclr1 4
aclr2 5
aclr3 7
ena[3..0] Same rows as the
Clock Signals DSP block-wide clock enable signals.
6–18 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Operational Modes
The row interface block has DirectLi nk™ connections that connect the
DSP block input or output signals to the left and right adjacent LABs at
each row. (The DirectLink connections provide interc onnects betwe en
LABs and adjacent blocks.) The DirectLink connection reduces the use of
row and column interconnects, providing higher performance and
flexibility.
Each row inte rface block receives 10 Dir ectLink connections from the
right adjacent LABs and 10 fro m the left adjacent LABs. Additionally, the
row interface block r eceives signals from the DSP block, making a total of
30 local interc onnects for each row interface blo ck. Al l of the row and
column r esou rces within the DSP block can access this interconnect
region (see Figure 6–7 on page 6–14).
A DSP block has nine outputs that drive the right adjacent LAB and nine
that drive the left adjacent LAB through DirectLink interconnects. All
18 outputs drive any row or column.
Operational
Modes You can use the DSP block in one of four operational modes, depending
on your application needs (see Table 6–4). The Quartus II software has
built-in megafunctions that you can use to control the mode. After you
have made your parameter settings using th e megafunction’s
MegaWizard® Plug-In, the Quartus II software automatically configures
the DSP block.
Simple Multiplier Mode
In simple multiplier mode, the DSP block performs individual
multiplication operations for general-purpose multipliers and for
applications such as equalizer coefficient updates that require many
individual multiplication operations.
Table 6–5. DSP Block Operational Modes
Mode 9 × 9 18 × 18 36 × 36
Simple multiplier Eight multipliers with eight
product outputs Four multipliers with four
product outputs One multiplier
Multiply accumulator Two 34-bit multiply-
accumulate blocks Two 52-bit multiply-
accumulate blocks –
Two-multiplier adder Four two-multiplier adders Two two-multiplier adders –
Four-multiplier adder Two four-multiplier adders One four-multiplier adder –
Altera Corporation 6–19
July 2005 Stratix Device Handbook, Volume 2
DSP Blocks in Stratix & Stratix GX Devices
9- & 18-Bit Multipliers
You can configur e each DSP block multiplier for 9 or 18 bits. A single DSP
block can support up to 8 indi vidual 9-bit or smaller multipliers, or up to
4 individual multipliers with opera nd widt hs between 10- and 18-bits.
Figure 6–10 shows the simple multiplier mode.
Figure 6–10. Simple Multiplier Mode
The multiplier operands can accept sign ed integers, unsigned integers, or
a combination. The signa and signb signals are dynamic and can be
register e d in the DSP block. Additionally, you can register the mult iplier
inputs and results independently. Pipeli ni ng the result, using the
pipeline registers in the block, increases the performance of the DSP
block.
36-Bit Multiplier
The 36-bit multiplie r is a subset of the simple multiplier mod e. It uses the
entire DSP b lock to implement one 36 × 36-bit multiplier. The four 18-bit
multipliers are fed part of each input, as shown in Figure 6–11 on
page 6–21. The adder/output block adds the partial products using the
CLRN
DQ
ENA
A
CLRN
DQ
ENA
CLRN
DQ
ENA
A
B
shiftoutb shiftouta
signb
signa
Adder Output Block
6–20 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Operational Modes
summation block. You can use pipeline registers between the multiplier
stage and the summation block. The 36 ×36-bit multiplier supports
signed and unsigned operation.
The 36-bit multiplier is useful when your application needs more than
18-bit precision, for example, for mantissa multiplication of precision
floating-point arithmetic applications.
Altera Corporation 6–21
July 2005 Stratix Device Handbook, Volume 2
DSP Blocks in Stratix & Stratix GX Devices
Figure 6–11. 36-Bit Multiplie r
CLRN
DQ
ENA
A[17..0]
A[17..0]
B[17..0]
B[17..0]
A[35..18]
A[35..18]
B[35..18]
B[35..18]
signa
signb
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
D Q
ENA
CLRN
DQ
ENA
CLRN
D Q
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
D Q
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
Data Out
Partial
Product
Summation
Block
A
B
C
D
6–22 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Operational Modes
Multiply Accumulator Mode
In multiply accumulator mode, the output of the multiplier stage feeds
the adder/output block, which is configured as an accumulator or
subtractor (see Figure 6–12). You can implement up to two independent
18-bit multiply accu mu lators in one DSP block. The Quartus II software
implements smaller multiplier-accumulators by tying the unused low-
orde r bits of an 18-bit multiplier to ground.
Figure 6–12. Multiply Accumulator Mode
Note to Figure 6–12:
(1) The signa and signb signals are the same in the multiplier stage and the adder/output block.
The multiply accumulator output can be up to 52 bits wide for a
maximum 36-bit result with 16-bits of accumulation. In this mode, the
DSP block uses output registers and the accum_sload and overflow
signals. The accum_sload[1..0] signal synchronously loads the
multiplier result to the accumulator output. This signal can be
unregistered or r egi stered once or twice. T he DSP block can then begin a
new accumulation without losing any clock cycles. The overflow signal
indicates an overflow or underflow in the accumulator. This sig n al is
CLRN
DQ
ENA
CLRN
DQ
ENA
Data A
Data B
Data Out
overflow
shiftoutb shiftouta
shiftina
shiftinb
aclr
clock
ena
signa (1)
signb (1)
CLRN
DQ
ENA
CLRN
DQ
ENA
Accumulator
addnsub1
signa
signb
accum_sload1
CLRN
DQ
ENA
Altera Corporation 6–23
July 2005 Stratix Device Handbook, Volume 2
DSP Blocks in Stratix & Stratix GX Devices
cleared for the next accumul ation cycle, and you can use an external latch
to preserve the signal. You can use the addnsub[1..0] signals to
perform accumulation or subtr a ction dynamically.
1If you want to use DSP blocks and your design only has an
accumulator, you can use a multiply by one followed by an
accumulator to force the software to implement the logic in the
DSP block.
Two-Multiplier Adder Mode
The two-multiplier adder mode uses the adder/output block to add or
subtract the outputs of the multiplie r block, which is useful for
applications such as FFT functions and complex FIR filte rs. Additionally,
in this mode, the DSP block outputs two sums or differences for
multipliers up to 18 bits, or 4 sums or differences for 9-bit or smaller
multipliers. A single DSP block can implement one 18 × 18-bit complex
multiplier or two 9 × 9-bit complex multipliers.
A complex multiplicatio n can be written as:
(a + jb) × (c + jd) = (a × c – b × d) + j × (a × d + b × c)
In this mode, a single DSP block calculates the real part (a × c–b × d) using
one adder/subtractor/accumulator and the imaginary part (a × d + b × c)
using another adder/subtractor/accumulator for data up to 18 bits.
Figure 6–13 shows an 18-bit comple x multiplication. For data widths up
to 9 bits, the DSP block can perform two complex multiplications using
four one-level adders. Res ources outside of the DSP block route each
input to the two multiplier inputs.
1You can only use the adder block if it follows multiplication
operations.
6–24 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Operational Modes
Figure 6–13. Complex Multiplier Implemented Using Two-Multiplier Adder
Mode
Four-Multiplier Adder Mode
In the four-multiplier adder mode, which you can use for 1-dimensional
and 2-dimensional filtering applications, the DSP block adds the results
of two adder/subtractor/accumulators in a final stage (the summation
block).
1You can only use the adder block if it follows multiplication
operations.
9- & 18-Bit Summation Blocks
A single DSP block can implement one 18 × 18 or two 9 ×9 summation
blocks (see Figure 6–14 on page 6–25). The multiplier product widths
must be the same size.
Subtractor
36
36
18
18
18 37
A
C
B
D
18
A × C - B × D
(Real Part)
Adder
36
36
18
18 37
A
D
B
C
A × D + B × C
(Imaginary Part)
18
18
18
DSP Block
Altera Corporation 6–25
July 2005 Stratix Device Handbook, Volume 2
DSP Blocks in Stratix & Stratix GX Devices
Figure 6–14. Four-Multiplier Adder Mode
CLRN
DQ
ENA
Data A
Data B
shiftinb
shiftina aclr
clock
ena
signa
signb
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
Data A
Data B
CLRN
DQ
ENA
CLRN
DQ
ENA
Adder/
Subtractor
CLRN
DQ
ENA
Data A
Data B
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
Data A
Data B
shiftoutb shiftouta
CLRN
DQ
ENA
CLRN
DQ
ENA
Adder/
Subtractor
addnsub0
signa
signb CLRN
DQ
ENA
Data Out
addnsub1
Adder
6–26 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Operational Modes
FIR Filters
The four-multiplier adder mode can be used for FIR filter and complex
FIR filter applications. The DSP block combines a four-multiplier adder
with the input registers configured as shift registers. One set of shift
inputs contains the filter data, while the other holds the coeffici ents,
which can be loaded serially or in parallel (see Figure 6–15).
The input shift register eliminates the need for shift registers external to
the DSP block (e.g., implemented in device logic elements). This
architecture simplifies filter design and improves performance because
the DSP block implements all of the filter circuitry.
1Serial shift inputs in 36-bit s im ple multiplier mode require
external registers.
One DSP block can implement an entire 18-bit FIR filter with up to four
taps. For FIR filters larger than four taps, you can cascade DSP blocks
with additional adder stages implemented in logic elements.
Altera Corporation 6–27
July 2005 Stratix Device Handbook, Volume 2
DSP Blocks in Stratix & Stratix GX Devices
Figure 6–15. Input Shift Registers Configured for a FIR Filter
CLRN
DQ
ENA
Data A
Data B
A[n] × B[n] (to adder)
CLRN
D Q
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
Data A
Data B
A[n - 1] × B[n - 1] (to adder)
CLRN
DQ
ENA
CLRN
D Q
ENA
CLRN
DQ
ENA
Data A
Data B
A[n - 2] × B[n - 2] (to adder)
CLRN
DQ
ENA
CLRN
DQ
ENA
6–28 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
Software
Support Altera provides two distinct methods for implementing various modes of
the DSP block in your design: instantiation and inference. Both methods
use the following three Quartus II megafunctions:
■lpm_mult
■altmult_add
■altmult_accum
You can instantiate the megafunctions in the Quartus II software to use
the DSP block. Alternatively, with inference, you can create a HDL design
an synthesize it using a third-party synthesis tool like LeonardoSpectrum
or Synplify or Quartus II Native Synthesis that infers the appropriate
megafunction by recognizing multipliers, multiplier adders, and
multiplier accumulators. Using either method, the Quartus II software
maps the functionality to the DSP blocks during compilation.
fSee the Implementing High-Performance DSP Functions in Stratix & Stratix
GX Devices chapter in the Stratix Device Handbook, Volume 2 or the
Stratix GX Device Handbook, Volume 2 for more information on using DSP
blocks to implement high-performance DSP functions su ch as FIR filters,
IIR filters, and disc reet cosine transforms (DCTs).
fSee Quartus II On-Line Help for instructions on using the megafunctions
and the MegaWizard Plug-In Manager.
fFor more information on DSP block inference support, see the
Recommended HDL Coding Styles chapter of the Quartus II Development
Software Handbook v4.1, Volume 1.
Conclusion The Stratix and Stratix GX device DSP blocks are optimized to support
DSP applications that need high data throughput, such as FIR filters, FFT
functions, and encoders. These DSP blocks are flexible and ca n be
configured in one of four operat ional modes to suit any application need.
The DSP block’s adder/subtractor/accumulator and the summation
blocks minimize the amount of logic r esources used and prov ide efficient
routing. This efficiency results in improved performance and data
throughput for DSP applications. The Quartus II software, to gether with
the LeonardoSpectrum and Synplify software, provides a complete and
easy-to-use flow for implementing functionality in the DSP block.
Altera Corporation 7–1
September 2004
7. Implementing High
Performance DSP Functions
in Stratix & Stratix GX Devices
Introduction Digital signal processing (DSP) is a rapidly advancing field. With
products increasing in complexity, designers face the challenge of
selecting a solution with both flexibility and high performance that can
meet fast time-to-market requir ements. DSP processors offer flexibility,
but they lack real-time performance, whi le application-specific stand ard
products (ASSPs) and application-specif ic integrated circuits (ASICs)
offer performance, but they are inflexible. Only programmable logic
devices (PLDs) offer both flexibility and high per form a nce to meet
advanced design challenges.
The mathematical theory unde rlying basic DSP building blo cks—such as
the finite impulse response (FIR) filter, infinite impulse response (IIR)
filter, fast fourier transform (FFT), and dir ect co sine transform (D CT)—is
computationally intensive. Altera® Stratix® and Stratix GX devices
featur e dedicated DSP blocks optimized for implement ing arithm etic
operations, such as multiply, multiply-add, and multiply-accumulate.
In addition to DSP blocks, Stratix and Stratix GX devices have
TriMatrix™ embedded memory blocks that featur e various sizes that can
be used for data buf fering, which is important for most DSP applications.
These dedicated hardware features make Stratix and Stratix GX device s
an ideal DSP solution.
This chapter describes the implementation of high performance DSP
functions, including filte rs, transforms, and arithmetic functions, using
Stratix and Stratix GX DSP blocks. The following topics are discussed:
■FIR filters
■IIR filters
■Matrix manipulation
■Discrete Cosine Transform
■Arithmetic functions
Stratix &
Stratix GX DSP
Block Overview
Stratix and Stratix GX devices feature DSP blocks that can efficiently
implement DSP functions, including multiply, mul tipl y-add, and
multiply-accumulate. The DSP blocks also have three built-in registers
sets: the input registers, the pipeline regist ers at the multiplier output,
and the output registers. Figure 7–1 shows the DSP block operating in the
18 ×18-bit mode.
S52007-1.1
7–2 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Stratix & Stratix GX DSP Block Overview
Figure 7–1. DSP Block Diagram for 18 x 18-bit Mode
Adder/
Subtractor/
Accumulator
2
Adder/
Subtractor/
Accumulator
1
Summation
Optional Pipeline
Register Stage
Multiplier Stage
Output Selection
Multiplexer
Optional Output
Register Stage
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
Optional Serial Shift Register
Inputs from Previous
DSP Block
Optional Stage Configurable
as Accumulator or Dynamic
Adder/Subtractor
Summation Stage
for Adding Four
Multipliers Together
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
Optional Serial
Shift Register
Outputs to
Next DSP Block
in the Column
to MultiTrack
Interconnect
Altera Corporation 7–3
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
The DSP blocks are organized into co lumns enabli ng efficient horizonta l
communication with adjacent TriMatrix memory blocks. Tables 7–1 and
7–2 show the DSP block resources in Stratix and Stratix GX devices,
respectively.
Table 7–1. DSP Block Resources in Stratix Devices
Device DSP Blocks Maximum 9 ×9
Multipliers Maximum 18 ×18
Multipliers Maximum 36 ×36
Multipliers
EP1S10 6 48 24 6
EP1S20 10 80 40 10
EP1S25 10 80 40 10
EP1S30 12 96 48 12
EP1S40 14 112 56 14
EP1S60 18 144 72 18
EP1S80 22 176 88 22
Table 7–2. DSP Block Resources in Stratix GX Devices
Device DSP Blocks Maximum 9 ×9
Multipliers Maximum 18 ×18
Multipliers Maximum 36 ×36
Multipliers
EP1SGX10C 6 48 24 6
EP1SGX10D 6 48 24 6
EP1SGX25C 10 80 40 10
EP1SGX25D 10 80 40 10
EP1SGX25F 10 80 40 10
EP1SGX40D 14 112 56 14
EP1SGX40G 14 112 56 14
7–4 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
TriMatrix Memory Overview
Each DSP block supports either eight 9 ×9-bit multipliers, four 18-bit
multipliers, or one 36 ×36-bit multiplier. These multipliers can feed an
adder or an accumulator unit based on the ope ration mode. Table 7–3
shows the diffe rent operation modes for the DSP blocks.
Implementing multipliers, multiply-adders, and multiply-accumulators
in the DSP blocks has a performance advantage over logic cel l
implementation. Using DSP bloc ks als o reduces logi c cell and ro uti n g
resource consumption. To achieve higher performance, register each
stage of the DSP block to allow pipelining. For implementing
applications, such as FIR fil ters, efficiently use the input registers of the
DSP block as shift registers.
fFor more information on DSP blocks, see the DSP Blocks in Stratix &
Stratix GX Devices chapter.
TriMatrix
Memory
Overview
Stratix and St r a tix GX devices feature the TriMatrix memory structure,
composed of three sizes of embedded RAM blocks. These include the
512-bit size M512 block, the 4-Kbit size M4K block, and the 512-Kbit size
M-RAM block. Each bloc k is configurable to support a wide range of
features.
Tables 7–4 and 7–5 show the number of memory blocks in each Stratix
and Stratix GX device, respectively.
Table 7–3. Operation Modes for DSP Blocks
DSP Block Mode Nu mber & Size of Multipliers per DSP Block
9 x 9-bit 18 x 18-bit 36 x 36-bit
Simple multiplier Eight multipliers with
eight product outputs Four multipliers with four
product outputs One multiplier with one
product output
Multiply-accumulate Two multiply and
accumulate (34 bit) Two multiply and
accumulate (52 bit)
Two-multipliers adder 4 two-multipliers adders 2 two-multipliers adders
Four-multipliers adder 2 four-multipliers adder 1 four-multipliers adder
Table 7–4. TriMatrix Memory Resources in Stratix Devices (Part 1 of 2)
Device M512 M4K M-RAM
EP1S10 94 60 1
EP1S20 194 82 2
EP1S25 224 138 2
Altera Corporation 7–5
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Most DSP applications require local data storage for interm edi ate
buffering or for filter storage. The TriMatrix memory blocks enable
efficient use of available resources for each application.
The M512 and M4K memory blocks can implement shift registers for
applications, such as mul ti-c h annel filtering, auto-correlation, and cross-
correlation functions. Implementing shift registers in embe dded memory
blocks reduces logic cel l and routing resource consumption.
fFor more information on TriMatrix memory blocks, see the TriMatrix
Embedded Memory Blocks in Stratix & Stratix GX Devices chapter.
DSP Function
Overview The following sections describe commonly used DSP functions. Each
section illustrates the implementation of a basic DSP building block,
including FIR and IIR filters, in Stratix and Stratix GX devices using DSP
blocks and TriMatrix memory blocks.
Finite Impulse
Response (FIR)
Filters
This section describes the basic theory and implementation of basic FIR
filters, time-domain multiplexed (TDM) FIR filters, and interpolation and
decimation polyphase FIR filters. An introduction to the complex FIR
filter is also presented in this section.
EP1S30 295 171 4
EP1S40 384 183 4
EP1S60 574 292 6
EP1S80 767 364 9
Table 7–5. TriMatrix Memory Resources in Stratix GX Devices
Device M512 M4K M-RAM
EP1SGX10C 94 60 1
EP1SGX10D 94 60 1
EP1SGX25C 224 138 2
EP1SGX25D 224 138 2
EP1SGX25F 224 138 2
EP1SGX40D 384 183 4
EP1SGX40G 384 183 4
Table 7–4. TriMatrix Memory Resources in Stratix Devices (Part 2 of 2)
Device M512 M4K M-RAM
7–6 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Finite Impulse Response (FIR) Filters
FIR Filter Background
Digital communications systems use FIR filters for a variety of functions,
including waveform sha ping, anti-aliasing, band selection,
decimation/interpolation, and low pass filtering. The basic stru cture of a
FIR filter consists of a series of multiplications followed by an addition.
The following equation r epresents an FIR filter operation:
where:
x(n) represents the seque nce of input samples
h(n) represents the filter coefficients
L is the number of filter taps
A sample FIR filter with L=8 is shown in Figure 7–2.
Figure 7–2. Basic FIR Filter
This example filter in Figure 7–2 uses the input values at eight different
time instants to produce an output. Hence, it is an 8-tap filter. Each
register provides a unit sample delay. The delayed inputs are multiplied
with their respective filter coe fficients and added together to pr oduce the
output. The width of the output bus depends on the number of taps and
the bit width of the input and coefficients.
yn() xn() hn()⊗
=
yn() xn i–()hi()
i0=
L1–
∑
=
x(n)
y(n)
h(2)
h(1) h(3) h(4) h(5) h(6) h(7)
h
(0)
Altera Corporation 7–7
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Basic FIR Filter
A basic FIR filter is the simplest FIR filter type. As shown in Figure 7–2, a
basic FIR filter has a single input channel and a single output channel.
Basic FIR Filter Implementation
Stratix and Stratix GX devices’ dedicated DSP blocks can implement basic
FIR filters. Because these DSP blocks have closely integrated multipliers
and adders, filters can be implemented with minimal routing resources
and delays. For implementing FIR filters, the DSP blocks are configured
in the four-multipliers adder mode.
fSee the DSP Blocks in Stratix & Stratix GX Devices chapter for more
information on the different modes of the DSP blocks.
This section describes the implementation of an 18-bit 8-tap FIR filter.
Because Stratix and Stratix GX devices support modula rity, cascading
two 4-tap filters can implement an 8-tap filter. Larger FIR filters can be
designed by extending this concept. Users can also increase the number
of taps available per DSP block if 18 bits of resolution are not required. For
example, by using only 9 bits of resolution for input samples and
coefficient values, 8 multipliers are available per DSP block. Therefore, a
9-bit 8-tap filter can be implemented in a single DSP bloc k provided an
external adder is impleme nte d in logic cells.
The four-multipliers adder mode, shown in Figure 7–3, provides four
18 ×18-bit multipliers and three adders in a single DSP block . Hence, it
can implement a 4-tap filter. The data width of the input and the
coefficients is 18 bits, which results in a 38-bit output for a 4-tap filter.
7–8 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Finite Impulse Response (FIR) Filters
Figure 7–3. Hardware View of a DSP Block in Four-Multipliers Adder Mode Notes (1). (2), (3)
Notes to Figure 7–3:
(1) The input registers feed the multiplier blocks. These registers can increase the DSP block performance, but are
optional. These registers can also function as shift registers if the dedicated shiftin/shiftout signals are used.
(2) The pipeline registers are fed by the multiplier blocks. These registers can incr ease th e DSP block performance, but
are optional.
(3) The output register s registe r the DSP block outpu t. These reg isters can incr ease the DSP blo ck performance, but are
optional.
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
18
18
18
18
18
18
18
18
18
18
18
36
36
36
36
37
37
38
Output
y(n)
x(n)
h(0)
x(n-1)
h(1)
x(n-2)
h(2)
x(n-3)
h(3) Multiplier D
Multiplier C
Multiplier B
Multiplier A
CLK1
CLR1
CLK2
CLR2
shiftout
input from
previous
block
shiftout
input from
previous
block
Data from
row
interface
block
Coefficients
from row
interface
block
shiftin
input to
next block
shiftin
input to
next block
Data from row
interface block
Data from row
interface block
Data from row
interface block
Coefficients
from row
interface
block
Coefficients
from row
interface
block
Coefficients
from row
interface
block
18
18
18
18
18
D Q
D Q
D Q
D Q
D Q
38
Altera Corporation 7–9
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Figure 7–4. Quartus II Software View of MegaWizard Implementation of a DSP Block in Four-Multipliers
Adder Mode
Each input register of the DSP block provides a shiftout output that
connects to the shiftin input of the adjacent input r egister of the same DSP
block. The registers on the boundaries of a DSP block also connect to the
registers of adjacent DSP blocks through the use of shiftin/shiftout
connect ions. Thes e connections create r egister chains spanning multiple
DSP blocks, which makes it easy to increase the length of FIR filters.
Figure 7–5 shows two DSP blocks connected to create an 8-tap FIR filter.
Filters with more taps can be implemented by connecting DSP blocks in
a similar manner, provided sufficient DSP bloc ks are availabl e in the
device.
1Adding the outputs of the two DSP blocks re quires an external
adder which can be imple mented using logic cells.
The input data ca n be fed dir ectly or by using the sh iftout/shiftin chains,
which allow a single input to shift down the r egister chain inside the DSP
block. The input to each of the registers has a mul tiplexer, hence, the data
can be fed either from outside the DSP block or the precedin g register.
This can be selected fr om the MegaWizard® in the Quartus® II software,
as shown in Figure 7–4. The example in Figure 7–5 uses the
shiftout/shiftin flip-flop chains where the multiplexers are configured to
use these chains. In this example, the flip-flops inside the DSP blocks
serve as the taps of the FIR filter.
7–10 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Finite Impulse Response (FIR) Filters
When the coef ficients are loaded i n parallel, they can be fed directly fr om
memory elements or any other muxing scheme. This facil itates th e
implementation of an adaptive (variable) filter.
Further, if the user wants to implement the shift register chains external
to the DSP block, this can be done by using the altshift_taps
megafunction. In this case, the coefficient and data shifting is done
external to the DSP block. The DSP block is only used to implement the
multiplications and the additions.
Parallel vs. Serial Implementation
The fastest implementations are fully parallel , but consume more logic
reso urces than serial implementations. To trade-of f performance for logic
reso urce s, implement a serial scheme with a specif ied number of taps . To
facilitate this, Altera provides the FIR Compiler core through its
MegaCore pr ogram. The FIR Compiler is an easy- to-use, fully-integrated
graphical user interface (GUI) based FIR filter design software.
fFor more information on the FIR Compiler MegaCore, visit the Altera
web site at www.altera.com and search for “FIR compiler” in the
“Intellectual Property” page.
It is important to note that the four-multipliers adder mode allows a DSP
block to be configured for pa rallel or serial input. When it is configured
for parallel input, as shown in Figure 7–6, the data input and the
coefficients can be load ed di rectly without the need for shiftin/shifto ut
chains between adjacent registers in the DSP b lock. W hen the DSP block
is configure d for serial input, as shown in Figure 7–5, the shiftin/shiftout
chains create a re gister cascade both within the DSP block and also
between adjacent DSP blocks.
Altera Corporation 7–11
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Figure 7–5. Serial Loading 18-Bit 8-Tap FIR Filter Using Two DSP Blocks
Notes (1), (2), (3)
Notes to Figure 7–5:
(1) Unused ports grayed out.
(2) The indexing x(n-1), ..., x(n-7) refers to the case of parallel loading and should be
ignored here. This indexing is retained in this figure for consistency with othe r
figures in this chapter.
(3) To increase the DS P block performanc e, include the pipeline and output registers.
See Figure 7–3 on page 7–8 for the details.
DQ
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
DSP block 1
Filter output
y(n)
h(0)
h
(
1
)
h
(
2
)
h
(
3
)
x(n)
Filter coefficients
Data input
x
(n-2)
x
x
x
(n-3)
xx
x
(n-1)
x
x
h
(
4
)
h
(5
)
h
(
6
)
h(7)
x
(n-4)
xx
x
(n-5)
xx
x
(n-6)
x
x
x
(n-7)
xx
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
DQ
DSP block 2
7–12 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Finite Impulse Response (FIR) Filters
Figure 7–6. Parallel Loading 18-Bit 8-Tap FIR Filter Using Two DSP Blocks
Notes (1), (2)
Notes to Figure 7–6:
(1) The indexing x(n-1), ..., x(n-7) refers to the case of parallel loading.
(2) To increase the DSP block performance, include the input, pipeline, and output
registers. See Figure 7–3 on page 7–8 for the details.
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
DSP block 1
Filter output
y(n)
h(0)
h(1)
h(2)
h(3)
x(n)
Filter coefficients
Data input
x(n-2)
x(n-3)
x(n-1)
h(4)
h(5)
h(6)
h(7)
x(n-4)
x(n-5)
x(n-6)
x(n-7)
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
DSP block 2
Altera Corporation 7–13
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Basic FIR Filter Implementation Results
Table 7–6 shows the results of the serial implementation of an 18-bit 8 tap
FIR filter as shown in Figure 7–5 on page 7–11
Basic FIR Filter Design Example
Download the Basic FIR Filter (base_fir.zip) design example from the
Design Examples section of the Altera web site at www.altera.com.
Time-Domain Multiplexed FIR Filters
A TDM FIR filter is clocked n-times faster than the sample rate in or der to
reuse the same hardware. Consider the 8-tap filter shown in Figure 7–2.
The TDM technique can be used with a TDM factor of 2, i.e., n = 2, to
implement this filte r usi ng only four multipliers, provided the filter is
clocked two times faster internally.
To understand this concept, consider Figure 7–7 that shows a TDM filter
with a TDM factor of 2. A 2×-multiplied clock is required to run the filter .
On cycle 0 of the 2× clock, the user loads four coefficients into the four
multiplier inpu ts. The resulting output is stored in a register. On cycle 1
of the 2× clock, the user loads the remaining four coefficients into the
multiplier inputs. The output of cycle 1 is added wit h the output of cycle
0 to create the overa ll output. See the “TDM Filter Implementation” on
page 7–14 section for details on the coefficient loading schedule.
The TDM implementation shown in Figure 7–7 requires only four
multipliers to achieve the functionality of an 8-tap filter. Thus, TDM is a
good way to save logic resources, provided the multipliers can run at n-
times the clock speed. The coefficients can be stored in ROM/RAM, or
any other muxing scheme.
Table 7–6. Basic FIR Filter Implementation Results
Part EP1S10F780
Utilization LCELL: 130/10570 (1%)
DSP Block 9-bit elements: 16/48 (33%)
Memory bits: 288/920448 (<1%)
Performance 247 MHz
7–14 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Finite Impulse Response (FIR) Filters
Figure 7–7. Block Diagram of 8-Tap FIR Filter with TDM Factor of n=2
TDM Filter Implementation
TDM FIR filters are implemented in Stratix and Stratix GX devices by
configuring the DSP blocks in the multiplier-adder mode. Figure 7–9
shows the implementation of an 8-tap TDM FIR filter (n=2) with 18 bits
of data and coefficient inputs. Becaus e the input data needs to be loaded
into the DSP block in paralle l, a shift re gister chain is implemented u sing
a combination of logic cells and the altshift_taps function. This shift
register is clocked with the same data sample rate (clock 1×). The filter
coefficients are store d in ROM and loaded into the DSP block in parallel
as well. Because the TDM factor is 2, both the ROM and DSP block are
clocked with clock 2×.
Figure 7–8 and Table 7–7 show the coefficient loadi ng sche dule. For
example, during cycle 0, only the flip-flops corresponding to h(1), h(3),
h(5), and h(7) are enabled. This pr oduces the temporary output, y0, which
is stored in a flip-flop o utside the DSP block. During cycle 1, only the flip-
D Q
FIR filter with
four multipliers
18-bit input
2x clock
Output
Table 7–7. Operation of TDM Filter (Shown in Figure 7–9 on page 7–16)
Cycle of
2×Clock Cycle Output Operation Overall Output,
y(n)
0y0 = x(n-1)h(1) + x(n-3)h(3) + x(n-5)h(5) + x(n-7)h(7) Store result N/A
1y1 = x(n)h(0) + x(n-2)h(2) + x(n-4)h(4) + x(n-6)h(6) Generate output y(n) = y0 + y1
2y2 = x(n)h(1) + x(n-2)h(3) + x(n-4)h(5) + x(n-6)h(7) Store result N/A
3y3 = x(n+1)h(0) + x(n-1)h(2) + x(n-3)h(4) + x(n-5)h(6) Generate output y(n) = y2 + y3
4y4 = x(n+1)h(1) + x(n-1)h(3) + x(n-3)h(5) + x(n-5)h(7) Store result N/A
5y5 = x(n+2)h(0) + x(n)h(2) + x(n-2)h(4) + x(n-4)h(6) Generate output y(n) = y4 + y5
6y6 = x(n+2)h(1) + x(n)h(3) + x(n-2)h(5) + x(n-4)h(7) Store result N/A
7y7 = x(n+3)h(0) + x(n+1)h(2) + x(n-1)h(4) + x(n-3)h(6) Generate output y(n) = y6 + y7
Altera Corporation 7–15
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
flops corresponding to h(0), h(2), h(4) and h(6) ar e enabled. This produces
the temporary output, y1, which is added to y0 to produce the overall
output, y(n). The following shows what the overall output, y(n), equals:
This is identical to the output of the 8-tap filter shown in Figure 7–2. After
cycle 1, this process is repeated at every cycle.
Figure 7–8. Coefficie nt Loading Schedule in a TDM Filter
yn() y0y1
+=
yn() x0()h0() xn 1–()h1() xn 2–()h2() xn 3–()h3()+++=
+ x n 4–()h4() xn 5–()h5() xn 6–()h6() xn 7–()h7()+++
Cycle 0
load h(1), h(3), h(5), h(7)
Cycle 1
load h(0), h(2), h(4), h(6)
Cycle 2
load h(1), h(3), h(5), h(7)
Cycle 3
load h(0), h(2), h(4), h(6)
Cycle 4
load h(1), h(3), h(5), h(7)
2x clock
1x clock
7–16 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Finite Impulse Response (FIR) Filters
Figure 7–9. TDM FIR Filter Implementation Note (1)
Note to Figure 7–9:
(1) To increase the DSP block performance, include the pipeline and output registers. See Figure 7–3 on page 7–8 for
details.
If the TDM factor is more than 2, then a multiply-accumulator needs to be
implemented. This multiply-accumulator can be implemented using the
soft logic outside the DSP block if all the multipliers of the DSP blo ck ar e
needed. Alternatively, the multiply-accumulator may be implemented
inside the DSP block if all the multipliers of the DSP block are not needed.
The accumulator needs to be zeroed at the start of each new sample input.
The user also needs a way to store additional sample inputs in memory.
For example, consider a sample rate of r and TDM factor of 4. Then, the
Filter output
y(n)
Clock input
(1x clock)
1x
c
l
ock
PLL
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
2x clock
x
(n)
x
x
DSP block
Data input
RAM
/
R
O
M
0
RAM
/
R
O
M 1
RAM
/
R
O
M
2
RAM
/
ROM
3
Filt
e
r
c
o
e
ffi
c
i
e
nt
s
DQ
Accumulator
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
Shift re
g
iste
r
Altera Corporation 7–17
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
user needs a way to accept this sample data and send it at a 4 r rate to the
input of the DSP block. One way to do this is using a first-in-first-out
(FIFO) memory with input clocked at rate r and output clocked at rate 4r.
The FIFO may be implemented in the TriMatrix memory.
TDM Filter Implementation Results
Table 7–8 shows the results of the implementation of an 18-bit 8-tap TDM
FIR filter as shown in Figure 7–9 on page 7–16.
TDM Filter Design Example
Download the TDM FIR Filter (tdm_fir.zip) design example from the
Design Examples section of the Altera web site at www.altera.com.
Polyphase FIR Interpolation Filters
An interpolation filter can be used to increase sample rate. An
interpolation filter is efficiently implemented with a polyphase FIR filter .
DSP systems frequently use polyphase filters because they simplify
overall system design and also reduce the number of computations per
cycle required of the hardwa re. This section first describes interpolation
filters and then how to implement them as polyphase filters in Stratix and
Stratix GX devices. See the “Polyphase FIR Decimation F ilt ers” on
page 7–24 section for a discussion of decimati on filters.
Interpolation Filter Basics
An interpolation filter increases the output sample rate by a factor of I
through the insertion if I-1 zeros between input samples, a process
known as zero padding. After the zero padding, the output samples in
time domain ar e separated by Ts/I = 1/(I×fs), w her e Ts and fs ar e the
sample period and sample frequency of the original signal, respectively.
Figure 7–10 shows the concept of signal interpolation.
Table 7–8. TDM Filter Implementation Results
Part EP1S10F780
Utilization Lcell: 196/10570 (1%)
DSP Block 9-bit elements: 8/48 (17%)
Memory bits: 360/920448 (<1%)
Performance 240 MHz (1)
Note to Table 7–8:
(1) This refers to the performance of the DSP blocks. The input and output rate is 120
million samples per second (MSPS), clocked in and out at 120 MHz.
7–18 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Finite Impulse Response (FIR) Filters
Inserting zeros between the samples creates reflections of the original
spectrum, thus, a low pass filter is needed to filter out the reflections.
Figure 7–10. Block Diagram Representation of Interpolation
To see how interpolation filters work, consider the Nyquis t Sam pling
Theorem. This theorem states that the maximum frequency of the input
to be sampled must be smaller than fs/2, where fs is the sampling
frequency, to avoid aliasing. This frequency, fs/2, is also known as the
Nyquist frequency (Fn). Typically, before a signal is sampled usin g an
analog to digital converter (ADC), it needs to be low pass filtered using
an analog anti-aliasing filter to prevent aliasing. If the input frequency
spectrum extends close to the Nyquist frequency, then the first alias is also
close to the Nyquist frequency. Therefore, the low pass filter needs to be
very sharp to reject this alias. A very sharp analog filter is har d to design
and manufacture and could increase passband ripple, thereby
compromising system performance.
The solution is to increase the sampli ng rate of the ADC, so that the new
Nyquist frequency is higher and the spacing between the desired signal
and the alias is also higher . Zer o padding as described above increase the
sample rate. This process also known as upsampling (oversampling)
relaxes t he roll of f requir ements of the anti-al iasing filter. Consequently, a
simpler filter achieves alias suppression. A simpler analog filter is easier
to implement, does not compromise system performance, and is also
easier to manufacture.
Similarly, the digital to analog converter (DAC) typically interpolates the
data before the digital to analog conversion. This relaxes the r equirement
on the analog low pass filter at the output of the DAC.
The interpolation filter does not need to run at the oversampled
(upsampled) rate of fs×I. This is because the extra sample points add ed
are zeros, so they do not contribute to the output.
Figure 7–11 shows the time and frequency domain representation of
interpolation for a specifi c case where the original signal spectrum is
limited to 2 MHz and the interpolation factor (I) is 4. The Nyquist
frequency of the upsampled signal must be greater than 8 MHz, and is
chosen to be 9 MHz for this example.
ILPF
Input Output
sample rate fssample rate I*fs
Altera Corporation 7–19
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Figure 7–11. Time & Frequency Domain Representations of Interpolation for I = 4
As an example, CD pla yers use interpolation, where the nominal sample
rate of audio input is 44.1 kilosamples per second. A typical
implementation might have an interpolation (oversampling) factor of 4
generating 176.4 kilosamples per second of oversampled data stream.
Polyphase Interpolation Filters
A direct implementation of an interpolation filter, as shown in
Figure 7–10, impose s a high computational burden. For ex ample, if the
filter is 16 taps long and a multiplication takes one cycle, then the number
of computations required per cycle is 16×I. Depending on the
interpolation factor (I), this number can be quite big and may not be
achievable in hard ware. A polyphase implementation of the low pass
filter can reduce the number of computa tions requir ed per cycle, often by
a large fa ctor, as will be evident later in this section.
The polyphase implementation “splits” the original filter into I
polyphase filters whose impulse responses are defined by the following
equation:
hkn() hk nI+()=
7–20 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Finite Impulse Response (FIR) Filters
where:
k = 0,1, …, I-1
n = 0,1, …, P-1
P = L/I = length of polyphase filters
L = length of the filter (selected to be a multiple of I)
I = interpolation factor
h(n) = original filter impulse response
This equation implies that the first polyphase filter, h0(n), has coef ficients
h(0), h(I), h(2I),..., h((P-1)I). The second polyphase filter, h1(n), has
coefficients h(1), h(1+I), h(1+2I), ..., h(1+(P-1)I). Continuing in this way,
the last polyphase filter, hI-1(n), has coeffi cients h(I-1), h((I - 1) + N), h((I
- 1) + 2I), ..., h((I - 1) + (P-1)I).
An example helps in understanding the polyphase implementation of
interpolation. Consider the polyphase representation of a 16-tap low pass
filter with an interpolation factor of 4. Thus, the output is given below:
Referring back to Figure 7–11 on page 7–19, the only nonzero samples of
the input are x(0), x(4), x(8,) and x(12). The first output, y(0), only depends
on h(0), h(4), h(8) and h(12) because x(i) is zero for i ≠ 0, 4, 8, 12. Table 7–9
shows the coef fi cients required to generate output samples.
Table 7–9 shows that this filter operation can be represented by four
parallel polyphase filters. This is shown in Figure 7–12. The outputs from
the filters are mult iplexed to generate the overall output. The multiplexer
is contro ll ed by a counter, which counts up modu lo-I starting at 0.
It is illuminating to compare the computational requirements of the direct
implementation versus polyphase implementation of the low pass filter.
In the direct implementation, the number of computations per cycle
yn() hn iI–()xi()
i0=
15
∑
=
Table 7–9. Decomposition of a 16-Tap Interpolating Filter into Four Polyphase Filters
Output Sample Coefficients Required Polyphase Filter Impulse Response
y(0), y(4)... h(0), h(4), h(8), h(12) h0(n)
y(1), y(5)... h(1), h(5), h(9), h(13) h1(n)
y(2), y(6)... h(2), h(6), h(10), h(14) h2(n)
y(3), y(7)... h(3), h(7), h(11), h(15) h3(n)
Altera Corporation 7–21
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
required is 16 × I = 16 × 4 = 64. In the polyphase implementation, the
number of computations per cycle required is 4 × 4 = 16. This is because
there are four polyphase filters, each with four taps.
Figure 7–12. Polyphase Representation of I=4 Interpolation Filter
Polyphase Interpolation Filter Implementation
Figure 7–13 shows the Stratix or Stratix GX implementation of the
polyphase interpolation filter in Figure 7–12. The four polyphase filters
share the same har dwar e, which is a 4-tap filter. One Stratix or Stratix GX
DSP block can implement one 4-tap filter with 18-bit wide data and
coefficients. A multiplexer can be used to load new coefficient values on
every cycle of the 4× clock. Stratix and Stratix GX phase lock loops (PLLs)
can generate the 4× clock. In the first cycle of the 4× clock, the user needs
to load coeffi cients for polyphase filter h0(n); in the second cycle of the 4×
I = 4
LPF with
coefficients
h(0), h(1), ... h(15)
Input
x(n)
Output
y(n)
Interpolation Using a Single Low-Pass Filter
Interpolation Using a Polyphase Filter
Polyphase filter
with coefficients
h(0), h(4), h(8), h(12)
Polyphase filter
with coefficients
h(1), h(5), h(9), h(13)
Polyphase filter
with coefficients
h(2), h(6), h(10), h(14)
Polyphase filter
with coefficients
h(3), h(7), h(11), h(15)
Output
y(n)
Input
x(n)
y1(n)
y2(n)
y3(n)
y4(n)
Modulo 4 up
counter
initialized at 0
4x Clock
0
1
2
3
7–22 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Finite Impulse Response (FIR) Filters
clock, the users needs to load coef ficients of the polyphase filter h1(n) and
so on. Table 7–10 summarizes the coefficient loading schedule. The
output, y(n), is clocked using the 4× clock.
Table 7–10. Polyphase Interpolation (I=4) Filter Coefficient Loading
Schedule
Cycle of 4× Clock Coefficients to Load Corresponding RAM/ROM
1, 5,... h(0), h(4), h(8), h(12) 0, 1, 2, 3
2, 6,... h(1), h(5), h(9), h(13) 0, 1, 2, 3
3, 7,... h(2), h(6), h(10), h(14) 0, 1, 2, 3
4, 8,... h(3), h(7), h(11), h(15) 0, 1, 2, 3
Altera Corporation 7–23
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Figure 7–13. Implementation of the Polyphase Interpolation Filter (I=4) Notes (1), (2), (3)
Notes to Figure 7–13:
(1) The 1× clock feeds the input data shiftin register ch ain.
(2) The 4×clock feeds the input registers for the filter coefficients and other optional registers in the DSP block. See
Note (3).
(3) To increase the DSP block performance, include the pipeline, and output registers. See Figure 7–3 for the detail s.
h
(
0
)
h
(
1
)
h
(
2
)
h
(
3
)
Filter output
y(n)
Note (2)
Clock input
(1x clock)
1x clock
PLL
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
4x clock
Note (1)
x
(n)
x
x
DSP block
Data input
RAM
/
R
O
M
0
RAM
/
R
O
M
1
RAM
/
R
O
M
2
RAM
/
ROM
3
Filt
e
r
c
o
e
ffi
c
i
e
nt
s
7–24 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Finite Impulse Response (FIR) Filters
Polyphase Interpolation Filter Implementation Results
Table 7–11 shows the results of the polyphase interpo lation filter
implementation in a Stratix device shown in Figure 7–13.
Polyphase Interpolation Filter Design Example
Download the Interpolation FIR Filter (interpolation_fir.zip) design
example from the Design Examples section of the Altera web site at
www.altera.com.
Polyphase FIR Decimation Filters
A decimation filter can be used to decr ease the sample rate. A decimation
filter is ef ficiently impl emented with a polyphase FIR filter. DSP systems
frequently us e polyphase filters because the y si mplify overall system
design and also reduce the number of computations per cycle requir ed of
the hardwar e. This section first describes decimation filters and then how
to implement them as polyphase filters in Stratix dev ices. See the
“Polyphase FIR Interpolation Filters” section for a discussion of
interpolation filters .
Decimation Filter Basics
A decimation filter decreases the output sample rate by a factor of D
through keeping only ev ery D-th input sample. Consequently, the
samples at the output of the decimation filter are separated by D×Ts=
D/fs, wher e Ts and fs are the sample period and sample frequency of the
original signal, respectively. Figure 7–14 shows the concept of signal
decimation.
The signal needs to be low pass filtered before downsampling can begin
in order to avoid the reflections of the original spectrum from being
aliased back into the output signal.
Table 7–11. Polyphase Interpolation Filter Implementation Results
Part EP1S10F780
Utilization Lcell: 3/10570 (<1%)
DSP Block 9-bit elements: 8/48 (17%)
Memory bits: 288/920448 (<1%)
Performance 240 MHz (1)
Note to Table 7–11:
(1) This refers to the performance of the DSP blocks, as well as the output clock rate.
The input rate is 60 MSPS, clocked in at 60MHz.
Altera Corporation 7–25
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Figure 7–14. Block Diagram Representation of Decimation
Decimation filters re verse the effect of the interpolation filters. Before the
decimation process, a low pass filter is applied to the signal to attenuate
noise and aliases pr esent beyond th e Nyquist frequency. The filtered
signal is then applied to the decimat ion filter , which pr ocesses every D-th
input. Therefore the values between samples D, D-1, D-2 etc. are ignored.
This allows the filter to run M times slower than the input data rate.
In a typical system, after the analog to digital conversion is c omplete, the
data needs to be filtered to remove aliases inherent in the sampled data.
Further, at this point there is no ne ed to continue to pr ocess this data at
the higher sample (oversampled) rate. Therefore, a decimat ion FIR filte r
at the output of the ADC lowers the data rate to a value that can be
proce ssed digitally.
Figure 7–15 shows a specific example whe r e a si gnal spr ea d over 8 MHz
is decimated by a factor of 4 to 2 MHz. The Nyquist frequency of the
downsampled signal must be greater than 2 MHz, and is chosen to be
2.25 MHz in this example.
D
LPF
Input Output
sample rate fssample rate fs/D
7–26 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Finite Impulse Response (FIR) Filters
Figure 7–15. Time & Frequency Domain Representations of Decimation for D=4
Polyphase Decimation Filters
Figure 7–14 shows a direct implementation of a decimation filter, which
imposes a high computational burden. For example, if the filter is 16 taps
long and a multiplication takes one cycle, the number of computations
required per cycle is 16×D. Depending on the decimation factor (D), this
number can be quite big and may not be achievable in hardware. A
polyphase implementation of the low pass filter can reduce the number
of computations requir ed, often by a large ratio, as will be evide nt later in
this section.
The polyphase implementation “splits” the original filter into D
polyphase filters with impulse responses defined by the following
equation.
hkn() hk nD+()=
Altera Corporation 7–27
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
where:
k = 0,1, …, D-1
n = 0,1, …, P-1
P = L/D = length of polyphase filters
L is the length of the filter (selected to be a multiple of D)
Dis the decimation factor
h(n) is the original filter impulse response
This equation implies that the first polyphase filter, h0(n), has coef ficients
h(0), h(D), h(2D)…h((P-1)D). The second polyphase filter, h1(n), has
coefficients h(1), h(1+D), h(1+2D), ..., h(1+(P-1)D). Continuing in this way,
the last polyphase filter, hD-1(n) has coefficients h(D-1), h((D - 1) + D),
h((D - 1) + 2D), ..., h((D - 1) + (P-1)D).
An example helps in the understanding of the polyphase implementation
of decimation. Consider the polyphase representation of a 16-tap low
pass filter with a decimation factor of 4. The output is given by:
Referring to Figure 7–15 on page 7–26, it is clear that the output, y(n) is
discarded for n ≠ 0, 4, 8, 12, hence the only values of y(n) that need to be
computed are y(0), y(4), y(8), y(12). Table 7–12 shows which coefficients
are required to generate the output samples.
Table 7–12 shows that the overall decimation filter operation can be
represented by 4 parallel polyphase filters. Figure 7–16 shows the
polyphase repr esentation of the decimation filter. A demultiplexer at the
input ensures that the input is applied to only one polyphase filter at a
yn() hi()xnD i–()
i0=
15
∑
=
Table 7–12. Decomposition of a 16-Tap Decimation Filter into Four Polyphase Filters
Output Sample (1) Coefficients Required Polyphase Filter Impulse Response
y(0)0, y(4)0, . . . h(0), h(4), h(8), h(12) h0(n)
y(0)1, y(4)1, . . . h(1), h(5), h(9), h(13) h1(n)
y(0)2, y(4)2, . . . h(2), h(6), h(10), h(14) h2(n)
y(0)3, y(4)3, . . . h(3), h(7), h(11), h(15) h3(n)
Note to Table 7–12:
(1) The output sample is the sum of the results from four p olyphase filters: y(n) = y(n)0 + y(n)1 + y(n)2 + y(n)3.
7–28 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Finite Impulse Response (FIR) Filters
time. The demultiplexer is controlled by a cou n ter, which counts down
modulo-D starting at 0. The overall output is taken by adding the outputs
of all the filters.
The polyphase representation of the decimation filter also reduces the
computational requirement. For the example in Figure 7–16, the direct
implementation requires 16 ×D=16×4 = 64 computations per cycle,
whereas the polyphase implementation requires only 4 ×4×1 = 16
computations per cyc le. This saving in computational com plexity is quite
significant and is often a very convincing reason to use polyphase filters.
Figure 7–16. Polyphase Filter Representation of a D=4 Decimation Filter
D = 4
LPF with
coefficients
h(0), h(1), ... h(15)
Input
x(n)Output
y(n)
Decimation Using a Single Low-Pass Filter
Decimation Using a Polyphase Filter
Polyphase filter
with coefficients
h(0), h(4), h(8), h(12)
Polyphase filter
with coefficients
h(1), h(5), h(9), h(13)
Polyphase Filter
with coefficients
h(2), h(6), h(10), h(14)
Polyphase Filter
with coefficients
h(3), h(7), h(11), h(15)
Output
y(n)
Input
x(n)
Modulo 4 down
counter
initialized at 0
4x clock
0
1
2
3
Altera Corporation 7–29
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Polyphase Decimation Filter Implementation
Figure 7–17 shows the decimation polyphase filter example of
Figure 7–16 as it would fit into St ratix or Stratix GX DSP blocks. The
coefficient s of the polyphase fil ters n eed to be cycled using the schedule
shown in Table 7–13. The output y(n), is clocked using the 1× clock.
Table 7–13. Coefficient Loading Schedule for Polyphase Decimation Filter
(D=4)
Cycle of 4× Clock Coefficients to Load Corresponding RAM/ROM
1, 5,... h(0), h(4), h(8), h(12) 0, 1, 2, 3
2, 6,... h(3), h(7), h(11), h(15) 0, 1, 2, 3
3, 7,... h(2), h(6), h(10), h(14) 0, 1, 2, 3
4, 8,... h(1), h(5), h(9), h(13) 0, 1, 2, 3
7–30 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Finite Impulse Response (FIR) Filters
Figure 7–17. Implementation of the Polyphase Decimation Filter (D=4) Notes (1), (2), (3)
Notes to Figure 7–17:
(1) The 1× clock feeds the register after the accumulator block.
(2) The 4× clock feeds the shift register for the data, the input registers for both the data and filter coefficient s, the other
optional registers in the DSP block (see Note (3)), and the accumulator block.
(3) To increase the DSP block performance, include the pipeline, and output registers. See Figure 7–3 on page 7–8 for
the details.
Filter output
y(n)
Note (2)
Clock input
(1x clock)
R
OM
R
OM
R
O
M
R
OM
1x clock
PLL
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
4x clock
Note (1)
DSP block
Filt
e
r
c
o
e
ffi
c
i
e
nt
s
x
(n)
xx
D
ata
i
n
p
u
t
DQ
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
Altera Corporation 7–31
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Polyphase Decimation Filter Implementation Results
Table 7–14 shows the results of the polyphase decimation filter
implementation in a Stratix device shown in Figure 7–17.
Polyphase Decimation Filter Design Example
Download the Decimation FIR Filter (decimation_fir.zip) design
example from the Design Examples section of the Altera web site at
www.altera.com.
Complex FIR Filter
A complex FI R filter takes r eal and im aginary input signals and performs
the filtering operation with real and imaginary filter coefficients. The
output also consists of real and imaginary signals. Therefore, a complex
FIR filter is similar to a r egular FIR filter except for the fact that the input,
output, and coefficients are all complex numbers.
One example application of complex FIR filters i s equalization. Consider
a Phase Shift Keying (PSK) system; a single complex channel can
repr esent the I and Q data channels. A FIR filter with complex coef ficients
could then process both data channels simultaneously. The filter
coefficient s are chosen in or d er to reverse the effects of intersymbol
interfer ence (ISI) inherent in practical communication channels. This
operation is called equalization. Often, the filter is adaptive, i.e. the filter
coefficients can be varied as desired, to optimize performance with
varying channel characteristics.
A complex variable FIR filter is a cascade of complex multiplications
followed by a complex addition. Figure 7–18 shows a block diagram
representation of a complex FIR filter. To compute the overall output of
the FIR filter, it is first necessary to determine the output of e ach complex
multiplier. This can be expressed as:
Table 7–14. Polyphase Decimation Filter Implementation Results
Part EP1S10F780
Utilization Lcell: 168/10570 (1%)
DSP Block 9-bit elements: 8/48 (17%)
Memory bits: 300/920448(<1%)
Performance 240 MHz (1)
Note to Table 7–14:
(1) This refers to the performance of the DSP blocks, as well as the input clock rate.
The output rate is 60 MSPS (clocked out at 60MHz).
7–32 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Finite Impulse Response (FIR) Filters
where:
xreal is the real input signal
ximag is the imaginary input signal
hreal is the real filter coefficients
himag is the imaginary filter coefficients
yreal is the real output signal
yimag is the imaginary output signal
In complex representation, this equals:
The overall real channel output is obtained by adding the real channel
outputs of all the multipliers. Similarly, the overall imaginary channel
output is obtained by adding the imaginary channel outputs of all the
multipliers.
Figure 7–18. Complex FIR Filter Block Diagram
Complex FIR Filter Implementation
Complex filters can be easily implemented in Stratix devices with the DSP
blocks configured in the two-multipliers adder m ode. One DSP block can
implement a 2-tap complex FIR filter with 9-bit inputs, or a single tap
complex FIR filter with 18-bit inputs. DSP blocks can be cascaded to
implement complex filters with more taps.
1The two-multipliers adder mode has two adders, each adding
the outputs of two multipliers. One of the adders is configured
as a subtractor.
yreal xreal hreal
×ximag himag
×–=
yimag xreal himag
×hreal ximag
×+=
yreal jyimag
+xreal jximag
+()hreal jhimag
+()×=
Complex
FIR filter
xreal
ximag
yreal
yimag
hreal himag
Altera Corporation 7–33
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
fFor more information on the different modes of the DSP blocks, see the
DSP Blocks in Stratix & Stratix GX Devices chapter.
Figure 7–19 shows an example of a 2-tap complex FIR filter design with
18-bit inputs. The real and the complex outputs of the DSP blocks are
added externally to generate the overall r eal and imaginary output. As in
the case of basic, TDM, or polyphase FIR fil ters, the coefficients may be
loaded in series or parallel.
Figure 7–19. 2-Tap 18-Bit Complex FIR Filter Implementation
DSP block Configured as a subtractor
himag1
hreal1
ximag1
xreal1 outreal1 = xreal1 * hreal1 - ximag1 * himag1
outimag1 = xreal1 * himag1 + ximag1 * hreal1
Configured as a adder
DSP block Configured as a subtractor
himag2
hreal2
ximag2
xreal2 outreal2 = xreal2 * hreal2 - ximag2 * himag2
outimag2 = xreal2 * himag2 + ximag2 * hreal2
Configured as a adder
Overall real output
Overall imaginary output
7–34 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Infinite Impulse Response (IIR) Filters
Infinite Impulse
Response (IIR)
Filters
Another class of digital filters are IIR filters. These are re cursive filters
where the current output is dependent on previous outputs. In order to
maintain stability in an IIR fil ter, careful desi gn consideration must be
given, especially to the effect s of word-length to avoid unbounded
conditions. The following section disc usses the general theory and
applications behind IIR Filters.
IIR Filter Background
The impulse response of an IIR filter extends for an infinite amount of
time because their output is based on feedback from previous outputs.
The general expression for IIR filters is:
where ai and bi represent the coeffi ci ents in the feed-forward path and
feedback path, respectively, and n represents the filter order. These
coefficients determine where the poles and zeros of the IIR filter lie.
Consequently, they also determine how the filter functions (i.e., cut-off
frequencies, band pass, low pass, etc.).
The feedback feature makes IIR filters useful in high data throughput
applications that require low hardware usage. However, feedback also
introduces complic ations and caution must be taken to make sure these
filters are not exposed to situations in which they may beco me unstable.
The complications include phase distortion and finite word length effects,
but these can be overcome by ensuring that the filter always operates
within its intended range.
Figure 7–20 shows a direct form II structure of an IIR filter.
yn() ai()xn i–()
i0=
n
∑bi()yn i–()
i1=
n
∑
–=
Altera Corporation 7–35
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Figure 7–20. Direct Form II Structure of an IIR Filter
The transfer function for an IIR filter is:
The numerator contains the zeros of the filter and the denominator
contains the poles. The IIR filter structure requires a multiplication
followed by an accumulation. Constructing the filter directly from the
transfer function shown above may result in finite word length
limitations and make the filter potentiality unstable. This becomes more
critical as the filter order increases, because it only has a finite number of
bits to represent the output. To prevent overflow or instability, the
transfer function can be split into two or more terms r epresenting several
second order filters called biquads. These biquads can be individually
scaled and cascaded, splitting the pole s into multiple s of two. For
example, an IIR filter having ten poles should be split into five biquad
sections. Doing this minimizes quantization and recursive accumulation
errors.
X(n)Σ
-b1a1
Σ
Σ
Σ
Z-1
Z-1
Z-1
Σ
Σ
Σ
Σ
-b2
-bn
Y(n)
a2
an
a0
w(n)
Hz()
aizi–
i0=
n
∑
1b
izi–
i1=
n
∑
+
------------------------------=
7–36 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Infinite Impulse Response (IIR) Filters
This cascaded structur e rearranges the transfer function. This is shown in
the equation below, where each product term is a second orde r IIR filter.
If n is odd, the last pr oduct term is a first or der IIR filter:
Figure 7–21 shows the casc aded structure.
Figure 7–21. Cascaded IIR Filter
Basic IIR Filters
In this section, the basic IIR filter is implemented u si ng cascaded second
order blocks or biquads in the direct form II structure.
Basic IIR FIlter Implementation
Multiplier blocks, adders and delay ele me nts can im plem ent a ba si c IIR
filter. The Stratix architecture lends itself to IIR filters because of its
embedded DSP blocks, which can eas il y be configur ed to perform these
operations. The altmult_add megafunction can be used to implement
the multiplier -ad der mo de in the D SP blocks. Figure 7–22 shows the
implementation of an individual biquad using Stratix and Stratix GX DSP
blocks.
Hz() Ca0k a1kz1–a+2kz2–
+
1b
1kz1–b2kz2–
++
----------------------------------------------------
k1=
n1+()2⁄
∏
×CH
kz()
k1=
n1+()2⁄
∏
×==
x(n) y(n
)
H (z)
1H (z)
kH (z)
n
C
Altera Corporation 7–37
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Figure 7–22. IIR Filter Biquad Note (1)
Note to Figure 7–22:
(1) Unused ports are grayed out.
7–38 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Infinite Impulse Response (IIR) Filters
The first DSP block in Figure 7–22 is configured in the two-multipliers
adder mode, and the second DSP block is in the four-multipliers adder
mode. For an 18-bit input to the IIR filter, each biquad requires five
multipliers and five adders (two DSP blocks). One of the adders is
implemented using logic elements. Cascading several biquads together
can implement more complex, higher order IIR filte rs . It is poss ible to
insert registers in between the biquad stages to improv e the performance.
Figure 7–23 shows a 4thorder IIR filt er realized usin g two cascaded
biquads in three DSP blocks.
Figure 7–23. Two Cascaded Biquads
x[n]
First
biquad
Second
biquad
y[n]
Two-multipliers
adder mode
DSP
block 2
Four-multipliers
adder mode
DSP
block 3
Four-multipliers
adder mode
DSP
block 1
a20
a21
b22
b21
a12
a22
a10
a11
b12
b11
Altera Corporation 7–39
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Basic IIR Filter Implementation Results
Table 7–15 shows the results of implementing a 4th order IIR filter in a
Stratix device.
Basic IIR Filter Design Example
Download the 4th Order IIR Filter (iir.zip) design example from the
Design Examples section of the Altera web site at www.altera.com.
Butterworth IIR Filters
Butterworth filters are the most popular version of IIR analog filters.
These filters are also known as “maximally flat” because they have no
passband ripple. Additional ly, they have a monotonic response in both
the stopband and the passband. Butterworth filters trade-off roll off
steepness for their no ripple characteristic. The distinguishing
Butterworth filter feature is its poles are arranged in a uniquely
symmetrical manner along a circle in the s-pla ne. The expression for the
Butterworth filter’s magnitude-squared function is as follows:
where:
ωc is the cut-off frequency
N is the filter order
The filter’s cutoff characteristics become sharper as N increases. If a
substitution is made such that jω = s, then the following equation is
derived:
Table 7–15. 4th Order IIR Filter Implementation Results
Part EP1S10F780C5
Utilization Lcell: 102/10570(<1%)
DSP Block 9-bit elements: 24/48 (50%)
Memory bits: 0/920448(0%)
Performance 73 MHz
Latency 4 clock cycles
Hcjω()
21
1jω
jωc
-------
⎝⎠
⎛⎞
2N
+
----------------------------=
7–40 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Infinite Impulse Response (IIR) Filters
with poles at:
for k=0,1,…,2N-1
There are 2N poles on the circle with a radius of ωc in the s-plane. These
poles are evenly spaced at π/N intervals along the circle. The poles chosen
for the implementation of the filter lie in the left half of the s-plane,
because these generate a stable, causal filter.
Each of the impulse invariance, the bilinear, and matched z transforms
can transform the Laplace transform of the Butterworth filter into the z-
transform.
■Impulse invariance transforms take the inverse of the Laplace
transform to obtain the impulse r esponse , then perform a
z-transform on the sampled impulse response. The impulse
invariance method can cause some aliasing.
■The bilinear transform maps the entire jω-axis in the s-plane to one
revolution of the unit cir c le in the z-plane. This is the most popular
method because it inherently eliminates alias in g.
■The matched z-transform maps the poles and the zeros of the filter
directly from the s-plane to the z-plane. Usually, these transforms are
transparent to the user because seve ral tools, such as MATLAB, exist
for determining the coefficients of the filter. The z-transform
generates the coefficients much like in the basic IIR filter discussed
earlier.
Butterworth Filter Implementation
For digital designs, consideration must be made to optimize the IIR
biquad structure so that it maps optimally into logic. Because speed i s
often a critical requir ement, the goal is to reduce the number of
operations per biquad. It is possible to reduce the number of multipliers
needed in each biquad to just two.
Hcs()Hcs–() 1
1s
jωc
-------
⎝⎠
⎛⎞
2N
+
----------------------------=
sk1–()
1
2N
------- jωc
()=
ωce
jπ
2N
-------
⎝⎠
⎛⎞
2k N 1–+()
=
Altera Corporation 7–41
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Through the use of integer feedforward multiplies, which can be
implemented by combining addition, shifting, and complimenting
operations, a Butterworth filter’s transfer function biquad can be
optimized for logic synthesis. The most efficient transformation is that of
an all pole filter. This is because ther e is a unique r elationship between the
feedforward integer coefficients of the filter represented as:
As can be seen by this equation, the z-1 coefficient in the numerator
(representin g the feedforward path) is twice the other two operands (z-2
and 1). This is always the case in the transfo r mation from the fr equency
to the digital domain. T his represents the normalized response, which i s
faster and smaller to implement in hardware than real multipliers. It
introduces a scaling factor as well, but this can be corrected at the end of
the cascade chain through a single multiply.
Figure 7–24 shows ho w a Butte rworth filter biquad is implemented in a
Stratix or Stratix GX device.
Hz() 12z
1–z2–
++
1b
1z1–b2z2–
++
-------------------------------------------=
7–42 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Infinite Impulse Response (IIR) Filters
Figure 7–24. Butterworth Filter Biquad Notes (1), (2)
Notes to Figure 7–24:
(1) Unused ports are grayed out.
(2) The z-1 coefficient is a multiple of the other coefficients (z-2 and 1) in the
feedforward path. This is implemented using a shift operation.
w(n-1)
w(n-2)
b1
b
2
w(n)
w(n-1)
y(n)
x
(
n
)
DSP block
w(n)
DQ
D
Q
Altera Corporation 7–43
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
The DSP block in Figure 7–24 is co nfigured in multiply and add mo de.
The three external adders are implemented in logic ele me nt s and
therefor e are not part of the DSP block. Therefore, for an 18-bit input, each
biquad requires half a DSP block and three logic element adders. The gain
factor can be compensated for at the end of the filtering stage and is not
shown in this simple example. More complex, higher order Butterworth
filters can be realized by cascading several biquads together, as in the IIR
example. Figure 7–25 below shows a 4th order Butterworth filter using
two cascaded biquads in a single DSP block.
7–44 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Infinite Impulse Response (IIR) Filters
Figure 7–25. Cascaded Butterworth Biquads Note (1)
Note to Figure 7–25:
(1) The gain factor is compensated for at the end of the filtering stage and is not shown in this figure.
D Q
D Q
D Q
D Q
w1(n-1)
b11
w1(n-2)
b12
D Q
D Q
w2(n-1)
b21
w2(n-2)
b22
w1(n)
w1(n-2)
DSP
block
w2(n)
D Q
D Q
w2(n-2)
w2(n-1)
y(n)
x(n)
w1(n-1)
Second
biquad
First
biquad
D Q
D Q
D Q
D Q
Altera Corporation 7–45
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Butterworth Filter Implementation Results
Table 7–16 shows the results of implementing a 4th order Butterworth
filter as shown in Figure 7–25.
Butter w or th Filter Design Example
Download the 4th Order Butterworth Filter (butterworth.zip) de sign
example from the Design Examples section of the Altera web site at
www.altera.com.
Matrix
Manipulation DSP relies heavily on matrix manipulation. The key idea is to transform
the digital signals into a format that can then be manipulated
mathematically.
This section desc ribes an example of matrix manipulation used in 2-D
convolution filter, and its implementation in a Stratix device.
Background on Matrix Manipulation
A matrix can represent all digital signals. Apart from the convenience of
compact notation, matrix representation also exploits the benefits of
linear algebra. As with one-dimensional, discrete sequences, this
advantage becomes more apparent when processing multi-dimensional
signals.
In image processing, matrix manipulation is important because it
requir es analysis in the spatial do main. Smoothing, tr end r eduction, and
sharpening are examples of common image processing operations, which
are performed by convolution. This can also be viewed as a digital filter
operation with the matrix of filter coefficients forming a convolutional
kernel, or mask.
Table 7–16. 4th Order Butterworth Filter Implementation Results
Part EP1S10F780C6
Utilization Lcell: 251/10570(2%)
DSP Block 9-bit elements: 16/48 (33%)
Memory bits: 0/920448 (0%)
Performance 80 MHz
Latency 4 clock cycles
7–46 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Matrix Manipulation
Two-Dimensional Filtering & Video Imaging
FIR filtering for video applications and image processing in general is
used in many applications, including noise removal, image sharpening to
featur e extraction.
For noise removal, the goal is to reduce the effects of undesirable,
contaminative signals that have been linearly added to the image.
Applying a low pass filter or smoothing function flattens the image by
reducing the rapid pixel-to-pixel variation in gray levels and, ultimately,
removing noise. It also has a blurring effect us ually used as a pr ecursor
for removing unwanted details before extracting certain features from the
image.
Image sharpening focuses on the fine details of the image and enhances
sharp transitions between the pixels. This acts as a high-pass filter that
reduc es broad features like the uniform background in an image and
enhances compact features or details that have been blurred.
Feature extraction is a form of image analysis slightly different from
image processing. The goal of image analysis in general is to extract
information based on certain characteristics from the image. This is a
multiple step process that includes edge detection. The easiest form of
edge detection is the derivative filter, using gradient operators.
All of the operations above involve transformation of the input image.
This can be presente d a s the convolution of the two-dimensi onal input
image, x(m,n) with the impulse respo nse of the transform, f(k,l), resulting
in y(m,n) which is the output image.
The f(k,l) function refers to the matrix of filte r coefficients. Because the
matrix operation is analogous to a filter operation, the matrix itself is
considered the impulse response of the filter. Depending on the type of
operation, the choice of the co nv olutional kernel or mask, f(k,l) is
different. Figure 7–26 shows an example of convolving a 3 ×3 mask with
a larger image.
ym n,()fk l,()xm n,()⊗=
ym n,() fk l,()xm k n l–,–()
lN–=
N
∑
kN–=
N
∑
=
Altera Corporation 7–47
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Figure 7–26. Convolution Using a 3 ×3 Kernel
The output pixel value, y(m,n) depends on the surrounding pixel values
in the input image, as well as the fil ter weights:
To complete the transformation, the kernel slides acr oss the entire image.
For pixels on the edge of the image, the convolution operation does not
have a complete set of input data. T o work around this problem, the pixels
on the edge can be left unchanged. In some cases, it is acceptable to have
an output image of reduced size. Alternatively, the matrix effect can be
applied to edge pixels as if they are surrounded on the “empty” side by
ym n,()w1xm 1 n 1–,–()w2xm 1 n,–()w3xm 1 n 1+,–()++=
+ w4xm n 1–,()w5xm n,()w6xm n 1+,()++
+ w7xm 1+n1–,()w8xm 1 n,+()w9xm 1 n 1+,+()++
7–48 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Matrix Manipulation
black pixels, that is pixels with valu e zero. This is similar to padding the
edges of the input image matrix with zeros and is referr ed to as the free
boundary condition. This is shown in Figure 7–27.
Figure 7–27. Using Free Boundary Condition for Edge Pixels
Convolution Implementat ion
This design example shows a 3 ×3 2-D FIR filter that takes in an 8 ×8
input image with gray pixel values ranging fr om 0-255 (8-bit). Data is fed
in serially starting from the top left pixel, moving horizontally on a row-
by-row basis. Next the data is stor ed in thr ee separate RAM blocks in the
buffering stage. Each M 512 memory block r epr esents a line o f the image,
and this is cycled through. For a 32 ×32 input image, the design needs
M4K memory blocks. For lar ger images (640 ×480), this can be extended
to M-RAM blocks or other buffering schemes. The control logic block
provides the RAM control signals to interleave the data across all three
x
(
x
x
m
+
1
,
n
+
1
)
x
(
x
x
m
+
1
,
n
)
x
(
xx
m
,
n
+
1
)
0
x
(
xx
3
x 3 kernel slides across ima
g
e
0
0
0
0
Image boundar
y
Ima
g
e
Image boundary
Altera Corporation 7–49
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
RAM blocks. The 9-bit signed fil ter coefficients feed d irectly into the filt er
block. As the data is shifted out from the RAM blocks, the multiplexer
block checks for edge pixels and uses the free boundary condition.
Figure 7–28 shows a top-level diagram of the design.
Figure 7–28. Block Diagram on Implementation of 3 ×3 Convolutional Filter for an 8 ×8 Pixel Input Image
The 3 ×3 filter block implements the nine multiply-add operations in
parallel using two DSP blocks. One DSP block can implement eight of
these multipliers. The second DSP block implements the ninth multiplier .
The first DSP block is in the four-multipliers adder mode, and the second
is in simple multi plier mode. In addition to the two DSP blocks, an
external adder is re quired to sum the output of all nine multipliers.
Figure 7–29 shows this implemen tation.
7–50 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Matrix Manipulation
Figure 7–29. Implementation of 3 ×3 Convolutional Filter Block
DSP Block in Four-Multipliers Adder Mode (9-bit)
LE implemented
adder
DSP Block in Sim
p
le Multi
p
lier Mode
(
8-bit
)
w9
x(m + 1, n + 1)
w8
x(m + 1, n )
w7
x(m + 1, n - 1)
w6
x(m , n + 1)
w5
x(m , n )
w4
x(m , n - 1)
w3
x(m - 1, n + 1)
w2
x(m - 1, n )
w1
x(m - 1, n - 1)
y(m , n )
Note: Unused multipliers and
adders grayed out. These
multipliers can be used by other
functions.
Altera Corporation 7–51
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
In cases where a symmetric 2-D fil ter is used, pixel s sharing the same
filter coeffi cients from thr ee separate line-stores A, B, and C can be added
together prior to the multiplication operation. This reduces the number of
multipliers used. Referring to Figure 7–30, w1, w2, and w3 are the filter
coefficients. Figure 7–31 shows the implementation of this circular
symmetric filter.
Figure 7–30. Symmetric 3 ×3 Kernel
Figure 7–31. Details on Implementation of Symmetric 3 ×3 Convolution Filter Block
DSP Block - Four Multipliers
Adder Mode (9-bit)
Logic Elements
G
N
D
w
3
w
w
w
2
w
w
w1
y
y
(m , n )
G
N
D
A
B
C
Note: Unused multipliers and adders grayed out. These
multipliers can be used by other functions.
7–52 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Discrete Cosine Transform (DCT)
Convolution Implementation Results
Table 7–17 shows the results of the 3 ×3 2-D FIR filter implementation in
Figure 7–28.
The design r equires the input to be an 8 ×8 image, with 8-bit input data
and 9-bit filter coef ficient width. The output is an image of the same size.
Convolution Design Example
Download the 3 ×3 2-D Convolutional Filter (two_d_fir.zip) design
example from the Design Examples section of the Altera web site at
www.altera.com.
Discrete Cosine
Transform (DCT) The discrete cosine transform (DCT) is widely used in video and audio
compr ession, for example in JP EG, MPEG video, and MP EG audio. It is a
form of transform coding, which is the preferred method for compression
techniques. Images tend to compact their energy in the frequency domain
making compression in the frequency domain much mor e ef fective. This
is an important element in compressing data, wher e the go al is to have a
high data compression rate without significant degradatio n in the image
quality.
DCT Background
Similar to the discr ete fourier transform (DFT), the DCT is a function that
maps the input signal or image fr om the spatial to the fr equency domain.
It transforms the input into a linear combination of weighted basis
functions. These basis functions are the frequency components of the
input data.
Table 7–17. 3 × 3 2-D Convolution Filter Implementation Results
Part EP1S10F780
Utilization L cell: 372/10570 (3%)
DSP block 9-bit elements: 9/48 (18%)
Memory bits: 768/920448 (<1%)
Performance 226 MHz
Latency 15 clock cycles
Altera Corporation 7–53
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
For 1-D with input data x(n) of size N, the DCT coeffi ci ents Y(k) are:
for 0 ≤ k ≤ N–1
where:
for k = 0
for 1 ≤ k ≤ N –1
For 2-D with input data x(m,n) of size N × N, the DCT coefficients for the
output image, Y(p,q) are:
where:
for p = 0
for q = 0
for 1 ≤ p ≤ N –1
for 1 ≤ q ≤ N–1
2-D DCT Algorithm
The 2-D DCT can be thought of as an extended 1-D DCT applied twice;
once in the x dir ection and again in the y direction. Because the 2-D DCT
is a separable transform, it is possible to calcul ate it u si ng efficient 1-D
algorithms. Figure 7–32 illustrates the concept of a separable transform.
Yk() αk()
2
----------- xn() 2n 1+()πk
2N
---------------------------
⎝⎠
⎛⎞
cos
n0=
N1
–
∑
=
αk() 1
N
----=
αk() 2
N
----=
Yp q,()
αp()αq()
2
-----------------------xm n,()2m 1+()πp
2N
-----------------------------
⎝⎠
⎛⎞
cos 2n 1+()πq
2N
---------------------------
⎝⎠
⎛⎞
cos
n0=
N1–
∑
m0=
N1–
∑
=
αp() 1
N
----=
αq() 1
N
----=
αp() 2
N
----=
αq() 2
N
----=
7–54 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Discrete Cosine Transform (DCT)
Figure 7–32. A 2-D DCT is a Separable Transform
This section uses a standard algorithm proposed in [1]. Figure 7–33
shows the flow graph for the algorithm. This is similar to the butterfly
computation of the fast fourier transform (FFT). Similar to the FFT
algorithms, the DCT algorithm r educes the complexity of the calculation
by decomposing the computation into successively smaller DCT
components. The even coefficients (y0, y2, y4, y6) are calculated in the
upper half and the odd coefficients (y1, y3, y5, y7) in the lower half. As a
result of the decomposition, the output is reordere d as well.
Figure 7–33. Implementing an N=8 Fast DCT
Stage 1 Stage 4
Stage 3
Stage 2
x0
x7
x6
x5
x4
x3
x2
x1
y0
y7
y5
y3
y1
y6
y2
y4
yk = cm1s31 + cm2s32 + ... + cmns3n
cx = cos(16
x π)
Multiplied by -1
b
aSum a and b
Multiply-addition block
Cm1
yk
S32
S31Cm2
Cmn
.
.
.
.
.
.
.
S3n
C7
C5
C3
C1
C6
C2C6
-C2
C4
-C5
-C1
-C7
C3
C3
C7
-C1
C5
-C1
C3
-C5
C7
Stage 3 output (S3)
Matrix coefficent (Cmn)
where
Altera Corporation 7–55
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
The following defines in matrix format, the 8-point 1-D DCT of
Figure 7–33:
where:
[x] is the 1 ×8 input matrix
Y1D xAdd1
×Add2
×Add3C
××=
Add1
10000001
01000010
00100100
00011000
0001 1–000
00100 1–00
010000 1–0
1000000 1–
=
Add2
10010000
01100000
01 1–00000
100 1–0000
00001000
00000100
00000010
00000001
=
Add3
11000000
11–000000
00100000
00010000
00001000
00000100
00000010
00000001
=
7–56 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Discrete Cosine Transform (DCT)
All of the additions in stages 1, 2 and 3 of Figure 7–32 appear in
symmetric add and subtract pairs. The entire first stage is simply four
such pairs in a very typical cross-over pattern. This pattern is r epeated in
stages 2 and 3. Multiplication operations are confined to stage 4 in the
algorithm. This impl ementation is shown in more detail in the next
section.
DCT Implementation
In taking advantage of the separa ble transform property of the DCT, the
implementation can be divided into separate stages; row pr ocessing and
column processing. Howev er, some data restructuring is nece ssary
before applying the column processing stage to the r esults from the row
processing stage. The data buffering stage must transpose the data first.
Figure 7–34 shows the differ ent stages.
Figure 7–34. Three Separate Stages in Implementing the 2-D DCT
Because the r ow processing and column processing blocks share the same
1-D 8-point DCT algorithm, the hardware implementation shows this
block as being shared. The DCT algorithm requires a serial-to-parallel
conversion block at the input because it works on blocks of eight data
C
10000000
0C
4000000
00C
6C–20000
00C
2C60000
0000C
7C–5C3C–1
0000C
5C–1C7C3
0000C
3C–7C–1C–5
0000C
1C3C5C7
=
Cxπx
16
------cos=
Row
processing Column
processing
Transpose
matrix
Altera Corporation 7–57
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
points in parallel. Ther e is also a parallel-to-serial conversion blo ck at the
output because the column processi ng stag e generates the output image
column-by-column. In order to have the output in the same order as the
input (i.e., row-by-r ow), this conversion is necessary. Appropriate scaling
needs to be applied to the completed transform but this can be combined
with the quantization stage which often follows a DCT [1]. Figure 7–35
shows a top-level block diagram of this design.
Figure 7–35. Block Diagram on Serial Implementation of 2-D DCT
The implementation of the 1-D DCT block is based on the algorithm
shown in Figure 7–33. The simple addition and s ubtraction operations in
stages 1, 2 and 3 are implemented using logic cells. The multiply and
multiply-addition operations in stage 4 are implemented using DSP
blocks in the Stratix device in the simple multiplier mode, two-multiplier
adder mode, and the four-multiplier adder mode. An example of the
multiply-addition block is shown in Figure 7–36.
7–58 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Discrete Cosine Transform (DCT)
Figure 7–36. Details on the Implementation of the Multiply-Addition Operation
in Stage 4 of the 1-D DCT Algorithm
Note to Figure 7–36:
(1) Referring to Figure 7–33. S3n is an output from stage 3 of the DCT and Cmn is a
matrix coefficient. Cx=cos (xπ/16).
DCT Implementation Results
Table 7–18 shows the results of implementing a 2-D DCT with 18-bit
precision, as shown in Figure 7–35.
DCT Design Example
Download the 2-D convolutiona l filter (d_dct.zip) design example from
the Design Examples section of the Altera web site at www.altera.com.
Table 7–18. 2-D DCT Implementation Results
Part EP1S20F780
Utilization Lcell: 1717/18460 (9%)
DSP Block 9-bit element: 18/80 (22%)
Memory bits: 2816/1669248 (<1%)
Performance 165 MHz
Latency 80 clock cycles
DSP Block - Four-Multipliers Adder Mode (18-bit)
Cm1
Cm2
Cm3
Cm4
S31
y
k
S34
S33
S32
Altera Corporation 7–59
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Arithmetic
Functions Arithmetic functions, such as trigonometric functions, including sine,
cosine, magnitude and phase calculation, are important DSP elements.
This section discusses the implementation of a simple vector magnitude
function in a Stratix device.
Background
Complex numbers can be expressed in two parts: real and imaginary.
where:
a is the real part
b is the imaginary part
j2= –1
In a two-dimensional plane, a vector (a,b) with refer ence to the origin
(0,0) can also be represented as a complex number. In essence, the x-axis
repr esents the real part , and the y-axis repr esents the imaginary part (see
Figure 7–37).
Figure 7–37. Magnitude of V ector (a,b)
Complex numbers can be converted to phas e and amplitude or
magnitude representation, using a Cartesian-to-polar coordinate
conversion. For a vector (a,b), the phase and magnitude r epresentation is
the following:
zajb+=
7–60 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Arithmetic Functions
Magnitude
Phase angle θ = tan-1(b/a)
This conversion is useful in different applications, such as position
control and position monitoring in robotics. It is also important to have
these transformations at very high speeds to accommodat e real-time
processing.
Arithmetic Function Implementation
A common approach to implementing th ese arithmetic functions is using
the coordinate rotation digital computer (CORDIC) algorithm. The
CORDIC algorithm calculates the trigonometric functions of sine, cosine,
magnitude, and phase using an iterative process. It is made up of a series
of micro-rotations of the vector by a set of predetermined constants,
which are powers of 2.
Using binary arithmetic, this algori thm es sentially replaces multipliers
with shift and add operat ions. In Stratix devices, it is poss ible to calculate
some of these arithmetic functions dir ectly, without having to implement
the CORDIC algorithm.
This section describes a desi gn exampl e tha t calculates the magnitud e of
a 9-bit signed vector (a,b) using a pipelined version of the square root
function available at the Altera IP Megastore. To calculate the sum of the
squares of the input (a2 + b2), configure the DSP block in the two-
multipliers adder mode. The square root function is implemented using
an iterative algorithm similar to the long division operatio n. The binary
numbers are paired off, and subtracted by a trial number. Depending on
if the remainder is positive or negative, each bit of the square root is
determined and the process is repeated. This square root function does
not require memory and is implemented in logic cells only.
In this example, the input bit precision (IN_PREC) feeding into the squar e
root ma cro is set to twenty, and the output precision (OUT_PREC) is set to
ten. The number of pr ecision bits is parameterizable. Also, there is a third
parameter, PIPELINE, which controls the ar chite cture of the square r oot
macro. If this parameter is set to YES, it includes pipeline stages in the
square root macr o . If se t to NO, the square root macro becomes a single-
cycled combinatorial function.
Figure 7–38 shows the implementation the magnitude design.
ma
2b2
+=
Altera Corporation 7–61
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Figure 7–38. Implementing the Vector Magnitude Function
DSP Block - Two Multipliers
Adder Mode (9-bit)
a
b
Note: Unused multipliers
and adders grayed out.
LE implemented
square root function
7–62 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Conclusion
Arithmetic Function Implementation Results
Table 7–19 shows the result s of the implementation shown in Figure 7–38
with the PIPELINE parameter set to YES. Table 7–20 shows the results of
the implementation shown in Figure 7–38 with the PIPELINE parameter
set to NO.
Arithmetic Function Design Example
Download the Vector Magnitude Function (magnitude.zip) design
example from the Design Examples section of the Altera web site at
www.altera.com.
Conclusion The DSP blocks in Stratix and Stratix GX devices are optimized to support
DSP functions requiring high data throughput, such as FIR filters, IIR
filters and the DCT. The DSP blocks are flexible and configurable in
different operation modes based on the application’s needs . The
TriM atrix memory provides the data storage capability often needed in
DSP applications.
The DSP blocks and TriMatrix memory in Stratix and Stratix GX devices
offer perform ance and flexibility that translates to higher performance
DSP functions.
Table 7–19. Vector Magnitude Function Implementation Results
(PIPELINE=YES)
Part EP1S10F780
Utilization Lcell: 497/10570 (4%)
DSP block 9-bit elements: 2/48 (4%)
Memory bits: 0/920448 (0%)
Performance 194 MHz
Latency 15 clock cycles
Table 7–20. Vector Magnitude Function Implementation Results
(PIPELINE=NO)
Part EP1S10F780
Utilization L cell: 244/10570 (2%)
DSP block 9-bit elements: 2/48 (4%)
Memory bits: 0/920448 (0%)
Performance 30 MHz
Latency 3 clock cycles
Altera Corporation 7–63
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
References See the following for more information:
■Optimal DCT for Hardwa re Implem entation
M. Langhammer. Proceedings of Internatio nal Confer ence on Signal
Processing Applications & Technology (ICSPAT) '95, October 1995
■Digital Signal Processing: Principles, Algorithms, and Applications
John G. Proakis, Dimitris G. Manolakis. Prentice Hall
■Hardware Implementation of Multirate Digital Filters
Tony San. Communication Systems Design, April 2000
■AN 73: Implementing FIR Filters in FLEX Devices
■Efficient Logic Synthesis Techniques for IIR Filters
M.Langhammer. Proceedings of International Conference on Signal
Processing Applications & Technology (ICSPAT) '95, October 1995
7–64 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
References
Altera Corporation Sectio n V–1
Section V. IP & Design
Considerations
This section pr ovides docu mentation o n some of the IP functions offe red
by Altera® for Stratix® devices. (Also see the Intellectual Prope rty section
of the Altera web site for a complete offering of IP cores for Stratix
devices.) The last chapter detail s des ign considerations for migrating
from the APEX™ architecture.
This section contains the following chapters:
■Chapter 8, Implementing 10-Gigabit Ethernet Using Stratix &
Stratix GX Devices
■Chapter 9, Implementing SFI-4 in Stratix & Stratix GX Devices
■Chapter 10, Transitioning APEX Designs to Stratix & Stratix GX
Devices
Revision History The table below shows the rev ision hist ory for Chapters 8 through 10.
Chapter Date/Version Changes Made
8 July 2005, v2.0 Updated Stratix GX device information.
September 2004, v1.2 ●Table 8–2 on page 8–10: updated table, deleted Note 1, and updated
Note 2.
●Updated Table 8–4 on page 8–12.
November 2003, v1.1 ●Removed support for series and parallel on-chip termination.
April 2003, v1.0 ●No new changes in Stratix Device Handbook v2.0.
9 July 2005, v2.0 ●Updated Stratix GX device information.
September 2004, v1.1 ●Table 9–2 on page 9–9: updated table , deleted Note 1, and updated
Note 2.
●Updated Table 9–4 on page 9–10.
April 2003, v1.0 ●No new changes in Stratix Device Handbook v2.0.
Section V–2 Altera Corporation
IP & Design Considerations Stratix Device Handbook, Volume 2
10 July 2005, v3.0 ●Updated Stratix GX device information.
September 2004, v2.1 ●Updated Table 10–9 on page 10–26.
April 2004, v2.0 ●Synchronous occurrences renamed pipelined.
●Asynchronous occurrences renamed flow-through.
November 2003, v1.2 ●Removed support for series and parallel on-chip termination.
October 2003, v1.1 ●Updated Table 10–6.
April 2003, v1.0 ●No new changes in Stratix Device Handbook v2.0.
Chapter Date/Version Changes Made
Altera Corporation 8–1
July 2005
8. Implementing 10-Gigabit
Ethernet Using Stratix &
Stratix GX Devices
Introduction Ethernet has evolved to meet ever-increasi ng bandwidth demands and is
the most prevalent local-area network (LAN) communications pro tocol.
10-Gigabit Ethernet extends that pr otocol to higher bandwidt h for future
high-speed applications. The accelerated growth of network traffic and
the resulti n g inc rease in bandwidth requirements is driving service
providers and enterprise network architects towards high-speed network
solutions. Potential applications for 10-Gigabit Ethernet include private
campus or LAN backbones, high-speed access links between service
providers and enterprises, and aggregation and transport in metropolitan
area networks (MANs).
The I/O features of Stratix® and Stratix GX devices enable support for 10-
Gigabit Ethernet, supporting 10-Gigabit 16-bit interface (XSBI) and 10-
Gigabit medium independe nt inte rface (XGMII). Stratix GX devices can
additionally support the 10-gigabit attachment unit interface (XAUI)
using the embedded 3.125-Gbps transceivers. You can find more
information on XAUI support in Section II, Stratix GX Transceiver User
Guide, of the Stratix GX De vice Handbook, Volume 1.
This chapter discusses the following topics:
■Fundamentals of 10-Gigabit Ethernet
■Description and implementation of XSBI
■Description and implementation of XGMII
■Description of XAUI
■I/O characteristics of XSBI, XGMII, and XAUI
Related Links
■10-Gigabit Ethernet Alliance at www.10gea.org
■The Stratix Device Family Data Sheet section of the Stratix Device
Handbook, Volume 1 and the Stratix GX Device Family Data Sheet
section of the Stratix GX Device Handbook, Volume 1
■The High-Speed Differential I/O Interfaces in Stra tix Devices chapter
10-Gigabit
Ethernet Ethernet speed has increased to keep pace with demand, initially to
10 megabits per second (Mbps), later to 100 Mbps, and recently to
1 gigabit per second (Gbps). Ethernet is the dominant network
technology in LANs, and with the advent of 10-Gigabit Ethernet , i t is
entering the MAN and wide area network (WAN) markets.
S52010-2.0
8–2 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
10-Gigabit Ethernet
The purpose of the 10-Gigabit Ethernet proposed standard is to extend
the operating speed to 10 Gbps defined by pr otocol IEEE 802.3 and
include WAN applications. These additions provide a significant increase
in bandwidth while maintaining maximum compatibility with current
IEEE 802.3 interfaces.
Since its inception in Mar ch 1999, the 10-Gigabit Etherne t Task Force has
been working on the IEEE 802.3ae Standard. Some of the information in
the following sections is derived from Clauses 46, 47, 49, and 51 of the
IEEE Draft P802.3ae/D3.1 document. A fully ratified standard is
expected in the first half of 2002. Figure 8–1 shows the relationship of
10-Gigabit Ethernet to the Open Systems Interconnection (OSI) protocol
stack.
Figure 8–1. 10-Gigabit Ethernet Protocol in Relation to OSI Protocol Stack
Notes to Figure 8–1:
(1) LLC: logical link controller
(2) MAC: media access controller
(3) PCS: physical coding sublayer
(4) PHY: phys ic al lay e r
(5) PMA: physical medium attachment
(6) PMD: physical medium dependent
(7) MDI: medium dependent interface
Application
Presentation
Session
Transport
Network
Data Link
Physical
Higher Layers
LLC (1)
MAC (2)
Reconciliation
PCS (3)
PMA (5)
PMD (6)
Medium
XGMII
XSBI
MDI (7)
PHY (4
)
OSI Reference
Model Layers
Altera Corporation 8–3
July 2005 Stratix Device Handbook, Volume 2
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
The Ethernet PHY (layer 1 of the OSI model) connects the medi a (optical
or copper) to the MAC (layer 2). The Ethernet ar chitecture further divides
the PHY (layer 1) into a PMD sublayer, a PMA sublayer, and a PCS. For
example, optical transceivers are PMD sublayers. The PMA converts the
data between the PMD sublayer and the PCS sublayer. The PCS is made
up of coding (e.g., 8b/10b, 64b/66b) and serializer or multiplexing
functions. Figure 8–2 shows the components of 10-Gigabit Ethernet and
how Altera implements certain blocks and interfaces.
10-Gigabit Ethernet has three different implementations for the PHY:
10GBASE-X, 10GBASE-R, and 10GBASE-W. The 10GBASE-X
implementation is a PHY that supports the XAUI interface. The XAUI
interface used in conjunction with the XGMII extender sublayer (XGXS)
allows more separati o n in di stance betwe en the MAC and PH Y.
10GBASE-X PCS uses four lanes of 8b/10b coded data at a rate of
3.125 Gbps. 10GBASE-X is a wide wave div ision m ultiplexing (WWD M)
LAN PHY. 10GBASE-R and 10GBASE-W are serial LAN PHYs and serial
WAN PHYs, respectively. Unlike 10GBASE-X, 10G BASE-R and
10GBASE-W implementations have a XSBI interface and ar e described in
more detail in the following section.
8–4 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
10-Gigabit Ethernet
Figure 8–2. 10-Gigabit Ethernet Block Diagram
Notes to Figure 8–2:
(1) The reconciliation sublayer (RS) interfaces the serial MAC data stream and the parallel data of XGMII.
(2) The XGMII extender sublayer (XGXS) extends the distance of XGMII when used with XUAI and provides the data
conversion between XGMII and XAUI.
(3) The WAN interface sublayer (WIS) impl em e nts th e OC-19 2 framing and scram b ling fu nc ti ons.
PCS
PMA
PCS
PMA
WIS (3)
10GBASE-R 10GBASE-W
XGMII (32 Bits at 156.25 Mbps DDR 1.5-V HSTL)
MAC
RS (1)
XGXS (2) 8b/10b
XAUI (4 Bits at 3.125 Gbps PCML)
XGMII (32 Bits at 156.25 Mbps DDR 1.5-V HSTL)
8b/10b
PHY
MDI
10GBASE-X
64b/66b8B/10B
XSBI (16 Bits at
622.08 Mbps LVDS)
64b/66b
OC-192 Framing
Interface directly covered in this
application note
Interface indirectly covered in this
application note
Can be implemented in Altera PLDs
XGXS
PCS
MDI
XSBI (16 Bits at
644.5 Mbps LVDS)
PMD
PMD
PMA
PMD
Altera Corporation 8–5
July 2005 Stratix Device Handbook, Volume 2
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
Interfaces The following sections discuss XSBI, PCS, XGMII, and XAUI.
XSBI
One of the blocks of 10-Gigabit Ethernet is the XSBI inte rface. XSBI is the
interface between the PCS and the PMA sublayers of the PHY la yer of the
OSI model. XSBI supports two types of PHY layers, LAN PHY and WAN
PHY. The LAN PHY is part of 10GBASE-R, and supports existing
Gigabit Ethernet applications at ten times the bandwidth. The WAN PHY
is part of 10GBASE-W, and supports connections to existing and future
installations of SONET/SDH circuit-switched access equipment.
10GBASE-R is a physical laye r implementation that is comprised of the
PCS sublayer, the PMA, and the PMD. 10GBASE-R is based upon
64b/66b data coding. 10GBASE-W is a PHY layer implementation that is
comprised of the PCS sublayer, the WAN interface sublayer (WIS), the
PMA, and the PMD. 10GBASE-W is based on STS-192c/SDH VC-4-64c
encapsulation of 64b/66b encoded data. Figure 8–3 shows the
construction of these two PHY layers.
Figure 8–3. XSBI Interface for the Two PHY Layers
PCS
PMA
PMD
Medium
PCS
PMA
PMD
Medium
WIS
XSBI
MDI
10GBASE-R 10GBASE-W
PHY
8–6 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Interfaces
Functional Description
XSBI uses 16-bit LVDS data to interface between the PCS and the PMA
sublayer. Figure 8–4 shows XSBI between these two sublayers.
Figure 8–4. XSBI Functional Block Diagram
On the transmitter side, the transmit data (TX_D[15..0]) is output by
the PCS and input at the PMA using the transmitter clock (PMA_TXCLK),
which is derived from the PMA source clock (PMA_TXCLK_SRC). The
PMA sour ce clock is generated from the PMA with its refer ence clock
(REFCLK). On the receiver side, the r ece iver data (RX_D[15..0]) is
output by the PMA and input at the PCS using the PMA-generated
receiver clock (PMA_RXCLK). The SYNC_ERR optional signal is sent to the
PCS by the PMA if the PMA f ails to reco ver the clock fr om the serial data
stream.
The ratios for these two clocks and data are dependent on the type of PHY
used. Table 8–1 shows the rates for both PHY types.
Table 8–1. XSBI Clock & Data Rates for WAN & LAN PHY
Parameter W AN PHY LAN PHY Unit
TX_D[15..0] 622.08 644.53125 Mbps
PMA_TXCLK 622.08 644.53125 MHz
PMA_TXCLK_SRC 622.08 644.53125 MHz
RX_D[15..0] 622.08 644.53125 Mbps
PMA_RXCLK 622.08 644.53125 MHz
TX_D[15..0]
Transmitter
PMA_TXCLK_SRC
RX_D[15..0]
PMA_RXCLK
Sync_Err (optional)
PMA_TXCLK
REFCLK
PCS
PCS
PMA
PMA
Receiver
Transmitter
Receiver
Altera Corporation 8–7
July 2005 Stratix Device Handbook, Volume 2
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
Implementation
The 16-bit full du plex LVDS implementatio n of XSB I in St ra tix devic es is
shown in Figure 8–5.
The sour ce-synchronous I/O implemented in Strati x GX devices
optionally includes dynamic phase alignment (DPA). DPA automatically
and continuously tracks fluctuations caused by system variations and
self-adjusts to eliminate the phase skew between the multiplied clock and
the serial data, allowing for data rates of 1 Gbps. In non DPA mode the
I/O behaves similarly to that of the Stratix I/O. This document assumes
that DPA is disabled. However , it is simple to implement the same system
with DPA enabled to take advantage of its features. For mor e information
on DPA, see the Stratix GX Transceivers chap ter in the Stratix GX Device
Handbook, Volume 1.
Figure 8–5. Stratix & Stratix GX Device XSBI Implementation
Transmitter
SERDES
Receiver
SERDES
×1
÷8
÷8180˚
Stratix & Stratix GX PCS
Data
Data
Transmitter
Receiver
PMA
TX_D[15..0]
PMA_TXCLK
PMA_TXCLK_SRC
PMA_RXCLK
RX_D[15..0]
Phase Shift
Receiver
Transmitter
PLL1
PLL2
Stratix &
Stratix GX
Logic Array
8–8 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Interfaces
The transmit serializer/deserializer (SERDES) clock comes from the
transmitter clock source (PMA_TXCLK_SRC). The receiver SERDES clock
comes from the PMA receiver recovered clock (PMA_RXCLK).
Figure 8–6 shows the transmitter output of the XSBI core. Data
transmitted from the PCS to the PMA starts at the core of the Stratix or
Stratix GX device and travels to the Stratix or Stratix GX transmitter
SERDES blo ck. The tra n smitter SERDES block converts the parallel data
to serial data for 16 individual channels (TX_D[15..0]). The PMA
source clock (PMA_TXCLK_SRC) is used to clock out the signal data.
PMA_TXCLK is generated from the same phase-locked loop (PLL) as the
data, and it travels to the PMA at the same rate a s the dat a. By using o ne
of the data channels in the middle of the bus as the clock (in this case, the
eighth channel CH8), the clock-to-data skew improves.
Figure 8–6. Stratix & Stratix GX Device XSBI Transmitter Implementation
Figure 8–7 shows the re ceiver input of the XSBI core. From the receiver
side, data (RX_D[15..0]) comes from the PMA to the Stratix or
Stratix GX receiver SERDES block along with the PMA receiver clock
(PMA_RXCLK). The PMA receiver clock is used to convert the serial data
to parallel data. The phase shift or inversion on the PMA r eceiver clock is
needed to capture the r ecei ver data.
TX_D[0]
Stratix & Stratix GX
Logic Array
Fast PLL
W = 1
J = 4 or 8
4 or 8
Stratix & Stratix GX SERDES
× W
CH0
CH16
PMA
Transmitter
TX_D[15]
PMA_TXCLK_SRC
Stratix & Stratix GX
PCS Transmitter
÷J
622 MHz
622 MHz
622 Mbps
CH9
CH7
Parallel
Register
Parallel-to-Serial
Register
4 or 8
CH8
TX_D[7]
PMA_TXCLK
TX_D[8]
Altera Corporation 8–9
July 2005 Stratix Device Handbook, Volume 2
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
Stratix and Stratix GX devices contain up to eight fast PLLs. These PLLs
provide high-spee d output s for high-speed differential I/O support as
well as general- purpose clocking with multiplication and phase shifting.
The fast PLL incorporates this 180° phase shift. The Stratix and Stratix GX
device’s data realignment feature enables you to save more logic
elements (LEs). This featur e pr ov ides a byte- alignment capab ility, which
is embedded inside the SE RDES. The data realignment circuitry can
correct for bit misalignments by slipping data bits.
fFor more information about fast PLLs, see the St ratix Device Family Data
Sheet section of the Stratix Device Ha ndbo ok, Volume 1 or the Stratix GX
Device Family Data Sheet section of the Stratix GX Device Handbook,
Volume 1.
Figure 8–7. Stratix & Stratix GX Device XSBI Receiver Implementation
RX_D[0]
Stratix & Stratix GX
Logic Array
Fast PLL
W = 1
J = 4 or 8
4 or 8
Stratix & Stratix GX SERDES
× W
CH0
CH15
PMA
Receiver
RX_D[15]
PMA_RXCLK_SRC
Stratix & Stratix GX PCS Receiver
÷J
622 MHz
622 MHz
622 Mbps
Parallel
Register
Parallel-to-Serial
Register
4 or 8
8–10 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Interfaces
W ith this XSBI transmitter and r eceiver block implementation, each XSBI
core requires two fast PLLs. The potential number of XSBI cores per
device corresponds to the number of fast PLLs each Stratix or St ratix GX
device contains. Tables 8–2 and 8–3 show the number of LVDS channels,
the number of fast PLLs, and the number of XSBI cores that can be
supported for each Stratix or Stratix GX device.
Table 8–2. Stratix Device XSBI Core Support
Stratix Device
Number of LVDS
Channels
(Receive/Transmit)
(1)
Number of Fast
PLLs
Number of XSBI
Interfaces
(Maximum)
EP1S10 44/44 4 2
EP1S20 66/66 4 2
EP1S25 78/78 4 2
EP1S30 82/82 8 4
EP1S40 90/90 8 4
EP1S60 116/116 8 4
EP1S80 152/156 8 4
Note to Table 8–2:
(1) The LVDS channels can go up to 840 Mbps for flip-chip packages and up to
624 Mbps for wire-bond packages. This number includes both high speed and
low speed channels. The high speed LVDS channels can go up to 840 Mbps. The
low speed LVDS channels can go up to 462 Mbps. The High-Speed Differential I /O
Support chapter in the Stratix Device Handb ook, Volume 1, and the device pin-outs
on the web (www.altera.com) specify which channels are high and low speed.
Altera Corporation 8–11
July 2005 Stratix Device Handbook, Volume 2
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
AC Timing Specifications
Stratix and Stratix GX devices support a PCS interface. Figures 8–8 and
8–9 and Tables 8–4 and 8–5 illustrate timing characteristics of the PCS
transmitter and receiver interfaces.
Figure 8–8 shows the AC timing diagram for the Stratix and Stratix GX
PCS transmitter. You can determine PCS channel-to-channel skew by
adding the data invalid window before the rising edge (T cq_pre) to t he data
invalid window after the rising edge (Tcq_post).
Figure 8–8. PCS Transmitter Timing Diagram
Table 8–3. Stratix GX Device XSBI Core Support
Stratix GX Device
Number of LVDS
Channels
(Receive/Transmit)
(1)
Number of Fast
PLLs
Number of XSBI
Interfaces
(Maximum)
EP1SGX10 22/22 2 1
EP1SGX25 39/39 2 2
EP1SGX40 45/45 4 2
Note to Table 8–3:
(1) The LVDS channels can go up to 840 Mbps for flip-chip packages and up to
624 Mbps for wire-bond packages. This number includes both high speed and
low speed channels. The high speed LVDS channels can go up to 840 Mbps. The
low speed LVDS channels can go up to 462 Mbps. The High-Speed Differential I /O
Support chapter in the Stratix Device Handb ook, Volume 1, and the device pin-outs
on the web (www.altera.com) specify which channels are high and low speed.
Tperiod
Tcq_pre Tcq_post Tsetup Thold
Valid
Data
TX_DATA[15..0]
PMA_TX_CLK
8–12 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Interfaces
Table 8–4 lists the AC timing specif i cations for th e PCS transmitter.
Figure 8–9 shows the AC timing diagram for the Stratix and Stratix GX
PCS receiv er interface . You can determine the PCS sampl ing wi nd ow by
adding T setup to Thold. Receiver skew mar gin (RSKM) refers to the amount
of skew tolerated on the printed circ uit board (PCB).
Figure 8–9. PCS Receiver Timing Diagram
Table 8–5 lists the AC timing specifications for the PCS r eceiver interface.
Table 8–4. PCS Transmitter Timing Specifications
Parameter Value Unit
Min Typ Max
PMA_TX_CLK Tperiod (WAN) 1,608 ps
PMA_TX_CLK Tperiod (LAN) 1,552 ps
Data invalid window before the rising edge
(Tcq_pre)200 ps
Data inv alid windo w after the rising edge (Tcq_post) 200 ps
PMA_TX_CLK duty cycle 40 60 %
PCS transmitter channel-to-channel skew 200 ps
Tperiod
Tcq_pre Tcq_post Tsetup Thold
Valid
Data
RX_DATA[15..0] RSKM
Sampling Window
RSKM
Transmitter Channel-to-Channel
Skew/2 Transmitter Channel-to-Channel
Skew/2
Tperiod
RX_DATA[15..0]
PMA_RX_CLK PMA_RX_CLK
Table 8–5. PCS Receiver Timing Specifications (Part 1 of 2)
Parameter Value Unit
Min Typ Max
PMA_RX_CLK Tperiod (WAN) 1,608 ps
PMA_RX_CLK Tperiod (LAN) 1,552 ps
Data invalid window before the rising edge (Tcq_pre)200ps
Data invalid window after the rising edge (Tcq_post)200ps
Altera Corporation 8–13
July 2005 Stratix Device Handbook, Volume 2
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
XGMII
The purpose of XGMII is to provide a simple, inexpensive, and easy to
implement interconnection between the MAC sublayer and the PHY.
Though XGMII is an optional interface, it is used extensively in the
10-Gigabit Ethernet standard as the basis for the specification. The
conversion between the parallel d ata paths of XGMII and t he serial MAC
data stream is carried out by the reconciliation sublayer. The
reconciliation sublayer maps the signal se t provided at the XGMII to the
physical layer signaling (PLS ) servi ce primitives provided at the MAC.
XGMII supports a 10-Gbps MAC data rate.
Functional Description
The XGMII is composed of independent transmit and r eceive paths. Each
direction uses 32 data signals, TXD[31..0] and RXD[31..0], 4 control
signals, TXC[3..0] and RXC[3..0], and a clock TX_CLK and RX_CLK.
Figure 8–10 shows the XGMII functional block diagram.
PMA_RX_CLK duty cycle 45 55 %
Data set-up time (Tsetup) 300 ps
Data hold time (Thold) 300 ps
PCS sampling window 600 ps
RSKM (WAN) 304 ps
RSKM (LAN) 276 ps
Table 8–5. PCS Receiver Timing Specifications (Part 2 of 2)
Parameter Value Unit
Min Typ Max
8–14 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Interfaces
Figure 8–10. XGMII Functional Block Diagram
The 32 TXD and four TXC signals as well as the 32 RXD and four RXC
signals are or ganized into four data lanes. The four lanes in each direction
share a common clock (TX_CLK for transmit and RX_CLK for receive). The
four lanes are used in round-robin sequence to carry an octet stream
(8 bits of data per lane). The reconciliation sublaye r generates continuous
data or control characters on the transmi t path and expect s continuous
data or control characters on the receive path.
Implementation
XGMII uses the 1.5-V HSTL I/O standard. Strat ix and Stratix GX devices
support the 1.5-V HSTL Class I and Class II I/O standard (EIA/JESD8-6).
The standar d requir es a differential input with an external reference
voltage (VREF) of 0.75 V, as well as a termination voltage VTT of 0.75 V, to
which termination resistors are connected. The HSTL Class I standard
requires a 1.5-V VCCIO voltage, which is supported by Stratix and
Stratix GX devices.
Figure 8–11 shows the 32-bit full-duplex 1.5-V HSTL implementation of
XGMII.
PCS
Transmit
PCS
PCS
Receive
PMA
XGMII
tx_data[15..0] rx_data[15..0]
TXD[31..0] RXD[31..0]
XSBI
TX_CLK
RX_CLK
RXC[3..0]
TXC[3..0]
Altera Corporation 8–15
July 2005 Stratix Device Handbook, Volume 2
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
Figure 8–11. Stratix & Stratix GX XGMII Implementation
For this implementation, the shift register clocks can either be generated
from a divided down MAC reconciliation sublayer transmitter clock
(MAC_TXCLK), or the asynchronous core clock, or both if using a FIFO
buffer.
Figure 8–12 shows one channel of the output half of XGMII. Data that is
transmitted from the PCS to the MAC reconciliation sublayer starts at the
core of the Stratix or Stratix GX device and travels to the shift register . The
shift register takes in the parallel data (even bits sent to the top register
and odd bits sent to the bottom r egister) and serializes the data. After the
data is serialized, it travels to the double data rate (DDR) output circuitry,
which is clocked with the ×4 clock fr om the PLL. Out of the DDR output
circuitry, the data drives off-chip along with the ×4 clock. This transaction
creates the DDR r elationship between the clock and the da ta output. This
implementation only shows one channel, but can be duplicated to include
all 32 bits of the RX_D signal and all 4 bits of the RX_C signal.
Shift
Register
Shift
Register
×4
÷4
Clk
Data
Clk
Data
Transmitter
Receiver
MAC (RS)
RX_D[31..0]
MAC_RXCLK
MAC_TXCLK
TX_D[31..0]
Receiver
Transmitter
Stratix & Stratix GX PCS
RX_C[3..0]
TX_C[3..0]
DDR Input Circuitry
DDR Output Circuitry
PLL1
PLL2
Stratix &
Stratix GX
Logic Array
8–16 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Interfaces
Figure 8–12. Stratix & Stratix GX XGMII Output Implementation (One Channel)
Figure 8–13 shows one channel of the input half of the XGMII interface.
From the r eceiver side, the DDR data is captur ed from the MAC to the
Stratix and Stratix GX PCS DDR input circuitry. The serial data is
separated into two individual data streams with the even bits routed to
the top register and odd bits routed to the bottom register . The DDR input
circuitry produces two output data streams that go into the shift registers.
From the shift registers, the data is deserialized using the clock from the
MAC, combining into an 8-bit word. This parallel data goes to a register
that is clocked by the divide-by-4 clock from the PL L. This data and clock
go to the Stratix and Stratix GX core. This implementation shows only one
channel, but can be duplicated to include all 32 bits of the TX_D signal and
all 4 bits of the TX_C signal.
RX_D[0]
8
4
MAC
Receiver
MAC_RXCLK
Stratix & Stratix GX PCS Output
156.25 MHz
312.5 Mbps
4
Shift
Register
D0,D2,D4,D6
D1,D3,D5,D7
DFF
DFF
PLL ×4
DATA
CLK
DATA
CLK
39.0625 MHz
156.25 MHz
DDR Output Circuitry
Shift
Register
Stratix &
Stratix GX
Logic Array
Altera Corporation 8–17
July 2005 Stratix Device Handbook, Volume 2
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
Figure 8–13. Stratix & Stratix GX XGMII Input Implementation (One Channel)
Stratix and Stratix GX devices contain up to four enhanced PLLs. These
PLLs prov ide features su ch as clock switchover, spread-spectru m
clocking, programmable bandwidth, phase and del ay control, and PL L
reconfiguratio n . Si nce the maximum cl ock rate is 156.25 MHz, you can
use a fast or enhanced PLL for both the XGMII output and input blocks.
fFor more information about fast PLLs, see the St ratix Device Family Data
Sheet section of the Stratix Device Ha ndbo ok, Volume 1 or the Stratix GX
Device Family Data Sheet section of the Stratix GX Device Handbook,
Volume 1.
With this implementation for the XGMII output and input blocks, the
number of XGMII cores per device corresponds to the number of PLLs
each Stratix and Stratix GX device contains. Tables 8–6 and 8–7 show the
number of 1.5-V HSTL I/O pins, PLLs, and XGMII cores that are
supported in each Stratix and Stratix GX device. Each core requir es 72 1.5-
TX_D[0]
8 8
MAC_TXCLK
Stratix & Stratix GX PCS Input
156.25 MHz
312.5 Mbps
4
Shift
Register
DDR Input Circuitry
D0,D2,D4,D6
D1,D3,D5,D7
39.0625 MHz
156.25 MHz
MAC
Transmitter
DATA
CLK
Stratix &
DATA
CLK
DFF
DFF Latch
DFF
PLL
4
Shift
Register
÷4
Stratix GX
Logic Array
8–18 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Interfaces
V HSTL I/O pins for data and control and 2 clock pins for the transmitter
and rece iver clocks. Each XGMII core also needs two PLLs (one for each
direction).
Reduced System Noise
The output buffer of each Stratix and Stratix GX device I/O pin has a
programmable drive stre ngth control for cert ain I/O standards. The 1.5-
V HSTL Class I standard supports the minimum setting, which is the
lowest drive strength that guarantees IOH and IOL of the standard. Using
minimum settings provides signal slew rate control to re duce system
noise and signal overshoot.
fFor more information on IOH and IOL values, see Operating Conditions in
the DC & Switching Characteristics chapter of the Stratix Device Handbook,
Volume 1 or Operating Condi tions in the DC & Switching Characteristics
chapter of the Stratix GX Device Handbook, Volume 1.
Table 8–6. Stratix XGMII Core Support
Stratix Device Number of 1.5-V
HSTL Class I I/O
Pins
Number of Fast
& Enhanced
PLLs
Number of XGMII
Interfaces
EP1S10 410 6 3
EP1S20 570 6 3
EP1S25 690 6 3
EP1S30 718 10 5
EP1S40 814 12 6
EP1S60 1,014 12 6
EP1S80 1,195 12 6
Table 8–7. Stratix GX XGMII Core Support
Stratix Device Number of 1.5-V
HSTL Class I I/O
Pins
Number of Fast
& Enhanced
PLLs
Number of XGMII
Interfaces
EP1SGX10 C, D 226 4 2
EP1SGX25 C 253 4 2
EP1SGX25 D, F 370 4 2
EP1SGX40 D, G 430 8 4
Altera Corporation 8–19
July 2005 Stratix Device Handbook, Volume 2
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
Timing
XGMII signals must meet the timing requirements shown in Figure 8–14.
Make all XGMII timing measurements at the driver output (shown in
Figure 8–14) and a capacitive load from all sources of 20 pF that ar e
specified relative to the VIL_AC(max) and VIH_AC(min) thresholds.
Figure 8–14. XGMII Timing Diagram
Table 8–8 shows the XGMII timing specifications.
Stratix and Stratix GX devices s upport DDR data with clock rates of up to
200 MHz, well above the XGMII clock rate of 156.25 MHz. For the HSTL
Class I I/O standard, Stratix and Stratix GX device I/O drivers provide a
1.0-V/ns slew rate at the input buffer of the receiving device.
XAUI
XAUI (pronounced Zowie) is located between the XGMII at the
reconciliation sublayer and the XGMII at the PHY layer. Figure 8–15
shows the location of XAUI. XAUI is designed to either extend or replace
XGMII in chip-to-chip applica tio ns of most Ethernet MAC to PHY
interconnects.
Table 8–8. XGMII Timing Specifications Note (1)
Symbol Driver Receiver Unit
Tsetup 960 480 ps
Thold 960 480 ps
Note to Table 8–8:
(1) The actual set-up and hold times will be made available after device
characte rization is complete.
tsetup thold
tsetup thold
TX_CLK
RX_CLK
TXC, TXD,
RXC, RXD
VIH_AC(min)
VIL_AC(max)
VIH_AC(min)
VIL_AC(max)
8–20 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Interfaces
Figure 8–15. XAUI Location
Functional Description
XAUI can replace the 32 bits of parallel data required by XGMII for
transmission with just 4 lanes of serial data. XAUI uses clock data
recovery (CDR) to elim inate the need for separate clock signals. 8b/10b
encoding is employed on the data stream to embed the clo ck in the data.
The 8b/10b protocol to encode an 8-bit word st ream to 10-bit codes that
results in a DC-balanced serial stream and eases the receiver
synchr onization. To support 10-Gigabit Ethernet, each lane must r un at a
speed of at least 2.5 Gbps. Using 8b/10b encoding increases the rate for
each lane to 3.125 Gbps, which will be supported in Stratix GX Gbps
devices. This circuitry is supported by the embedded 3.125 Gbps
transceivers within the Stratix GX architecture. You can find more
XGXS
PHY
XAUI
XGMII
XGMII
Reconciliation
MAC
XGMII Extender
Sublayer (XGXS)
Altera Corporation 8–21
July 2005 Stratix Device Handbook, Volume 2
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
information on XAUI support in Section II, Stratix GX Transceiver User
Guide of the Stratix GX Device Handbook, Volume 2. Figure 8–16 shows how
XAUI is implemented.
Figure 8–16. Stratix GX XAUI Implementation
I/O
Characteristics
for XSBI, XGMII
& XAUI
The three interfaces of 10-Gigabit Ethernet (XSBI, XGMII, and XAUI) each
have different rates and I/O standards. Table 8–9 shows the
characteristic s for each interface.
TX_D[0]
8
8
CH0
CH0 RX_D[0]
Stratix GX XAUI
CDR Tx
TX_D[3]
8CH3
CDR Tx
8CH3 RX_D[3]
PCS
Receiver
Transmitter
CDR Rx
CDR Rx
3.125 Gbps
Stratix GX
Logic Array
Table 8–9. 10-Gigabit Ethernet Interfaces Characteristics
Interface Width Clock Rate
(MHz) Data Rate
Per Channel Clocking
Scheme I/O Type
XGMII 32 156.25 312.5 Mbps DDR source
synchronous 1.5-V
HSTL
XSBI 16 644.5 or
622.08 644.5 or
622.08
Mbps
SDR source
synchronous LVDS
XAUI 4 None 3.125 Gbps Clock data
recovery
(CDR)
1.5-V
PCML
8–22 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
I/O Characteristics for XSBI, XGMII & XAUI
Software Implementation
You can use the Assignment Organizer in the Altera® Quartus® II
software to implement the I/O standards for a particular interface. For
example, set the I/O standard to LVDS for XSBI and to HSTL Class I for
XGMII. You can use the MegaWizard® Plug-In Manager to create the
PLLs and transmitter and receiver SERDES blocks fo r the XSB I
implementation and PLLs and DDR input and output circuitry for the
XGMII implementation. For more information on the Assignment
Organizer or MegaWizard Plug-In Manager, see the Quartus II Software
Help.
AC/DC Specifications
Table 8–10 lists the XSBI DC electrical characteristics, similar to Stratix
and Stratix GX devices, that are based on the ANSI/TIA-644 LVDS
specification.
I/O characteristics for the 1.5-V HSTL standard for Stratix and Stratix GX
devices ar e shown in Figure 8–17 and comply with XGMII electrical
specifications available in 10-Gigab it Ethernet draf t IEEE P802.3ae.
Table 8–10. XSBI DC Specifications
Parameter Value Unit
Min Typ Max
Output differential voltage (VOD) 250 400 (1) mV
Output offset voltage (VOS) 1,125 1,375 mV
Output Impedance, single ended 40 140 W
Change in VOD between ‘0’ and ‘1’ 50 mV
Change in VOS between ‘0’ and ‘1’ 50 mV
Input voltage range (VI) 900 1,600 mV
Differential impedance 100 W
Input differential voltage (VID) 100 600 mV
Receiver differential input impedance 70 130 W
Ground potential difference (betw een PCS and PMA) 50 mV
Rise and fall times (20% to 80%) 100 400 ps
Note to Table 8–10:
(1) Larger VOD is possible for better signal intensity.
Altera Corporation 8–23
July 2005 Stratix Device Handbook, Volume 2
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
Figure 8–17. Electrical Characteristics for Stratix & Stratix GX Devices
(1.5-V HSTL Class I)
VREF
CL = 20pF
VIN
VOUT
RT = 50 Ω
VTT
Output Buffer Input Buffer
tz(min) = 1 V/ns
tPD
HSTL AC Load Circuit for Class I
HSTL AC Waveform & I/O Interface
tf(min) = 1 V/ns
VSWING = 1.0 V
Input
Output
Tri-Stated
Output
tPL2
tPH2
80% VSWING
VREF
20% VSWING
VOH = VCCN − 0.4 V = 1.1 V
VTT = VCCN/2 = 0.75 V
VOL = 0.4 V
VIH(AC) = 0.95 V
VTT = 0.75 V
VIL(AC) = 0.55 V
8–24 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
I/O Characteristics for XSBI, XGMII & XAUI
Table 8–11 lists the DC specifications for Stratix and Strati x GX devices
(1.5-V HSTL Class I).
10-Gigabit Ethernet MAC Core
As an Altera Megafunction Partners Program (AMPPSM) member,
MorethanIP provides a 10-Gigabit Ethernet MAC core for Altera
customers. MorethanIP’s 10-Gigabit Ethernet MAC core implements the
RS, the MAC layer, and user-pro grammable FIFO buffers for clock and
data decoupling.
Core Features
MorethanIP’s 10-Gigabit Ethernet MAC core provides the following
features:
■Includes automatic pause frame generation (per IEEE 802.3 ×31) with
user-programmable pause quanta and pause-frame termination
■Includes a programmable 48-bit MAC address with a promiscuous
mode option, and a programmable Ethernet frame length that
supports IEEE 802.1Q VLAN-tagged frames or jumbo Ethernet
frames
Table 8–11. DC Specifications for Stratix & Stratix GX Devices (1.5-V HSTL Class I) Note (1)
Symbol Parameter Conditions Minimum Typical Maximum Units
VCCIO I/O supply voltage 1.4 1.5 1.6 V
VREF Input reference voltage 0.68 0.75 0.9 V
VTT Termination voltage 0.7 0.75 0.8 V
VIH (DC) DC high-level input voltage VREF + 0.1 V
VIL (DC) DC low-level input voltage –0.3 VREF – 0.1 V
VIH (AC) AC high-level input voltage VREF + 0.2 V
VIL (AC) AC low-level input voltage VREF – 0.2 V
IIInput pin leakage current 0 < VIN < VCCIO –10 10 μA
VOH High-level output voltage IOH = –8 mA VCCIO – 0.4 V
VOL Low-level output voltage IOL = 8 mA 0.4 V
IOOutput leakage current
(when output is high Z) GND ≤ VOUT ≤
VCCIO
–10 10 μA
Note to Table 8–11:
(1) Drive strength is programmable according to values shown in the Stratix Device Family Data Sheet section of the
Stratix Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device
Handbook, Volume 1.
Altera Corporation 8–25
July 2005 Stratix Device Handbook, Volume 2
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
■Supports broadcast traffic and multi-cast address resolution with a
64-entry hash table
■Compliant with the IEEE802.3ae Draft 4.0
■Implements XGMII, allowing it to interface to XAUI through a
10-Gigabit commercial SERDES
Conclusion
10-Gigabit Ethernet takes advantage of the existing Gigabit Ethernet
standard. With their rich I/O features, Stratix and Stratix GX devices
support the components of 10-Gigabit Ethernet as well as XSBI and
XGMII. Stratix GX devices also support XAUI. These interfaces are easil y
implemented using the core ar chitectur e, diffe rential I/O capabi lities,
and superior PLLs of Stratix and Stratix GX devices.
8–26 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
I/O Characteristics for XSBI, XGMII & XAUI
Altera Corporation 9–1
July 2005
9. Implementing SFI-4 in
Stratix & Stratix GX Devices
Introduction The growth of the Internet has cr eated huge bandwidth demands as
voice, video, and data push the limit s of the existing wide area network
(WAN) backbones. To facilitate this bandwidth growth, speeds of OC-192
and higher are being deployed in WAN backbones (see Figure 9–1).
Today’s carrier backbone networks are supported by SONET/SDH
transmission technology. SONET/SDH is a transmission technology for
transporting optical signals at speeds ranging from 51 megabits per
second (Mbps) up to 40 gigabits per second (Gbps). SONET/SDH rings
make up the majority of the existing backbone infrastr ucture of the
Internet and the public switched telephone network (PSTN).
The Optical Internetworking Forum (OIF) standar d SFI-4 is a 16-bit L VDS
interface used in an OC-192 SONET system to link the framer and the
serializer/deserializer (SERDES). Stratix® and Stratix GX devices support
the required data rates of up to 622.08 Mbps along with the one-to-one
relat ionshi p required between clock frequency and data rate. The fast
phase-locked loop (PLL) was de signed to support the high clock
frequencies and the one-to-one relationship (between clock and data rate)
needed for interfaces such as XSBI and SFI-4. Support for SFI-4 extends
the reach of high-density programmable logic from the backplane to the
physical layer (PHY) devices.
This chapter focuses on the implementation of the interface between the
SERDES and the framer.
Figure 9–1. WAN Backbone
A SONET/SDH transmission network is composed of several pieces of
equipment, including terminal multiplexers, add-drop multiplexers, and
repeater and digital cross-connect systems. SONET is the standard used
in North America and SDH is the standar d used outsi de North America.
SONET OC-48 SONET OC-192 SDH STM-64
DWDM
40 G
~~
S52011-2.0
9–2 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Introduction
The SONET/SDH specification outlines the frame format, multiplexing
method, synchronization method, and optical interface between the
equipment, as well a s the spec ific optical interface.
SONET/SDH continues to play a key role in the next generation of
networks for many carriers. In the core network, the carriers offer services
such as telephone, dedicated leased lines, and Internet protocol (IP) data,
which are continuously transmitted. The individual data channels are not
transmitted on separate lines; instead, they are multiplexed into higher
speeds and transmitted on SONET/SDH networks at the corresponding
transmission speed.
Figure 9–2 shows a typical SONET/SDH line card. The system operates
as follows:
1. The SONET/SDH line card first takes a high-speed serial optical
signal and converts it into a high-s peed serial electrical signal. The
devices are called physical media dependent (PMD) devices.
2. The system then recovers the clock from the electrical dat a using a
clock data recovery (CD R) unit.
3. The SERDES parallelizes the data so that it can be manipulated
easily at lower clock rates.
4. The interface between the SERDES and framer is calle d the SERDES
framer interface. The interface requirements are defined by the OIF.
5. The framer identifies the beginning of the SONET/SDH frames and
monitors the performance of the system.
6. The mapper following the framer maps asynchronous transfer
mode (ATM) cells, IP packet s, or T/E carrier signals into the SONET
frame.
7. The PHY-link layer interface provides a bus interface to packet/cell
proce ssors or othe r link-layer devices.
Altera Corporation 9–3
July 2005 Stratix Device Handbook, Volume 2
Implementing SFI-4 in Stratix & Stratix GX Devices
Figure 9–2. SONET/SDH Line Card
The OIF has defined the electrical interface (SFI) between the
SONET/SDH frame r and high-spee d SERDES devices. To keep up with
evolving transmission speeds and technology enhancements, dif ferent
versions of electrica l interfaces are defined. SFI-4 is the version of SFI that
acts as an interface between an OC-192 SERDES and SONET framer, as
shown in Figure 9–2. An aggregate of 9953.28 Mbps is transferr ed in each
direction. With their differential I/O capabilities, Stratix and Stratix GX
devices ar e ideally suited to support the framer side of the SFI-4 interface.
Support for SFI-4 extends the reach of high-density programmable logic
from the backplane to the PHY devices.
System Topology
The SFI-4 interface uses 16 channels of source-synchronous LVDS to
interface between a SONET framer and an OC-192 SERDES. Figure 9–3
shows the SFI-4 interface.
CDR
OE Module SONET/SDH
Mapper/Protocol
Processor
SONET/SDH
Framer
SERDES
Optical
Signal
SERDES Framer
Interface
Optical-Electrical
Conversion Link Layer
Interface
To Packet
Processor &
Switch Fabri
c
7
65
4
312
9–4 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Introduction
Figure 9–3. SFI-4 Interface Signals
The framer transmits outbound data via TXDATA[15..0] and is
rece ived at the SERDES using TXCLK. TXCLK is derived from
TXCLK_SRC, which is provided by the OC-192 SERDES. The framer
receives incoming dat a on RXDATA[15..0] from the OC-192 SERDES.
The data received is latched on the rising edge of RXCLK. Table 9–1
provi des t he data rates and clock frequencies specified by SFI-4. T he
modes of TXCLK are specified by the SFI-4 standard. In required mode
(622 MHz clock mode or ×1 mode), TXCLK should run at 622.08 MHz. In
optional mode (311 MHz clock mode or ×2 mode), TXCLK should run at
311.04 MHz.
Table 9–1. SFI-4 Interface Data Rates & Clock Frequencies
Signal Performance
TXDATA[15..0] 622.08 Mbps
TXCLK 622.08 MHz or 311.04 MHz
TXCLK_SRC 622.08 MHz
RXDATA[15..0] 622.08 Mbps
RXCLK 622.08 MHz
REFCLK 622.08 MHz
SONET Framer
Transmitter OC-192 SERDES
Transmitter
TXDATA[15..0]
TXCLK
TXCLK_SRC
RXDATA[15..0]
RXCLK
SONET Framer
Receiver Recovered Clock
Receiver
REFCLK
Altera Corporation 9–5
July 2005 Stratix Device Handbook, Volume 2
Implementing SFI-4 in Stratix & Stratix GX Devices
Interface Implementation in Stratix & Stratix GX Devices
The 16-bit full-duplex LVDS implementation of the framer part of the
SFI-4 interface is shown in Figure 9–4. Stratix devices support source-
synchronous interfacing and LVDS differ ential signaling up to 840 Mbps.
Stratix devices have embedded SERDES circuitry for serial and parallel
data conversion.
The sour ce-synchronous I/O implemented in Strati x GX devices
optionally includes dynamic phase alignment (DPA). DPA automatically
and continuously tracks fluctuations caused by system variations and
self-adjusts to eliminate the phase skew between the multiplied clock and
the serial data, allowing for data rates of 1 Gbps. In non DPA mode the
I/O behaves similarly to that of the Stratix I/O. This document assumes
that DPA is disabled. However , it is simple to implement the same system
with DPA enabled to take advantage of its features. For mor e information
on DPA, see the Stratix GX Transceivers chap ter in the Stratix GX Device
Handbook, Volume 1.
The fast PLL enables 622.08 Mbps data transmission by transmitting and
receiving a differential clock at rates of up to 645 MHz. The clocks
required in the SERDES for parallel and serial data conve r s ion can be
configured from the received RXCLK (divi ded down), the TXCLK_SRC
(divided down), or the asynchronous core clock. See Figure 9–4.
9–6 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Introduction
Figure 9–4. Implementation of SFI-4 Interface Using Stratix & Stratix GX Devices
fFor details on differ ential I/ O buf fers, SERDES , and clock di viders using
PLLs, see the High-Speed Differential I/O Interfaces in Stratix Devices
chapter in the Stratix Device Handbook or the Strati x GX Devi ce Handbook.
Figure 9–5 shows the transmitter block (from Figure 9–4) of the SFI-4
framer interface implemented in Stratix and Stratix GX devices. The data
starts in the logic array and goes into the Stratix and Stratix GX SERDES
block. The transmitter SERDES of the framer converts the parallel data to
serial data for the 16 TXDATA channels (TXDATA[15..0]). A fast PLL is
used to generate TXCLK from TXCLK_SRC. The fast PLL keeps the
TXDATA and TXCLK edge -aligned. A divided down (÷8) clock generated
from TXCLK_SRC is used to convert the parallel data to serial in the
transmitter SERDES. The divided down clock also clocks some of the
logic in the logic array.
Transmitter
SERDES
Receiver
SERDES
×1
÷8
÷8180˚
Stratix Framer
Clk
Data
Clk
Data
Transmitter
Receiver
OC-192
SERDES
TXDATA[15..0]
TXCLK
TXCLK_SRC
RXCLK
RXDATA[15..0]
Phase Shift
Receiver
Transmitter
PLL1
128
128
REFCLK
PLL2
Stratix &
Stratix GX
Logic Array
Altera Corporation 9–7
July 2005 Stratix Device Handbook, Volume 2
Implementing SFI-4 in Stratix & Stratix GX Devices
Figure 9–5. Framer Transmitter Interface in Stratix & Stratix GX Devices
Figure 9–6 shows the r eceiver block (fr om Figure 9–4) o f the SFI-4 framer
interface implemented in Stratix and Str atix GX devices.
RXDATA[15..0] is received from the OC-192 SERDES on the differential
I/O pins of the Stratix or Stratix GX device. The receiver SERDES
converts the high-speed serial data to parallel. You can generate the
clocks r equ ired in the SERDES for parall el and seri al data conversion
from the received RXCLK. RXCLK is inverted (phase-shifted by 180°) to
capture received data. While normal I/O operation guarantees that data
is captured, it does not guarantee the parallelization boundary, which is
randomly determined based on the power up of both communicating
devices. The SERDES has embedded data realignment capability, which
can be used to save logic elements (LEs).
TXDATA[0]
Fast PLL
W = 1
J = 8
8
8
Stratix & Stratix GX SERDES
× W
CH0
CH15
OC-192
SERDES
TXDATA[15]
TXCLK
TXCLK_SRC
Stratix & Stratix GX SFI-4 Transmitter
÷J
622 MHz
622 MHz
622MHz
622 Mbps
Parallel
Register
Parallel-to-Serial
Register
Stratix & Stratix GX
Logic Array
9–8 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Introduction
Figure 9–6. Framer Receiver Interface in Stratix & Stratix GX Devices
Note to Figure 9–6:
(1) The figure shows Stratix GX DPA disabled.
fFor more information on the byte-alignment feature in Stratix and
Stratix GX devices, see the High-Speed Differential I/O Interf aces in Stra tix
Devices chapter in the Stratix Device Handbook or the Stratix GX Device
Handbook.
RXDATA[0]
Fast PLL
W = 1
J = 8
8
8
Stratix & Stratix GX SERDES
× W
CH0
CH15
OC-192
SERDES
RXDATA[15]
RXCLK
Stratix & Stratix GX SFI-4 Receiver
÷J
622 MHz
622 MHz
Parallel
Register
Serial-to-Parallel
Register
622 Mbps
Stratix & Stratix GX
Logic Array
Altera Corporation 9–9
July 2005 Stratix Device Handbook, Volume 2
Implementing SFI-4 in Stratix & Stratix GX Devices
Tables 9–2 and 9–3 list the number of SFI-4 cores that can be implemented
in Stratix and Stratix GX devices. See the High-Speed Differential I/O
Interfaces in Stratix Devices chapter in the Stratix Device Handbook or the
Stratix GX Device Handbook for the package type and the maximum
number of channels supported by each package.
Table 9–2. Stratix SFI-4 Core Support
Stratix Device
Number of LVDS
Channels
(Receiver/Transmitter)
(1)
Number of PLLs Number of SFI-4
Interfaces
(Maximum)
EP1S10 44/44 4 2
EP1S20 66/66 4 2
EP1S25 78/78 4 2
EP1S30 82/82 8 4
EP1S40 90/90 8 4
EP1S60 116/116 8 4
EP1S80 152/156 8 4
Note to Table 9–2:
(1) The LVDS channels can go up to 840 Mbps (or 1 Gbps using DPA in Stratix GX
devices). This number includes both high speed and low speed channels. The
high speed LVDS channels can go up to 840 Mbps. The low speed L VDS channels
can go up to 462 Mbps. The High-Speed Differential I/O Support chapters in the
Stratix Device Handbook, Volume 1 and the Stratix GX Device Handbook, Volume 1
and the device pin-outs on the web (www.altera.com) specify which channels are
high and low speed.
Table 9–3. Stratix GX SFI-4 Core Support
Stratix GX
Device
Number of LVDS
Channels
(Receiver/Transmitter)
(1)
Number of PLLs Number of SFI-4
Interfaces
(Maximum)
EP1SGX10 22/22 2 1
EP1SGX25 39/39 2 2
EP1SGX40 45/45 4 2
Note to Table 9–3:
(1) The LVDS channels can go up to 840 Mbps, or 1 Gbps using DPA. This number
includes bo th high speed and low spee d channels. The high speed LVDS channels
can go up to 840 Mbps. The low speed L VDS channels can go up to 462 Mbps. The
High-Speed Differential I/O Support chapter in the Stratix Device Handbook, Volume
1 and the Stratix GX Device Handbook, V olume 1 and the device pin-outs on the web
(www.altera.com) specify which channels are high and low speed.
9–10 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Introduction
AC Timing Specifications
Figures 9–7 thr ough 9–9 and Tables 9–4 through 9–6 illustrate the tim ing
characteristics of SFI-4 at the framer. Stratix and Stratix GX devices
support all the timing requirements needed to support transmitter and
receiver functions of a SFI-4 framer; only framer-related timing
specifications are applicable.
fFor details on the timing specifications of LVDS I/O stand ards in Stratix
and Stratix GX devices, see the Stra tix Devic e Family Data Sheet section of
the Stratix Device Handboo k, Volume 1 and the High-Speed Di fferential I/O
Interfaces in Stratix Devices chapter or the Stratix GX Device Family Data
Sheet section of the Stratix GX Device Handbook, Volume 1 and the High-
Speed Differential I/O Interfaces in Stratix Devices chapter
Figure 9–7 shows the timing diagram for the Stratix and Stratix GX
framer transmitter ×1 (622 MHz clock) mode.
Figure 9–7. Framer Transmitter ×1 (622 MHz Clock) Mode Timing Diagram
Table 9–4 lists the timing specificatio ns for the SFI-4 framer transmitter in
×1 (622 MHz clock) mode.
Tperiod
Tcq_pre Tcq_post Tsetup Thold
Valid
Data
TX_DATA[15..0]
Table 9–4. SFI-4 Framer Transmitter ×1 (622 MHz Clock) Mode Timing Specifications
Parameter Value Unit
Min Typ Max
TX_CLK (Tperiod)1,608 ps
Data invalid window before the rising edge (Tcq_pre)200ps
Data invalid window after the rising edge (Tcq_post)200ps
TX_CLK duty cycle 40 60 %
Framer transmitter channel-to-channel skew 200 ps
Altera Corporation 9–11
July 2005 Stratix Device Handbook, Volume 2
Implementing SFI-4 in Stratix & Stratix GX Devices
Figure 9–8 shows the timing diagram for the SFI-4 framer transmitter in
×2 (311 MHz clock) mode
Figure 9–8. Framer Transmitter ×2 (311 MHz Clock) Mode Timing Diagram
Table 9–5 lists the timing specificatio ns for the SFI-4 framer transmitter in
×2 (311 MHz clock) mode.
Figure 9–9 shows the timing diagram for the SFI-4 framer receiver.
Figure 9–9. Framer Receiver Timing Diagram
Tperiod/2
Tcq_pre Tcq_post
Valid
Data
TX_DATA[15..0] Valid
Data
TX_CLK(P)
Table 9–5. SFI-4 Framer Transmitter ×2 (311 MHz Clock) Mode Timing Specifications
Parameter Value Unit
Min Typ Max
TX_CLK (Tperiod)3,215 ps
Data invalid window before the rising edge (Tcq_pre)200ps
Data invalid window after the rising edge (Tcq_post)200ps
TX_CLK duty cycle 48 52 %
Framer transmitter channel-to-channel skew 200 ps
Tperiod
Tcq_pre Tcq_post Tsetup Thold
Valid
Data
RX_DATA[15..0]
RX_CLK(P) RX_CLK(P)
RSKM
Sampling Window
RSKM
Transmitter Channel-to-Channel
Skew/2 Transmitter Channel-to-Channel
Skew/2
Tperiod
RX_DATA[15..0]
9–12 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Introduction
Table 9–6 lists the timing specifications for the SFI-4 framer receive r.
Electrical Specifications
SFI-4 uses LVDS as a high-speed data transfer mechanism to implement
the SFI-4 interface. Table 9–7 lists the DC electrical characteristics for the
interface, which are based on the IEEE Std. 1596.3-1996 7 specification.
For more informati on on the voltage specification of LVDS I/O standards
in Stratix and Stratix GX devices, see the Stratix Device Family Data Sheet
section of the Stratix Device Handbook, Volume 1 and the High-Speed
Differential I/O Interfaces in Stratix Devices chapter or the Stratix GX Device
Family Data Sheet section of the Stratix GX Device Handbook, Volume 1 and
the High-Speed Differential I/O Interfaces in Stra tix Devices chapter.
Table 9–6. Framer Receiver Timing Specifications
Parameter Value Unit
Min Typ Max
RX_CLK (Tperiod)1,608 ps
Data invalid window before the rising edge (Tcq_pre)200ps
Data invalid window after the rising edge (Tcq_post)200ps
RX_CLK duty cycle 45 55 %
Data set-up time (Tsetup) 300 ps
Data hold time (Thold) 300 ps
Framer sampling window 600 ps
Receiver skew margin (RSKM) 304 ps
Altera Corporation 9–13
July 2005 Stratix Device Handbook, Volume 2
Implementing SFI-4 in Stratix & Stratix GX Devices
Software Implementation
The SFI-4 interface uses a 16-bit LVDS I/O interface. The Altera®
Quartus® II software version 2.0 supports Stratix and Stratix GX devices,
allowing you to implement LVDS I/O buffers through the Quartus II
Assignment Organizer.
fFor information on the Quartus II Assignment Organizer, see the
Quartus II Software Help.
Conclusion
SFI-4 is the standard interface between SONET framers and optical
SERDES for OC-192 interfaces. With embedded SERDES and fast PLLs,
Stratix and Stratix GX devices can easily support the SFI-4 framer
interface, enabling
10-Gbps (OC-192) data transfer rates. Stratix and Stratix GX I/O supports
the required data rates of up to 622.08 Mbps. Stratix and Stratix GX fast
PLLs are designed to support the high clock frequencies and one-to-one
relationship needed for interfaces such as XSBI and SFI-4. Stratix and
Stratix GX devices can support multiple SFI-4 functions on one device.
Table 9–7. Framer LVDS DC Specifications
Parameter Value Unit
Min Typ Max
Output differential voltage (VOD) 250 600 (1) mV
Output offset voltage (VOS) 1,125 1,375 mV
Output Impedance, single ended 40 140 W
Change in VOD between ‘0’ and '1' 50 mV
Change in VOD between '1' and '0' 50 mV
Input voltage range (VI) 0 2,400 mV
Differential impedance 100 W
Input differential voltage (VID) 100 600 mV
Receiver differential input impedance 70 130 W
Ground potential difference (between PCS and PMA) 50 mV
Rise and fall times (20% to 80%) 100 400 ps
Note to Table 9–7:
(1) The IEEE standard requires 400 mV. A larger swing is encouraged, but not required.
9–14 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Introduction
Altera Corporation 10–1
July 2005
10. Transitioning APEX
Designs to Stratix &
Stratix GX Devices
Introduction Stratix® and Strati x GX devices are Altera’s next-generation, system-on-
a-programmable-chip (SOPC) solution. Stratix and Stratix GX devices
simplify the block-based design methodology and bridge the gap
between system bandwidth requirements and programmable logic
performance.
This chapter highlights the new features in the Stra tix and Strat ix G X
devices and provides assistance when transitioning designs from
APEXTM II or APEX 20K devices to the Stratix or Stratix GX architecture.
You should be familiar with the APEX II or APEX 20K archite cture and
available device features before using this chapter. Use this chapter in
conjunction with the Stratix Device Family Data Sheet section of the Stratix
Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet
section of the Stratix GX Device Handbook, Volume 1.
General
Architecture Stratix and Stratix GX devices offer many new features and architectural
enhancements. Enhanced logic elements (LEs) and the MultiTrackTM
interconnect structure offer reduced resource utilizatio n and
considerable design performance improvement. The MultiTrack
interconnect uses DirectDriveTM technology to ensure the availability of
deterministic routing resources for any design block, regar dless of its
placement within the device.
All ar chi tec tural changes between Stratix and Stratix GX and APEX II or
APEX 20K devices described in this section do not r equ ire any design
changes. However, you must resynthesize your design and recompile in
the Quartus® II software to target Strat ix and Stratix GX devices .
S52012-3.0
10–2 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
General Architecture
Logic Elements
Stratix and Stratix GX device LEs include several new, advanced featur es
that improve design performance and reduce logic resource consumption
(see Table 10–1). The Quartus II software automatically uses these new
LE features to impro ve device utilization.
In addition to the new LE features described in Table 10–1, there are
enhancements to the chains that connect LEs together. Carry chains are
implemented vertically in Stratix and Stratix GX devices, instead of
horizontally as in APEX II and APEX 20K devices, and continue across
rows, instead of acr oss columns, as shown in Figure 10–1. Also note that
the Stratix and Stratix GX architecture s do not support the cascade
primitive. Ther efore, the Quartus II Compiler automatically converts
Table 10–1. Stratix & Stratix GX LE Features
Feature Function Benefit
Register chain interconnects Direct path between the register output
of an LE and the register input of an
adjacent LE within the same logic arra y
block (LAB)
Conserves LE resources
Provides fast shift register
implementation
Saves local interconnect routing
resources within an LAB
Look-up table (LUT) chain
interconnects Direct path between the combinatorial
output of an LE and the fast LUT input
of an adjacent LE within the same LAB
Allows LUTs within the same LAB to
cascade together for high-speed wide
fan-in functions, such as wide XOR
operations
Bypasses local interconnect for
faster performance
Register-to-LUT feedback
path Allows the register output to feed back
into the LUT of the same LE, such that
the register is packed with its own fan-
out LUT
Enhanced register packing mode
Uses resources more efficiently
Dynamic arithmetic mode Uses one set of LEs for implementing
both an adder and subtractor
Improves performance for functions
that switch between addition and
subtraction frequently, such as
correlators
Carry-select chain Calculates outputs for a possible carry-
in of 1 or 0 in parallel
Gives immediate access to result f or
both a carry-in of 1 or 0
Increases speed of carry functions
for high-speed operations, such as
counters, adders, and comparators
Asynchronous clear and
asynchronous preset
function
Supports direct asynchronous clear
and preset functions
Conserves LE resources
Does not require additional logic
resources to implement NOT-gate
push-back
Altera Corporation 10–3
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
cascade primiti ves in APEX II and APEX 20K designs t o a wir e primitive
when compiled for Stratix and Stratix GX devices. These architectural
changes are transparent to the user and do not requir e des ign changes .
Figure 10–1. Carry Chain Implementation in APEX II & APEX 20K Devices vs.
Stratix & Stratix GX Devices
MultiTrack Interconnect
Stratix and Stratix GX devices use the MultiTrack interconnect structure
to provide a high-speed connection between logic r esources using
performance-optimized routing channels of different lengths. This
feature maximizes overall design performance by placing critical paths
on routin g li nes with greater speed, resulting in minimal propagation
delay.
LABs (with 10 LEs Each)
Carry Chains
APEX II & APEX 20K Devices Stratix Devices
Carry-Selec
t
Chains
10–4 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
General Architecture
Stratix and Stratix GX device MultiTrack interconnect resources are
described in Table 10–2.
Direct link routing saves ro w routing resources while providing fast
communication paths between resource blocks. Dir ect li nk int er connects
allow an LAB, digital signal processing (DSP) block, or TriMatrix TM
memory block to drive dat a into the local interconnect of its left and right
neighbors. LABs, DSP blocks, and TriMatrix memory blocks can also use
direct link interconnects to drive data back into themselves for feedback.
The Quartus II software automatically uses these routing resources to
enhance design performance.
fFor more information about LE architecture and the MultiTrack
interconnect structure in Stratix and Str atix GX devices, see the Stratix
Device Family Data Sheet section of the Stratix Device Handbook, Volume 1
or the Stratix GX Device Family Data Sheet section of the Stratix GX Device
Handbook, Volume 1.
DirectDrive Technology
When using APEX II or APE 20K devices, you must place critical pa ths in
the same MegaLABTM column to impr ove performance. Additionally, you
should place cri t ical paths in the same MegaLA B structure for optimal
performance. However, this restriction does not exist in Stratix and
Stratix GX devices because they do not contain MegaLAB structures.
W ith the new Dir ectDriveTM technology in Stratix and Stratix GX devices,
the actual distance between the source and destination of a path is the
most important criteria for meet ing timing performance. DirectDrive
technology ensures that the same routing resourc es are available to each
design block, regardless of its locat ion in the device.
Table 10–2. Stratix & Stratix GX Device MultiTrack Interconnect Resources
Routing Type Interconnect Span
Row Direct link Adjacent LABs and/or blocks
Row R4 Four LAB units horizontally
Row R8 Eight LAB units horizontally
Row R24 Horizontal routing across the width of the device
Column C4 Four LAB units vertically
Column C8 Eight LAB units vertically
Column C16 Vertical routing across the length of the device
Altera Corporation 10–5
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
Architectural Element Names
The architectural el ement naming system within Stratix and Stratix GX
devices differs from the row-column coordinate system (for example,
LC1_A2, LAB_B1) used in previous Altera de vice families. Stratix and
Stratix GX devices uses a new naming system based on the X-Y
coordinate system, (X, Y). A number (N) designates the location within the
block where the logic resides, such as LEs within an LAB. Because the
Stratix and Stratix GX architectures are column-based, this naming
simplifies location assignments. Stratix and Stratix GX architectural
blocks include:
■LAB: logic array block
■DSP: digital signal processing block
■DSPOUT: adder/s ubtrac tor/accum ul ator or summation block of the
DSP block
■M512: 512-bit memory block
■M4K: 4-Kbit memory block
■M-RAM: 512-Kbit memory block
Elements within architectural blocks include:
■LE: logic element
■IOC: I/O element
■PLL: phase-locked loop
■DSPMULT: DSP block mul tiplier
■SERDESTX: transmitter serializer/deserializer
■SERDESRX: receiver serializer/deserializer
10–6 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
General Architecture
Table 10–3 highlights the new location syntax used for Stratix and
Stratix GX devices.
Use the following guidelines with the new naming system:
■The anchor point, or origin, in Stratix and Stratix GX devices is in the
bottom-left corner, instead of the top-left corner as in APEX II and
APEX 20K devices.
■The anchor point, or origin, of a large block element (e.g., a M-RAM
or DSP block) is also the bottom-left corner.
■All numbers ar e zero-b ased, meaning the origin at the bo ttom-left of
the device is X0, Y0.
■The I/O pins constitute the first and last rows and columns in the
X-Y coordinates. Therefore, the bottom row of pins resides in
X<number>, Y0, and the first left column of pins resides in X0,
Y<number>.
■The sub-location of elements, N, numbering begins at the top.
Therefore, the LEs in an LAB are still numbe red fr om top to bo ttom,
but start at zero.
Figure 10–2 show the Stratix and Stratix GX architectural element
numbering convention. Figure 10–3 dis plays the floorplan view in the
Quartus II software.
Table 10–3. Stratix & Stratix GX Location Assignment Syntax
Architectural
Elements Element Name Location Syntax Example of Location Syntax
Location Description
Blocks LAB, DSP,
DSPOUT, M512,
M4K, M-RAM
<element_name>_X<number>
_Y<number>LAB_X1_Y1 Designates the LAB in
row 1, column 1
Logic LE, IOC, PLL,
DSPMULT,
SERDESTX,
SERDESRX
<element_name>_X<number>
_Y<number>_N<number>LC_X1_Y1_N0 Designates the first
LE, N0, in the LAB
located in row 1,
column 1
Pins (1) I/O pins pin_<pin_label> pin_5 Pin 5
Note to Table 10–3:
(1) You can make assignments to I/O pads using IOC_X<number>_Y<number>_N<number>.
Altera Corporation 10–7
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
Figure 10–2. Stratix & Stratix GX Architectural Elements Note (1)
Notes to Figure 10–2:
(1) Figure 10–2 shows part of a Stratix and Stratix GX device.
(2) Large block elements use their lower-left corner for the coordinate location.
(3) The Stratix GX architectural elem ents include transceiver blocks on the right side of the device.
Origin (0, 0)
LAB
(16,18)
LAB
(16,17)
LAB
(16,16)
LAB
(16,15)
LAB
(13,18)
LAB
(13,17)
LAB
(13,16)
LAB
(13,15)
LAB
(11,18)
LAB
(11,17)
LAB
(11,16)
LAB
(11,15)
LAB
(1,18)
LAB
(1,17)
LAB
(1,16)
LAB
(1,15)
M512
(12,18)
M512
(12,17)
M512
(12,16)
M512
(12,15)
LAB
(13,1)
LAB
(11,1)
LAB
(1,1)
PLL
(0,1,0)
M512
(12,1)
LAB
(16,14)
LAB
(16,13)
LAB
(16,2)
LAB
(16,1)
M4K
(14,18)
M4K
(14,17)
M4K
(14,16)
M4K
(14,15)
M4K
(14,14)
M4K
(14,13)
M4K
(14,2)
M4K
(14,1)
M4K RAM Blocks are
Two Units Wide and
One Unit High
Mega RAM (1,2)
DSPMULT
(17,7,0)
and
(17,7,1)
DSPMULT
(17,5,0)
and
(17,5,1)
DSPMULT
(17,3,0)
and
(17,3,1)
DSPMULT
(17,1,0)
and
(17,1,1)
DSPOUT
(18,1,0)
and
(18,1,7)
DSP Block (17,1)
is Two Units Wide
and Eight Units High
(2)
Mega RAM Block is
13 Units Wide and
13 Units High
Pins
(2)(2)
(3
)
10–8 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
TriMatrix Memory
Figure 10–3. LE Numbering as Shown in the Quartus II Software
TriMatrix
Memory TriMatrix memory has three different sizes of memory blocks, each
optimized for a different purpose or application. M512 blocks consist of
512 bits plus parity (576 bits), M4K blocks consist of 4K bits plus parity
(4,608 bits), and M-RAM blocks consist of 512K bits plus parity
(589,824 bits). This new structur e differs from APEX II and APEX 20K
devices, which feature uniformly sized embed ded system blocks (E SBs)
either 4 Kbits (APEX II devices) or 2 Kbits (APEX 20K devices) large.
Stratix and Stratix GX TriMatrix memory blocks give you advanced
control of each memory block, with features such as byte enables, parity
bit storage, and shift-register mode, as well as mixed-port width support
and true dual-port mode operation.
Altera Corporation 10–9
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
Table 10–4 compares TriMatrix memory with ESBs.
Stratix and Stratix GX TriMatrix memory blocks only support pipelined
mode, while APEX II and APEX 20K ESBs support both pipelined and
flow-through modes. Since all TriMatrix memory bloc ks can be
pipelined, all inpu t data and address li nes are registered, while outputs
can be either registered or combinatorial. You can use Stratix and
Stratix GX memory block registers to implement input and output
regis ters without utilizing additional r esourc es. You can compile designs
containing pipelined memory blocks (inputs registered) for Stratix and
Stratix GX devices without any modifications. However, if an APEX II or
Table 10–4. Stratix & Stratix GX TriMatrix Memory Blocks vs. APEX II & APEX 20K ESBs
Features Stratix & Stratix GX APEX II ESB APEX 20K ESB
M512 RAM M4K RAM M-RAM
Size (bits) 576 4,608 589,824 4,096 2,048
Parity bits Yes Yes Yes No No
Byte enable No Yes Yes No No
True dual-port
mode No Yes
Includes support
for mixed width
Yes
Includes support
for mixed width
Yes
Includes support
for mixed width
No
Embedded shift
register Yes Yes No No No
Dedicated
content-
addressable
memory (CAM)
support
No No No Yes Yes
Pre-loadable
initialization with a
.mif (1)
Yes Yes No Yes Yes
Packed mode (2) No Yes No Yes Yes
Feed-through
behavior Rising edge Rising edge Rising edge Falling edge Falling edge
Output power-up
condition Powers up
cleared even if
using a .mif (1)
Powers up
cleared even if
using a .mif (1)
Powers up with
unknown state Powers up
cleared or to
initialized value,
if using a .mif (1)
Powers up
cleared or to
initialized value,
if using a .mif (1)
Notes to Table 10–4:
(1) .mif: Memory Initialization File.
(2) Packed mode refers to combining two single-port RAM blocks into a single RAM block that is placed into true
dual-port mode.
10–10 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
TriMatrix Memory
APEX 20K design contains flow-through memory, you must modify the
memory modules to target the Stratix and Stratix GX architectures (see
“Memory Megafunctions” on page 10–12 for more information).
fFor more information about TriMatrix memory and converting flow-
through memory modules to pipelined, see the TriMatrix Embedded
Memory Blocks in Stratix & Stratix GX Devices chapter in the Stratix GX
Device Handbook and AN 210: Converting Memory from Asynchronous to
Synchronous for Stratix & Stratix GX Designs.
Same-Port Read-During-Wr ite Mode
In same-port read-during-write mode, the RAM block can be in single-
port, simple dual-port, or true dual-port mode. One port fr om the RAM
block both reads and writes to the same address location using the same
clock. When APEX II or APEX 20K devices perform a same-port read-
during-write operation, the new data is available on the falling edge of
the clock cycle on which it was writte n, as shown in Figure 10–4. When
Stratix and Stratix GX devices perform a same-port read-during-write
operation, the new data is available on the rising edge of the same clock
cycle on which it was written, as shown in Figure 10–5. This holds true for
all TriMatrix memory blocks.
Figure 10–4. Falling Edge Feed-Through Behavior
(APEX II & APEX 20K Devices) Note (1)
Note to Figure 10–4:
(1) Figures 10–4 and 10–5 assume that the address stays constan t throughout and that
the outputs are not register ed.
inclock
data_in
wren
data_out A
BA
Old
Altera Corporation 10–11
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
Figure 10–5. Rising Edge Feed-Through Behavior
(Stratix & Stratix GX Devices) Note (1)
Note to Figure 10–5:
(1) Figures 10–4 and 10–5 assume that the address stays constan t throughout and that
the outputs are not register ed.
Mixed-Port Read-During-Write Mode
Mixed-port r ead-during-write mode occurs when a RAM block in simple
or true dual- port mode has one port read ing and the other port writing to
the same addr ess location using the same clock. In APEX II and
APEX 20K designs, the ESB outputs the old data in the first half of the
clock cycle and the new data in the second half of the clock cycle, as
indicated by Figure 10–6.
Figure 10–6. Mixed-Port Feed-Through Behavior
(APEX II & APEX 20K Devices) Note (1)
Note to Figure 10–6:
(1) Figure 10–6 assumes that outputs are not registered.
Stratix and Stratix GX device RAM outputs the new data on the rising
edge of the clock cycle immediately after the data was written. When yo u
use Stratix and Stratix GX M512 and M4K blocks, you can choose whether
to output the old data at the targeted addr ess or output a don’t car e value
during the clock cycl e when the new data is written. M-RAM blocks
inclock
data_in
wren
data_out A
BA
Old
inclock
Port A
data_in
Port A
wren
Port B
data_out
A
B
A
Old
Port B
wren
B
10–12 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
TriMatrix Memory
always output a don’t care value. Figures 10–7 and 10–8 show the feed-
through behavior of the mixed-port mode. You can use the altsyncram
megafunction to set the output behavior during mixed-port read-during-
write mode.
Figure 10–7. Mixed-Port Feed-Through Behavior (OLD_DATA) Note (1)
Note to Figure 10–7:
(1) Figures 10–7 and 10–8 assume that the address stays constan t throughout and that
the outputs are not register ed.
Figure 10–8. Mixed-Port Feed-Through Behavior (DONT_CARE) Note (1)
Note to Figure 10–8:
(1) Figures 10–7 and 10–8 assume that the address stays constan t throughout and that
the outputs are not register ed.
Memory Megafunctions
To convert RAM and ROM originally tar geting the APEX II or APEX 20K
architect ure to St ratix or Stratix GX memory, specify Stratix or Stratix GX
as the target family in the MegaWi zard Plug-In Manager. The software
inclock
Port A
data_in
Port A
wren
Port B
data_out
AB
AOld
Port B
wren
B
Address Q
addressA and
addressB
inclock
Port A
data_in
Port A
wren
Port B
data_out
AB
BUnknown
Port B
wren
Address Q
addressA and
addressB
Altera Corporation 10–13
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
updates the memory module for the Stratix or Stratix GX architecture and
instantiates the new synchronous memory megafunction, altsyncram,
which supports both RAM and ROM blocks in the Stratix and Stratix GX
architectures.
FIFO Conditions
First-in first-out (FIFO) functionality is slightly different in Stratix and
Stratix GX devices compared to APEX II and APEX 20K devices. Stratix
and Stratix GX devices do not support simultaneous reads and writes
from an empty FIFO buffer. Also, Stratix and Stratix GX devices do not
support the lpm_showahead parameter when targeting a FIFO buffer
because the TriMatrix memory blocks are synchronous. The
lpm_showahead parameter for APEX II and APEX 20K devices puts the
FIFO buffer in “read-acknowledge” mode so the first data written into the
FIFO buffer immediately flows through to the output. Other than these
two differences, all APEX II and APEX 20K FIFO functions are fully
compatible with the Stratix and Stratix GX architect ures.
Design Migration Mode in Quartus II Software
The Quartus II software features a migration mode for simplifying the
process of converting APEX II and APEX 20K memory functions to the
Stratix or Stratix GX architecture. If the design can use the Stratix or
Stratix GX altsyncram megafunction as a replacement for a previous
APEX II or APEX 20K memory function while maintaining functionally
similar behavior, the Quartus II software automatically converts the
memory. The software produces a warning message during compilation
reminding you to verify that the design migrated correctly.
For memory blo cks wit h all inpu ts registe r ed , the existi ng me gafunction
is converted to the new altsyncram megafunction. The softwar e
generates a warning when the altsyncram megafunction is
incompatible. For example, a RAM block with all inputs registered except
the read enable compiles with a warning message indicating that the
read-enable port is regi stered.
You can suppress warning messages for the entire project or for
individual memory blocks by setting the
SUPPRESS_MEMORY_CONVERSION_WARNINGS parameter to “on” as a
global parameter by selecting Assignment Organizer (Tools menu). In
the Assignment Organizer window, click Parameters in the Assignment
Categories box. Type SUPPRESS_MEMORY_CONVERSION_WARNINGS in
the Assignment Name box and type ON in the Assignment Se tting box.
To suppress these warning messages on a per -memory-instance basis, set
the SUPPRESS_MEMORY_CONVERSION_WARNINGS parameter in the
Assignment Organizer to “on” for the memo ry instance.
10–14 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
TriMatrix Memory
If the functionality of the APEX II or APEX 20K memory megafunction
differs from the altsyncram functionality and at least one clock feeds
the memory megafunction, the Quartus II software co nverts the APEX II
or APEX 20K memory megafunction to the Stratix or Stratix GX
altsyncram megafunction. This conversion is useful for an initial
evaluation of how a design might perform in Stratix or Stratix GX devices
and should only be used for evaluation purposes. During this process, the
Quartus II software generates a warning that the conversion may be
functionally incorrect and timing r esults may not be accurate. Since the
functionality may be incorrect and the compilation is only intended for
comparative purposes, the Quartus II software does not generate a
programm ing file. A functionally correct conversion requires manually
instantiating the altsyncram megafunction and may requir e additional
design changes.
If the previous memory function does not hav e a clock (fully
asynchronous), the fitting-evaluation conversion results in an error
message during compilation and does not successfully convert the
design.
fSee AN 210: Converting Memor y from Asynchronous to Synchronous for
Stratix & Stratix GX Designs for more information.
Table 10–5 summarizes the possible scenarios when using design
migration mode and the resulting behavior of the Quartus II software.
The most common cases where design-migration mode may have
difficulty converting the existing design are when:
■A port is reading from an address that is being written to by another
port (mixed-port read-during-write mode). If both ports are using
the same clock, the r ead port in Stratix and Stratix GX devices do not
see the new data until the next clock cycle, after the new data was
written.
Altera Corporation 10–15
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
■There are differences in power-up behavior betwee n APEX II,
APEX 20K, and Stratix and Stratix GX devices. You should manually
account for these differences to maintain desired operation of the
system.
Table 10–5. Migration Mode Summary
Memory
Configuration Conditions Possible
Instantiated
Megafunctions
Quartus II Warning
Message(s)
Programming
File
Generated
Single-port All inputs are registered. altram
altrom
lpm_ram_dq
lpm_ram_io
lpm_rom
Power-up differences. (1) Yes
Multi-port (two-,
thre e-, or f our-port
functions)
All inputs are registered. altdpram
lpm_ram_dp
altqpram
alt3pram
Power-up differences.
Mixed-port read- during-
write. (1)
Yes
Dual-port Read-enable ports are
unregistered.
Other inputs registered.
altdpram
lpm_ram_dp
altqpram
alt3pram
Power-up differences.
Mixed-port read- during-
write.
Read enable will be
registered. (1)
Yes
Dual-port Any other unregistered
port except read-enable
ports.
Clock available.
altdpram
lpm_ram_dp
altqpram
alt3pram
Compile for fitting- evaluation
purposes. No
Single-port At least one registered
input.
Clock available.
altram
lpm_ram_dq
lpm_ram_io
Compile for fitting- evaluation
purposes. No
No clock No clock. altram
altrom
altdpram
altqpram
alt3pram
altdpram
lpm_ram_dq
lpm_ram_io
lpm_rom
lpm_ram_dp
lpm_ram_dp
Error – no conversion
possible. No
Note to Table 10–5:
(1) If the SUPPRESS_MEMORY_COUNVERSION_WARNINGS parameter is turned on, the Quartus II software does not
issue these warnings.
10–16 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
DSP Block
DSP Block Stratix and Stratix GX device DSP blocks outperform LE-based
implementations for common DSP functions. Each DSP block contains
several multipliers that can be configured for widths of 9, 18, or 36 bits.
Depending on the mode of operation, these multipliers can optionally
feed an adder/subtractor/accumulator or summation unit.
You can configure the DSP block’s input registers to efficiently
implement shift registers for serial input sharing, eliminating the need for
external shift registers in LEs. You can add pipeline registers to the DSP
block for accelerated operation. Registers are available at the input and
output of the multiplier, and at the output of the
adder/subtractor/accumulator or summation block.
DSP blocks have four modes of operation:
■Simple multipl ier mode
■Multiply-accumulator mode
■Two-mul tipl iers adder mode
■Four-multipliers adder mode
Associated megafunctions are available in the Quartus II software to
implement each mode of the DSP block.
DSP Block Megafunctions
You can use the lpm_mult megafunction to configure the DSP block for
simple multiplier mo de. You can set the lpm_mult Multiplier
Implementation option in the MegaWizard Plug-In Manager to either
use the default implementatio n, ESBs, or the DSP blocks. If you select the
Use Default option, the compiler first attempts t o place the multiplier in
the DSP blocks. However, under certain conditions, the compiler ma y
implement the multiplier in LEs. The placement depends on factors such
as DSP block resource consumption, the width of the multiplier, whether
an operand is a constant, and other options chosen for the me gafunction.
Stratix and Stratix GX devices do not suppo rt the Use ESBs option. If you
select this option, the Quartus II software tries to place the multiplier in
unused DSP blocks.
You can recompile APEX II or APEX 20K designs using the lpm_mult
megafunction for Stratix and Stratix GX devices in the Quartus II
software without changing the megafunction. This makes converting
lpm_mult megafunction designs to Stratix or Stratix GX devices
straightforward.
Altera Corporation 10–17
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
APEX II and APEX 20K designs use pipeline stages to impr ove registered
performance of LE-based multipliers at the expense of latency. However,
you may not need to use pipeline stages when targeting Stratix and
Stratix GX high-speed DSP blocks. The DSP blocks offer thr ee sets of
dedicated pipeline registers. Therefore, Alte ra recommends that you
reduce the number of pipeline stages to thr ee or fewer and implement
them in the DSP blocks. Additional pipeline stages are implemented in
LEs, which add latency without providing any performance benefit.
For example, you can configure a DSP block for 36 ×36-bit multiplication
using the lpm_mult megafunction. If you specify two pipeline stages,
the software uses the DSP block input and pipeline registers. If you
specify three pipeline stages, the soft war e places the third pipeline stage
in the DSP block output registers. This design yields the same
performance with three pipeline stages because the critical path for a
36 ×36-bit operation is within the multiplier. With four or more pipeline
stages, the device ineffici ently uses LE resources for the additional
pipeline stages . Therefor e, if multiplier modules in APEX II or APE X 20K
designs ar e conve rted to Strati x or Stratix GX designs and do not require
the same number of pipelin e stages, the surrounding circuitry must be
modified to preserve the original functionality of the design.
A design with multipliers feeding an accumulator can use the
altmult_accum (MAC) megafunction to set the DSP block in multiply-
accumulator mode. If the APEX II or APEX 20K design already uses LE-
based multipliers feeding an accumul ator, the Quartus II software does
not automatically instantiate the new altmult_accum (MAC)
megafunction. Therefore, you should use the MegaWizard Plug-In
Manager to instantiate the altm ult_accum (MAC) megafu nct ion. You
can also use LeonardoSpectrum™ or Synplify synthesis tools, which have
DSP block inference support, to instantiate the megafunction.
Designs that use multipliers fee ding into adders can instantiate the new
altmult_add megafunction to configure the DSP blocks for two-
multipliers adder or four-multipliers adder mode. You can also use the
altmult_add megafunction for stand-alone multipliers to take
advantage of the DSP blocks featur es suc h as dynami c sign cont rol of the
inputs and the input shift register connections. These features are not
accessible through the lpm_mult megafunction. If your APEX II or
APEX 20K designs already use multipliers feeding an adder/subtractor,
the Quartus II software does not automat ically infer the new
altmult_add megafunction. Therefore, you should ste p through the
MegaWizard Plug-In Manager to instantiate the new altmult_add
megafunction or use LeonardoSpectrum or Synplify synthesis tools,
which have DSP block inference support.
10–18 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
PLLs & Clock Networks
Furthermore, the altmult_add and altmul t_accum (MAC)
megafunctions are only available for Stratix and Stratix GX devices
because these megafunctions target Stratix and Stratix GX DSP blocks,
which are not available in other device families. If you attempt to use
these megafunctions in designs that target other Altera device families,
the Quartus II software repo rts an error message. Use lpm_mult and an
lpm_add_sub or an altaccumulate megafunction for similar
functionality in other device famili es.
If you use a third-party synthesis tool, you may be able to avoid the
megafunction conversion process. LeonardoSpectrum and Synplify
provide inference support for lpm_mult, altmult_add, and
altmult_accum (MAC) to use the DSP blocks.
If your design does not require you to implement all the multipliers in
DSP blocks, you must manually set a global parameter or a parameter for
each instance to for ce the tool to implement the lpm_mult megafunction
in LEs. Depending on the synthesis tools, inference of DSP blocks is
handled differently.
fFor more information about using DSP blocks in Stratix and Stratix GX
devices, see the DSP Blocks in Stratix & Stratix GX Devices chapter of the
Stratix Device Handbook.
PLLs & Clock
Networks Stratix and Stratix GX devices provide exceptional clock management
with a hierarchical clock network and up to four enhanced phase-locked
loops (PLLs) and eight fast PLLs ve rsus the four general-purpose PLLs
and four True-LVDSTM PLLs in APEX II devices. By prov iding superior
clock interfacing, numer ous advanced clocking features, and significant
enhancements over APEX II and APEX 20K PLLs, the Stratix and
Stratix GX device PLLs increase system performance and bandwidth.
Clock Networks
There are 16 global clock networks available throughout each Stratix or
Stratix GX device as well as two fast regional and four regional clock
networks per device quadrant, resulting in up to 40 uni q ue clock
networks per device. The incr eased number of dedicated clock r esources
available in Stratix and Stratix GX devices eliminate the need to use
general-purpose I/O pins as clock inputs.
Stratix EP1S25 and smaller devices have 16 dedicated clock pins and
EP1S30 and larger devices have four additional clock pins to feed vario us
clocking networks. In comparison, APEX II d evices have eight dedicated
clock pins and APEX 20K E and APEX 20KC devic es have four dedicate d
clock pins.
Altera Corporation 10–19
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
The dedicated clock pins in Stratix and Stratix GX devices can feed the
PLL clock inputs, the global clock networks, and the regional clock
networks. PLL outputs and internally-generated signals can also drive
the global clock network. These global clocks are available throughout
the entire device to clock all device resources.
Stratix and Stratix GX devices are divided into four quadrants, each
equipped with fo ur r egion al clock ne tworks. The r egional clock ne twork
can be fed by either the dedicated clock pins or the PLL outputs within its
device quadrant. The regional clock network can only feed device
reso urces within its particular device quadrant.
Each Stratix and Stratix GX device provides eight dedicated fast clock
I/O pins FCLK[7..0] versus four dedicated fast I/O pins in APEX II
and APEX 20K devices. The fast regional clock network can be fed by
these dedicated FCLK[7..0] pins or by the I/O interc onnect. The I/O
interconnect allows internal logic or any I/O pin to drive the fast regional
clock network. The fast regional clock network is available for general-
purpose clocking as well as high fan-out control signals such as clear,
prese t, enable, TRDY and IRDY for PCI applications, or bidirectional or
output pins.
EP1S25 and smaller devices have eight fast regional clock networks, two
per device quadrant. The quadrants in EP1S30 and lar g er devices are
divided in half, and each half-quadrant can be clocked by one of the eight
fast regional networks. Additionally, each fast regional clock network can
drive its neighboring half-quadrant (within the same devic e quadrant).
PLLs
Table 10–6 highlights Stratix and Stratix GX PLL enhancements to
existing APEX II, APE X 20KE and APEX 20KC PLL features.
Table 10–6. Stratix & Stratix GX PLL vs. APEX II, APEX 20KE & APEX 20KC PLL Features (Part 1 of 2)
Feature Stratix & Stratix GX APEX II PLLs APEX 20KE &
APEX 20KC PLLs
Enhanced PLLs Fast PLLs
Number of PLLs Two (EP1S30 and
smaller devices);
four (EP1S40 and
larger devices) (9)
Four (EP1S25 and
smaller devices);
eight (EP1S30
and larger
devices) (10)
Four general-
purpose PLLs and
four LVDS PLLs
Up to four general-
purpose PLLs. Up
to two LVDS PLLs.
(1)
Minimum input frequency 3 MHz 15 MHz 1.5 MHz 1.5 MHz
Maximum input frequency 250 to 582 MHz (2) 644.5 MHz (11) 420 MHz 420 MHz
10–20 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
PLLs & Clock Networks
Enhanced PLLs
Stratix and Stratix GX devices provide up to four enhanced PLLs with
advanced PLL features. In addition to the feature changes mentioned in
Table 10–6, Stratix and Stratix GX device PLLs include many new,
Internal clock outputs per
PLL 63 (3) 22
External clock outputs per
PLL Four
differential/eight
singled-ended or
one single-ended
(4)
Yes (5) 11
Phase Shift Down to 160-ps
increments (6) Down to 125-ps
increments (6) 500-ps to 1-ns
resolution 0.4- to 1-ns
resolution
Time shift 250-ps increments
for ± 3 ns (7) No No No
M counter values 1 to 512 1 to 32 1 to 160 2 to 160
N counter values 1 to 512 N/A 1 to 16 1 to 16
PLL clock input sharing No Yes Yes Yes
T1/E1 rate conversion (8) No No Yes Yes
Notes to Table 10–6:
(1) EP20K200E and smaller device s only have two general-purpose PLLs. EP20K400E and larger devices have two
LVDS PLLs and four general-purpose PLLs. For more information, see AN 115: Using the ClockLock & ClockBoost
PLL Features in APEX Devices.
(2) The maximum input frequency for Stratix and Stratix GX enhanced PLLs depends on the I/O standard used with
that input clock pin. For more information, see the Stratix Device Family Data Sheet section of the Stratix Device
Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of the Stratix GX Device Handbook, Volume 1.
(3) Fast PLLs 1, 2, 3, and 4 have three internal clock output ports per PLL. Fast PLLs 7, 8, 9, and 10 have two internal
clock output ports per PLL.
(4) Every Stratix device has two enhanced PLLs with eight single-ended or four differential outputs each. Two
additional enhanced PLLs in EP1S80, EP1S60, and EP1S40 devices each have one single-ended output.
(5) Any I/O pin can be driven by the fast PLL global or regional outputs as an external clock output pin.
(6) The smallest phase shift unit is determined by the voltage-controlled oscillator (VCO) period divided by 8.
(7) There is a maximum of 3 ns between any two PLL clock outputs.
(8) The T1 clock frequency is 1.544 MHz and the E1 clock frequency is 2.048 MHz, which violates the minimum clock
input frequency requirement of the Stratix PLL.
(9) Stratix GX EP1SGX10 and EP1SGX25 co nt ai n two. EP1SGX40 contain s four.
(10) Stratix GX EP1SGX10 and EP1SGX25 contain tw o. EP1S GX4 0 contains four.
(11) Stratix GX supports clock rates of 1 Gbps using DPA.
Table 10–6. Stratix & Stratix GX PLL vs. APEX II, APEX 20KE & APEX 20KC PLL Features (Part 2 of 2)
Feature Stratix & Stratix GX APEX II PLLs APEX 20KE &
APEX 20KC PLLs
Enhanced PLLs Fast PLLs
Altera Corporation 10–21
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
advanced features to improve system timing management and
performance. Table 10–7 shows some of the new features available in
Stratix and Stratix GX enhanced PLLs.
Fast PLLs
Stratix and Stratix GX fast PLLs are similar to the APEX II True-LVDS
PLLs in that the W setting, which governs the relationship between the
clock input and the data rate, and the J setting, which controls the width
Table 10–7. Stratix & Stratix GX Enhanced PLL Features
Feature Description
Programmable duty cycle (1) Allows variable duty cycle for each PLL clock output.
PLL clock outputs can feed
logic array (1) Allows the PLL cloc k outputs to feed data ports of registers or combinatorial logic.
PLL locked output can feed
the logic array (1) Allows the PLL locked port to feed data ports of registers or combinatorial logic.
Multiplication allowed in
zero-delay buffer mode or
external feedback mode
The PLL clock outputs can be a multiplied or divided down ratio of the PLL input
clock.
Programmable phase shift
allowed in zero-delay buffer
mode or external feedback
mode (2)
The PLL clock outputs can be phase shifted. The phase shift is relative to the PLL
clock output.
Phase frequency detector
(PFD) disable Allows the VCO to operate at its last set control voltage and frequency with some
long term drift.
Clock output disable (3) PLL maintains lock with output clocks disabled. (4)
Programmable lock detect &
gated lock Holds the lock signal low for a programmable number of input clock cycles.
Dynamic clock switchover Enables the PLL to switch between two reference input clocks, either for clock
redundancy or dual-clock domain applications.
PLL reconfiguration Allows the counters and delay elements within the PLL to be reconfigured in real-
time without reloading a programmer object file (.pof).
Programmable bandwidth Provides advanced control of the PLL bandwidth by using the programmable
control of the PLL loop characteristics.
Spread spectrum Modulates the target frequency over a frequency range to reduce
electromagnetic interference (EMI) emissions.
Notes to Table 10–7:
(1) These features are also available in fast PLLs.
(2) In addition to the delay ch ains at each cou nter, you can specify the pr ogramm able phase shift for each PLL out put
at fine and coarse levels.
(3) Each PLL clock output has an associated clock enable sign al.
(4) If the PLL is used in external feedback mode, the PLL will need to relock.
10–22 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
PLLs & Clock Networks
of the high-speed differential I/O data bus, do not have to be equal.
Additionally, Stratix and Stratix GX fast PLLs offer up to three clock
outputs, two multiplied high-speed PLL clocks to drive the
serializer/deserializer (SERDES) block and/or an external pin, and a
low-speed clock to drive the logic array. You can use fast PLLs for both
high-speed interfacing and for general-purpose PLL applications.
Table 10–8 shows the differences between Stratix and Stratix GX fast
PLLs and APEX II and APEX 20K True-LVDS PLLs.
The Stratix and Stratix GX fast PLL VCO frequency range is 300 to 840
MHz, and the APEX II True-L VDS PLL VCO frequency range is 200 MHz
to 1 GHz. Therefor e, you must update designs that use a data rate of less
than 300 megabits per second (Mbps) to use the enhanced PLLs and M512
RAM blocks in SERDES bypass mode. Additionally, you must update
designs that use a data rate faster than 840 Mbps.
altpll Megafunction
Altera recommends that you replace instances of the altclklock
megafunction with the altpll megafunction to take advantage of new
Stratix and Stratix GX PLL features. Although in most cases you can
retarget your APEX II or APEX 20K design to a Stratix or Stratix GX
Table 10–8. Stratix & Stratix GX Fast PLL vs. APEX II & APEX 20K True-LVDS PLL
Feature Stratix & Stratix GX APEX II APEX 20KE
APEX 20KC
Number of fast PLLs or True-
LVDS PLLs (1) Four (EP1S25 and smaller
devices) fast PLLs
Eight (EP1S30 and larger
devices) fast PLLs (4)
Four True-LVDS
PLLs Two True-LVDS
PLLs (2)
Number of channels per
transmitter/receiver block 20 18 18
VCO frequency 300 to 840 MHz (5) 200 MHz to 1GHz 200 to 840 MHz
Minimum input frequency
M = 4, 5, 6 300 – M MHz 50 MHz 50 MHz
M = 4 (3)
Minimum input frequency
M = 7, 8, 9, 10 300 – M MHz 30 MHz 30 MHz
M = 7, 8 (3)
Notes to Table 10–8:
(1) You can also use Stratix and Stratix GX device fast PLLs for general-purpose PLL applications.
(2) EP20K400E and larger devices have tw o True-LVDS PLLs.
(3) In APEX 20KE and APEX 20KC devices, M = 4, 7, or 8.
(4) Stratix GX EP1SGX10 and EP1SGX25 co nt ai n two. EP1SGX10 contain s four.
(5) Stratix GX supports a frequency range of 300–1000 MHz (using DPA).
Altera Corporation 10–23
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
device with the altclklock megafunction, there are specific cases
where yo u must use the altpll megafunction, as explained in this
section.
In the MegaW izar d Plug-In Manager, select the altpll megafunction in
the I/O directory from the Available Megafunctions box (see
Figure 10–9). The altclklock megafunction is also available from the
Quartus II software for backward compatibility, but instantiates the new
altpll megafunction when targeting Stratix or Stratix GX devices. The
Quartus II Compiler automatically selects whether the altpll modu le
uses either an enhanced PLL or a fast PLL based on the design’s PL L
needs and the feature requirements of each PLL.
Figure 10–9. altpll Megafunction Selection in the MegaWizard Plug-In
Manager
You can compile APEX II, APEX 20KE, and APEX 20KC designs using the
altclklock megafunction in normal mode for Stratix and Stratix GX
devices without updating the megafunction. However, you should
replace the altclklock megafunction with the altpll megafunction.
If the Quartus II software cannot implement the requested clock
multiplication and division of the PLL, the comp iler reports an er ror
message with the appropriate reason stated.
10–24 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
PLLs & Clock Networks
APEX II, APEX 20KE, and APEX 20KC devices have only one external
clock output available per PLL. Therefore, when retargeting an APEX II,
APEX 20KE, or APEX 20KC design that uses PLLs in zero delay buffer
mode or external feedback mo de to a Stratix or St ra t ix GX device, y ou
should replace instances of the altclklock megafunction. If an
APEX II, APEX 20KE, or APEX 20KC altclklock module only uses one
PLL clock output (internal or external) and is compiled t o targe t a Stratix
or Stratix GX device, the design compile s su cc essfully with a warning
that the design uses the Stratix or Stratix GX PLL external clock output,
extclk0. However, if the APEX II, APEX 20KE, or APEX 20KC PLL has
more than one PLL clock output, you must replace instances of the
altclklock megafunction w ith the altpll megafunction because t he
Quartus II Compiler does not know which PLL clock output is fed to an
external output pin or fed back to the Stratix or Stratix GX device fbin
pin. For example, if an APEX II, APEX 20KE, or APEX 20KC design with
an altclklock megafunction uses the clock0 output port to feed the
external clock output pin and the clock1 output port to feed the internal
logic array, the Quartus II software generates an error during
compilation and you must use the MegaWizard Plug-In Manager to
instantiate the altpll megafunction. By using the altpll
megafunction, you can choose which of the four external clock outputs to
use and take advantage of the new Stratix and Stratix GX PLL features
now available in the zer o delay buffer mode or external feedback mode.
Timing Analysis
When the Quartus II software performs a timing analysis for APEX II,
APEX 20KE, or APEX 20KC designs, PLL cloc k settings override the
project clock settings. However, during timing analysis for Stratix and
Stratix GX designs using PLLs, the project clock settings override the PLL
input clock frequency and duty cycle settings. The MegaWizard Plug-In
Manager does not use the project clock settings to determine the altpll
parameters. This save s time with designs that use features such as clock
switchover or PLL reconfiguration because the Quartus II software can
perform a timing analysis without recompili ng the design. It is important
to note the following:
■A warning during compilation r eports that the project clock set tings
overrides the PLL clock settings.
■The project clock setting overrides the PLL clock settings for timing-
driven compilation.
■The compiler will check the lock fr equency range of the PLL. If the
frequency specified in the project clock settings is outside the lock
frequency range, the PLL clock settings will not be overridden.
■Performing a timing analysis without r ecompiling your design does
not change the programming files. You must recompile your design
to update the programming files.
Altera Corporation 10–25
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
■A Default Required fMAX setting does not override the PLL clock
settings. Only individual cl ock settings override the PLL clock
settings.
Therefor e, you can enter dif fere nt pro ject clock settings corr espond ing to
new PLL settings and accelerate timing analysis by eliminating a full
compilation cycl e.
fFor more information about using Stratix and Stratix GX PLLs, see the
General-Purpose PLLs in Stratix & Stratix GX Devices chapter.
I/O Structure The Stratix and Stratix GX I/O element (IOE) architecture is similar to the
APEX II architecture, with a total of six registers and a lat ch in each IOE.
The regi sters are organi zed in three sets: two output registers to drive a
single or double-data rate (DDR) output path, two input registers and a
latch to support a single or DDR input path, and two output enable
registers to enhance clock-to-output enable timing or fo r DDR SDRAM
interfacing. A ne w synchronous reset signal is available to each of the
three sets of registers for pre set or clear, or neither. In addition to the
advanced IOE architecture, the Stratix and Stratix GX IOE features
dedicated circuitry for external RAM interfacing, new I/O standards,
differential on-chip termination, and high-speed differ enti al I/O
standard support.
External RAM Interfacing
The advanced Stratix and Stratix GX IOE architectur e includes ded icated
circuitry to interface with external RAM. This circuitry provides
enhanced support for external high-speed memory devices such as DDR
SDRAM and FCRAM. The DDR SDRAM interface uses a bidirec tional
signal, DQS, to clock data, DQ, at both the transmitting and receiving
device. Stratix and Stratix GX devices transmit the DQS signal with the DQ
data signals to minimize clock to data skew.
Stratix and Stra tix GX devices include gr oups of programmable DQS and
DQ pins, in the top and bottom I/O banks of the device. Each group
consists of a DQS pin that supports a fixed number of DQ pins. The number
of DQ pins depends on the DQ bus mode. When using the external RAM
interfacing circuitry, the DQS pin drives a dedicated clock network that
feeds the DQ pins residing in that bank. The Stratix and Stratix GX IOE has
programmable delay chains that can phase shift the DQS signal by 90° or
72° to ensure data is sampled at the appr opriate po int in time. Ther efor e,
the Stratix and Stratix GX devices make full u se of t he IO Es , and remove
the need to build the input data path in the logic array. You can make
these I/O assignments in the Quartus II Assignment Organizer.
10–26 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
I/O Structure
fFor more information on external RAM i nterfacing, see the St ratix Device
Family Data Sheet secti o n of th e Stratix Device Handbook, Volume 1 or the
Stratix GX Device Family Data Sheet in the Stratix GX Device Family
Handbook, Volume 1.
I/O Standard Support
The Stratix and Stratix GX devices support all of the I/O standards that
APEX II and APEX 20K devices support, including high-speed
differential I/O standards such as LVDS, LVPECL, PCML, and
HyperTransportTM technology, differential HSTL on input and output
clocks, and differential SSTL on output clocks. Stratix and Stratix GX
devices also introduce support for SSTL-18 Class I & II. Similar to APEX II
devices, Stratix and Stratix GX devices only support certain I/O
standards in designated I/O banks. In add ition, vref pins ar e dedicate d
pins in Stratix and Stratix GX devices and now support up to 40 input
pins.
fFor more information about I/O standard support in Stratix and
Stratix GX devices, see the Selectable I/O Standards in Stratix &
Stratix GX Devices chapter.
High-Speed Differential I/O Standards
Stratix and Stratix GX devices support high-speed differential interfaces
at speeds up to 840 Mbps using high-speed PLLs that drive a dedicated
clock network to the SERDES. Each fast PLL can drive up to 20 high-
speed channels . Stratix and Stratix GX devices use enhanced PLLs and
M512 RAM blocks to provide up to 420 Mbps performance for SERDES
bypass clock interfacing. There is no restriction on the number of
channels that can be clocked using this scenario.
Stratix and Stratix GX devices have a different number of differential
channels than APEX II devices. Tables 10–9 and 10–10 highlight the
number of differential channels supported in Stratix and Stratix GX
devices.
Table 10–9. Number of Dedicated DIfferential Channels in Stratix Devices
(Part 1 of 2) Note (1)
Device Pin Count Number of Receiver
Channels Number of
Transmitter Channels
EP1S10 672 36 36
780 44 44
Altera Corporation 10–27
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
EP1S20 672 50 48
780 66 66
EP1S25 672 58 56
780 66 70
1,020 78 78
EP1S30 780 66 70
956 80 80
1,020 80 80
22
EP1S40 956 80 80
1,020 80 80
10 10
1,508 80 80
10 10
EP1S60 956 80 80
1,020 80 80
10 12
1,508 80 80
36 36
EP1S80 956 80 80
040
1,508 80 80
56 72
Note to Table 10–9:
(1) For information on channel speeds, see the Stratix Device Family Data Sheet section
of the Stratix Device Handbook, Volume 1 and the High-Speed Differential I/O
Interfaces chapter in the Stratix Device Handbook, Volume 2.
Table 10–9. Number of Dedicated DIfferential Channels in Stratix Devices
(Part 2 of 2) Note (1)
Device Pin Count Number of Receiver
Channels Number of
Transmitter Channels
10–28 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
I/O Structure
The differential I/O within Stratix GX also provides dynamic phase
alignment (DPA). DPA enables the differential I/O to operate up to
1 Gbps per channel. DPA automatically and continuously tracks
fluctuations caused by system vari ations and self-adjusts t o eliminate the
phase skew between the multiplied clock and the serial data. The block
contains a dynamic phase selector for phase detection and selection, a
SERDES, a synchronizer, and a data realigner circuit. You can bypass the
dynamic phase aligner without affecting the basic source-synchronous
operation of the channel by using a separate deserializer.
If you compile an APEX II LVDS design that uses clock-data
synchroniz ation (CDS) for a Stratix or Strat ix GX device, the Quartus II
software is sues a warning during compilation that Stratix a nd Stratix GX
devices do not support CDS.
Stratix and Stratix GX devices offer a flexible solutio n using new byte
realignment circuitry to correct for byte misalignment by shifting, or
slipping, data bits. Stratix and Stratix GX devices activate the byte
realignment circuitry when an external pin (rx_data_align) or an
internal custom-made state machine asserts the SYNC node high.
APEX II, APEX 20KE, an d AP EX 20KCde vi ces have a dedicated
transmitter clock output pin (LVDSTXOUTCLK). In Stratix and Stratix GX
devices, a transmitter dataout channel with an LVDS clock (fast clock)
generates the transmitter clock output. There f ore, you can drive any
Table 10–10. Number of Dedicated DIfferential Channels in Stratix GX
Devices Note (1)
Device Pin Count Number of
Transceivers
Number of Source-
Synchronous
Channels
EP1SGX10 C 672 4 22
EP1SGX10 D 672 8 22
EP1SGX25 C 672 4 39
EP1SGX25 D 672/1,020 8 39
EP1SGX25 F 1,020 16 39
EP1SGX40 D 1,020 8 45
EP1SGX40 G 1,020 20 45
Note to Table 10–10:
(1) For information on channel speeds, see the Stratix GX Device Family Data Sheet
section of th e Stratix GX Device Handbook, Volume 1 and the High-Speed
Source -Synchro nous Differential I/O Interfaces in Stratix GX Devices chapter of the
Stratix GX Device Handbook, Volume 2.
Altera Corporation 10–29
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
channel as an output clock to an I/O pin, not just dedicated clock output
pins. This solution offers better versatility to address various applications
that requ ire more comp lex clocking schemes.
fFor more information on differential I/O support, data r ealignment, and
the transmitter clock output in Stratix and Stratix GX devices, see the
High-Speed Differential I/O Interfaces in Stratix Devices chapter.
altlvds Megafunction
To take full advantage of the high-speed diff erential I/O standards
available in Stratix and Stratix GX devices, you should update each
instance of the altlvds megafunction in APEX II, APEX 20KE, and
APEX 20KC designs. In the MegaWizard Plug-In Manager, choose the
altlvds megafunction, select Stratix or Stratix GX as the target device
family, update the megafunction, and recompile your design.
The altlvds megafunction supports new Stratix and Stratix GX
parameters that are not available for APEX II, APEX 20KE, and
APEX 20KC devices. Tables 10–11 and 10–12 describe the new
parameters for the LVDS receiver and LVDS transmitter, respectively.
Table 10–11. New altlvds Parameters for Stratix LVDS Receiver Note (1)
Parameter Function
input_data_rate (2) Specifies the data rate in Mbps. This parameter replaces the
multiplication factor W.
inclock_data_alignment Indicates the alignment of rx_inclk and rx_in data.
rx_data_align Drives the data alignment port of the fast PLL and enables byte
realignment circuitry.
registered_data_align_input Registers the rx_data_align input port to be clocked by
rx_outclock.
common_rx_tx_pll (3) Indicates the fast PLL can be shared between receiv er and transmitter
applications.
Table 10–12. New altlvds Parameters for Stratix LVDS Transmitter (Part 1 of 2) Note (1)
Parameter Function
output_data_rate (2) Specifies the data rate in Mbps. This parameter replaces the
multiplication factor W.
inclock_data_alignment Indicates the alignment of tx_inclk and tx_in data.
outclock_alignment Specifies the alignment of tx_outclock and tx_out data.
10–30 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration
Above the standard I/O offered by APEX II, APEX 20K, and Stratix
devices, Stratix GX devices pr ovide up to 20 3.175 Gbps transceivers. The
transceivers provide high-speed serial links for chip-to-chip, backplane,
and line-side connectiv ity and su pport a number of the e me rging
high-speed protocols. You can find more information in the Stratix GX
Family Data Sheet in the Str ati x GX Family Handbook, Vol ume 1 .
Configuration The Stratix and Stratix GX devices supports all current configuration
schemes, including the use of enhanced configuration devices, passive
serial (PS), passive parallel asynchronous (PPA), fast passive parallel
(FPP), and JTAG. Stratix and Stratix GX devices also provid e a number of
new configuration enhancements that you can take advantage of when
migrating APEX II and APEX 20K designs to Stratix and Stratix GX
devices.
Configuration Speed & Schemes
You can confi gure Stratix and Strati x GX devices at a maximum clock
speed of 100 MHz, which is faster than the 66-MHz and 33-MHz
maximum configuration speeds for APEX II and APEX 20K de v ices,
respectively. Similar to APEX II devices, you can use 8-bit parallel data to
configure Stratix and Stratix GX devices (the target device can receive
byte-wide configuration data on each clock cycle) significantly speeding
up configuration times.
You can se le c t a config uration scheme based on how the MSEL pins are
driven. Stratix and Stratix GX devices have three MSEL pins (APEX II and
APEX 20K devices have two MSEL pins) for determining the
configuration sche me.
registered_input Specifies the clock source for the input synchronization registers,
which can be either tx_inclock or tx_coreclock. Used only
when the Registered Inputs option is selected.
common_rx_tx_pll (3) Indicates the fast PLL can be shared between receiv er and transmitter
applications.
Notes to Tables 10–11 and 10–12:
(1) You can specify these parameters in the MegaWizard Plug-In Manager.
(2) You must specify a data rate in the MegaWizard Plug-In Manager instead of a W factor.
(3) The same fast PLL can be used to clock both the receiver and transmitter only if both are running at the same
frequency.
Table 10–12. New altlvds Parameters for Stratix LVDS Transmitter (Part 2 of 2) Note (1)
Parameter Function
Altera Corporation 10–31
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
fFor more information about Stratix and Stratix GX configuration
schemes, see the Configuring Stratix & Stratix GX Devices chapter.
Remote Update Configuration
The APEX 20K device family intr odu ced the concept of remote update
configuration, where you could send the APEX 20K device new
configuration files from a rem ote source and the device would store the
files in flash memory and reconfigure itself with the new configuration
data. The Stratix and Stratix GX devices enhance support for remote
update configuration with new , dedicated circuitry to handle and r ecover
from errors. If an error occurs either during device configuration or in
user mode, this new circuitry reconfigures the Stratix or Stratix GX device
to a known state. Additionally, the Stratix and Stratix GX devices have a
user watchdog timer to ensure the application configuration data
executes successfully during user mode. User logic must continually reset
this watchdog timer in order to validate that the application
configuration data is functioning properly.
fFor more information about how to use the remote and local update
modes, see the Remote System Configuration with Stratix & Stratix GX
Devices chapter.
JTAG Instruction Support
Stratix and Stratix GX devices support two new JTAG instructions,
PULSE_NCONFIG and CONFIG_IO. The PULSE_NCONFIG instruction
emulates pulsing the nCONFIG signal low to trigger reconfiguration,
while the actual nCONFIG pin on the device is unaffected. The
CONFIG_IO instruction allows you to use the JTAG chain to conf igure
I/O standard s for all pins. Because this instruc tion interrupts device
configuration, you should reconfigure the Stratix or Stratix GX device
after you finish JTAG testing to ensure proper device operation.
Table 10–13 compares JTAG instruction support in Stratix and Stratix GX
devices versus APEX II and APEX 20K devices. For further info rmation
about the supported JTAG instructions, s ee the appropriate device family
data sheet.
Table 10–13. JTAG Instruction Support (Part 1 of 2)
JTAG Instruction Stratix APEX II APEX 20K
SAMPLE/PRELOAD vvv
EXTEST vvv
BYPASS vvv
USERCODE vvv
10–32 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Conclusion
Conclusion The Stratix and Stratix GX devices extend the advanced features available
in the APEX I I and AP EX 20K device families to delive r a co mple te
system-on-a-programmable-chip (SOP C) solution. By following these
guidelines, you can easily transition current APEX II and APEX 20K
designs to take advantage of the new features available in Stratix and
Stratix GX devices.
IDCODE vvv
ICR Instructions vvv
SignalTapTM II Instructions vvv
HIGHZ vv
CLAMP vv
PULSE_NCONFIG v
CONFIG_IO v
Table 10–13. JTAG Instruction Support (Part 2 of 2)
JTAG Instruction Stratix APEX II APEX 20K
Altera Corporation Section VI–1
Section VI. System
Configuration & Upgrades
This section desc ribes configuration and remote system upgrade. This
section also provides configuration information for all of the supported
configuration schemes for Stratix® devices. These conf iguration sche mes
use either a microprocessor, configuration device, or download cable.
There is detailed information on how to design with Altera® enhanced
configuration devices which includes information on how to manage
multiple configuration files an d acc es s the on-chip FLASH memory
space. The last chapter shows you how to perform remote and local
upgrades for your designs.
This section contains the following chapters:
■Chapter 11, Configuring Stratix & Stratix GX Devices
■Chapter 12, Remote System Configuration with Stratix & Stratix GX
Devices
fFor information on Altera enhanced configuration devices, see the
Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet chapter
in the Configuration Handbook, Volume 2.
Section VI–2 Altera Corporation
System Configuration & Upgr ades Stratix Device Handbook, Volume 2
Revision History The table below shows the revision history for Chapters 11 through 12.
Chapter Date/Version Changes Made
11 July 2005, v3.2 ●Updated “PORSEL Pins” and “nIO_PULLUP Pins” sections.
●Updated “FPP Configuration Using an Enhanced Configuration
Device” section.
●Updated “PPA Configuration” section.
September 2004, v3.1 ●Corrected spelling error.
April 2004, v3.0 ●In the “PORSEL Pins” section and the “nIO_PULLUP Pins” section,
several pull-down resistors were changed to pull-up resistors.
●Updated notes in Figure 11–3.
●Two vertical VCC lines removed in Figures 11–12 to 11–14.
●Three paragraphs added regarding the CONF_DONE and
INIT_DONE pins on page 13-18.
●Value in Note 1 changed in Tables 11–8 and 11–9.
●Deleted reference to AS in Table 11–15 because Stratix does not
support AS mode.
●Text added before callout of Figure 11–7.
July 2003, v2.0 ●Updated Remote/local update PPA typical use description on page
11-1.
●Updated VCCSEL Pins section on page 11-3.
●Updated figures to use 10k resistors throughout for configuration
control signals.
●Updated text on page 11-23 to tell how to connect a microprocessor
to nSTATUS.
●Figure 11–19, Note 3.
●Updated Table 11–12.
●Added Note 6 to Figure 11–21 and the text below the figure describing
the nCE pin.
●Updated definitions for CLKUSR, and JTAG pins in Table 11–16.
12 September 2004, v3.1 ●Editorial corrections.
April 2004, v3.0 ●The input file in Figure 12–22 was changed to
remote_update_initial_pgm.pdf.
●Title in Figure 12–23 was changed from Local... to Remote Update
Partial Programming File Generation.
●Rearranged the “Quartus II Software Support” section.
July 2003, v2.0 ●Added altremote_update Megafunction section on pages 12-18 to 12-
21.
Altera Corporation 11–1
July 2005
11. Configuring Stratix &
Stratix GX Devices
Introduction You can confi gure Stratix® and Stratix GX devices using one of several
configuration sche mes. All configuration schemes use either a
microprocessor, configuration device, or a download cable. See
Table 11–1.
This chapter discu sses how to configure one or more Strat ix or Stratix GX
devices. It should be used together with the following documents:
■MasterBlaster Serial/USB Communications Cable Data Sheet
■USB Blaster USB Port Download Cable Development Tools Data Sheet
■ByteBlaster II Parallel Port Download Cable Data Sheet
■ByteBlasterMV Parallel Port Download Cable Data Sheets
■Configuration Devices for SRAM-Based LUT Devices Data Sheet
■Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet
Table 11–1. Stratix & Stratix GX Device Configuratio n Schemes
Configuration Scheme Typical Use
Fast passive parallel (FPP) Configuration with a parallel synchronous configuration de vice or microprocessor
interface where eight bits of configuration data are loaded on every clock cycle.
Passive serial (PS) Configuration with a serial synchronous microprocessor interface or the
MasterBlasterTM communications cable, USB Blaster, ByteBlasterTM II, or
ByteBlasterMV parallel port download cable.
Passive parallel
asynchronous (PPA) Configuration with a parallel asynchronous microprocessor interface. In this
scheme, the microprocessor treats the target device as memory.
Remote/local update FPP Configuration using a NiosTM (16-bit ISA) and Nios®II (32-bit ISA) or other
embedded processor. Allows you to update the Stratix or Stratix GX device
configuration remotely using the FPP scheme to load data.
Remote/local update PS Passive serial synchronous configuration using a Nios or other embedded
processor. Allows you to update the Stratix or Stratix GX device configuration
remotely using the PS scheme to load data.
Remote/local update PPA Passive parallel asynchronous configuration using a Nios or other embedded
processor. In this scheme, the Nios microprocessor treats the target device as
memory. Allows you to update the Stratix or Stratix GX device configuration
remotely using the PPA scheme to load data.
Joint Test Action Group
(JTAG) Configuration through the IEEE Std. 1149.1 JTAG pins. You can perform JTAG
configuration with either a download cable or an embedded de vice. Ability to use
SignalTap®II Embedded Logic Analyzer.
S52013-3.2
11–2 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Device Configuration Overview
■The Remote System Configuration with Stratix & Stratix GX Devices
chapter
fFor more information on setting device co nfiguration options or
generating configuration files, see the Software Setting chapter in
Volume 2 of the Configuration Handbook.
Device
Configuration
Overview
During device operation, the FPGA stor es configuration data in SRAM
cells. Becau se SRAM memory is volatile, you must load the SRAM cells
with the configuration data each time the device powers up. After
configuration, the device m us t initialize its registers and I/O pins. Af ter
initialization, the device enters user mode. Figure 11–1 shows the state of
the device during the configurati on, initialization, and user mode.
Figure 11–1. Stratix & Stratix GX Configuration Cycle
Notes to Figure 11–1:
(1) During initial power up and configuration, CONF_DONE is low. After configuration, CONF_DONE goes high. If the
device is reconfigured, CONF_DONE goes low after nCONFIG is driven low.
(2) User I/O pins are tri-stated during configuration. Stratix and Stratix GX devices also have a weak pull-up resistor
on I/O pins during configuration that are enabled by nIO_PULLUP. After initialization, the user I/O pins perform
the function assigned in the user’s design.
(3) If the INIT_DONE pin is used, it will be high because of an external 10 kΩresistor pull-up when nCONFIG is low
and during the beginning of configuration. Once the option bit to enable INIT_DONE is pr ogrammed into the device
(during the first frame of configuration data), the INIT_DONE pin will go low.
(4) DCLK should not be left floating. It should be driven high or low.
(5) DATA0 should not be left floating. It should be driven high or low.
You can load the configuration data for the Stratix or Stratix GX device
using a passive configuration scheme. When using any passive
configuration scheme, the Stratix or Stratix GX device is incorporated into
a system with an intelligent host, such as a microprocessor, that controls
the configuration process. The host supplies configura tion data from a
storage device (e.g., a hard disk, RAM, or other system memory). When
using passive configuration, you can change the target device’s
High-Z
nCONFIG
nSTATUS
CONF_DONE (1)
DCLK
DATA
User I/O Pins (2)
INIT_DONE (3)
MODE
High-Z D0 D1 D2 D3
D(N – 1)
DN
Configuration Initialization User
High-Z User I/O
Configuration
(4)
(5)
Altera Corporation 11–3
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
functionality while the system is in operation by reconfiguring the device.
You can al s o perfor m in-fiel d upgrades by distributing a new
programming file to system users.
The following sections describe the MSEL[2..0], VCCSEL, PORSEL, and
nIO_PULLUP pins used in Stratix and Stratix GX device co nfiguration.
MSEL[2..0] Pins
You can select a Stratix or Stratix GX device configuration scheme by
driving its MSEL2, MSEL1, and MSEL0 pins either high or low, as shown
in Table 11–2.
The MSEL[] pins can be tied to VCCIO of the I/O bank they reside in or
ground.
VCCSEL Pins
You can configure Stratix and Stratix GX devices using the 3.3-, 2.5-, 1.8-,
or 1.5-V LVTTL I/O standard on configuration and JTAG input pins.
VCCSEL is a dedicate d input on Stratix and Stratix GX devices that selects
between 3.3-V/2.5-V input buffers and 1.8-V/1.5-V input buffers for
dedicated configuration input pins. A logic low supports 3.3-V/2.5-V
signaling, and a logic high supports 1.8-V/1.5-V signaling. A logic high
can also support 3.3-V/2.5-V signaling. VCCSEL affects the configuration
Table 11–2. Stratix & Stratix GX Device Configuration Schemes
Description MSEL2 MSEL1 MSEL0
FPP configuration 000
PPA configuration 001
PS configuration 010
Remote/local update FPP (1) 100
Remote/local update PPA (1) 101
Remote/local update PS (1) 110
JTAG-based configuration (3) (2) (2) (2)
Notes to Table 11–2:
(1) These schemes require that you drive a secondary pin RUnLU to specify whether
to perform a remote update or local update.
(2) Do not leave MSEL pins floating. Connect them to VCCIO or GND. These pins
support the non-JTAG configuration scheme used in production. If only JTAG
configuration is used you should connect the MSEL pins to ground.
(3) JTAG- based configuration takes preceden ce over other configuration schemes,
which means the MSEL pins are ignored.
11–4 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Device Configuration Overview
related I/O banks (3, 4, 7, and 8) where the following pins reside: TDI,
TMS, TCK, TRST, MSEL0, MSEL1, MSEL2, nCONFIG, nCE, DCLK, PLL_ENA,
CONF_DONE, nSTATUS. The VCCSEL pin can be pulled to 1.5, 1.8, 2.5, or
3.3-V for a logic high level. There is an int ernal 2.5-kΩ pull-down resistor
on VCCSEL. There fore, if you are using a pull-up res is ter to pull up this
signal, you need to use a 1-kΩ resistor.
VCCSEL also sets the power-on-reset (POR) trip point for all the
configuration related I/O banks (3, 4, 7, an d 8), ensuring that these I/O
banks have powered up to the appropriate voltage levels before
configuration begins. Upon power-up, the FPGA does not release
nSTATUS until VCCINT and all of the VCCIOs of the configuration I/O
banks are above their POR trip points. If you set VCCSEL to gr ound (logic
low), this sets the POR trip point for all configuration I/O banks to a
voltage consistent with 3.3-V/2.5-V signaling. When VCCSEL = 0, the
POR trip point for these I/O banks may be as high as 1.8 V. If VCCIO of any
of the configuration banks is set to 1.8 or 1.5 V, the voltage supplied to this
I/O bank(s) may never reach the POR trip poi nt, which will not allow the
FPGA to begin configuration.
1If the VCCIO of I/O banks 3, 4, 7, or 8 is set to 1.5 or 1.8 V and the
configuration signals used require 3.3-V or 2.5-V signaling you
should set VCCSEL to VCC (logic high) in order to lower the POR
trip point to enable successful configuration.
Table 11–3 shows how you should set the VCCSEL depending on the
VCCIO setting of the configuration I/O banks and your configuration
input signaling voltages.
The VCCSEL signal does not contr ol any of the dual-purpose pins,
including the dual-purpose configuration pins, such as the DATA[7..0]
and PPA pins (nWS, nRS, CS, nCS, and RDYnBSY). During configuration,
these dual-purpose pins drive out voltage levels corresponding to the
VCCIO supply voltage that powers the I/O bank containing the pin. After
configuration, the dual-purpose pins inherit the I/O standards specified
in the design.
Table 11–3. VCCSEL Setting
VCCIO (banks 3,4,7,8) Configuration Input
Signaling Vo ltage VCCSEL
3.3-V/2.5-V 3.3-V/2.5-V GND
1.8-V/1.5-V 3.3-V/2.5-V/1.8-V/1.5-V VCC
3.3-V/2.5-V 1.8-V/1.5-V Not Supported
Altera Corporation 11–5
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
PORSEL Pins
PORSEL is a dedicated input pin used to select POR delay times of 2 ms
or 100 ms during power-up. When the PORSEL pin is connected to
ground, the POR time is 100 ms; when the PORSEL pin is connected to
VCC, the POR time is 2 ms. There is an internal 2.5-kΩ pull-down resistor
on PORSEL. Therefore if you are using a pull-up resistor to pull up this
signal, you need to use a 1-kΩ resistor.
When using enhanced configuration devices to configur e Stratix devices,
make sure that the PORSEL setting of the Stratix device is the same or
faster than the PORSEL setting of the enhanced configuration device. If
the FPGA is not powered up after the enhanced configuration device exits
POR, the CONF_DONE signal will be high since the pull-up resistor is
pulling this signal high. When the enhanced configuration device exits
POR, OE of the enhanced configuration device is rele ased and pulled
high by a pull-up resistor. Since the enhanced configuration device sees
its nCS/CONF_DONE signal also high, it enters a test mode. Therefore, you
must ensure the FPGA powers up before the enhanced configuration
device exits POR.
For more margin, the 100-ms setting can be selected when using an
enhanced configuration device to allow the Stratix FPGA to power -up
before configuration is attempted (see Table 11–4).
nIO_PULLUP Pins
The nIO_PULLUP pin enables a built-in weak pull-up resistor to pull all
user I/O pins to VCCIO before and during device configuration. If
nIO_PULLUP is connected to VCC during configuration, the weak pull-
ups on all user I/O pins and all dual-purpose pins are dis a bled. If
connected to gr ound, the pull-ups ar e enabled during confi guration. The
nIO_PULLUP pin can be pulled to 1.5, 1.8, 2.5, or 3.3-V for a logic level
high. There is an internal 2.5-kΩ pull-down resistor on nIO_PULLUP.
Therefore, if you are using a pull-up resistor to pull u p this sig n al, you
need to use a 1-kΩ re sistor.
Table 11–4. PORSEL Settings
PORSEL Settings POR Time (ms)
GND 100
VCC 2
11–6 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration File Size
TDO & nCEO Pins
TDO and nCEO pins drive out the same voltage levels as the VCCIO that
powers the I/O bank where the pin resides. You mus t sel e ct the VCCIO
supply for the bank containing TDO accordingly. For example, when
using the ByteBlasterMV cable, the VCCIO for the bank containing TDO
must be powered up at 3.3-V. The current strength for TDO is 12 mA.
Configuration
File Size Tables 11–5 and 11–6 summarize the approximate configuration file size
required for each Stratix and Stratix GX device. To calculate the amount
of storage space required for multi-device configurations, add the file size
of each device together.
You should only use the numbers in Tables 11–5 and 11–6 to estimate the
file size before design compilation. The exact file size may vary because
different Altera® Quartus® II software versions may add a slightly
Table 11–5. Stratix Confi guration File Sizes
Device Raw Binary File (.rbf) Size (Bits)
EP1S10 3,534,640
EP1S20 5,904,832
EP1S25 7,894,144
EP1S30 10,379,368
EP1S40 12,389,632
EP1S60 17,543,968
EP1S80 23,834,032
Table 11–6. Stratix GX Configuration File Sizes
Device Raw Binary File Size (Bits)
EP1SGX10C 3,579,928
EP1SGX10D 3,579,928
EP1SGX25C 7,951,248
EP1SGX25D 7,951,248
EP1SGX25F 7,951,248
EP1SGX40D 12,531,440
EP1SGX40G 12,531,440
Altera Corporation 11–7
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
differ ent number of padding bits during pr ogramming. However , for any
specific version of the Quartus II software, any design targeted for the
same device has the same configuration file size.
Altera
Configuration
Devices
The Altera enhanced configuration devices (EPC16, EPC8, and EPC4
devices) support a single-device configuration solution for high-density
FPGAs and can be used in the FPP and PS configuration sche mes. They
are ISP-capable through its JTAG interface. The enhanced configuration
devices are divided into two major bloc ks , the controller and the flash
memory.
fFor information on enhanced configuration devices, see the Enhanced
Configuration Devi ces (EPC4, EPC8 & EPC16) Data Sheet and the Using
Altera Enhanced Configuration Devices chapter in the Configuration
Handbook.
The EPC2 and EPC1 configuration devices provide configuration support
for the PS configuration scheme. The EPC2 device is ISP-capable through
its JTAG interface. The EPC2 and EP C1 can be cascaded to hold large
configuration files.
fFor more informati on on EPC2, EPC1, and EPC14 41 configu r ation
devices, see the Configuration Devices for SRAM-Based LUT Devices Data
Sheet.
Configuration
Schemes This section desc ribes how to configure Stratix and Stratix GX devices
with the following configuration schemes:
■PS Configuration with Configuration Devi ce s
■PS Configuration with a Download Cable
■PS Configuration with a Microprocessor
■FPP Configuration
■PPA Configuration
■JTAG Programming & Configuration
■JTAG Programming & Configuration of Multiple Devices
PS Configuration
PS configuration of Stratix and Stratix GX devices can be performed using
an intelligent host, such as a MAX® device, microprocessor with flash
memory, an Altera configuration device, or a download cable. In the PS
scheme, an external host (MAX device, embedded processor,
configuration device, or ho st PC) controls configuration. Configuration
data is clocked into the target St ratix devices via the DATA0 pin at each
rising edge of DCLK.
11–8 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
PS Configuration with Configuration Devices
The configuration devic e sche me uses an Altera configuration device to
supply data to t h e Stratix or Stra tix GX device in a se ria l bitstream (see
Figure 11–3).
In the configuration device scheme, nCONFIG is usually tied to VCC
(when using EPC16, EPC8, EPC4, or EPC2 devic es, nCONFIG may be
connected to nINIT_CONF). Upon dev ice power -up, the tar get Stratix or
Stratix GX device senses the low-to-high transition on nCONFIG and
initiates configuration. The target device then drives the open-drain
CONF_DONE pin low, which in-turn drives the configuration device’s nCS
pin low. When exiting power-on reset (POR), both the target and
configuration device release the open-drain nSTATUS pin.
Before configuration begins, the configuration device goes through a POR
delay of up to 200 ms to allow the power supply to stabilize (power the
Stratix or Stratix GX device before or during the POR time of the
configuration device). This POR delay has a maximum of 200 ms for
EPC2 devices. For enhanced configuration devices, you can select
between 2 ms and 100 ms by connecting PORSEL pin to VCC or GND,
accordingly. During this time, the configuration device drives its OE pin
low. This low signal delays configuration beca use the OE pin is connected
to the target device’s nSTATUS pin. When the target and configuration
devices comple te POR, they r ele ase nSTATUS, which is then pulled high
by a pull-up resistor.
When configuring multiple devices, configuration does not begin until all
devices release their OE or nSTATUS pins. When all devices are r eady, the
configuration device clocks data out serially to the target devices using an
internal oscilla tor.
After successful configuration, the Stratix FPGA starts initialization using
the 10-MHz internal oscillator as the reference clock. After initialization,
this internal oscillator is turned off. The CONF_DONE pin is r eleased by the
target device and then pulled high by a pull -up resistor. When
initialization is complete, the FPGA enters user mode. The CONF_DONE
pin must have an external 10-kΩ pull-up resistor in order for the device
to initialize.
If an error occu rs du ring configu ra tion, the target devic e dr ives its
nSTATUS pin low, resetting itself internally and resetting the
configuration device . I f the Auto-Restart Configuration on Frame Error
option—available in the Quartus II Global Device Options dialog box
(Assign menu)—is turned on, the device reconfigur es automatically if an
error occurs. To find this option, choose Compiler Settings (Processing
menu), then click on the Chips & Devices tab.
Altera Corporation 11–9
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
If this option is turned off, the external system must monitor nSTATUS for
errors and then pulse nCONFIG lo w to restart configuration. The external
system can pulse nCONFIG if it is under system control rather than tied to
VCC. When configuration is complete, the target device releases
CONF_DONE, which disables the configuration device by driv ing nCS
high. The configuration device drives DCLK low before and after
configuration.
In addition, if the configuration device sends all of its data and then
detects that CONF_DONE has not gone high, it recognizes that the target
device has not configured successfull y. In this case, the configuration
device pulses its OE pin low for a few microseconds, driving the target
device’s nSTATUS pin low. If the Auto-Restart Configuration on Frame
Error option is set in the software, the target device r esets and then pulses
its nSTATUS pin low. When nSTATUS returns high, the configuration
device re confi gures the target device. When configuration is complete,
the configuration devic e dri v es DCLK low.
Do not pull CONF_DONE low to delay initialization. Instead, use the
Quartus II software’s Enable User-S uppli ed Start-U p Cl ock (CLK US R)
option to synchronize the initialization of multiple de vices that are not in
the same config ur ation chain. Devices in the same configuration chain
initialize together. When CONF_DONE is driven low after device
configuration, the configuration device re cognizes that the target device
has not configured successfully.
Figure 11–2 shows how to configure one Stratix or Stratix GX device with
one configuration device.
11–10 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
Figure 11–2. Single Device Configuration Circuit
Notes to Figure 11–2:
(1) The pull-up resistor should be connected to the same supply voltage as the
configuration devi ce.
(2) The enhanced configuration devices and EPC2 devices have internal
programmable pull-ups on OE and nCS. You should only use the internal pull-ups
of the configuration device if the nSTATUS and CONF_DONE signals are pulled up
to 3.3 V or 2.5 V (not 1.8 V or 1.5 V). If external pull-ups are used, they should be
10 kΩ.
(3) The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices. If
nINIT_CONF is not used, nCONFIG must be pulled to VCC through a resistor. he
nINIT_CONF pin has an internal pull-up resistor that is always active in EPC16,
EPC8, EPC4, and EPC2 devices. These devices do not need an external pull-up
resistor on the nINIT_CONF pin.
Figure 11–3 shows how to configure multiple Stratix and Stratix GX
devices with multiple EPC2 or EPC1 configuration devices.
Stratix or Stratix GX Device
DCLK
DATA
OE
nCS
nINIT_CONF (3)
MSEL1
MSEL0
MSEL2
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
VCC VCC
GND GND
(1) (1)
nCE
VCC (1)
nCEO N.C.
Configuration
Device
VCC
10 kΩ
(2) 10 kΩ
(2)
(2)
(2)
10 kΩ
(3)
Altera Corporation 11–11
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Figure 11–3. Multi-Device Configuration Circuit Note (1)
Notes to Figure 11–3:
(1) When performing multi-device active serial configuration, you must generate the configuration device programmer
object file (.pof) fr om each project’s SOF . You can combine multiple SOFs using the Quartus II software through the
Device & Pin Option dialog box. For more information on how to create configuration and programming files, see
the Softwa re Settings section in the Configuration Handbook, Volume 2.
(2) The pull-up resistor should be connected to the same supply voltage as the configuration device.
(3) The enhanced configuration devices and EPC2 devices have internal programmable pull-ups on OE and nCS. You
should only use the internal pull-ups of the configuration device if the nSTATUS and CONF_DONE signals are pulled
up to 3.3 V or 2.5 V (not 1.8 V or 1.5 V). If external pull-ups are used, they should be 10 kΩ
(4) The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC through a resistor. The nINIT_CONF pin has an internal pull-up r esistor that is always active
in EPC16, EPC8, EPC4, and EPC2 devices. These devices do not need an external pull-up resistor on the
nINIT_CONF pin.
After the first Stratix or Stratix GX device completes configuration during
multi-device configuration, its nCEO pin activa tes the second device’s
nCE pin, prompting the second device to begin configuration. Because all
device CONF_DONE pins are tied together, all dev ic e s initialize and en te r
user mode at the same time.
In addition, all nSTATUS pins are tied together; thus, if any device
(including the configuration devices) detects an error , configuration stops
for the entir e chain. Also, if the firs t configur ation dev ice d oes not detect
CONF_DONE going high at the end of configuratio n, it resets the chain by
pulsing its OE pin low for a few microseconds. This low pulse drives the
OE pin low on the second configuration device and drives nSTATUS low
on all Stratix and Stratix GX devices, causing them to enter an error state.
If the Auto-Restart Configuration on Frame Error option is turned on in
the softwar e, the Stratix or Stratix GX device releases its nSTATUS pins
after a reset time-out period. When the nSTATUS pins are released and
pulled high, the configuration d evi ces reconfigure the chain. If the Auto-
EPC1/EPC2
DCLK
DATA
OE
nCS
nINIT_CONF (4)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
VCC VCC
GND
nCE
VCC
DCLK
DATA
nCS
OE
EPC1/EPC2
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
GND
nCE
MSEL2
MSEL1
nCEO
nCASC
(2)(2)
(2)
nCEO
N.C.
Stratix or Stratix GX Device 2 Stratix or Stratix GX Device 1
MSEL0
VCC
GND
MSEL2
MSEL1
MSEL0
VCC
10 kΩ10 kΩ
(3)(4) (3)
(3)
(3)
10 kΩ
nINIT_CONF (4)
11–12 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
Restart Configuration on Frame Error option is not turned on, the Stratix
or Stratix GX devices drive nSTATUS low until they are reset with a low
pulse on nCONFIG.
You can also cascade several EPC2/EPC1 configuration devices to
configure multiple Stratix and Strati x GX devices. When all data fr om the
first configuration device is sent, it dri v es nCASC low, which in turn
drives nCS on the subsequent configur ation device. Beca us e a
configuration device requires less than one clock cycle to activate a
subsequent configuration device, the data stream is uninterrupted.
1You cannot cascade enhanced (EPC16, EPC8, and EPC4)
configuration devices.
You can use a single configuration chain to configur e multiple Stratix and
Stratix GX dev ic es. In this scheme, the nCEO pin of the first device is
connected to the nCE pin of the second device in the chain. If there ar e
additional devices, connect the nCE pin of the next device to the nCEO pin
of the previous device. To configure properly, all of the device
CONF_DONE and nSTATUS pins must be tied together.
Figure 11–4 shows an example of configuring multiple Stratix and Stratix
GX devices using a configuration device.
Altera Corporation 11–13
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Figure 11–4. Configuring Multiple Stratix & Stratix GX Devices with A Single Configuration Device Note (1)
Notes to Figure 11–4:
(1) When performing multi-device active serial configuration, you must generate the configuration device programmer
object file (.pof) fr om each project’s SOF. Y ou can combine multiple SOFs using the Quartus II software thr ough the
Device & Pin Option dialog box. For more information on how to create configuration and programming files, see
the Softwa re Settings section in the Configuration Handbook, Volume 2.
(2) The pull-up resistor should be connected to the same supply voltage as the configuration device.
(3) The enhanced configuration devices and EPC2 devices have internal programmable pull-ups on OE and nCS. You
should only use the internal pull-ups of the configuration device if the nSTATUS and CONF_DONE signals are pulled
up to 3.3 V or 2.5 V (not 1.8 V or 1.5 V). If external pull-ups are used, they should be 10 kΩ.
(4) EPC16, EPC8, and EPC4 configuration devices cannot be cascaded.
(5) The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC through a resistor. The nINIT_CONF pin has an internal pull-up r esistor that is always active
in EPC16, EPC8, EPC4, and EPC2 devices. These devices do not need an external pull-up resistor on the
nINIT_CONF pin.
Configuration
Device (4)
DCLK
DATA
OE
nCS
nINIT_CONF (5)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
VCC VCC
GND
nCE
VCC
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
GND
nCE
MSEL2
MSEL1
nCEO
nCASC
(2)(2)
(2)
nCEO
N.C.
Stratix or Stratix GX Device 2 Stratix or Stratix GX Device 1
MSEL0
VCC
GND
MSEL2
MSEL1
MSEL0
VCC
(3)
10 kΩ10 kΩ
11–14 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
Table 11–7 shows the status of the device DATA pins during and after
configuration.
PS Configuration with a Download Cable
In PS configuration with a download cable, an intelligent host transfers
data from a storage device to the Stratix or Stratix GX device t hrough the
MasterBlaster, USB-Blaster, ByteBlaster II or ByteBlasterMV cable. To
initiate configuration in this scheme, the download cable generates a
low-to-high transition on the nCONFIG pin. The programming hardwar e
then places the configuration data one bit at a time on the device’s DATA0
pin. The data is clocked into the target device until CONF_DONE goes high.
The CONF_DONE pin must have an external 10-kΩ pull-up resistor in
order for the device to initialize.
When using programming har dwar e for the Stratix or Stratix GX device,
turning on the Auto-Restart Configuration on Frame Error option does
not affect the configuration cycle because the Quartus II softwar e must
restart configuration when an error occurs. Additionally, the Enable
User-Supplied St art-Up Clock (CLKUSR) option has no affect on the
device initialization since this option is disabled in the SOF when
programming the FPGA using the Quartus II software programmer and
a download cable. Ther efor e, if you turn on the CLKUSR option, you do
not need to provide a clock on CLKUSR when you are configuring the
FPGA with the Quartus II programmer and a download cable.
Figure 11–5 shows PS configuration for the Stratix or Stratix GX device
using a MasterBlaster, USB-Blaster, ByteBLaster II or ByteBlasterMV
cable.
Table 11–7. DATA Pin Status Before & After Configuration
Pins Stratix or Stratix GX Device
During After
DATA0 (1) Used for configuration User defined
DATA[7..1] (2) Used in some configuration modes User defined
I/O Pins Tri-state User defined
Notes to Table 11–7:
(1) The status shown is for configuration with a configuration device.
(2) The function of these pins depends upon the setting s sp e cif ied in the Quartus II
software using the Device & Pin Option dialog box (see the Software Settings
section in the Configuration Handbook, V olume 2, and the Quartus II Help software
for more information).
Altera Corporation 11–15
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Figure 11–5. PS Configu ration Circuit with a Download Cable
Notes to Figure 11–5:
(1) Y ou should connect the pull-up r esistor to the same supply voltage as the MasterBlaster (VIO pin) or ByteBlasterMV
cable.
(2) The pull-up resistors on the DATA0 and DCLK pins are only ne ede d if the downloa d cable is the only config uration
scheme used on the board. This is to ensure that the DATA0 and DCLK pins are not left floating after configuration.
For example, if the design also uses a configuration device, the pull-up resistors on the DATA0 and DCLK pins are
not necess a ry.
(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. This pin is a no-connect pin for the ByteBlasterMV header.
You can use programming hardware to configure multiple Stratix and
Stratix GX devices by connecting each device’s nCEO pin to the
subsequent device’s nCE pin. All other configuration pins are connected
to each device in the chain.
Because all CONF_DONE pins are tied togethe r, all devices in the chain
initialize and enter user mode at the same time. In addition, because the
nSTATUS pins are tie d together , the entir e chain halts configuration if any
device detects an error. In this situation, the Quartus II software must
restart configuration; the Auto-Restart Configuration on Frame Error
option does not affect the configuration cycle.
Figure 11–6 shows how to configure multiple Stratix and Stratix GX
devices with a MasterBlaster or ByteBlasterMV cable.
Download Cable
10-Pin Male Header
(PS Mode)
VCC
(1)
VCC
(1)
VCC
VCC
(1)
VCC
(1)
VCC
(1)
Stratix or
Stratix GX Device
MSEL2
DCLK
nCONFIG
CONF_DONE
Shield
GND
MSEL1
MSEL0
10 kΩ10 kΩ10 kΩ
10 kΩ
10 kΩ
nSTATUS
DATA0
Pin 1
nCE
GND
GND
VIO
(3)
VCC
(2)(2)
(2)
nCEO N.C.
11–16 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
Figure 11–6. Multi-Device PS Configuration with a Download Cable
Notes to Figure 11–6:
(1) Y ou should connect the pull-up r esistor to the same supply voltage as the MasterBlaster (VIO pin) or ByteBlasterMV
cable.
(2) The pull-up resistors on the DATA0 and DCLK pins are only ne ede d if the downloa d cable is the only config uration
scheme used on the board. This is to ensure that the DATA0 and DCLK pins are not left floating after configuration.
For example, if the design also uses a configuration device, the pull-up resistors on the DATA0 and DCLK pins are
not necess a ry.
(3) VIO is a reference voltage for the MasterBlaster output driver. VIO should match the device’s VCCIO. See the
MasterBlas ter Serial/USB Communications Cable Data Sheet for this value.
If you are using a download cable to configure device(s) on a board that
also has configuration devices, you should electrically isolate the
configuration devices from the target device(s) and cable. One way to
isolate the configuration devices is to add logic, such as a multiplexer , that
can select between the configuration device s and the cabl e. The
multiplexer device should allow bidirectional transfers on the nSTATUS
and CONF_DONE signals. Another option is to add switches to the five
common signals (CONF_DONE, nSTATUS, DCLK, nCONFIG, and DATA0)
between the cable and the configuration devices. The last option is to
remove the configuration devices from the boar d when configuring with
the cable. Figure 11–7 shows a combination of a configuration de vice and
a download cable to configure a Stratix or Stratix GX device.
Stratix or
Stratix GX Device 1
Stratix or
Stratix GX Device 2
MSEL0
nCE
nCONFIG
CONF_DONE
DCLK
nCE nCEO
nCONFIG
CONF_DONE
DCLK
nCEO
GND
(PS Mode)
VCC
VCC
(1)
GND
VCC
(1)
VCC
(1)
VCC
(1)
VCC
(1)
nSTATUS
nSTATUS
DATA0
DATA0
MSEL1
MSEL0
MSEL1
10 kΩ
10 kΩ
10 kΩ
1
0 kΩ
10 kΩ
Pin 1
Download Cable
10-Pin Male Header
N.C.
VIO
(3
)
GND
VCC
MSEL2
MSEL2
GND
VCC
(2)
(2)
Altera Corporation 11–17
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Figure 11–7. Configuring with a Combined PS & Configuration Device Scheme
Notes to Figure 11–7:
(1) You should connect the pull-up resistor to the same supply voltage as the configuration device.
(2) The pull-up resistors on the DATA0 and DCLK pins are only ne ede d if the downloa d cable is the only config uration
scheme used on the board. This is to ensure that the DATA0 and DCLK pins are not left floating after configuration.
For example, if the design also uses a configuration device, the pull-up resistors on the DATA0 and DCLK pins are
not necess a ry.
(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the target
device’s VCCIO. This is a no-connect pin for the ByteBlasterMV header.
(4) You should not attempt configuration with a download cable while a configuration device is connected to a Stratix
or Stratix GX device. Instead, you should either remove the configuration device from its socket when using the
download cable or place a switch on the five common signals between the download cable and the configuration
device. Remove the download cable when configuring with a configuration device.
(5) If nINIT_CONF is not used, nCONFIG must be pulled to VCC either directly or through a resistor.
(6) If external pu ll-ups ar e used on CONF_DONE and nSTATUS pins, they should always be 10 kΩresistors. You can use
the internal pull-ups of the configuration device only if the CONF_DONE and nSTATUS signals are pulled-up to 3.3 V
or 2.5 V (not 1.8 V or 1.5 V).
fFor more information on how to use the MasterBlaster or ByteBlasterMV
cables, see the following documents:
■USB-Blaster USB Port Download Cable Data Sheet
■MasterBlaster Serial/USB Communications Cable Data Sheet
■ByteBlasterMV Parallel Port Download Cable Data Sheet
■ByteBlaster II Parallel Port Download Cable Data Sheet
Stratix or Stratix GX Device
MSEL0
nCE
nCONFIG
CONF_DONE
DCLK
nCEO
GND
Download Cable
10-Pin Male Header
(PS Mode)
VCC
VCC
VCC VCC
(1)
VCC
(1)
VCC
(1)
nSTATUS
DATA0
MSEL1
10 kΩ
10 kΩ
1
0 kΩ
10 kΩ
Pin 1
DCLK
DATA
OE
nCS
nINIT_CONF
(5)
Configuration
Device
(4)
(4) (4) (4)
(4)
GND
VIO
(3)
N.C.
(1)
(1)
GND
MSEL2
VCC
(6)
10 kΩ
(6) (2)
(2)
(6)
(6)
11–18 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
PS Configuration with a Microprocessor
In PS configuration with a microprocessor, a microprocessor transfers
data from a storage device to the target Stratix or Stratix GX device. To
initiate configuration in this scheme, the microprocessor must generate a
low-to-high transition on the nCONFIG pin and the target device must
release nSTATUS. The micropr ocessor or program mi ng hardware then
places the configuration data one bit at a time on the DATA0 pin of the
Stratix or Stratix GX device. The lea st significant bit (LSB) of each data
byte must be presented first. Data is clocked continuously into the tar get
device until CONF_DONE goes high.
After all configuration data is sent to the Stratix or Stratix GX device, the
CONF_DONE pin goes hi gh to show successful configuration and the start
of initialization. The CONF_DONE pin must have an external 10-kΩ pull-
up resistor in order for the device to initialize. Initialization, by default,
uses an internal oscillator, which runs at 10 MHz. After initiali zation, this
internal oscillator is turned off. If you are using the clkusr option, afte r all
data is transferred clkusr must be clocked an additional 136 times for
the Stratix or Stratix GX device to initialize pr operly. Driving DCLK to the
device after configuration is complete does not affect device operation.
Handshaking signals are no t used in PS configuration modes. Ther efo re,
the configuration clock speed must be below the specified freque ncy to
ensure correct configuration. No maximum DCLK period exists. You can
pause configuration by halting DCLK for an indefinite amount of time.
If the target device detects an error during configuration, it drives its
nSTATUS pin low to alert the microprocessor. The microprocessor can
then pulse nCONFIG low to restart the configuration process.
Alternatively, if the Auto-Restart Configuration on Frame Error option
is turned on in the Quartus II software, the target device releases
nSTATUS after a reset time-out period. Af ter nSTATUS is released, the
microprocessor can reconfigur e the target device without needing to
pulse nCONFIG low.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. If the microprocessor sends all
data and the initialization clock starts but CONF_DONE and INIT_DONE
have not gone high, it must reconfigure the target device. By default the
INIT_DONE output is disabled. You can enable the INIT_DONE output by
turning on Enable INIT_DONE output option in the Quartus II software.
If you do not turn on the Enable INIT_DONE output option in the
Quartus II software, you are advised to wait for the maximum value of
tCD2UM (see Table 11–8) after the CONF_DONE signal goes high to ensure
the device has been initialized properly and that it has entered user mode.
Altera Corporation 11–19
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
During configuration and initia lization, and before the device enters user
mode, the microprocessor must not drive the CONF_DONE signal low.
1If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configur ation during device initialization, you need to
ensure CLKUSR continues toggl ing during the time nSTATUS is
low (maximum of 40 µs).
Figure 11–8 shows the cir cuit for PS configuration with a micropr oces sor.
Figure 11–8. PS Configuration Circuit with Microprocessor
PS Configuration Timing
Figure 11–9 shows the PS configuration timing waveform for Stratix and
Stratix GX devices . Table 11–8 shows the PS timing parameters for Stratix
and Stratix GX devices.
Microprocessor
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
Stratix Device
Memory
ADDR DATA0
GND
MSEL1
MSEL2
VCC
VCC
10 kΩ10 kΩ
GND
DCLK
nCEO N.C.
MSEL0
VCC
11–20 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
Table 11–8. PS Ti ming Parameters for Stratix & Stratix GX Devices
Symbol Parameter Min Max Units
tCF2CD nCONFIG low to CONF_DONE low 800 ns
tCF2ST0 nCONFIG low to nSTATUS low 800 ns
tCF2ST1 nCONFIG high to nSTATUS high 40 (2) µs
tCFG nCONFIG low pulse width 40 µs
tSTATUS nSTATUS low pulse width 10 40 (2) µs
tCF2CK nCONFIG high to first rising edge on DCLK 40 µs
tST2CK nSTATUS high to first rising edge on DCLK 1µs
tDSU Data setup time before rising edge on DCLK 7ns
tDH Data hold time after rising edge on DCLK 0ns
tCH DCLK high time 4ns
tCL DCLK low time 4ns
tCLK DCLK period 10 ns
fMAX DCLK maximum frequency 100 MHz
tCD2UM CONF_DONE high to user mode (1) 620µs
Notes to Table 11–8:
(1) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 136 to obtain this value.
(2) This value is obtainable if users do not delay configuration by extending the nSTATUS low pulse width.
Altera Corporation 11–21
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Figure 11–9. PS Ti ming Waveform for Stratix & Stratix GX Devices Note (1)
Notes to Figure 11–9:
(1) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
(2) Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay.
(3) Upon power-up, before and during configuration, CONF_DONE is low.
(4) DCLK should not be left floating after configuration. It should be driven high or low, whichever is convenient.
DATA[] is available as user I/Os after configuration and the state of these pins depends on the dual-purpose pin
settings.
FPP Configuration
Parallel configuration of Stratix and Stratix GX devices meets the
continuously increasing demand for faster config urati o n tim es. Stratix
and Stratix GX devices can receive byte-wide configuration data per clock
cycle, and guarantee a configuration time of less than 100 ms with a 100-
MHz configuration clock. Stratix and Stratix GX devices support
programming data bandwidth up to 800 megabits per second (Mbps) in
this mode. You can use parallel configuration with an EPC16, EPC8, or
EPC4 device, or a microprocessor.
This section discusses the following schemes for FPP configur ation in
Stratix and Stratix GX devices:
■FPP Configuration Using an Enhanced Configuration Device
■FPP Configuration Using a Microprocessor
nCONFIG
nSTATUS (2)
CONF_DONE (3)
DCLK
DATA
User I/O
INIT_DONE
Bit 0 Bit 1 Bit 2 Bit 3 Bit n
tCD2UM
tCF2ST1
tCF2CD
tCFG
tCH tCL
tDH
tDSU
tCF2CK
tSTATUS
tCLK
tCF2ST0
tST2CK
High-Z User Mode
(4)
(4)
11–22 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
FPP Configuration Using an Enhanced Configuration Device
When using FPP with an enhanced c onfiguration device, it supplies data
in a byte-wide fashion to the Stratix or Stratix GX device every DCLK
cycle. See Figure 11–10.
Figure 11–10. FPP Configuration Using Enhanced Configuration Devices
Notes to Figure 11–10:
(1) The pull-up resistors should be connected to the same supply voltage as the
configuration devi ce.
(2) The enhanced configuration devices and EPC2 devices have internal
programmable pull-ups on OE and nCS. You should only use the internal pull-ups
of the configuration device if the nSTATUS and CONF_DONE signals are pulled up
to 3.3 V or 2.5 V (not 1.8 V or 1.5 V). If external pull-ups are used, they should be
10 kΩ.
(3) The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices. If
nINIT_CONF is not used, nCONFIG must be pulled to VCC through a resistor. The
nINIT_CONF pin has an internal pull-up resistor that is always active in EPC16,
EPC8, EPC4, and EPC2 devices. These devices do not need an external pull-up
resistor on the nINIT_CONF pin.
In the enhanced configuration device scheme, nCONFIG is tied to
nINIT_CONF. On power up, the target St ratix or Stratix GX device senses
the low-to-high transition on nCONFIG and initiates configuration. The
target Stratix or Stratix GX device then drives the open-drain CONF_DONE
pin low, which in-turn drives the enhanced configuration device’s nCS
pin low.
Before configuration starts, there is a 2-ms POR delay if the PORSEL pin
is connected to VCC in the enhanced configuration device. If the PORSEL
pin is connected to ground, the POR delay is 100 ms. When each device
determines that its power is stable , it releases its nSTATUS or OE pin.
Because the enhanced configuration device’s OE pin is con n e cte d to the
target Stratix or Stratix GX device’s nSTATUS pin, configuration is
delayed until both the nSTATUS and OE pins ar e released by each device.
The nSTATUS and OE pins are pulled up by a resistor on their respective
Stratix or
Stratix GX Device
Enhanced
Configuration
Device
DCLK
DATA[7..0]
OE
(2)
nCS
(2)
nINIT_CONF
(3)
MSEL2
MSEL1
DCLK
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
VCC VCC
GND GND
(1) (1)
nCE
nCEO N.C.
MSEL0
10 kΩ
(2)
10 kΩ
(2)
Altera Corporation 11–23
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
devices once they are released. When configur ing multiple devic es,
connect the nSTATUS pins together to ensure configuration only happens
when all devices release their OE or nSTATUS pins. The enhanced
configuration device then clocks data out in parallel to the Stratix or
Stratix GX device using a 66-MHz internal oscillator, or drives it to the
Stratix or Stratix GX device through the EXTCLK pin.
If there is an error during configuration, the Stratix or Stratix GX device
drives the nSTATUS pin low, resetting itself internally and resetting the
enhanced configuration device. The Quartus II software provides an
Auto-restart configuration after error option that automatically initiates
the reconfiguration whenever an error occurs. See the Software Settings
chapter in Volume 2 of the Configuration Handbook for information on how
to turn this option on or off.
If this option is turned off, you must set monitor nSTATUS to check for
errors. To initiate reconfiguration, pulse nCONFIG lo w. The external
system can pulse nCONFIG if it is under system control rather than tied to
VCC. Therefore, nCONFIG must be connected to nINIT_CONF if you want
to reprogram the Stratix or Stratix GX device on the fly.
When configuration is complete, the S tratix or Strati x GX dev ice r elea ses
the CONF_DONE pin, which is then pull ed up by a resistor. This action
disables the EPC16, EPC8, or EPC4 enhanced configuration device as nCS
is driven high. Initialization, by default, uses an internal oscillator , which
runs at 10 MHz. After initialization, this internal osc ill ator is turned off.
When initialization is co mple te , the S tratix or Stratix GX device enters
user mode. The enhanced configuration device drives DCLK low before
and after configuration.
1CONF_DONE goes high one byte early in parallel synchronous
(FPP) and asynchronous (PPA) modes using a micr oprocessor
with .rbf, .hex, and .ttf file formats. This does not apply to FPP
mode for enhanced configuration devices using .pof file format.
This also does not apply to serial modes.
If, after sending out all of its data, the enhanced configuration device does
not detect CONF_DONE going high, it recognizes that the Stratix or
Stratix GX device has not configured successfully. The enhanced
configuration device pulses its OE pin low for a few microseconds,
driving the nSTATUS pin on the Stratix or Stratix GX device low. If the
Auto-restart configuration after error option is on, the Stratix or Stratix
GX device resets and then pulses its nSTATUS low. When nSTATUS
returns high, reconfiguration is restarted (se e Figure 11–11 on
page 11–25).
11–24 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
Do not drive CONF_DONE low after device configuration to delay
initializatio n. Instead, use the Enable User-Supplied Start-Up Clock
(CLKUSR) option in the Device & Pin Options dialog box. You can use
this option to synchronize the init ialization of multiple devices that are
not in the same configuration chain. Devices in the same configuration
chain initialize together.
After the first Stratix or Stratix GX device completes configuration during
multi-device configuration, its nCEO pin activa tes the second Stratix or
Stratix GX device’s nCE pin, prompting the second device to begin
configuration. Because CONF_DONE pins are tied together, all devices
initialize and enter user mode at the same time. Because nSTATUS pins
are tied together, configuration stops for the whole chain if any device
(including enhanced configuration devices) detects an error. Also, if the
enhanced configuration device does not detect a high on CONF_DONE at
the end of configuration, it pulses its OE low for a few microseconds to
reset the chain. Th e lo w OE pulse drives nSTATUS low on all Stratix and
Stratix GX devic es, cau sing them to enter an error state. This state is
similar to a Stratix or Stratix GX device detecting an error.
If the Auto-restart configuration after error option is on, the Stratix and
Stratix GX devices release their nSTATUS pins after a reset time-out
period. When the nSTATUS pins are released and pulled high, the
configuration device reconfigures the chain. If the Auto-restart
configuration after error option is of f, nSTATUS st ays low until the
Stratix and Stratix GX devices are reset with a low pulse on nCONFIG.
Figure 11–11 shows the FPP configuration with a configuration device
timing waveform for Stratix and Stratix GX devices.
Altera Corporation 11–25
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Figure 11–11. FPP Configuration with a Configuration Device Timing Waveform Note (1)
Notes to Figure 11–11:
(1) For timing information, see the Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet.
(2) The configuration device drives DATA high after configuration.
(3) Stratix and Stratix GX devices enter user mode 136 clock cyc les afte r CONF_DONE goes high.
FPP Configuration Using a Microprocessor
When using a microprocessor for parallel configuration, the
microprocessor transfers data from a storage device to the Stratix or
Stratix GX device through configuration hardware. To initiate
configuration, the microprocessor needs to generate a low-to-high
transition on the nCONFIG pin and the Stratix or Stratix GX device must
release nSTATUS. The microprocess or then places the configuration data
to the DATA[7..0] pins of the Stratix or Stratix GX device. Data is
clocked continuously into the Stratix or Stratix GX device until
CONF_DONE goes high.
The configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists. You can pause configuration by halting DCLK for an indefinite
amount of time.
After all configuration data is sent to the Stratix or Stratix GX device, the
CONF_DONE pin goes hi gh to show successful configuration and the start
of initialization. The CONF_DONE pin must have an external 10-kΩ pull-
up resistor in order for the device to initialize. Initialization, by default,
uses an internal oscillator, which runs at 10 MHz. After initiali zation, this
internal oscillator is turned off. If you are using the clkusr option, after all
data is transferred clkusr must be clocked an additional 136 times for
the Stratix or Stratix GX device to initialize pr operly. Driving DCLK to the
device after configuration is complete does not affect device operation. By
Byte0 Byte1 Byte2 Byte3 Byten
Tri-State User Mode
(3)
(2)
tOEZX
tPOR
tCH
tCL
tDSU
tCO
tDH
Tri-State
OE/nSTATUS
nCS/CONF_DONE
DCLK
DATA[7..0]
User I/O
INIT_DONE
nINIT_CONF or VCC/nCONFIG
11–26 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
default, the INIT_DONE output is disabled. You can enable the
INIT_DONE output by turning on the Enable INIT_DONE output
option in the Quartus II software.
If you do not turn on the Enable INIT_DONE output option in the
Quartus II software, you are advised to wait for maximum value of
tCD2UM (see Table 11–9) after the CONF_DONE signal goes high to ensure
the device has been initialized properly and that it has entered user mode.
During configuration and initial ization and befor e the dev ice enters user
mode, the microprocessor must not drive the CONF_DONE signal low.
1If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configur ation during device initialization, you need to
ensure CLKUSR continues toggl ing during the time nSTATUS is
low (maximum of 40 µs).
If the Stratix or St ratix GX device detects an error during configuration, it
drives nSTATUS low to alert the microprocessor. The pin on the
microprocessor connected to nSTATUS must be an input. The
microprocessor can then pulse nCONFIG low to rest art the configur ation
error. With the Auto-restart configuration after error option on, the
Stratix or Stratix GX device releases nSTATUS after a reset time-out
period. After nSTATUS is released, the microprocessor can reconfigure
the Stratix or Stratix GX device without pulsing nCONFIG low.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. If the microprocessor sends all
the data and the initialization clock starts but CONF_DONE and
INIT_DONE have not gone high, it must r econfigure the Stra tix or
Stratix GX device. After waiting the specified 136 DCLK cycles, the
microprocessor should restart configuration by pulsing nCONFIG low.
Figure 11–12 shows the circuit for Stratix and Stratix GX parallel
configuration using a microprocessor.
Altera Corporation 11–27
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Figure 11–12. Paralle l Configuration Using a Microprocessor
Note to Figure 11–12:
(1) The pull-up resistors should be connected to any VCC that meets the Stratix high-
level input voltage (VIH) specification.
For multi-device parallel configuration with a microprocessor, the nCEO
pin of the first Stratix or Stratix GX device is cascaded to the second
device’s nCE pin. The second device in the chain begins configuration
within one clock cycle; therefore, the transfer of data de stinations is
transparent to the micropr ocessor. Because the CONF_DONE pins of the
devices ar e connected together, all devices initialize and enter user mo de
at the same time.
Because the nSTATUS pins are also tied together, if any of the devices
detects an error, the entire chain halts configuration and drives nSTATUS
low. The microprocessor can then pulse nCONFIG low to restart
configuration. If the Auto-restart configuration after error option is on,
the Stratix and Stratix GX devices r ele ase nSTATUS after a r eset time-o ut
period. The microprocessor can then reconfigure the devices once
nSTATUS is r e leased. Figure 11–13 shows multi-device conf ig uration
using a microprocessor. Figure 11–14 shows multi-device configuration
when both Stratix and Stratix GX devices ar e receiving t he same data. In
this case, the microprocessor sends the data to both devices
simultaneousl y, and the devices configure simultaneously.
Microprocessor
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
Stratix Device
Memory
ADDR DATA[7..0]
GND
MSEL1
MSEL2
V
CC
(1)
V
CC
(1)
GND
DCLK
nCEO N.C.
MSEL0
10 kΩ10 kΩ
11–28 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
Figure 11–13. Parallel Data Transfer in Serial Configuration with a Microprocessor
Note to Figure 11–13:
(1) You should connect the pull-up resistors to any VCC that meets the Stratix high-level input volt age (VIH)
specification.
Figure 11–14. Multiple Device Parallel Configuration with the Same Data Using a Microprocessor
Notes to Figure 11–14:
(1) You should connect the pull-up resistors to any VCC that meets the Stratix high-level input volt age (VIH)
specification.
(2) The nCEO pins are left unconnected when configuring the same data into multiple Stratix or Stratix GX devices.
fFor more information on configuring mu ltiple Altera devices in the same
configuration chain, see the Configuring Mixed Altera FPGA Chains
chapter in the Configuration Handbook, Volume 2.
Microprocessor
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
Stratix Device
Memory
ADDR DATA[7..0]
GND
VCC
(1)
VCC
(1)
DCLK
nCEO
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
Stratix Device
MSEL1
MSEL2
DCLK
nCEO N.C.
GND
MSEL0
MSEL1
MSEL2
MSEL0
GND
10 kΩ
10 kΩ
Microprocessor
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
Stratix Device
Memory
ADDR DATA[7..0]
GND
VCC
(1)
VCC
(1)
DCLK
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
Stratix Device
MSEL1
MSEL2
DCLK
nCEO N.C.
(2)
GND
MSEL0
MSEL1
MSEL2
GND
MSEL0
nCEO N.C.
(2)
GND
10 kΩ
10 kΩ
Altera Corporation 11–29
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
FPP Configuration Timing
Figure 11–15 shows FPP timing waveforms for configuring a Stratix or
Stratix GX device in FPP mode. Table 11–9 shows the FPP timing
parameters for Stratix or Stratix GX devices.
Figure 11–15. Timing Waveform for Config uring Devices in FPP Mode Note (1)
Notes to Figure 11–15:
(1) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
(2) Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay.
(3) Upon power-up, before and during configuration, CONF_DONE is low.
(4) DCLK should not be left floating after configuration. It should be driven high or low, whichever is convenient.
DATA[] is available as user I/Os after configuration and the state of these pins depends on the dual-purpose pin
settings.
Table 11–9. FPP Timing Parameters for Stratix & Stratix GX Devices (Part 1 of 2)
Symbol Parameter Min Max Units
tCF2CK nCONFIG high to first rising edge on DCLK 40 µs
tDSU Data setup time before rising edge on DCLK 7ns
tDH Data hold time after rising edge on DCLK 0ns
tCFG nCONFIG low pulse width 40 µs
tCH DCLK high time 4ns
tCL DCLK low time 4ns
tCLK DCLK period 10 ns
nCONFIG
nSTATUS (2)
CONF_DONE (3)
DCLK
DATA[7..0}
User I/O
INIT_DONE
Byte 0 Byte 1 Byte 2 Byte 3 Byte n
tCD2UM
tCF2ST1
tCF2CD
tCFG
tCH tCL
tDH
tDSU
tCF2CK
tSTATUS
tCLK
tCF2ST0
tST2CK
High-Z User Mode
(4)
(4)
User Mode
11–30 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
PPA Configuration
In PPA schemes, a microprocessor drives data to the Stratix or Stratix GX
device thro ugh a download cable. When using a PPA scheme, use a 1-kΩ
pull-up resistor to pull the DCLK pin high to pr ev ent unused
configuration pins from floating.
To begin configuration, the microprocessor drives nCONFIG high and
then asserts the target device’s nCS pin low and CS pin high. Next, the
microprocessor places an 8-bit configuration word on the target device ’s
data inputs and pulses nWS low. On the rising edge of nWS, the target
device latches a byte of configuration data and th en drives its RDYnBSY
signal low, indicating that it is processing the byte of configurat ion data.
The microprocessor then performs other system functions while the
Stratix or Stratix GX device is processing the byte of configuration data.
Next, the micropr ocessor checks nSTATUS and CONF_DONE. If nSTATUS
is high and CONF_DONE is low, the microprocessor sends the next data
byte. If nSTATUS is low, the device is signaling an error and the
microprocessor should restart configuration. However, if nSTATUS is
high and all the configuration data is received, the device is ready for
initialization. At the beginning of i nitialization, CONF_DONE goes high to
indicate that configuration is complete. The CONF_DONE pin must have
an external 10-kΩ pull-up resistor in order for the device to initialize.
Initialization, by default, uses an internal oscillator, which runs at
10 MHz. Afte r initialization, this inte rnal oscillator is turned off. When
initialization is complete, the Stratix or Stratix GX device enters user
mode.
fMAX DCLK frequency 100 MHz
tCD2UM CONF_DONE high to user mode (1) 620µs
tCF2CD nCONFIG low to CONF_DONE low 800 ns
tCF2ST0 nCONFIG low to nSTATUS low 800 ns
tCF2ST1 nCONFIG high to nSTATUS high 40 (2) µs
tSTATUS nSTATUS low pulse width 10 40 (2) µs
tST2CK nSTATUS high to firstrising edge of DCLK 1µs
Notes to Table 11–9:
(1) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 136 to obtain this value.
(2) This value is obtainable if users do not delay configuration by extending the nSTATUS low pulse width.
Table 11–9. FPP Timing Parameters for Stratix & Stratix GX Devices (Part 2 of 2)
Symbol Parameter Min Max Units
Altera Corporation 11–31
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Figure 11–16 shows the PPA configuration circuit. An optional address
decoder controls the device’s nCS and CS pins. This decoder allows the
microprocessor to select the Stratix or Stratix GX device by accessing a
particular address, simplifying the configuration process.
Figure 11–16. PPA Configuration Circuit
Note to Figure 11–16:
(1) The pull-up resistor should be connected to the same supply voltage as the Strati x or Stratix GX device.
The device’s nCS or CS pins can be toggled during PPA configuration if
the design meets the specifications for tCSSU, tWSP, and tCSH given in
Table 11–10 on page 11–36. The microprocessor can al so di rectly control
the nCS and CS signals. You can tie one of the nCS or CS signals to its
active state (i.e., nCS may be tied low) and toggle the other signal to
control configuration.
Stratix and Stratix GX devices can serialize data internally without the
microprocessor. When the Stratix or Stratix GX device is ready for the
next byte of configuration data, it drives RDYnBSY high. If the
micro processor senses a high si gnal when it polls RDYnBSY, the
microprocessor strobes the ne xt byte of configuration da ta into the
device. Alternativ el y, the nRS signal can be strobed, causing the
RDYnBSY signal to appear on DATA7. Because RDYnBSY does not need to
MSEL2
MSEL1
MSEL0
Stratix Device
DCLK
10 kΩ
10 kΩ
10 kΩ
10 kΩ
nCS
CS
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nWS
nRS
nCONFIG
RDYnBSY
Address Decoder
VCC
VCC
VCC
ADDR
Microprocessor VCC
VCC
Memory
ADDR DATA[7..0]
GND nCEO N.C.
(1)
(1)
(1)
(1)
GND
11–32 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
be monitor ed, reading the state of the configuration data by strobing nRS
low saves a system I/O port. Do not drive data onto the data bus while
nRS is low because it causes co ntention on DATA7. If the nRS pin is not
used to monitor configuration, you should tie it high. To simplify
configuration, the microprocessor can wait for the total time of
tBUSY(max) + tRDY2WS + tW2SB before sending the next data bit.
After configuration, the nCS, CS, nRS, nWS, and RDYnBSY pins act as user
I/O pins. However, if the PPA scheme is chosen in the Quartus II
software, these I/O pins are tri-stated by default in user mode and should
be driven by the micropr ocessor. To change the default settings in the
Quartus II software, select Device & Pin Option (Compiler Setting
menu).
If the Stratix or St ratix GX device detects an error during configuration, it
drives nSTATUS low to alert the micropr oces sor. The micr oproces sor can
then pulse nCONFIG low to restart the configuration process.
Alternatively, if the Auto-Restart Configuration on Frame Error option
is turned on, the Stratix or Stratix GX device releases nSTATUS after a
rese t time-out period. After nSTATUS is released, the micr opro cessor can
reconfigure the Stratix or Stratix GX de vice. At this point, the
microprocessor does not need to pulse nCONFIG low.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successfu l configuration. The m icroprocessor mu st
monitor the nSTATUS pin to detect errors and the CONF_DONE pin to
determine when programming completes (CONF_DONE goes high one
byte early in parallel mode). If the micr oprocessor sends all configuration
data and starts initialization but CONF_DONE is not assert ed, the
microprocessor must r econfigure the Stratix or Stratix GX device.
By default, the INIT_DONE is disabled. You can enable the INIT_DONE
output by turning on the Enable INIT_DONE output option in the
Quartus II software. If you do not turn on the Enable INIT_DONE
output option in the Quartus II software, you are advised to wait for the
maximum value of tCD2UM (see Table 11–10) after the CONF_DONE signal
goes high to ensure the device has been initialized properly and that it has
entered user mode.
During configuration and initia lization, and before the device enters user
mode, the microprocessor must not drive the CONF_DONE signal low.
1If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configur ation during device initialization, you need to
ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 μs).
Altera Corporation 11–33
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
You can al so use PPA mode to configure multiple Stratix and Stratix GX
devices. Multi-device PPA configuration is similar to single-device PPA
configuration, except that the Stratix and Stratix GX devices ar e cascaded.
After you configure the first Stratix or Stratix GX device, nCEO is asserted,
which asserts the nCE pin on the second device, initiating conf iguration.
Because the second Stratix or Stratix GX device begins configura tion
within one write cycle of the first device, the t ransfer of data des tinations
is transparent to the microprocessor. All Stratix and Stratix GX device
CONF_DONE pins ar e tied together; therefore, all devices initiali ze and
enter user mode at the same time. See Figure 11–17.
Figure 11–17. PPA Multi-Device Configuration Circuit
Notes to Figure 11–17:
(1) If not used, you can connect the CS pin to VCC directly. If not us ed , the nCS pin can be connected to GND directly.
(2) Connect the pull-up resistor to the same supply voltage as the Stratix or Stratix GX device.
GND
Address Decoder
ADDR
ADDR
Memory
DATA[7..0]
nCS
CS
(1)
CONF_DONE
nSTATUS
nCE
nWS
nRS
nCONFIG
RDYnBSY
nCS
CS
(1)
CONF_DONE
nSTATUS
nCE
nWS
nRS
nCONFIG
RDYnBSY
Microprocessor
DATA[7..0] DATA[7..0]
nCEO N.C.
nCEO
(2)
(3)
DCLK
(2)
DCLK
(2)
10 kΩ
10 kΩ10 kΩ
10 kΩ
Stratix Device 1 Stratix Device 2
MSEL2
MSEL1
MSEL0
VCC
GND
VCC
GND
VCC
VCC
VCC
VCC
(2)
10 kΩ
VCC
MSEL2
MSEL1
MSEL0
11–34 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
PPA Configuration Timing
Figure 11–18 shows the Stratix and Stratix GX device timing waveforms
for PPA configuration.
Figure 11–18. PPA Timing Waveforms for Stratix & Stratix GX Devices
Notes to Figure 11–18:
(1) Upon power-up, nSTATUS is held low for the time of the POR delay.
(2) Upon power-up, before and during configuration, CONF_DONE is low.
(3) After configuration, the state of CS, nCS, nWS, and RDYnBSY depends on the des ign programmed into the St ratix or
Stratix GX device.
(4) Device I/O pins are in user mode.
Byte 0 Byte 1
t
DH
t
WSP
t
CF2WS
nCONFIG
nSTATUS
(
1)
CONF_DONE
(
2)
DATA[7..0]
CS
(
3)
nCS
(
3)
nWS
(
3)
RDYnBSY
(
3)
Byte n Ð 1 Byte n
t
BUSY
t
WS2B
t
RDY2WS
t
CFG
t
STATUS
User I/Os
INIT_DONE
High-Z
t
CF2ST0
t
CF2CD
(
4)
(
4)
(
4)
(
4)
(
4)
t
CF2ST1
t
DSU
t
CSSU
t
CSH
t
CD2UM
t
CSSU
Altera Corporation 11–35
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Figure 11–19 shows the Stratix and Stratix GX timing waveforms when
using strobed nRS and nWS signals.
Figure 11–19. PPA T iming Waveforms Using Strobed nRS & nWS Signals
Notes to Figure 11–19:
(1) The user can toggle nCS or CS during configuration if the design meets the specification for tCSSU, tWSP, and tCSH.
(2) Device I/O pins are in user mode.
(3) The DATA[7..0] pins are available as user I/Os after configuration and the state of theses pins depends on th e
dual-purpose pin settings. Do not leave DATA[7..0] floating. If these pins are not used in user-mode, you should
drive them high or low, whichever is more convenient.
(4) DATA7 is a bidirectional pin. It represents an input for data input, but repr esents an output to show the status of
RDYnBSY.
Byte 0 Byte 1 Byte n
nCONFIG
nSTATUS
CONF_DONE
nCS (1)
CS (1)
DATA[7..0]
nWS
nRS
INIT_DONE
User I/O
DATA7/RDYnBSY (4)
tCSSU
tCFG
tWSP
tWS2RS
tRSD7
tRDY2WS
tDH
tBUSY
tCSH
tDSU
tCF2WS
(2)
(2)
(3)
(2)
(2)
(2)
(2)
tCD2UM
tRS2WS
tCF2ST1
tCF2SCD
tCF2ST0
tSTATUS
tWS2RS
tWS2B
11–36 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
Table 11–10 defines the Stratix and St ratix GX timing parameters f or PPA
configuration
fFor information on how to create configuration and programming files
for this configuration scheme, see the Software Settings section in the
Configuration Handbook, Volume 2.
JTAG Programming & Configuration
The JTAG has developed a specifica tion for bound a ry-scan testing. This
boundary-scan test (BST) architecture of fers the capability to efficiently
test components on printed cir cuit boards (PCBs) with tight lead spacing.
The BST architecture can test pin connections without using physical test
Table 11–10. PPA Timing Parameters for Stratix & Stratix GX Devices
Symbol Parameter Min Max Units
tCF2WS nCONFIG high to first rising edge on nWS 40 µs
tDSU Data setup time before rising edge on nWS 10 ns
tDH Data hold time after rising edge on nWS 0ns
tCSSU Chip select setup time before rising edge on nWS 10 ns
tCSH Chip select hold time after rising edge on nWS 0ns
tWSP nWS low pulse width 15 ns
tCFG nCONFIG low pulse width 40 µs
tWS2B nWS rising edge to RDYnBSY low 20 ns
tBUSY RDYnBSY low pulse width 745ns
tRDY2WS RDYnBSY rising edge to nWS rising edge 15 ns
tWS2RS nWS rising edge to nRS falling edge 15 ns
tRS2WS nRS rising edge to nWS rising edge 15 ns
tRSD7 nRS falling edge to DATA7 valid with RDYnBSY signal 20 ns
tCD2UM CONF_DONE high to user mode (1) 620µs
tSTATUS nSTATUS low pulse width 10 40 (2) µs
tCF2CD nCONFIG low to CONF_DONE low 800 ns
tCF2ST0 nCONFIG low to nSTATUS low 800 ns
tCF2ST1 nCONFIG high to nSTATUS high 40 (2) µs
Notes to Table 11–10:
(1) The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 136 to obtain this value.
(2) This value is obtained if you do not delay configuration by extending the nstatus to low pulse width.
Altera Corporation 11–37
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
probes and captur e functio nal data while a device is operating normally.
You can al so use the JTAG circuitry to shift configuration data into the
device.
fFor more information on JTAG boundary-scan testing, see AN 39: IEEE
1149.1 (JTAG) Boundary-Scan Testing in Altera Devices .
To use the SignalTap®II embedded logic analyzer, you need to connect
the JTAG pins of your Stratix device to a download cable header on your
PCB.
fFor more information on SignalTap II, see the Design Debugging Using
SignalTap II Embedded Logic Analyzer chapter in the Quartus II Handbook,
Volume 2.
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS,
and TCK, and one optional pin, TRST. The four JTAG input pins (TDI,
TMS, TCK and TRST) have weak, internal pull-u p resistors, whose valu es
range from 20 to 40 kΩ. All other pins are tri-stated during JTAG
configuration. Do not begin JTAG configuration until all other
configuration is complete . Table 11–11 shows each JTAG pin’s function.
Table 11–11. JTAG Pin Descriptions
Pin Description Function
TDI Test data input Serial input pin for instructions as well as test and programming data. Data is
shifted in on the rising edge of TCK. The VCCSEL pin controls the input buffer
selection.
TDO Test data output Serial data output pin for instructions as well as test and progr amming data. Data
is shifted out on the falling edge of TCK. The pin is tri-stated if data is not being
shifted out of the device. The high level output voltage is determined by VCCIO.
TMS Test mode select Input pin that provides the control signal to determine the transitions of the Test
Access Port (TAP) controller state machine. Transitions within the state machine
occur on the rising edge of TCK. Therefore , TMS must be set up bef ore the rising
edge of TCK. TMS is evaluated on the rising edge of TCK. The VCCSEL pin
controls the input buffer selection.
TCK Test clock input The clock input to the BST circuitry. Some operations occur at the rising edge,
while others occur at the falling edge. The VCCSEL pin controls the input buffer
selection.
TRST Test reset input
(optional) Active-low input to asynchronously reset the boundary-scan circuit. The TRST
pin is optional according to IEEE Std. 1149.1. The VCCSEL pin controls the input
buffer selection.
11–38 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
During JTAG configuratio n, data is downloaded to t he device on the PCB
through the MasterBlaster or ByteBlasterMV header . Configuring devices
through a cable is similar to programming devices in-system. One
difference is to connect the TRST pin to VCC to ensure that the TAP
controller is not reset. See Figure 11–20.
Figure 11–20. JTAG Configuration of a Single Device
Notes to Figure 11–20:
(1) You should connect the pull-up resistor to the same supply voltage as the
download cable.
(2) You should connect the nCONFIG, MSEL0, and MSEL1 pins to support a non-JTAG
configuration scheme. If you only use JTAG configuration, connect nCONFIG to
VCC, and MSEL0, MSEL1, and MSEL2 to ground. Pull DATA0 an d DCLK to high or
low.
(3) VIO is a reference voltage for the MasterBlaster output driver . VIO should match the
device’s VCCIO. See the MasterBlaster Serial/USB Communications Cable Data Sheet for
this value.
To configure a single dev ic e in a JTAG chain, the programming software
places all other devices in BYPASS mode. In BYPASS mode, devices pass
programming data fr om the TDI pin to the TDO pin through a single
bypass register without being af fected internally. This scheme enables the
programming software to program or verify the target device.
Configuration data driven into the device appears on the TDO pin one
clock cycle later.
nCE
MSEL0
MSEL1
nCONFIG
CONF_DONE
VCC (1)
VCC (1)
GND
VCC
VCC
GND
VCC
(2)
(2)
(2)
VCC (1)
1 kΩ
10 kΩ
10 kΩ
1 kΩ
nSTATUS
Pin 1
MasterBlaster or ByteBlasterMV
10-Pin Male Header
(Top View)
GND
TRST
TCK
TDO
TMS
TDI
1 kΩ
GND
VIO (3)
Stratix or
Stratix GX Device
MSEL2
DATA0
DCLK
(2)
(2)
(2)
Altera Corporation 11–39
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Stratix and Stratix GX device s have de dicated JTAG pins. You can
perform JTAG testing on Stratix and Stratix GX devices before and after,
but not during configuration. The chip-wide reset and output enable pins
on Stratix and Stratix GX devices do not affect JTAG boundary-scan or
programming operations. Toggling these pins does not affect JTAG
operations (other than the usual boundary-scan operation).
When designing a board for JTAG configuration of Stratix and Stratix GX
devices, you should consider the r egular configur ation pins. Table 11–12
shows how you should connect these pins during JTAG configuration.
JTAG Programming & Configuration of Multiple Devices
When programming a JTAG device chain, one JTAG-compatible header,
such as the ByteBlasterMV header, is connected to several devices. The
number of devices in the JT AG chain is limited only by the drive capacity
of the download cable. However, when more than five devices ar e
connected in a JTAG chain, Altera recommends buffering the TCK, TDI,
and TMS pins with an on-board buffer.
Table 11–12. Dedicated Configuration Pin Co nnections During JTAG Configuration
Signal Description
nCE On all Stratix and Stratix GX devices in the chain, nCE should be driven low by connecting it to
ground, pulling it low via a resistor, or driving it by some control circuitry. For de vices that are also
in multi-device PS, FPP or PPA configuration chains, the nCE pins should be connected to GND
during JTAG configuration or JTAG configured in the same order as the configuration chain.
nCEO On all Stratix and Stratix GX devices in the chain, nCEO can be left floating or connected to the
nCE of the next device. See nCE pin description above.
MSEL These pins must not be left floating. These pins support whichever non-JTAG configuration is used
in production. If only JTAG configuration is used, you should tie both pins to ground.
nCONFIG nCONFIG must be driven high through the JTAG programming process. Driven high by connecting
to VCC, pulling high via a resistor, or driven by some control circuitry.
nSTATUS Pull to VCC via a 10-kΩ resistor . When configuring multiple devices in the same JTAG chain, each
nSTATUS pin should be pulled up to VCC individually. nSTATUS pulling low in the middle of JTAG
configuration indicates that an error has occurred.
CONF_DO
NE Pull to VCC via a 10-kΩ resistor. When configuring multiple devices in the same JTAG chain, each
CONF_DONE pin should be pulled up to VCC individually. CONF_DONE going high at the end of
JTAG configuration indicates successful configuration.
DCLK Should not be left floating. Drive low or high, whichever is more convenient on your board.
DATA0 Should not be left floating. Drive low or high, whichever is more convenient on your board.
11–40 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
JT AG-chain device programming is ideal when the PCB contains multiple
devices, or when testing the PCB using JTAG BST circuitry. Figure 11–21
shows multi-device JTAG configuration.
Figure 11–21. Multi-Device JTAG Configuration Notes (1), (2)
Notes to Figure 11–21:
(1) Stratix, Stratix GX, APEXTM II, APEX 20K, MercuryTM, ACEX® 1K, and FLEX® 10K devices can be placed within the
same JTAG chain for device programming and configuration.
(2) For more information on all configuration pins connected in this mode, see Table 11–11 on page 11–37.
(3) Connect the nCONFIG, MSEL0, MSEL1, and MSEL2 pins to support a non-JTAG configuration scheme. If only JTAG
configuration is used, connect nCONFIG to VCC, and MSEL0, MSEL1, and MSEL2 to ground. Pull DATA0 and DCLK
to either high or low.
(4) VIO is a reference voltage for the MasterBlaster output driver. VIO should match the device’s VCCIO. See the
MasterBlas ter Serial/USB Communications Cable Data Sheet for this value.
(5) nCE must be connected to GND or driven low for successful JTAG configuration.
The nCE pin must be connected to GND or driven low during JTAG
configuration. In mul ti-device PS, FPP and PPA configuration chains, the
first device's nCE pin is connected to GND while its nCEO pin is connected
to nCE of the next device in the chain. The las t device's nCE input comes
from the pr evious device, while its nCEO pin is left floating. After the first
device complete s configuration in a mu lti-device c onfiguration chain, its
nCEO pin drives low to activate the second device's nCE pin, which
prompts the second device to begin configuration. Therefore, if these
devices are also in a JTAG chain, you should make sure the nCE pins are
connected to GND during JT AG configuration or that the devices ar e JT AG
configured in the same order as the configuration chain. As long as the
devices are JTAG configured in the same order as the multi-device
configuration chain, the nCEO of the previous device drives nCE of the
next device low when it has successfully been JTAG configured.
TMS TCK
MasterBlaster or ByteBlasterMV
10-Pin Male Header
TDI TDO
VCC
VCC
VCC
Pin 1
nSTATUS
nCONFIG
MSEL2
MSEL1
nCE
VCC
CONF_DONE
VCC
TMS TCK
TDI TDO
nCONFIG
MSEL2
MSEL1
nCE
VCC
CONF_DONE
VCC
TMS TCK
TDI TDO
nCONFIG
MSEL2
MSEL1
nCE
VCC
CONF_DONE
VCC
1 kΩ
(3)
(3)
(3)
MSEL0
(3)
(3)
(3)
(3)
MSEL0
(3)
(3)
DCLK DCLK DCLK
(3)
(3) (3)
DATA 0 DATA0 DATA0
(3)
(3) (3)
(3)
(3)
MSEL0
(3)
VIO
(4)
Stratix Device Stratix Device Stratix Device
1 kΩ
nSTATUS nSTATUS
10 kΩ10 kΩ10 kΩ10 kΩ10 kΩ10 kΩ
(5) (5) (5)
1 kΩ
Altera Corporation 11–41
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
The Quartus II software verifies successful JTAG configuration upon
completion. The software checks the sta te of CONF_DONE through the
JTAG port. If CONF_DONE is not in the correct state, the Quartus II
software indicates that configuration has failed. If CONF_DONE is in the
correct state, the software indicates that configuration was successful.
1If VCCIO is tied to 3.3 V, both the I/O pins and JTAG TDO port
drive at 3.3-V levels.
Do not attempt JT AG and non-JTAG configuration simultaneously. When
configuring through JTAG, allow any non-JTAG configuration to
complete first.
Figure 11–22 shows the JTAG configuration of a Stratix or Stratix GX
device with a microprocessor.
Figure 11–22. JTAG Configuration of Stratix & Stratix GX Devices with a
Microprocessor
Notes to Figure 11–22:
(1) Connect the nCONFIG, MSEL2, MSEL1, and MSEL0 pins to support a non-JTAG
configuration scheme. If your design only uses JTAG configuration, connect the
nCONFIG pin to VCC and the MSEL2, MSEL1, and MSEL0 pins to ground.
(2) Pull DATA0 and DCLK to either high or low.
Configuration with JRunner Software Driver
JRunner is a software driver that allows you to configure Altera FPGAs
through the ByteBl asterMV download cable in JTAG mode. The
programming input file supported is in Raw Binary File (.rbf) format.
JRunner also require s a Chain Description File (.cdf) generated by the
Quartus II software. JRunner is targeted for embedded JTAG
configuration. The source code has be en develo ped for the Windows NT
operating system. You can customize the code to make it run on other
platforms.
nCONFIG
DATA0
DCLK
TDI
TCK
TMS
Microprocessor
Memory
ADDR DATA
TDO
Stratix or
Stratix GX Device
nSTATUS
CONF_DONE
VCC
VCC
10 kΩ
10 kΩ
(2)
(1)
(2)
(1)
(1)
(1)
MSEL2
MSEL1
MSEL0
11–42 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
fFor more information on the JRunner software driver, see the JRunner
Software Driver: An Embedded Solution to the JTAG Configuration White
Paper and zip file.
Jam STAPL Programming & Test Language
The JamTM Standard Test and Programming Language (STAPL), JEDEC
standard JESD-71, is a standar d file format for in-system
programmabilit y (ISP) purposes. Jam STAPL supports programming or
configuration of pr ogrammable devices and testing of electr onic systems,
using the IEEE 1149.1 JTAG interface. Jam ST APL is a freely licensed open
standard.
Connecting the JTAG Chain to the Embedded Processor
There are two ways to connect the JTAG chain to the embedded processor .
The most straightforward method is to connect the embedded processor
directly to the JTAG chain. In this method, four of the processor pins are
dedicated to the JTAG interface, saving board space but reducing the
number of available embedded processor pins.
Figure 11–23 illustrates the second method, which is to connect the JTAG
chain to an existing bus through an interface PLD. In this method, the
JTAG chain becomes an address on the existing bus. The processor then
reads from or writes to the address representing the JTAG chain.
Altera Corporation 11–43
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Figure 11–23. Embedded System Block Diagram
Notes to Figure 11–23:
(1) Connect the nCONFIG, MSEL2, MSEL1, and MSEL0 pins to support a non-JT AG configuration scheme. If your design
only uses JTAG configuration, connect the nCONFIG pin to VCC and the MSEL2, MSEL1, and MSEL0 pins to gr ound.
(2) Pull DATA0 and DCLK to either high or low.
Both JTAG connection methods should include space for the
MasterBlaster or ByteBlasterMV header connection. The header is useful
during prototyping because it allows you to verify or modify the Stratix
or Stratix GX device’s contents. During production, you can remove the
header to save cost.
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
ControlControl
d[3..0]d[7..0]
adr[19..0]
Control
d[7..0]
adr[19..0]adr[19..0]
Interface
Logic
(Optional)
Any JTAG
Device
EPROM or
System
Memory
to/from ByteBlasterMV
Embedded
Processor
Embedded System
8
8
4
20
2020
MAX® 9000,
MAX 9000A,
MAX 7000S,
MAX 7000A,
MAX 7000AE,
or MAX 3000
Device
Cyclone FPGA
TDI
TMS
TRST
CONF_DONE
nSTATUS
nCONFIG
MSEL0
MSEL1
nCE
TCK
TDO
Any Cyclone,
FLEX 10K,
FLEX 10KA,
FLEX10KE,
APEX 20K,
or APEX 20KE
Device
10 kΩ10 kΩ
V
CC
V
CC
V
CC
GND
DATA0
DCLK
nCONFIG
(2)
(2)
(1)
(1)
(1)
MSEL1
MSEL0
11–44 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
Program Flow
The Jam Player provides an interface for manipulating the IEEE
Std. 1 149.1 JTAG TAP state machine. The TAP controller is a 16-state state
machine that is clocked on the rising edge of TCK, and uses the TMS pin to
control JTAG operation in a device. Figure 11–24 shows the flow of an
IEEE Std. 1149.1 TAP controller state machine.
Altera Corporation 11–45
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Figure 11–24. JTAG TAP Controller State Machine
While the Jam Player provides a driver that manipulates the TAP
contro ller, the Jam Byte-Code File (.jbc) provides the high-level
intelligence ne e ded to program a given device. All Jam in struc t ions that
SELECT_DR_SCAN
CAPTURE_DR
SHIFT_DR
EXIT1_DR
PAUSE_DR
EXIT2_DR
UPDATE_DR
SHIFT_IR
EXIT1_IR
PAUSE_IR
EXIT2_IR
UPDATE_IR
TMS = 0
TMS = 0
TMS = 0
TMS = 1
TMS = 0
TMS = 1
TMS = 1
TMS = 0
TMS = 1
TMS = 0
TMS = 1
TMS = 1
TMS = 0
TMS = 0
TMS = 1
TMS = 1
TMS = 0
TMS = 1
TMS = 0
TMS = 0
TMS = 1
TMS = 0
TMS = 0
TMS = 1
TMS = 0
RUN_TEST/
IDLE
TMS = 0
TEST_LOGIC/
RESET
TMS = 1
TMS = 0
TMS = 1 TMS = 1
TMS = 1 TMS = 1
CAPTURE_IR
SELECT_IR_SCAN
11–46 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
send JTAG data to the device involve moving the TAP controller thr ough
either the data register leg or the instruction register leg of the state
machine. For example, loadi ng a JTAG instruction involves movi ng the
T AP contr oller to the SHIFT_IR state and shifting the instruction into the
instruction register through the TDI pin. Next, the TAP controller is
moved to the RUN_TEST/IDLE state where a delay is implemented to
allow the instruction time to be latc hed. This pr ocess is identic al for data
register scans, except that the data register leg of the state machine is
traversed.
The high-level Jam instructions are the DRSCAN instruction for scanning
the JTAG data register, the IRSCAN instruction for scanning the
instruction register , and the WAIT command that causes the state machine
to sit idle for a specified period of time. Each leg of the TAP controller is
scanned repeatedly, according to instructions in the JBC file, until all of
the target devices are programmed.
Figure 11–25 illustrates the functional behavior of the Jam Player when it
parses the JBC file. When the Jam Player encounters a DRSCAN, IRSCAN,
or WAIT instr uction, it generates the proper data on TCK, TMS, and TDI to
complete the instruction. The flow diagram shows branches for the
DRSCAN, IRSCAN, and WAIT instructions. Although the Jam Player
supports other instructions, they are omitted from the flow diagram for
simplicity.
Altera Corporation 11–47
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Figure 11–25. Jam Player Flow Diagram (Part 1 of 2)
Set TMS to 1
and Pulse TCK
Twice
Set TMS to 0
and Pulse TCK
Twice
Switch
Case[]
EOF
Start
Switch
End
EOF?
Test-Logic-Reset
Run-Test/Idle
Set TMS to 1
and Pulse TCK
Five Times
Set TMS to 0
and Pulse TCK
Read Instruction
from the Jam
File
Set TMS to 1
and Pulse TCK
Three Times
F
T
Test-Logic-Reset
Parse Argument
IRSCAN
DRSCAN
Switch
Set TMS to 0
and Pulse TCK
Delay
WAIT
Run-Test/Idle
Select-IR-Scan
Shift-IR
Set TMS to 0
and Pulse TCK
and Write TDI
Set TMS to 0
and Pulse TCK
and Write TDI
Set TMS to 1
and Pulse TCK
Set TMS to 0
and Pulse TCK
Set TMS to 1
and Pulse TCK
Twice
Set TMS to 0
and Pulse TCK
Shift-IR
Exit1-IR
Pause-IR
Update-IR
Run-Test/Idle
Shift-DR
Set TMS to 0
and Pulse TCK
and Write TDI
Set TMS to 0
and Pulse TCK
Twice
Set TMS to 1
and Pulse TCK
Parse Argument
Shift-DR
Select-DR-Scan
Continued on
Part 2 of
Flow Diagram
F
T
Shift-IR
11–48 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
Figure 11–26. Jam Player Flow Diagram (Part 2 of 2)
Execution of a Jam program starts at the beginning of the program. The
program flow is controlled using GOTO, CALL/RETURN, and FOR/NEXT
structures. The GOTO and CALL statements see labels that are symbolic
names for program statements located elsewhere in the Jam program. The
language itself enforces almost no constraints on the organizational
structure or control flow of a program.
1The Jam language does not support linking multiple Jam
programs together or including the contents of another file into
a Jam program.
Switch
Update-IR
Run-Test/Idle
Set TMS to 1
and Pulse TCK
Set TMS to 0
and Pulse TCK
Switch
Update-IR
Run-Test/Idle
Set TMS to 1
and Pulse TCK
Set TMS to 0
and Pulse TCK
Set TMS to 1
and Pulse TCK
and Store TDO
Set TMS to 0
and Pulse TCK,
Write TDI, and
Store TDO
Shift-DR Exit1-DR
F
F
T
Report
Error
Default
Case[]
Loop<
DR Length
Set TMS to 1
and Pulse TCK
and Store TDO
Set TMS to 0
and Pulse TCK,
Write TDI, and
Store TDO
Compare
Capture
Exit1-DR
Switch
Update-IR
Run-Test/Idle
Set TMS to 1
and Pulse TCK
Set TMS to 0
and Pulse TCK
Loop<
DR Length
Set TMS to 1
and Pulse TCK
and Store TDO
Set TMS to 0
and Pulse TCK
and Write TDI
Exit1-DR
Continued from
Part 1 of
Flow Diagram
Correct
TDO Value
T
F
F
T
T
Loop<
DR Length
Altera Corporation 11–49
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Jam Instructions
Each Jam statement begins with one of the instruction nam es listed in
Table 11–13. The instruction names, in cl uding the names of the optional
instructions, are reserved keywords that you cannot use as variable or
label identifiers in a Jam program.
Table 11–14 shows the state names that are reserved keywords in the Jam
language. These keywords correspond to the state names spec ified in the
IEEE Std. 1149.1 JTAG specification.
Table 11–13. Instruction Names
BOOLEAN INTEGER PREIR
CALL IRSCAN PRINT
CRC IRSTOP PUSH
DRSCAN LET RETURN
DRSTOP NEXT STATE
EXIT NOTE WAIT
EXPORT POP VECTOR (1)
FOR POSTDR VMAP (1)
GOTO POSTIR –
IF PREDR –
Note to Table 11–13:
(1) This instruction name is an optional language extension.
Table 11–14. Reserved Keywords (Part 1 of 2)
IEEE Std. 1149.1 JTAG State Names Jam Reserved State Names
Test-Logic-Reset RESET
Run-Test-Idle IDLE
Select-DR-Scan DRSELECT
Capture-DR DRCAPTURE
Shift-DR DRSHIFT
Exit1-DR DREXIT1
Pause-DR DRPAUSE
Exit2-DR DREXIT2
Update-DR DRUPDATE
Select-IR-Scan IRSELECT
11–50 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
Example Jam File that Reads the IDCODE
Figure 11–27 illustrates the flexibility and utility of the Jam STAPL. The
example reads the IDCODE out of a single devic e in a JTAG chain.
1The array variable, I_IDCODE, is initialized with the IDCODE
instruction bits ordered the LSB first (on the left) to most
significant bit (MSB) (on the right). This order is important
because the array field in the IRSCAN instruction is always
interpreted, and sent, MSB to LSB.
Figure 11–27. Example Jam File Reading IDCODE
Capture-IR IRCAPTURE
Shift-IR IRSHIFT
Exit1-IR IREXIT1
Pause-IR IRPAUSE
Exit2-IR IREXIT2
Update-IR IRUPDATE
Table 11–14. Reserved Keywords (Part 2 of 2)
IEEE Std. 1149.1 JTAG State Names Jam Reserved State Names
BOOLEAN read_data[32];
BOOLEAN I_IDCODE[10] = BIN 1001101000; ‘assumed
BOOLEAN ONES_DATA[32] = HEX FFFFFFFF;
INTEGER i;
‘Set up stop state for IRSCAN
IRSTOP IRPAUSE;
‘Initialize device
STATE RESET;
IRSCAN 10, I_IDCODE[0..9]; ‘LOAD IDCODE INSTRUCTION
STATE IDLE;
WAIT 5 USEC, 3 CYCLES;
DRSCAN 32, ONES_DATA[0..31], CAPTURE
read_data[0..31];
‘CAPTURE IDCODE
PRINT “IDCODE:”;
FOR i=0 to 31;
PRINT read_data[i];
NEXT i;
EXIT 0;
Altera Corporation 11–51
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Configuring
Using the
MicroBlaster
Driver
The MicroBlaste rTM software driver allows you to configure Altera
devices in an embedde d environment using PS or FPP mode. The
MicroBlaster softwar e dri ver su pports a Raw Binary File (.rbf)
programming input file. The source code is developed for the Wi ndows
NT operating system, although you can customize it to run on other
operating systems. For more informat ion on the MicroBlaster software
driver, go to the Altera web site (www.altera.com).
Device
Configuration
Pins
The following tables describe the connections and functionality of all the
configuration re lated pins on the Stratix or Stratix GX devi ce. Table 11–15
describes the dedicated configuration pins, which are required to be
connected prope rly on your board for successful configuration. Some of
these pins may not be required for your configuration schemes.
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 1 of 8)
Pin Name User Mode Configuration
Scheme Pin Type Description
VCCSEL N/A All Input Dedicated input that selects which input buff er
is used on the configuration input pins;
nCONFIG, DCLK, RUnLU, nCE, nWS, nRS, CS,
nCS and CLKUSR.
The VCCSEL input buffer is powered by
VCCINT and has an internal 2.5 kΩ pull-down
resistor that is always active.
A logic high (1.5-V, 1.8-V, 2.5-V, 3.3-V) selects
the 1.8-V/1.5-V input buffer, and a logic low
selects the 3.3-V/2.5-V input buffer. See the
“VCCSEL Pins” section for more details.
PORSEL N/A All Input Dedicated input which selects between a POR
time of 2 ms or 100 ms. A logic high (1.5-V, 1.8-
V, 2.5-V, 3.3-V) selects a POR time of about 2
ms and a logic low selects POR time of about
100 ms.
The PORSEL input buffer is powered by
VCCINT and has an internal 2.5 kΩ pull-down
resistor that is always active.
11–52 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Device Configuration Pins
nIO_PULLUP N/A All Input Dedicated input that chooses whether the
internal pull-ups on the user I/Os and dual-
purpose I/Os (DATA[7..0], nWS, nRS,
RDYnBSY, nCS, CS, RUnLU, PGM[], CLKUSR,
INIT_DONE, DEV_OE, DEV_CLR) are on or
off before and during configuration. A logic high
(1.5-V, 1.8-V, 2.5-V, 3.3-V) turns off the weak
internal pull-ups, while a logic low turns them
on.
The nIO_PULLUP input buffer is powered by
VCCINT and has an internal 2.5 kΩ pull-down
resistor that is always active.
MSEL[2..0] N/A All Input 3-bit configuration input that sets the Stratix or
Stratix GX device configuration scheme. See
Table 11–2 for the appropriate connections.
These pins can be connected to VCCIO of the
I/O bank they reside in or ground. This pin uses
Schmitt trigger input buffers.
nCONFIG N/A All Input Configuration control input. Pulling this pin low
during user-mode causes the FPGA to lose its
configuration data, enter a reset state, tri-state
all I/O pins. Returning this pin to a logic high
level initiates a reconfiguration.
If your configuration scheme uses an
enhanced configuration device or EPC2
device, nCONFIG can be tied directly to VCC or
to the configuration device’s nINIT_CONF
pin. This pin uses Schmitt trigger input buffers.
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 2 of 8)
Pin Name User Mode Configuration
Scheme Pin Type Description
Altera Corporation 11–53
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
nSTATUS N/A All Bidirectional
open-drain The device drives nSTATUS low immediately
after power-up and releases it after the POR
time.
Status output. If an error occurs during
configuration, nSTATUS is pulled low by the
target device. Status input. If an external
source drives the nSTATUS pin low during
configuration or initialization, the target device
enters an error state.
Driving nSTATUS low after configuration and
initialization does not affect the configured
device. If a configuration device is used, driving
nSTATUS low causes the configuration de vice
to attempt to configure the FPGA, but since the
FPGA ignores transitions on nSTATUS in user-
mode, the FPGA does not reconfigure. To
initiate a reconfiguration, nCONFIG must be
pulled low.
The enhanced configuration devices’ and
EPC2 devices’ OE and nCS pins hav e optional
internal programmable pull-up resistors. If
internal pull-up resistors on the enhanced
configuration device are used, external 10-kΩ
pull-up resistors should not be used on these
pins. When using EPC2 de vices, only e xternal
10-kΩ pull-up resistors should be used.
This pin uses Schmitt trigger input buffers.
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 3 of 8)
Pin Name User Mode Configuration
Scheme Pin Type Description
11–54 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Device Configuration Pins
CONF_DONE N/A All Bidirectional
open-drain Status output. The target FPGA drives the
CONF_DONE pin low before and during
configuration. Once all configuration data is
received without error and the initialization
cycle starts, the target device releases
CONF_DONE.
Status input. After all data is received and
CONF_DONE goes high, the target device
initializes and enters user mode. The
CONF_DONE pin must have an external
10-kΩ pull-up resistor in order for the de vice to
initialize.
Driving CONF_DONE low after configuration
and initialization does not affect the configured
device.
The enhanced configuration devices’ and
EPC2 devices’ OE and nCS pins hav e optional
internal programmable pull-up resistors. If
internal pull-up resistors on the enhanced
configuration device are used, external 10-kΩ
pull-up resistors should not be used on these
pins. When using EPC2 de vices, only e xternal
10-kΩ pull-up resistors should be used.
This pin uses Schmitt trigger input buffers.
nCE N/A All Input Active-low chip enable. The nCE pin activates
the device with a low signal to allow
configuration. The nCE pin must be held low
during configuration, initialization, and user
mode. In single device configuration, it should
be tied low. In multi-device configuration, nCE
of the first de vice is tied lo w while its nCEO pin
is connected to nCE of the next device in the
chain.
The nCE pin must also be held low for
successful JTAG programming of the FPGA.
This pin uses Schmitt trigger input buffers.
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 4 of 8)
Pin Name User Mode Configuration
Scheme Pin Type Description
Altera Corporation 11–55
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
nCEO N/A All Multi-
Device
Schemes
Output Output that drives low when device
configuration is complete. In single device
configuration, this pin is left floating. In multi-
device configuration, this pin feeds the next
device’s nCE pin. The nCEO of the last device
in the chain is left floating.
The voltage levels driven out by this pin are
dependent on the VCCIO of the I/O bank it
resides in.
DCLK N/A Synchronous
configuration
schemes
(PS, FPP)
Input
(PS, FPP) In PS and FPP configuration, DCLK is the clock
input used to clock data from an external
source into the target device. Data is latched
into the FPGA on the rising edge of DCLK.
In PPA mode, DCLK should be tied high to VCC
to prevent this pin from floating.
After configuration, this pin is tri-stated. In
schemes that use a configuration device,
DCLK is driven low after configuration is done.
In schemes that use a control host, DCLK
should be driven either high or low, whichever
is more convenient. Toggling this pin after
configuration does not affect the configured
device. This pin uses Schmitt trigger input
buffers.
DATA0 I/O PS, FPP, PPA Input Data input. In serial configuration modes, bit-
wide configuration data is presented to the
target device on the DATA0 pin. The VIH and
VIL levels for this pin are dependent on the
VCCIO of the I/O bank that it resides in.
After configuration, DATA0 is available as a
user I/O and the state of this pin depends on
the Dual-Purpose Pin settings.
After configuration, EPC1 and EPC1441
devices tri-state this pin, while enhanced
configuration and EPC2 devices drive this pin
high.
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 5 of 8)
Pin Name User Mode Configuration
Scheme Pin Type Description
11–56 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Device Configuration Pins
DATA[7..1] I/O Parallel
configuration
schemes
(FPP and
PPA)
Inputs Data inputs. Byte-wide configuration data is
presented to the target device on
DATA[7..0]. The VIH and VIL levels for
these pins are dependent on the VCCIO of the
I/O banks that they reside in.
In serial configuration schemes, they function
as user I/Os during configuration, which means
they are tri-stated.
After PPA or FPP configuration, DATA[7..1]
are available as a user I/Os and the state of
these pin depends on the Dual-Purpose Pin
settings.
DATA7 I/O PPA Bidirectional In the PPA configuration scheme, the DATA7
pin presents the RDYnBSY signal after the nRS
signal has been strobed low. The VIL and VIL
levels for this pin are dependent on the VCCIO
of the I/O bank that it resides in.
In serial configuration schemes, it functions as
a user I/O during configuration, which means it
is tri-stated.
After PPA configuration, DATA7 is av ailable as
a user I/O and the state of this pin depends on
the Dual-Purpose Pin settings.
nWS I/O PPA Input Write strobe input. A low-to-high transition
causes the device to latch a b yte of data on the
DATA[7..0] pins.
In non-PPA schemes, it functions as a user I/O
during configuration, which means it is tri-
stated.
After PPA configuration, nWS is available as a
user I/O and the state of this pin depends on
the Dual-Purpose Pin settings.
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 6 of 8)
Pin Name User Mode Configuration
Scheme Pin Type Description
Altera Corporation 11–57
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
nRS I/O PPA Input Read strobe input. A low input directs the
device to drive the RDYnBSY signal on the
DATA7 pin.
If the nRS pin is not used in PPA mode, it
should be tied high. In non-PPA schemes, it
functions as a user I/O during configuration,
which means it is tri-stated.
After PPA configuration, nRS is available as a
user I/O and the state of this pin depends on
the Dual-Purpose Pin settings.
RDYnBSY I/O PPA Output Ready output. A high output indicates that the
target device is ready to accept another data
byte. A low output indicates that the target
device is busy and not ready to receive another
data byte.
In PPA configuration schemes, this pin drives
out high after power-up, before configuration
and after configuration before entering user-
mode. In non-PPA schemes, it functions as a
user I/O during configuration, which means it is
tri-stated.
After PPA configuration, RDYnBSY is available
as a user I/O and the state of this pin depends
on the Dual-Purpose Pin settings.
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 7 of 8)
Pin Name User Mode Configuration
Scheme Pin Type Description
11–58 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Device Configuration Pins
nCS/CS I/O PPA Input Chip-select inputs. A low on nCS and a high on
CS select the target device for configuration.
The nCS and CS pins must be held active
during configuration and initialization.
During the PPA configuration mode, it is only
required to use either the nCS or CS pin.
Therefore , if only one chip-select input is used,
the other must be tied to the active state. For
example, nCS can be tied to GND while CS is
toggled to control configuration.In non-PPA
schemes, it functions as a user I/O during
configuration, which means it is tri-stated.
After PPA configuration, nCS and CS are
availab le as a user I/Os and the state of these
pins depends on the Dual-Purpose Pin
settings.
RUnLU N/A if using
Remote
Configuration;
I/O if not
Remote
Configuration
in FPP, PS or
PPA
Input Input that selects between remote update and
local update. A logic high (1.5-V, 1.8-V, 2.5-V,
3.3-V) selects remote update and a logic low
selects local update.
When not using remote update or local update
configuration modes, this pins is available as
general-purpose user I/O pin.
PGM[2..0] N/A if using
Remote
Configuration;
I/O if not using
Remote
Configuration
in FPP, PS or
PPA
Input These output pins select one of eight pages in
the memory (either flash or enhanced
configuration device) when using a remote
configuration mode.
When not using remote update or local update
configuration modes, these pins are available
as general-purpose user I/O pins.
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device (Part 8 of 8)
Pin Name User Mode Configuration
Scheme Pin Type Description
Altera Corporation 11–59
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
Table 11–16 describes the optional configuration pins. If these optional
configuration pins are not enabled in the Quartus II software, they are
available as general-purpose user I/O pins. Therefore during
configuration, these pins function as user I/O pins and are tri-stated with
weak pull-ups.
Table 11–16. Optional Configuration Pins
Pin Name User Mode Pin Type Description
CLKUSR N/A if option is
on. I/O if option
is off.
Input Optional user-supplied clock input. Synchronizes the
initialization of one or more devices. This pin is enabled by
turning on the Enable user-supplied start-up clock
(CLKUSR) option in the Quartus II software.
INIT_DONE N/A if option is
on. I/O if option
is off.
Output open-
drain Status pin. Can be used to indicate when the device has
initialized and is in user mode. When nCONFIG is low and
during the beginning of configuration, the INIT_DONE pin is
tri-stated and pulled high due to an external 10-kΩ pull-up.
Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data),
the INIT_DONE pin goes low. When initialization is
complete, the INIT_DONE pin is released and pulled high
and the FPGA enters user mode. Thus, the monitoring
circuitry must be able to detect a low-to-high transition. This
pin is enabled b y turning on the Enable INIT_DONE output
option in the Quartus II software.
DEV_OE N/A if option is
on. I/O if option
is off.
Input Optional pin that allows the user to override all tri-states on
the device . When this pin is driven low, all I/Os are tri-stated.
When this pin is driven high, all I/Os behave as programmed.
This pin is enabled by turning on the Enable device-wide
output enable (DEV_OE) option in the Quartus II software.
DEV_CLRn N/A if option is
on. I/O if option
is off.
Input Optional pin that allows you to override all clears on all
device registers . When this pin is driven low , all registers are
cleared. When this pin is driven high, all registers beha ve as
programmed. This pin is enabled by turning on the Enable
device-wide reset (DEV_CLRn) option in the Quartus II
software.
11–60 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Device Configuration Pins
Table 11–17 describes the dedi cated JTAG pins. JTAG pins must be kept
stable before and during configuration to prevent accidental loading of
JTAG instructions. If you plan to use the SignalTap II Embedded Logic
Analyzer, you will need to connect the JTAG pins of your device to a
JTAG header on your board.
Table 11–17. Dedicated JTAG pins
Pin Name User Mode Pin Type Description
TDI N/A Input Serial input pin for instructions as well as test and
programming data. Data is shifted in on the rising edge of
TCK. If the JTAG interf ace is not required on the board, the
JTAG circuitry can be disabled by connecting this pin to
VCC. This pin uses Schmitt trigger input buffers.
TDO N/A Output Serial data output pin for instructions as well as test and
programming data. Data is shifted out on the falling edge
of TCK. The pin is tri-stated if data is not being shifted out
of the device. If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by leaving this
pin unconnected.
TMS N/A Input Input pin that provides the control signal to determine the
transitions of the TAP controller state machine. Transitions
within the state machine occur on the rising edge of TCK.
Therefore, TMS must be set up before the rising edge of
TCK. TMS is evaluated on the rising edge of TCK. If the
JTAG interface is not required on the board, the JTAG
circuitry can be disabled by connecting this pin to VCC.
This pin uses Schmitt trigger input buffers.
TCK N/A Input The clock input to the BST circuitry. Some operations
occur at the rising edge, while others occur at the falling
edge. If the JTAG interface is not required on the board, the
JTAG circuitry can be disabled by connecting this pin to
GND. This pin uses Schmitt trigger input buffers.
TRST N/A Input Active-low input to asynchronously reset the boundary-
scan circuit. The TRST pin is optional according to IEEE
Std. 1149.1. If the JTAG interface is not required on the
board, the JTAG circuitry can be disabled by connecting
this pin to GND . This pin uses Schmitt trigger input buffers.
Altera Corporation 12–1
September 2004
12. Remote System
Configuration with Stratix &
Stratix GX Devices
Introduction Altera® Stratix® and Stratix GX devices are the first programmable logic
devices (PLDs) featuring dedicated support for remote system
configuration. Using r emote system co nfiguration, a Stratix or Strati x GX
device can receive new configuration data from a re mo te source, update
the flash memory content (through enhanced configuration devices or
any other storage device), and then reconfigure itself with the new data.
Like all Altera SRAM-based devic es, Stratix and Stratix GX devices
support standar d confi gu ration modes such as passive serial (PS), fas t
passive para llel (FPP), and pass ive parallel asynchronous (PPA). You can
use the standar d configuratio n modes with r emote syst em configuratio n.
This chapter discusses remote system configuration of Stratix and Stratix
GX devices, and how to interface them with enhanced configuration
devices to enable this capability. This document also explains some
related remote system configuration topics, su ch a s the watchdog timer,
remote system configuration registers, and factory or application
configurations files. The Quartus® II software (version 2.1 and later)
supports remote system configuration.
Remote
Configuration
Operation
Remote system configuration has three major parts:
■The Stratix or Stratix GX device r eceives updated or new data from a
remote source over a network (or through any other sour ce that can
transfer data). You can implement a Nios™ (16-bit ISA) or Nios®II
(32-bit ISA) embedded pr ocessor within either a Stratix or Stratix GX
device or an external processor to control the read and write
functions of configuration files from the remote source to the
memory device.
■The new or updated information is stored into the memory device,
which can be an enhanced configuration device, industry-standard
flash memory device, or any other storage device (see Figure 12–2).
■The Stratix or Stratix GX device updates itself with the new data from
the memory.
Figure 12–1 shows the concept of remote sys tem configura tion in Stratix
and Stratix GX devices.
S52015-3.1
12–2 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Remote Configuration Operation
Figure 12–1. Remote System Configuration with Stratix & Stratix GX Devices
Figure 12–2. Different Options for Remote System Configuration
Development
Location
Stratix or
Stratix GX
Device
Control Module
Memory
Stratix Device Configuration
Network
Data
Data
Data
External
Processor
Stratix or
Stratix GX
Device
Processor
Flash
Enhanced
Configuration
Device
Stratix or
Stratix GX
Device
Enhanced
Configuration
Device
MAX
Device
Flash
Memory
Nios
MAX Device &
Flash Memory
Stratix or
Stratix GX
Device
Processor Nios
Processor
Altera Corporation 12–3
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
Remote System Configuration Modes
Stratix and Stratix GX device remote system configuration has two
modes: r emote configuration mode and loca l configuration mode.
Table 12–1 shows the pin selection settings for each configuration mode.
Remote Configuration Mode
Using remo te configuration mode, you can manage up to seven dif fer ent
application configurations for Strati x and Stratix GX devices. The seven-
configuration-file limit is due to the number of pages that the PGM[] pins
in the Stratix or Stratix GX device and enhanced configuration devices
can select.
1If more than seven files are sent to a system using remote
configuration mode, previous files are overwritten.
Stratix and Stratix GX device s support remote configuration mode for PS,
FPP, and PPA modes. Specify remote configuration mode by setting the
MSEL2 and RUnLU pins to high. (See Table 12–1).
On power-up in r emote configuration mode, the Stratix or Stratix GX
device loads the user-specified f actory configuration file, located in the
default page address 000 in the enha nced configuration d evice. After the
device configures, the r emote configuration cont r ol register points to the
Table 12–1. Standard, Remote & Local Configuration Options Note (1)
RUnLU (2) MSEL[2] (3) MSEL[1..0] System Configuration Mode Configuration Mode
– 0 00 Standard FPP
– 0 01 Standard PPA
– 0 10 Standard PS
1100 Remote FPP
1101 Remote PPA
1110 Remote PS
0 1 00 Local FPP
0 1 01 Local PPA
0 1 10 Local PS
Notes to Table 12–1:
(1) For detailed information on standard PS, FPP, and PPA models, see the Configuring Stratix & Stratix GX Devices
chapter of t he Stratix Device Handbook, Volume 2.
(2) In Stratix and Stratix GX devices, the RUnLU (remote update/local update) pin, selects between local or remote
configuration mode.
(3) The MSEL[2] select mode selects between standard or remot e system configuration mode.
12–4 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Remote Configuration Operation
page address of the applicati on configuration that should be loaded into
the Stratix or Stratix GX device. If an error occurs during user mode of an
application configuration, the device reloads the default factory
configuration page. Figure 12–3 shows a diagram of remote configuration
mode.
Figure 12–3. Remote Configuration Mode
Local Configuration Mode
Local configuration mode— a s impli fied v ersion of remote configur ation
mode—is suitable for systems that load an application imme diately upon
power-up. In this mode you can only use one application configuration,
which you can update either remotely or locally.
In local configuration mode, upon power-up, or when nCONFIG is
asserted, t h e Stratix or St ra tix GX device loads the application
configuration immediatel y. Factory configuration loads only if an error
occurs during the application configuration’s user mode. If you use an
enhanced configuration device, page address 001 is the location for the
application configuration data, and page address 000 is the lo cation for
the factory configuration data.
If the configuration data at page address 001 does not load corre ctly due
to cyclic redundancy code (CRC) failure, or it times-out of the enhanced
configuration device, or the external processor times-out, then the factory
configuration located at the default page (page address 000) loads into
the Stratix or Stratix GX device.
In local configuration mo de (shown in Figure 12–4), the user watchdog
timer is disabled. For more inform ation on the watchdog timer, see
“Watchdog Timer” on page 12–7.
Power Up
Configuration
Error
Errors
Reconfigure
Errors
Reconfigure
Application 7
Configuration
PGM [111]
Factory
Configuration
Page (000)
Application 1
Configuration
PGM [001]
Altera Corporation 12–5
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
Figure 12–4. Local Configuration Mode
In local configuration mode, one application configuration is available to
the device. For remote or local configuration mode selec tion, see
Table 12–1.
Remote System Configuration Components
The following components are used in Stratix and Stratix GX devices to
support rem ote and loc al configuration modes:
■Page mode feature
■Factory configuration
■Application configuration
■Watchdog timer
■Remote update sub-block
■Remote configuration registers
A description of each component follows.
Page Mode Feature
The page mode feature enables Stratix and Stratix GX devices to select a
location to read back data for configuration. The enhanced configuration
device can r e ceive and store up to eigh t dif fer ent configuration fil es (one
factory and seven application files ). Se lection of pages to read from is
performed th rough the PGM[2..0] pins on the Stratix or Stratix GX
device and enhanced configuration devices. These pins in the Stratix or
Stratix GX device can be designated user I/O pins during standard
configuration mode, but in remote system co nfiguration mode, they are
dedicated output pins. Figure 12–5 shows the page mode featur e in
Stratix or Stratix GX dev ic es and enhanced configuration devices.
Power Up or
nCONFIG Assertion
nCONFIG nCONFIG Configuration
Error
Configuration Error
Application
Configuration
PGM[001]
Factory
Configuration
PGM[000]
12–6 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Remote Configuration Operation
Figure 12–5. Page Mode Feature in Stratix or Stratix GX Devices & Enhanced
Configuration Devices
Upon power-up in r emote configuratio n mode, the facto ry configuration
(see description below) sel ec ts the user-specified page add ress through
the Stratix or Stratix GX PGM[2..0] output pins. These pins drive the
PGM[2..0] input pins of the enhanced configuration device and sele ct
the requested page in the memory.
If an intelligent host is us ed instead of an enhanced configuration device,
you should create logic in the intelligent host to support page mode
settings similar to that in enhanced configur ation devices.
Factory Configuration
Factory configuration is the default configuration data setup. In enhanced
configuration devices, t his default page address is 000. Factory
configuration data is written into the me mory device only once by the
system manufacturer and should not be remotely updated or altered. In
remote configuration mode, the factory configuration loads into the
Stratix or Stratix GX device upon power-up.
The factory configuration specifications are as follows:
■Receives new configuration data and writes it to the enhanced
configuration or other memory devices
■Determines the page address for the next application configuration
that should be loaded to the Stratix or Stratix GX device
■Upon an error in the application configuration, the system reverts to
the factory configuration
■Determines the rea son for any application configuration error
■Determines whether to enable or disable the user watchdog timer for
application configurations
Enhanced Configuration
Device
Stratix or
Stratix GX
Device
Page Select
POF 8
POF 1
Stratix 1
Page0
tix7
Altera Corporation 12–7
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
■Determines the user watchdog timer’s settings if the timer is enabled
(remote configuration mode)
■If the user watchdog timer is not rese t after a predetermined amount
of time, it times-out and the system loads the factory configurati on
data back to the Stratix or Stratix GX device
If a system encounters an error while loading application configuration
data, or if the device re-configures due to nCONFIG assertion, the Stratix
or Stratix GX device loads the factory configuration. The remote system
configuration re gister determines the reason for factory r e-configuration.
Based on this information, the factory configuration determines which
application configuration needs to be loaded.
Application Configuration
The application configuration is the configuration data received from the
rem ote source and u p dated into differe nt locations or pages of the
memory storage device (excluding the factory default page).
Watchdog Timer
A watchdog timer is a circuit that determines whether another
mechanism functions properly. The watchdog timer functions like a time-
delay relay that remains in the reset state while an application runs
properly. This action periodically sends a reset command from the
working application to the watchdog timer. Stratix and Stratix GX
devices are equipped with a built-in watchdog timer for remote system
configuration.
A user watchdog timer prevents a faulty application configuration from
indefinitely stalling the Stratix or Stratix GX device. The timer functions
as a counter that c ounts down from an initial value, which is lo aded into
the device from the factory configuration. This is a 29-bit counter, but you
use only the upper 12 bits to set the value for the watchdog timer. You
specify the counter value according to your de sign needs.
The timer begins counting once the Stratix or Stratix GX device goes into
user mode. If the application configuration does not reset the user
watchdog timer after the specified time, the timer times-out. At this point,
the Stratix or Stratix GX device is re-configured by loading the factory
configuration and resetti ng the user watchdog timer.
1The watchdog timer is disabled in local configu ration mode.
12–8 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Remote Configuration Operation
Remote Update Sub-Block
The remote update sub-block is responsible for administrating the remote
configuration feature. This sub-block, which is controlled by a remote
configuration state machine, generates the control signals required to
control different remote configuration registers.
Remote Configuration Registers
Remote configuration registers are a series of registers required to keep
track of page addresses and the cause of configuration errors. Table 12–2
gives descriptions of the registers’ functions. You can control both the
update and shift registers; the status and control registers are controlled
by internal logic, but can be read via the shift register.
Figure 12–6 shows the control, update, shift, and stat us registers and the
data path used to control remote system configuration.
Table 12–2. Remote Configuration Registers
Register Description
Control register This register contains the current page address , the watchdog timer setting, and
one bit specifying if the current configuration is a factory or application
configuration. During a capture in an application configuration, this register is
read into the shift register.
Update register This register contains the same data as the control register, except that it is
updated by the factory configuration. The factory configuration updates the
register with the values to be used in the control register on the next re-
configuration. During capture in a factory configuration, this register is read into
the shift register.
Shift register This register is accessible by the core logic and allows the update, status, and
control registers to be written and sampled by the user logic. The update register
can only be updated by the factory configuration in remote configuration mode.
Status register This register is written into by the remote configuration block on every re-
configuration to record the cause of the re-configuration. This inf ormation is used
by factory configuration to determine the appropriate action following a re-
configuration.
Altera Corporation 12–9
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
Figure 12–6. Remote Configuration Registers & Related Data Path
Table 12–3 describes the user configuration signals that are driven
to/from the dev ice logic array. The remote configuration logic has one
input signal to the device logic array and six output signals from the
device logi c array.
Status Register Control Register
Update Register
Logic
Shift Register
Control Logic
to Reconfig Logic
User
Watchdog
Timer
RU_Dout RU_shftnhld RU_captnupdt RU_Din RU_clk RU_Timer RU_nCONFIG
Device Core
Bit4...Bit10 Bit16...Bit0
Bit0...Bit16
Table 12–3. User Configuration Signals To/From Device Core (Part 1 of 2)
Signal Name To/From Device Core Description
RU_Timer Output from the core to the
remote update block Request from the application to reset the user watchdog
timer with its initial count. A falling edge of this signal
triggers a reset of the user watchdog timer.
RU_nCONFIG Output from the core to the
remote update block When driven low, this signal triggers the device to
reconfigure. If requested by the f actory configuration, the
application configuration specified in the remote update
control register is loaded. If requested by the application
configuration, the factory configuration is loaded.
RU_Clk Output from the core to the
remote update block Clocks the remote configuration shift register so that the
contents of the status and control registers can be read
out, and the contents of update register can be loaded.
The shift register latches data on the rising edge of the
RU_Clk.
12–10 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Remote Configuration Operation
All of the seven device core signals (see Figure 12–6), are enabled for both
remote and local configuration for both factory and application
configuration, except RU_Timer and RU_captnupdt. Figure 12–7 and
Table 12–4 specify the content of control register upon power-on reset
(POR).
The differ ence between local configuration and remote configuration is
how the control register is updated during a re-configuration and which
core signals are enabled.
RU_shftnhld Output from the core to the
remote update block If its value is “1”, the remote configuration shift register
shifts data on the rising edge of RU_Clk. It its value is
“0” and RU_captnupdt is “0”, the shift register updates
the update register. If its value is “0”, and
RU_captnupdt is “1”, the shift register captures the
status register and either the control or update register
(depending on whether the configuration is factory or
application).
RU_captnupdt Output from the core to the
remote update block When RU_captnupdt is at value “1” and
RU_shftnhld is at value”0”, the system specifies that
the remote configuration shift register should be written
with the content of the status register and either the
update register (in a factory configuration) or the control
register (in an application configuration). This shift
register is loaded on the rising edge of RU_Clk. When
RU_captnupdt is at value “0” and RU_shftnhld is at
value”0”, the system specifies that the remote
configuration update register should be written with the
content of the shift register in a factory configuration. The
update register is loaded on the rising edge of RU_Clk.
This pin is enabled only for factory configuration in
remote configuration mode (it is disabled for the
application configuration in remote configuration or for
local configuration modes). If RU_shftnhld is at value
“1”, RU_captnupdt has no function.
RU_Din Output from the core to the
remote update block Data to be written into the remote configuration shift
register on the rising edge of RU_Clk. To load into the
shift register, RU_shftnhld must be asserted.
RU_Dout Input to the core from the remote
update block Output of the remote configuration shift register to be
read by core logic. New data arrives on each rising edge
of RU_Clk.
Table 12–3. User Configuration Signals To/From Device Core (Part 2 of 2)
Signal Name To/From Device Core Description
Altera Corporation 12–11
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
Figure 12–7. Remote System Configuration Control Register
Table 12–4 shows the content of the control register upon POR.
The status register specifies the reason why re-configuration has occurred
and determines if the re-configuration was due to a CRC error, nSTATUS
pulled low due to an err or , the device cor e caused an error, nCONFIG was
reset, or the watchdog timer timed-out. Figure 12–8 and Table 12–5
specify the content of the status register.
Figure 12–8. Remote System Configuration Status Register
Table 12–4. Control Register Contents
Parameter Definition POR Reset Value Comment
AnF Current configuration is factory or
applications 1 bit ‘1’ Applications
1 bit ‘0’ Factory
PGM[2..0] Page mode selection 3 bits ‘001’ Local configuration
3 bits ‘000’ Remote configuration
Wd_en User watchdog timer enable 1 bit ‘0’ –
Wd_timer
[11..0] User watchdog timer time-out value 12 bits ‘0’ High order bits of 29 bit counter
Wd nCONFIG CORE nSTATUS CRC
43210
12–12 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Quartus II Software Support
Table 12–5 shows the content of the status register upon POR.
Quartus II
Software
Support
The Quartus II software supports implementation of both remote and
local configuration modes in your Stratix or Stratix II device. To include
the remote or loc al configuration feature to your design, select remote or
local as the configuration mode under the Device & Pin Options
compiler setting s (prior to compilation). This sel ection reserves the dual-
purpose RUnLU and PGM[2:0] pins for use as dedicated inputs in
remote/local configuration modes.
To set the configuration mode as remote or local, follow these steps (See
Figure 12–9):
1. Open the Device & Pin Options settings window under the
Assignments menu.
2. Select D evice & Pin Options dialog box. The Device & Pin Options
dialog box is displayed.
3. Click the Configuration tab.
4. In the Configuration mode list, select Remote or Local.
The Standar d mode selection disables the remote sy stem configuration
feature. In addition to the mode selection, you can specify the
configuration scheme and configura tion device (if any) used by your
setup.
Table 12–5. Status Register Contents
Parameter Definition POR Reset
Value
CRC (from
configuration) CRC caused re-configuration 1 bit ‘0’
nSTATUS nSTATUS caused re-configuration 1 bit ‘0’
CORE (1) Device core caused re-configuration 1 bit ‘0’
nCONFIG NCONFIG caused re-configuration 1 bit ‘0’
Wd Watchdog Timer caused re-configuration 1 bit ‘0’
Note to Table 12–5:
(1) Core re-configuration enforces the system to load the application configuration
data into the Stratix or Stratix GX device. This occurs after factory configuration
specifies the appropriate application configuration data.
Altera Corporation 12–13
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
Figure 12–9. Device & Pin Options Dialog Box
Additionally, the remote configuratio n mode requ ires you to either
instantiate the altremote_update megafunction or the WYSIWYG
(what-you-see-is-what-you-get) atom into your design. Without this
atom or megafunction, you ar e not be able to access the dedicated re mote
configuration circuitry or registers within the Stratix or Stratix GX device.
See Figure 12–10 for a symbol of the altremote_update megafunction.
The local configuration mode, however, can be enabled with only the
device Configuration Options compiler setting.
12–14 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Quartus II Software Support
Figure 12–10. altremote_update Megafunction Symbol
altremote_update Megafunction
A remote update megaf unction, altremote_update, is pr ovided in the
Quartus II software to provide a memory-like interface to allow for easy
control of the remote update parameters. Tables 12–6 and 12–7 describe
the input and output ports available on the altremote_update
megafunction. Table 12–8 shows the param[2..0] bit setti n gs.
Table 12–6. Input Ports of the altremote_update Megafunction (Part 1 of 2)
Port Name Required Source Description
clock Y Logic Array Clock input to the altremote_update block. All operations are
performed with respects to the rising edge of this clock.
reset Y Logic Array Asynchronous reset, which is used to initialize the remote update
block. To ensure proper operation, the remote update block must be
reset before first accessing the remote update bloc k. This signal is not
affected by the busy signal and will reset the remote update block
ev en if b usy is logic high. This means that if the reset signal is driven
logic high during writing of a parameter, the parameter will not be
properly written to the remote update block.
reconfig Y Logic Array When driven logic high, reconfiguration of the de vice is initiated using
the current parameter settings in the remote update block. If busy is
asserted, this signal is ignored. This is to ensure all parameters are
completely written before reconfiguration begins.
reset_timer N Logic Array This signal is required if you are using the watchdog timer feature. A
logic high resets the internal watchdog timer. This signal is not
affected by the busy signal and can reset the timer even when the
remote update block is busy. If this port is left connected, the default
value is 0.
Altera Corporation 12–15
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
read_param N Logic Array Once read_param is sampled as a logic high, the busy signal is
asserted. While the parameter is being read, the busy signal remains
asserted, and inputs on param[] are ignored. Once the busy signal
is deactivated, the next parameter can be read. If this port is left
unconnected, the default value is 0.
write_param N Logic Array This signal is required if you intend on writing parameters to the
remote update block. When driv en logic high, the parameter specified
on the param[] port should be written to the remote update block
with the value on data_in[]. The number of valid bits on
data_in[] is dependent on the parameter type. This signal is
sampled on the rising edge of clock and should only be asserted for
one clock cycle to prevent the parameter from being re-read on
subsequent clock cycles. Once write_param is sampled as a logic
high, the busy signal is asserted. While the parameter is being
written, the busy signal remains asserted, and inputs on param[]
and data_in[] are ignored. Once the busy signal is deactivated,
the next parameter can be written. This signal is only valid when the
Current_Configuration parameter is factory since parameters
cannot be written in application configurations. If this port is left
unconnected, the default value is 0.
param[2..0] N Logic Array 3-bit bus that selects which parameter should be read or written. If this
port is left unconnected, the default value is 0.
data_in[11..0] N Logic Array This signal is required if you intend on writing parameters to the
remote update block 12-bit bus used when writing parameters, which
specifies the parameter value. The parameter value is requested
using the param[] input and by driving the write_param signal
logic high, at which point the busy signal goes logic high and the v alue
of the parameter is captured from this bus . For some par ameters, not
all 12-bits will be used in which case only the least significant bits will
be used. This port is ignored if the Current_Configuration
parameter is set to an application configuration since writing of
parameters is only allowed in the factory configuration. If this port is
left unconnected, the default values is 0.
Note to Table 12–6:
(1) Logic array source means that you can drive the port from internal logic or any general-purpose I/O pin.
Table 12–6. Input Ports of the altremote_update Megafunction (Part 2 of 2)
Port Name Required Source Description
12–16 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Quartus II Software Support
Table 12–7. Output Ports of the altremote_update Megafunction
Port Name Required Destination Description
busy Y Logic Array When this signal is a logic high, the remote update block is busy
either reading or writing a parameter . When the remote update b lock
is busy, it ignores its data_in[], param[], and reconfig
inputs. This signal will go high when read_param or
write_param is asserted and will remain asserted until the
operation is complete.
pgm_out[2..0] Y PGM[2..0]
pins 3-bit bus that specifies the page pointer of the configuration data to
be loaded when the device is reconfigured. This port must be
connected to the PGM[] output pins, which should be connected to
the external configuration device
data_out[11..0] N Logic Array 12-bit bus used when reading parameters, which reads out the
parameter value. The parameter value is requested using the
param[] input and by driving the read_param signal logic high,
at which point the busy signal will go logic high. When the busy signal
goes low, the value of the parameter will be driven out on this bus.
The data_out[] port is only valid after a read_param has been
issued and once the busy signal is de-asserted. At any other time, its
output values are invalid. For example, even though the
data_out[] port may toggle during a writing of a parameter , these
values are not a valid representation of what was actually written to
the remote update block. F or some parameters, not all 12-bits will be
used in which case only the least significant bits will be used.
Note to Table 12–7:
(1) Logic array destination means that you can drive the port to internal logic or any general-purpose I/O pin.
Table 12–8. Parameter Settings for the altremote_update Megafunction (Part 1 of 2)
Selected
Parameter param[2..0]
bit setting
width of
parameter
value
POR Reset
Value Description
Status
Register
Contents
000 5 5 bit '0 Specifies the reason for re-configuration,
which could be caused by a CRC error during
configuration, nSTATUS being pulled low due
to an error, the device core caused an error,
nCONFIG pulled low, or the watchdog timer
timed-out. This parameter can only be read.
Watchdog
Timeout Value 010 12 12 bits '0 User watchdog timer time-out v alue. Writing of
this parameter is only allowed when in the
factory configuration.
Watchdog
Enable 011 1 1 bit '0 User watchdog timer enable. Writing of this
parameter is only allowed when in the factory
configuration
Altera Corporation 12–17
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
Remote Update WYSIWYG ATOM
An alternative to using the altremote_update megafunction is to
directly instantiate the remote update WYSIWYG atom. This atom should
be included in the factory configuration and any application
configuration image to access the remote configuration shift registers.
When implementing the atom, you should consider following:
1. Only one atom can be used in the circuit; more than one gives a
no-fit.
2. All signals for the ce ll must be c onnected. T he clock port ( CLK) must
be connected to a live cell. The others can be constant VCC or GND.
3. The pgmout port must be connected and must feed PGM[2.0]
output pins (it cannot be connected to anything else but output
pins).
4. The Quartus II software reserves RUnLU as an input pin, and you
must connect it to VCC.
Page select 100 3 3 bit '001' - Local
configuration Page mode selection. Writing of this parameter
is only allowed when in the factory
configuration.
3 bit '000' -
Remote
configuration
Current
configuration
(AnF)
101 1 1 bit '0' - Factory Specifies whether the current configuration is
factory or and application configuration. This
parameter can only be read.
1 bit '1' -
Application
Illegal values 001
110
111
Table 12–8. Parameter Settings for the altremote_update Megafunction (Part 2 of 2)
Selected
Parameter param[2..0]
bit setting
width of
parameter
value
POR Reset
Value Description
12–18 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Quartus II Software Support
The Stratix and Stratix GX remote update atom ports are:
Stratix_rublock <rublock_name>
(.clk(<clock source>),
.shiftnld(<shiftn ld source>),
.captnupdt(<shiftnld source>),
.regin(<regin input source from the core>),
.rsttimer(<input signal to reset the watchdog timer>),
.config(<input signal to in iti ate con fi g ura t ion>),
.regout(<data output destination to core>),
.pgmout(<program output destinations to pins>)
Table 12–9 shows the remote update block input and output port names
and descriptions.
Table 12–9. Remote Update Block Input & Output Ports
Ports Definition
<rublock_name> The unique identifier for the instance. This identifier name can be anything as
long as it is legal for the given description language (i.e., Verilog, VHDL, AHDL,
etc.). This field is required.
.clk(<clock source>) Designates the clock input of this cell. All operation is with respect to the rising
edge of this clock. This field is required.
.shiftnld(<shiftnld source>) An input into the remote configuration block. When .shiftnld = 1, the data shifts
from the internal shift registers to the regout port at each rising edge of clk,
and the data also shifts into the internal shift registers from regin port. This field
is required.
.captnupdt(<shiftnld
source>) An input into the remote configuration block. This controls the protocol of when
to read the configuration mode or when to write into the registers that control the
configuration. This field is required.
.regin(<regin input source
from the core>)An input into the configuration block for all data loading into the core. The data
shifts into the internal registers at the rising edge of clk. This field is required.
.rsttimer(<input signal to
reset the watchdog timer>)An input into the watchdog timer of the remote update block. When this is high, it
resets the watchdog timer. This field is required.
.config(<input signal to
initiate configuration>)An input into the configuration section of the remote update block. When this
signal goes high, the part initiates a re-configuration. This field is required.
.regout(<data output
destination to core>) A 1-bit output, which is the output of the internal shift register , and updated ev ery
rising edge of clk. The data coming out depends on the control signals. This
field is required.
.pgmout(<program output
destinations to pins>)A 3-bit bus . It should alw ays be connected only to output pins (not bidir pins).
This bus gives the page address (000 to 111) of the configuration data to be
loaded when the device is getting configured. This field is required.
Altera Corporation 12–19
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
fFor more information on the control signals for the remote block, see
Table 12–3 on page 12–9.
Using Enhanced
Configuration
Devices
This section describes remote system configuration of Stratix and
Stratix GX devices with the Nios embedded processor using enhanced
configuration devices. Enhanced configuration devices are composed of
a standard flash memory and a controller. The flash memory stores
configuration data, and the controller r eads and writes to the flash
memory.
In remote system configuration, only PS and FPP modes are supported
using an enhanced configuration device. A Stratix or Stratix GX device
running a Nios embedded processor can receive data from a r emote
source through a network or any other appropriate me dia. A specific
page of the enhanced configuration device stores the received data.
This scheme uses the page mode option in Stratix and Strati GX devices.
Up to eight pages can be store d in e a ch enhanced configuration dev ic e,
each of which can store a configuration file.
In enhanced configuration devices, a page is a section of the flash
memory space. Its boundary is determined by the Quartus II software
(the page size is programmable). In the software, you can specify which
configuration file should be stored in which page within the flash
memory. To access the configuration file on each page, set the three input
pins (PGM[2..0]), which provide acces s to all ei ght pages. Because the
PGM[2..0] pins of an enhanced configuration device connect to the
same pins of the Stratix or Stratix GX device, the Stratix or Stratix GX
device selects one of the eight memory pages as a target location to read
from. Figure 12–11 shows the allocation of different pages in the
enhanced configuration device.
fFor more information on enhanced configuration devices, see the
Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet and the
Altera Enhanced Configuration Devices chapter.
12–20 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Using Enhanced Configuration Devices
Figure 12–11. Memory Map in Enhanced Configuration Device
When the Stratix or Stra tix GX device powers-up in re mote configuration
mode, the devices loads configuration data located at page address 000.
You should always load the factory default configuration data at this
location and make sure this information is not altered.
The factory configuration contains information to determine the next
application configuration to load into the Stratix or Stratix GX device.
When the Stratix or Stratix GX device successfully loads the application
configuration fr om the page selected by the PGM[2..0] pins, it enters
user mode.
In user mode, the Nios embedded processor (or any other logic) assists
the Stratix or Stratix GX device in detecting remote system configuration
information. In r e mote system configuration, the Nios embed ded
proce ss or receives the incomi ng data from the remote source via the
network, writes it to the ECP16 enhanced configuratio n device, and then
initiates loading of the factory configuration into the Stratix or Stratix GX
device. Factory configuration reads the remote configuration status
register and determines the appropriate application configuration to load
into the Stratix or Stra tix GX device. Figure 12–12 shows the remote
system configuration.
Unused Memory
Processor
Space
Enhanced Configuration Devices
Page7
Configuration
Space
Page1
Page0
Option Bits
Boot & Parameter Block
Altera Corporation 12–21
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
Figure 12–12. Remote System Configuration Using Enhanced Configuration Devices
The user watchdog timer in Stratix and Stratix GX devices ensur es that an
application configuration has loaded su cc essfully and checks if the
application configuration is operating correctly in user mode. The
watchdog timer must be continually reset by the user logic. If an error
occurs while the application configuration loads, or if the watchdog timer
times-out during user mode, the factory conf iguration is reloaded to
prevent the system from halting in an erroneous state. Figure 12–3 on
page 12–4 illustrates the r em ote configuration mode.
Upon power-up in local configuration scheme, the application
configuration at page 001 (PGM[001] of the enhanced configuration
device) loads into the Stratix or Stratix GX device. This application can be
remotely or locally updated. If an erro r occurs during loading of the
configuration data, the factory configuration loads automatically (see
Figure 12–4 on page 12–5). The rest is identical to remote configuration
mode.
Local Update Programming File Generation
This section describes the programming file generation process for
performing remote system upgrades. The Quartus II convert
programming files (CPF) utility generates the initial and partial
programming files for configuration memory within the enhanced
configuration devices.
The two pages that local configuration mode uses are a factory
configuration stored at page 000, and an application configuration stored
at page 001. The factory configuration cannot be updated after initial
production pr ogramming. However , the application configuration can be
erased and reprogrammed after initial system deployment.
Remote Source
Application
Configuration Data
(Network)
Stratix or
Stratix GX Device
Nios
Processor
Configuration
Control Signals
Application/Factory
Configuration Data
PGM[2..0]
Application
Configuration Data
Enhanced
Configuration Device
Application Data 1
Application Data 7
Factory Data Selecting Next
Application from
Factory Data
Watchdog
Circuitry
12–22 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Using Enhanced Configuration Devices
In local updat e mode, you wo uld first cr eate the initial pr ogramm ing file
with the factory configuration image and a version of the application
configuration. Subseque ntly, you can generate partial programmi ng files
to update the application configuration (stored in page 001). Quartus II
CPF can create partial programming files in .hex (Hexadecimal file), JAM,
.jbc (JAM Byte-Code File), and POF form ats.
In addition to the two configuration pa ges, user data or processor code
can also be pre-programmed in the bottom boot and main data areas of
the enhanced configuration device memory. The CPF utility accepts a
HEX input file for the bottom and main data ar eas, and includes this data
in the POF output file. However, this is only supported for initial
programming file generation. Partial programming file generation for
updating user HEX data is not supported, but can be performed using the
enhanced configuration device external flash interface.
Initial Programming File Generation
The initial programming file includes configuration data for both factory
and application configuration pages. The enhanced configuration devic e
option’s bits are always located betwe en byte addresses 0x00010000
and 0x0001003F. Also, page 0 always starts at 0x00010040 while its
end addres s is dependent on the size of the factory configuration data.
The two memory allocation options that exist for the application
configuration are auto addressing and block addressing. In auto
addressing mode, Quartus II automatica lly all ocates memory for the
application configuration. Al l the configuration memory sec tors that are
not used by the page 0 f actory configuration ar e allocate d for page 1. The
memory allocated is maximized to allow future versions of the
application configuration to grow and have bigger configuration files
(when the compr ession feature is enabled). Processor or user da ta storage
(HEX input file) is only supported by the bottom boot area in auto
addressing mode.
The following steps and screen shot (see Figure 12–13) describe initial
programming file generation with auto addressing mode.
1. Open the Convert Programming Files window from the File menu.
2. Select Programmer Object File (*.pof) from the drop-down list
titled Programming File Type.
Altera Corporation 12–23
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
3. Select the enhanced configuration device used (EPC4, EPC8,
EPC16), and the mode used (1-bit Pass ive Serial or Fast Passive
Parallel). Only during the initial programming file generation can
you specify the Options, Configuration Device, or Mode settings.
While generating the partial programming file, all of these settings
are grayed out and inaccessible.
4. In the Input files to convert box, highlight SOF Data at Page 0 and
click Add File. Select input SOF file(s) for this configuration page
and insert them.
5. Repeat Step 4 for the Page 1 application configuration pa ge.
6. Check the Memory Map File box to generate a memory map output
file that specifies the start/end add resses of each co nfiguration page
and user data blocks.
7. Save the CPF setup (optionally), by selecting Save Conversion
Setup… and specifying a name for the .cof output file.
8. Click OK to generate initial programming and memory map files.
12–24 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Using Enhanced Configuration Devices
Figure 12–13. CPF Setup for Initial Programming File (Auto Addressing)
A sample memory map output file for the preceding setup is shown
below. Configuration option bits and page 0 data occupy main flash
sectors 0 throu gh 4. Se e the Sharp LHF16J06 Flash memory used in EPC16
devices Data Sheet at www.altera.com to correlate me mory addresses to
the EPC16 flash sectors. In auto addressi ng m o de, page 1 allocates all
unused flash sectors. For this example, this unused area includes main
sectors 5 through 30, and all of the bottom boot sectors. While this large
portion of memory is allocated for page 1, the real application
configuration data is top justified within this region with filler 1'b1 bits in
lower memory addresses. Notice that the page 1 configuration data
Altera Corporation 12–25
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
wraps around the top of the memory and fills up the bottom boot area.
The wrap around does not occur if the bottom boot area is used for
processor/user HEX data file storage.
The block addressing mode allows better control of flash memory
allocation. You can allocate a specific flash memory region for each
application configuration page. This allocation is done by specifying a
block starting and block ending address. While selecting the size of the
region, you should account for growth in compressed configuration
bitstr eam sizes due to design change s and additions. In local update
mode, all configuration data is top justified within this allotted memory.
In other words, the last byte of config uration data is stored such that it
coincides with the highest byte address location within the allotted space.
Lower unused memory address locations within the allotted r egio n are
filled with 1's. These filler bits are transmitted during a configuration
cycle using page 1, but are ignored by the Stratix device. The memory
map output file provid es the exact byte address wher e real configuration
data for page 1 begins. Note that any partial update of page 1 should erase
all allotted flash sectors before storing new configuration data.
In the block addressing mode, HEX input files can be optionally added to
the bottom boot and main flash data areas (one HEX file per area is
allowed). The HEX file can be stored wi th relative addr essing or absolut e
addressing. For more information on relative and absolute addressing,
see the Using Altera Enhanced Configuration Devices chapter of the
Configuration Handbo ok.
Figures 12–14 and 12–15, and the following steps illustrate generating an
initial programming file with block addressing for local update mode.
This example also illustrates preloading user HEX data into bottom boot
and main flash sectors.
1. Open the Convert Programming Files window from the File menu.
2. Select Programmer Object File (.pof) from the dr op-down list titled
Programming file type.
Block Start Address End Address
OPTION BITS 0x00010000 0x0001003F
PAGE 0 0x00010040 0x00054CC8
PAGE 1 0x001CB372 0x0000FFFD wrapped around
12–26 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Using Enhanced Configuration Devices
3. Select the enhanced configuration device (E PC4, EPC8 , EPC16), and
the mode used (1-bit Passive Serial or Fast Passive Parallel). Only
during the initial programming file generation can you specify the
Options, Configuration devi ce, or Mode settings. While generating
the partial programming file, all of these settings ar e grayed out and
inaccessible.
4. In the Input files to convert box, highlight SOF Data at Page 0 and
click Add File. Select input SOF file(s) for this configuration page
and insert them.
5. Repeat Step 4 for the Page 1 application configuration page.
6. For enabling block addressing, select the SOF Data entry for Page 1,
and click Properties. This opens the SOF Data Properties dialog
box (see Figure 12–15).
7. Pick Block from the Address Mode drop down selection, and enter
32-bit Hexadecimal byt e address for block Starting Address and
Ending Address. Note that for partial programming support, the
block start and end addresses should be aligned to a flash sector
boundary. This prevents two configuration pages from overlapping
within the same flash boundary. See the flash memory datasheet for
data sector boundary information. Click OK to save SOF data
properties.
8. Check the Memory Map File box to generate a memory map output
file that specifies the start/end add resses of each co nfiguration page
and user data blocks.
9. Save the CPF setup (optionally), by selecting Save Conversion
Setup… and specifying a name for the COF output file.
10. Click OK to generate initial programming and memory map files.
Altera Corporation 12–27
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
Figure 12–14. CPF Setup for Initial Programm ing File Generation (Block Addressing)
12–28 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Using Enhanced Configuration Devices
Figure 12–15. Specifying Block Addresses for Application Configuration
A sample memory map output file for the preceding example is sh own
below. Note that the allocated memory for page 1 is between
0x00080000 and 0x001EFFFF, while the actual region used by the
current a pplication configuration bitstr eam is between 0x001AB36C and
0x001EFFF7. The configuratio n data is top justified withi n the allocated
SOF data region.
Also note that the HEX data stored in the main data area uses absolute
addressing. If relative addressing were to be used, the ma in data contents
would be justified with the top (higher addr ess locations) of the memory.
Block Start Address End Address
BOTTOM BOOT 0x00000000 0x000001FF
OPTION BITS 0x00010000 0x0001003F
PAGE 0 0x00010040 0x00054CC8
PAGE 1 0x001AB36C 0x001EFFF7
TOP BOOT/MAIN 0x001F0000 0x001F01FF
Altera Corporation 12–29
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
The initial programming file (POF) can be converted to an Intel
Hexadecimal format file (*.HEXOUT) using the Quartus II CPF utility.
See Figure 12–16.
Figure 12–16. Converting POF Programming File to Intel HEX Format
Partial Programming File Generation
The enhanced Quartus II CPF utility allows an existing application
configuration page to be replaced with new data. Partial programming
files are generated to perform such configuration data updates.
In order to generate a partial pr ogramming file, you have to input the
initial programming file (POF) and new configuration data (SOF) to the
Quartus II CPF utility. In addition, you have to specify the addre ssing
mode (auto or manual) that was used during initial POF creation. And if
12–30 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Using Enhanced Configuration Devices
block addressing was used, you should specify the block start and end
addr ess es . With this information, Quartus II ensures that the partial
programming file only updates the flash region containing the
application configuration. The factory configuration (page 0) and
configuration option bits are left unaltered during this pr ocess.
Figure 12–17 and the following step s illustrate generation of a partial
programming file:
1. Open the Convert Programming Files window from the File menu.
2. Select Programmer Object File for Local Update (.pof) from the
drop-down list titled Programming file type, and specify an output
File name.
3. In the Input files to convert box, highlight POF Data and click Add
File. Select the initial pr ogramming POF file for this design and
insert it.
4. In the Input files to convert box, highlight SOF Data and click Add
File. Select the new application confi guration bitstream (SOF) and
insert it.
5. When using block addressing, select the SOF Data entry for Page 1,
and click Properties. This opens the SOF Data Properties dialog
box (see Figure 12–18).
6. Pick Block from the Address Mode drop down selection, and enter
32-bit Hexadecimal byt e address for block Starting Address and
Ending Address. These addresses should be identical to those used
to generate the initial pr ogramming file. Click OK to save SOF data
properties.
7. Check the Memory Map File box to generate a memory map output
file that specifies the start /end address es of the new application
configuration data in page 1.
8. Pick a local update difference file from the Remote/Local Update
Difference File drop-down menu. You can select between an Intel
HEX, JAM, JBC, and POF out p ut file types. The output file name is
the same as the POF output file name with a _dif suffix.
9. Save the CPF setup (optionally), by selecting Save Conversion
Setup… and specifying a name for the COF output file.
10. Click OK to generate initial programming and memory map files.
Altera Corporation 12–31
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
Figure 12–17. Local Update Partial Programming File Generation
12–32 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Using Enhanced Configuration Devices
Figure 12–18. Specifying Block Addresses for Application Configuration
Remote Update Programming File Generation
This section describes the programming file generation process for
performing remote system upgrades. The Quartus II CPF utility
generates the initial and partial programming files for configuration
memory within the enhanced configuration devices.
Remote configuration mode uses a factory configuration stored at page 0,
and up to seven application configurations stored at pages 1 through 7.
The factory configuration cannot be updated after initial production
programming. However, the most recent application configuration can
be erased and reprogrammed after initial system deployment.
Alternatively, a new application configuration can be added provided
adequate configuration memory availability.
In remote update mode, you would first create the initial programming
file with the factory configuration image and the application
configuration(s). Subsequently, you can generate partial programming
files to update the most recent application configuration or add a new
application configuration. Quartus II CPF can create partial
programming files in HEX, JAM, JBC, and POF formats.
In addition to the configuration pages, user data or processor code can
also be pre-programmed in the bottom boot and main data areas of the
enhanced configuration device memory. The CPF utility accepts a HEX
input file for the bottom and main data areas, and includes this data in the
Altera Corporation 12–33
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
POF output file. However , this is only supported for initial programming
file generation. Partial programming file generation for updating user
HEX data is not supported, but can be performed using the enhanced
configuration device ext ernal flash interface.
Initial Programming File Generation
The initial programming file includes configuration data for both factory
and application configuration pages. The enhanced configuration devic e
option’s bits are always located betwe en byte addresses 0x00010000
and 0x0001003F. Also, page 0 always starts at 0x00010040 while its
end addres s is dependent on the size of the factory configuration data.
Two memory allocation options exist for application configurations: auto
addressing and block addressing. In auto addressing mode, Quartus II
packs all application configur ations as close together as possi ble. This
maximizes the number of application configurations that can be stored in
memory. However, when auto addressing is used you cannot update
existing application configurations. Only new application configurations
can be added to the memory.
The following steps and screen shot (see Figure 12–19) describe initial
programming file generation with auto addressing mode.
1. Open the Convert Programming Files window from the File menu.
2. Select Programmer Object File (*.pof) from the drop-down list
titled Programming file type.
3. Select the enhanced configuration device used (EPC4, EPC8,
EPC16), and the mode used (1-bit Pass ive Serial or Fast Passive
Parallel). Only during the initial programming file generation can
you specify the Options, Configuration device, or Mode settings.
While generating the partial programming file, all of these settings
are grayed out and inaccessible.
4. In the Input files to convert box, highligh t SOF Data at Page 0 and
click Add File. Select input SOF file(s) for this configuration page
and insert them.
5. Repeat Step 4 for all application configurations (up to 7 maximum).
6. Check the Memory Map File box to generate a memory map output
file that specifies the start/end add resses of each co nfiguration page
and user data blocks.
12–34 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Using Enhanced Configuration Devices
7. Save the CPF setup (optionally), by selecting Save Conversion
Setup… and specifying a name for the COF output file.
8. Click OK to generate initial programming and memory map files.
Figure 12–19. CPF Setup for Initial Programm ing File Generation (Auto Add ressing)
Altera Corporation 12–35
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
A sample memory map output file for the preceding setup is shown
below. Notice all configuration pages ar e packed such that two pages can
share a flash data sector. This disallows partial programming of
application configurations in auto addres sing mod e.
fSee the Sharp LHF16J06 Data Sheet Flash memory used in EPC16 devices at
www.altera.com to correlate memory addresses to the EPC16 flash
sectors.
The block addressing mode allows better control of flash memory
allocation. You can allocate a specific flash memory region for each
application configuration page. This allocation is done by specifying a
block starting and block ending address. While selecting the size of the
region, you should account for growth in compressed configuration
bitstr eam sizes due to design change s and additions. In remote update
mode, all configuration data is top justified within this allotted memory.
In other words, the last byte of config uration data is stored such that it
coincides with the highest byte address location within the allotted space.
Lower unused memory address locations within the allotted r egio n are
filled with 1's. These filler bits are transmitted during the application
configuration cycle, but are ignor ed by the Stratix dev ic e. The memory
map output file provides the exact byte addre ss where real application
configuration data for each page begins. Note that any partial update of
the most recent application configuration should erase all allotted flash
sectors for that page befor e storing new configuration data.
In the block addressing mode, HEX input files can be optionally added to
the bottom boot and main flash data areas (one HEX file per area is
allowed). The HEX file can be stored wi th relative addr essing or absolut e
addressing. For more information on relative and absolute addressing,
see the Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
chapter of the Configuration Handbook, Volume 2.
Figures 12–20 and 12–21, and the following steps illustrate generating an
initial pr ogra mming f ile wit h blo ck addressing for remote u pda te mod e.
This example also illustrates preloading user HEX data into bottom boot
and main flash sectors.
1. Open the Convert Programming Files window from the File menu.
Block Start Address End Address
OPTION BITS 0x00010000 0x0001003F
PAGE 0 0x00010040 0x00054EFA
PAGE 1 0x00054EFC 0x00099DB6
PAGE 2 0x00099DB8 0x000DEC72
12–36 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Using Enhanced Configuration Devices
2. Select Programmer Object File (*.pof) from the drop-down list
titled Programming file type.
3. Select the enhanced configuration device used (EPC4, EPC8,
EPC16), and the mode used (1-bit Pass ive Serial or Fast Passive
Parallel). Only during the initial programming file generation can
you specify the Options, Configuration device, or Mode settings.
While generating the partial programming file, all of these settings
are grayed out and inaccessible.
4. In the Input files to convert box, highlight SOF Data at Page 0 and
click Add File. Select input SOF file(s) for this configuration page
and insert them.
5. Repeat Step 4 for all the application configuration pages (pages 1
and 2 in this example).
6. For enabling block addressing, select the SOF Data entry for Page 1,
and click Properties. This opens the SOF Data Properties dialog
box (see Figure 12–21).
7. Pick Block from the Address Mode drop down selection, and enter
32-bit Hexadecimal byt e address for block Starting Address and
Ending Address. Note that for partial programming support, the
block start and end addresses should be aligned to a flash sector
boundary. This prevents two configuration pages from overlapping
within the same flash boundary. See the flash memory datasheet for
data sector boundary information. Click OK to save SOF data
properties.
8. Check the Memory Map File box to generate a memory map output
file that specifies the start/end add resses of each co nfiguration page
and user data blocks.
9. Save the CPF setup (optionally), by selecting Save Conversion
Setup… and specifying a name for the COF output file.
10. Click OK to generate initial programming and memory map files.
Altera Corporation 12–37
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
Figure 12–20. CPF Setup for Initial Programm ing File Generation (Block Addressing)
12–38 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Using Enhanced Configuration Devices
Figure 12–21. Specifying Block Addresses for an Application Configuration
A sample memory map output file for the preceding example is sh own
below. Note that the allocated memory for page 1 is between
0x00070000 and 0x000BFFFF, while the actual region used by the
current a pplication configuration bitstr eam is between 0x0007B144 and
0x000BFFFF. The configuration data is top justified wi thin the allocated
SOF data region. Similarly, the allocated memory for page 2 is between
0x000D0000 and 0x0012FFFF, while the actual region used by the
application configuration is between 0x000EB13E and 0x0012FFF9.
Also note that the HEX data stored in the main data area uses absolute
addressing. If relative addressing were to be used, the ma in data contents
would be justified with the top (higher addr ess locations) of the memory.
The initial POF can be converted to an Intel Hexadeci mal format file
(*.HEXOUT) using the Quartus II CPF utility. See Figure 12–22.
Block Start Address End Address
BOTTOM BOOT 0x00000000 0x000001FF
OPTION BITS 0x00010000 0x0001003F
PAGE 0 0x00010040 0x00054EFA
PAGE 1 0x0007B144 0x000BFFFF
PAGE 2 0x000EB13E 0x0012FFF9
TOP BOOT/MAIN 0x001F0000 0x001F01FF
Altera Corporation 12–39
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
Figure 12–22. Converting POF Programming File to Intel HEX Format
Partial Programming File Generation
In remote update mode, the Quartus II CPF utility allows an existing
application configuration page to be replaced with new data, or a new
application configuration to be added. Partial programming files are
generated to perform such configuration data updates.
In order to generate a partial pr ogramming file, you have to input the
initial POF and ne w configuration da ta (SOF) to the Quartus II CPF
utility. In addition, you have to specify the addressing mode (auto or
manual) that was used during initial POF creation. And if block
addr ess ing was used, you should spec ify the block start and end
12–40 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Using Enhanced Configuration Devices
addresses. With this information, Quartus II ensures that the partial POF
only updates the flash region containing the application configuration.
The factory configuration (page 0) and configurat ion option bits are left
unaltered during this process. The only exception is whe n a new
application configuration is added, the configu r ation options bits ar e
updated to include start/end addresses for the new page. All existi ng
page addresses and other configuration options bits remain unchanged.
Figure 12–23 and the following step s illustrate generation of a partial
programm ing file to replace the most recent applica tion configuration. In
this example, the initial programmi ng file contained one factory and two
application configurations. Hence, the page 2 application configuration is
being updated with new data.
1. Open the Convert Programming Files window from the File menu.
2. Select Programmer Object File for Remote Update (*.pof) from the
drop-down list titled Programming file type, and specify an output
file name.
3. In the Input files to convert box, highlight POF Data and click Add
File. Select the initial pr ogramming POF file for this design and
insert it.
4. In the Input files to convert box, highlight SOF Data and click Add
File. Select the new application configuration bitstream (SOF) and
insert it.
5. When using block addressing, select the SOF Data entry for Page 2,
and click Properties. This opens the SOF Data Properties dialog
box (see Figure 12–24 on page 12–42).
6. Pick Block from the Address Mode drop down selection, and enter
32-bit Hexadecimal byt e address for block Starting Address and
Ending Address. These addresses should be identical to those used
to generate the initial pr ogramming file. Click OK to save SOF data
properties.
7. Check the Memory Map File box to generate a memory map output
file that specifies the start /end address es of the new application
configuration data in page 1.
8. Pick a remote update difference file from the Remote/Loc al Update
Difference File drop-down menu. You can select between an Intel
HEX, JAM, JBC, and POF out p ut file types. The output file name is
the same as the POF output file name with a _dif suffix.
Altera Corporation 12–41
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
9. Save the CPF setup (optionally), by selecting Save Conversion
Setup… and specifying a name for the COF output file.
10. Click OK to generate initial programming and memory map files.
Figure 12–23. Remote Update Partial Programming File Generation
12–42 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Combining MAX Devices & Flash Memory
Figure 12–24. Specifying Block Addresses for Application Configuration
For adding a new application co nfiguration, follow the steps listed above
with one modification. In Step 5, select SOF Data and click on Properties.
In the SOF Data Properties dialog box, select a new page (for example,
page 3) and specify the addressing mode information. Continue with
steps 7 through 10. When a new page is added, the memory map output
file lists the start/end addresses for this page. A sample is shown below:
Combining MAX
Devices & Flash
Memory
This section describes remote system configuration with the Stratix or
Stratix GX device and the Nios embedded processor , using a combination
of MAX® devices and flash memory.
You can use MAX 3000 or MAX 7000 devices and an industry-standard
flash memory device instead of enhanc ed configuration devices. In thi s
scheme, flash memory stores configu ration data, and the MAX device
contro ls reading and writing to the flash memory, keeping track of
address locations.
The MAX device determines which address location and at what length
to store configuration data in flash memory. The Nios embedded
processor, running in the Stratix or Stratix GX device, receives the
Block Start Address End Address
OPTION BITS 0x00010000 0x0001003F
PAGE 3 0x0012FFFA 0x00174EB4
Altera Corporation 12–43
September 2004 Stratix Device Handbook, Volume 2
Remote System Configuration with Stratix & Stratix GX Devices
incoming data from the remote source and writes it to the address
location in flash memory. The Nios embedd ed processor init iates loading
of factory configuration into the Stratix or Stratix GX device. Figure 12–25
shows remote system confi g uration using a MAX device and flash
memory combination.
Figure 12–25. Remote System Configuration Using a MAX Device & Flash Memory
You can use both remote and local configuration modes in this scheme.
You should specify a default page for factory configuration and make
sure it is not altered or remove d at any time. In r emote system
configuration mode, PS, FPP, and PPA modes are supported when
configuring with MAX and flash devices.
Using an
External
Processor
This section de scribes remote sys tem configuration with Stratix or Stratix
GX devices and the Nios embedded processor, using an external
processor and flash memory devices.
In this scheme, the external processor and flash memory device replace
the enhanced configuration device. Flash memory stores configuration
data, and the proce ssor controls r eading and writing to the flash memory
and also keeps track of the address location. This type of remote system
configuration supports PS, FPP, and PPA modes.
The processor determines at which address which length to store the
configuration data in flash memory. The Nios embedded processor
receives the incoming data from a remote source and writes it to the
address location in the flash memory, and then initiates loading of factory
Remote Source
Application
Configuration Data
Stratix or
Stratix GX Device
MAX Device
MAX & Flash Memory
Nios
Processor
Application
Configuration Data
Configuration
Control Signals
Application/Factory
Configuration Data
Flash Memory
Application Data 1
Application Data 7
Factory Data Selecting Next
Application from
Factory Data
Watchdog
Circuitry
12–44 Altera Corporation
Stratix Device Handbook, Volume 2 September 2004
Conclusion
configuration data into the Stratix or Stratix GX device. Figure 12–26
shows the remote system configuration using a Nios embedded
processor and flash memory.
You can use both remote and local configuration modes in this scheme.
You should specify a default page for factory configuration and make
sure it is not alte red or removed at any time.
Figure 12–26. Remote System Configuration Using External Processor & Flash Memory
Conclusion Stratix and Stratix GX devices are the first PLDs with dedicated support
for remo te system configu ration. By allowing re al-time system upgrades
from a remote source, you can use Stratix and Stratix GX devices in a
variety of applicatio ns that require automatic configuration updates.
With the built-in watchdog timer circuitry, Stratix and Stratix GX devices
avoid incorrect or erroneous states. Using Stratix and Stratix GX devices
with remote system configu ration enhances design flexibility and
reduces time to market.
Remote Source
Application
Configuration Data
Stratix or
Stratix GX Device
External Processor
External Processor
& Flash Memory
Nios
Processor
Application
Configuration Data
Configuration
Control Signals
Application/Factory
Configuration Data
Flash Memory
Application Data 1
Application Data 7
Factory Data Selecting Next
Application from
Factory Data
Watchdog
Circuitry
Altera Corporation Section VII–1
Section VII. PCB Layout
Guidelines
This section provides inf ormation for board layout designers to
successfully layout their boards for Stratix® devices. This section contains
the requi red PCB layou t gui delines and package specific ations.
This section contains the following chapters:
■Chapter 13, Package Information for Stratix Devices
■Chapter 14, Designing with 1.5-V Devices
Revision History The table below shows the rev ision hist ory for Chapters 13 and 14.
Chapter Date/Version Changes Made
13 July 2005, v3.0 Updated packaging information.
September 2004, v2.1 ●Changed from Chapter 8, Volume 3 to Chapter 13, Volume 2.
●Corrected spelling error.
April 2003, v1.0 ●No new changes in Stratix Device Handbook v2.0.
14 January 2005, v1.2 ●This chapter was formerly chapter 15.
September 2004, v1.1 ●Changed from Chapter 10, Volume 3 to Chapter 15, Volume 2.
●Corrected spelling error.
April 2003, v1.0 ●No new changes in Stratix Device Handbook v2.0.
Section VII–2 Altera Corporation
PCB Layout Guidelines Stratix Device Handbook, Volume 2
Altera Corporation 13–1
July 2005
13. Package Information for
Stratix Devices
Introduction This data sheet prov ides package information for Altera®dev ic e s. It
includes these sections:
Section Page
Device & Package Cross Reference. . . . . . . . . . . . . . . . . . . . . 13–1
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–2
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–3
In this data sheet, packages are listed in order of ascending pin count.
Device &
Package Cross
Reference
Table 13–1 shows which Altera Stratix® devices are available in BGA,
FineLine BGA and Ultra FineLine BGA packages.
Table 13–1. Stratix Devices in BGA, FineLine BGA & Ultra FineLine BGA
Packages (Part 1 of 2)
Device Package Pins
EP1S10 Flip-chip FineLine BGA 484
BGA 672
FineLine BGA 672
Flip-chip FineLine BGA 780
EP1S20 Flip-chip FineLine BGA 484
BGA 672
FineLine BGA 672
Flip-chip FineLine BGA 780
EP1S25 BGA 672
FineLine BGA 672
Flip-chip FineLine BGA 780
Flip-chip FineLine BGA 1,020
EP1S30 Flip-chip FineLine BGA 780
Flip-chip BGA 956
Flip-chip FineLine BGA 1,020
S53008-3.0
13–2 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Thermal Resistance
Thermal
Resistance Table 13–2 provides θJA (junction-to-ambient thermal resistance) and θJC
(junction-to-case thermal resistance) values for Altera Stratix devices.
EP1S40 Flip-chip FineLine BGA 780
Flip-chip BGA 956
Flip-chip FineLine BGA 1,020
Flip-chip FineLine BGA 1,508
EP1S60 Flip-chip BGA 956
Flip-chip FineLine BGA 1,020
Flip-chip FineLine BGA 1,508
EP1S80 Flip-chip BGA 956
Flip-chip FineLine BGA 1,020
Flip-chip FineLine BGA 1,508
Table 13–1. Stratix Devices in BGA, FineLine BGA & Ultra FineLine BGA
Packages (Part 2 of 2)
Device Package Pins
Table 13–2. Thermal Resistance of Stratix Devices (Part 1 of 2)
Device Pin Count Package θJC (° C/W) θJA (° C/W)
Still Air θJA (° C/W)
100 ft./min. θJA (° C/W)
200 ft./min.
θJA (° C/W)
400
ft./min.
EP1S10 484 FineLine
BGA 0.38 11.9 9.8 8.4 7.2
672 BGA 3.2 16.8 13.7 11.9 10.5
672 FineLine
BGA 3.4 17.2 14 12.2 10.8
780 FineLine
BGA 0.43 10.9 8.8 7.4 6.3
EP1S20 484 FineLine
BGA 0.30 11.8 9.7 8.3 7.1
672 BGA 2.5 15.5 12.4 10.7 9.3
672 FineLine
BGA 2.7 16 12.8 11 9.6
780 FineLine
BGA 0.31 10.7 8.6 7.2 6.1
Altera Corporation 13–3
July 2005 Stratix Device Handbook, Volume 2
Package Information for Stratix Devices
Package
Outlines The package outlines on the following pages are listed in order of
ascending pin count. Altera package outlines meet the requirements of
JEDEC Publication No. 95.
EP1S25 672 BGA 2.2 14.8 11.7 10.0 8.7
672 FineLine
BGA 2.3 15.3 12 10.4 9
780 FineLine
BGA 0.25 10.5 8.5 7.1 6.0
1020 FineLine
BGA 0.25 10.0 8.0 6.6 5.5
EP1S30 780 FineLine
BGA 0.2 10.4 8.4 7.0 5.9
956 BGA 0.2 9.1 7.1 5.8 4.8
1020 FineLine
BGA 0.2 9.9 7.9 6.5 5.4
EP1S40 780 FineLine
BGA 0.17 10.4 8.3 6.9 5.8
956 BGA 0.18 9.0 7.0 5.7 4.7
1020 FineLine
BGA 0.17 9.8 7.8 6.4 5.3
1508 FineLine
BGA 0.18 9.1 7.1 5.8 4.7
EP1S60 956 BGA 0.13 8.9 6.9 5.6 4.6
1020 FineLine
BGA 0.13 9.7 7.7 6.3 5.2
1508 FineLine
BGA 0.13 8.9 7.0 5.6 4.6
EP1S80 956 BGA 0.1 8.8 6.8 5.5 4.5
1020 FineLine
BGA 0.1 9.6 7.6 6.2 5.1
1508 FineLine
BGA 0.1 8.8 6.9 5.5 4.5
Table 13–2. Thermal Resistance of Stratix Devices (Part 2 of 2)
Device Pin Count Package θJC (° C/W) θJA (° C/W)
Still Air θJA (° C/W)
100 ft./min. θJA (° C/W)
200 ft./min.
θJA (° C/W)
400
ft./min.
13–4 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Package Outlines
484-Pin FineLine BGA - Flip Chip
■All dimensions and tolerances conform to ASME Y14.5M – 1994.
■Controlling dimension is in millimeters.
■Pin A1 may be indicated by an ID dot, or a special feature, in its
proximity on the package surface.
Tables 13–3 and 13–4 show the package information and package outline
figure references, respectively, for the 484-pin FineLine BGA packaging.
Table 13–3. 484-Pin FineLine BGA Package Information
Description Specification
Ordering code reference F
Package acronym FineLine BGA
Substrate material BT
Solder ball composition Regular: 63Sn:37Pb (Typ.)
Pb-free: Sn:3Ag:0.5Cu (Typ.)
JEDEC outline reference MS-034 variation: AAJ-1
Maximum lead coplanarity 0.008 inches (0.20 mm)
Weight 5.8 g
Moisture sensitivity level Printed on moisture barrier bag
Table 13–4. 484-Pin FineLine BGA Package Outline Dimensio ns
Symbol Millimeter
Min. Nom. Max.
A––3.50
A1 0.30 – –
A2 0.25 – 3.00
A3 – – 2.50
D 23.00 BSC
E 23.00 BSC
b 0.50 0.60 0.70
e 1.00 BSC
Altera Corporation 13–5
July 2005 Stratix Device Handbook, Volume 2
Package Information for Stratix Devices
Figure 13–1 shows a package outline for the 484-pin FineLine BGA
packaging.
Figure 13–1. 484-Pin FineLine BGA Package Outline
D
A1
A3
A2
A
E
e
e
b
Pin A1 ID
Pin A1
Corner
BOTTOM VIEWTOP VIEW
13–6 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Package Outlines
672-Pin FineLine BGA - Flip Chip
■All dimensions and tolerances conform to ASME Y14.5M - 1994.
■Controlling dimension is in millimeters.
■Pin A1 may be indicated by an ID dot, or a special feature, in its
proximity on package surface.
Tables 13–5 and 13–6 show the package information and package outline
figure references, respectively, for the 672-pin FineLine BGA packaging.
Table 13–5. 672-Pin FineLine BGA Package Information
Description Specification
Ordering code reference F
Package acronym FineLine BGA
Substrate material BT
Solder ball composition Regular: 63Sn:37Pb (Typ.)
Pb-free: Sn:3Ag:0.5Cu (Typ.)
JEDEC Outline Reference MS-034 Variation: AAL-1
Maximum lead coplanarity 0.008 inches (0.20 mm)
Weight 7.7 g
Moisture sensitivity level Printed on moisture barrier bag
Table 13–6. 672-Pin FineLine BGA Package Outline Dimensio ns
Symbol Millimeters
Min. Nom. Max.
A––3.50
A1 0.30 – –
A2 0.25 – 3.00
A3 – – 2.50
D 27.00 BSC
E 27.00 BSC
b 0.50 0.60 0.70
e 1.00 BSC
Altera Corporation 13–7
July 2005 Stratix Device Handbook, Volume 2
Package Information for Stratix Devices
Figure 13–2 shows a package outline for the 672-pin FineLine BGA
packaging.
Figure 13–2. 672-Pin FineLine BGA Package Outline
E
D
e
e
A1
A2
b
A3
A
Pin A1 ID
Pin A1
Corner
BOTTOM VIEWTOP VIEW
13–8 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Package Outlines
780-Pin FineLine BGA - Flip Chip
■All dimensions and tolerances conform to ASME Y14.5M - 1994.
■Controlling dimension is in millimeters.
■Pin A1 may be indicated by an ID dot, or a special feature, in its
proximity on package surface.
Tables 13–7 and 13–8 show the package information and package outline
figure references, respectively, for the 780-pin FineLine BGA packaging.
Table 13–7. 780-Pin FineLine BGA Package Information
Description Specification
Ordering code reference F
Package acronym FineLine BGA
Substrate material BT
Solder ball composition Regular: 63Sn:37Pb (Typ.)
Pb-free: Sn:3Ag:0.5Cu (Typ.)
JEDEC outline reference MS-034 variation: AAM-1
Maximum lead coplanarity 0.008 inches (0.20 mm)
Weight 8.9 g
Moisture sensitivity level Printed on moisture barrier bag
Table 13–8. 780-Pin FineLine BGA Package Outline Dimensio ns
Symbol Millimeters
Min. Nom. Max.
A––3.50
A1 0.30 – –
A2 0.25 – 3.00
A3 – – 2.50
D 29.00 BSC
E 29.00 BSC
b 0.50 0.60 0.70
e 1.00 BSC
Altera Corporation 13–9
July 2005 Stratix Device Handbook, Volume 2
Package Information for Stratix Devices
Figure 13–3 shows a package outline for the 780-pin FineLine BGA
packaging.
Figure 13–3. 780-Pin FineLine BGA Package Outline
Pin A1 ID
Pin A1
Corner
BOTTOM VIEWTOP VIEW
E
D
e
e
A1
A2
b
A3
A
13–10 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Package Outlines
956-Pin Ball Grid Array (BGA) - Flip Chip
■All dimensions and tolerances conform to ASME Y14.5M - 1994.
■Controlling dimension is in millimeters.
■Pin A1 may be indicated by an ID dot, or a special feature, in its
proximity on package surface.
Tables 13–9 and 13–10 show the package information and package
outline figure references, respectively, for the 956-pin BGA packaging.
Table 13–9. 956-Pin BGA Package Information
Description Specification
Ordering code reference B
Package acronym BGA
Substrate material BT
Solder ball composition Regular: 63Sn:37Pb (Typ.)
Pb-free: Sn:3Ag:0.5Cu (Typ.)
JEDEC outline reference MS-034 Variation: BAU-1
Maximum lead coplanarity 0.008 inches (0.20 mm)
Weight 14.6 g
Moisture sensitivity level Printed on moisture barrier bag
Table 13–10. 956-Pin BGA Package Outline Dimensions
Symbol Millimeters
Min. Nom. Max.
A––3.50
A1 0.30 – –
A2 0.25 – 3.00
A3 – – 2.50
D 40.00 BSC
E 40.00 BSC
b 0.60 0.75 0.90
e 1.27 BSC
Altera Corporation 13–11
July 2005 Stratix Device Handbook, Volume 2
Package Information for Stratix Devices
Figure 13–4 shows a package outline for the 956-pin BGA packaging.
Figure 13–4. 956-Pin BGA Package Outline
D
E
be
A3
A1
A2
Pin A1
Corner
A
1624
31 29 27 25
2830 26
23 21 19 17
2022 18
AG
AK
AL
AH
AJ
AD
AF
AE
AB
AC
Y
AA
W
T
V
U
8
15 13 11 9
1214 10
7531
462
K
NP
R
M
L
GH
J
F
E
B
D
C
A
e
Pin A1 ID
BOTTOM VIEWTOP VIEW
13–12 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Package Outlines
1,020-Pin FineLine BGA - Flip Chip
■All dimensions and tolerances conform to ASME Y14.5M - 1994.
■Controlling dimension is in millimeters.
■Pin A1 may be indicated by an ID dot, or a special feature, in its
proximity on package surface.
Tables 13–11 and 13–12 show the package information and package
outline figure r e ferences, respectively, for the 1,020-pin FineLine BGA
packaging.
Table 13–11. 1,020 FineLine BGA Package Information
Description Specification
Ordering code reference F
Package acronym FineLine BGA
Substrate material BT
Solder ball composition Regular: 63Sn:37Pb (Typ.)
Pb-free: Sn:3Ag:0.5Cu (Typ.)
JEDEC outline reference MS-034 variation: AAP-1
Maximum lead coplanarity 0.008 inches (0.20 mm)
Weight 11.5 g
Moisture sensitivity level Printed on moisture barrier bag
Table 13–12. 1,020-Pin FineLine BGA Package Outline Dimensions
Symbol Millimeters
Min. Nom. Max.
A––3.50
A1 0.30 – –
A2 0.25 – 3.00
A3 – – 2.50
D 33.00 BSC
E 33.00 BSC
b 0.50 0.60 0.70
e 1.00 BSC
Altera Corporation 13–13
July 2005 Stratix Device Handbook, Volume 2
Package Information for Stratix Devices
Figure 13–5 shows a package outline for the 1,020-pin FineLine BGA
packaging.
Figure 13–5. 1,020-Pin FineLine BGA Package Outline
D
E
Pin A1 ID
be
e
A3
A1
A2
Pin A1
Corner
A
BOTTOM VIEWTOP VIEW
13–14 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Package Outlines
1,508-Pin FineLine BGA - Flip Chip
■All dimensions and tolerances conform to ASME Y14.5M - 1994.
■Controlling dimension is in millimeters.
■Pin A1 may be indicated by an ID dot, or a special feature, in its
proximity on package surface.
Tables 13–13 and 13–14 show the package information and package
outline figure r e ferences, respectively, for the 1,508-pin FineLine BGA
packaging.
Table 13–13. 1,508-Pin FineLine BGA Package Information
Description Specification
Ordering code reference F
Package acronym FineLine BGA
Substrate material BT
Solder ball composition Regular: 63Sn:37Pb (Typ.)
Pb-free: Sn:3Ag:0.5Cu (Typ.)
JEDEC outline reference MS-034 Variation: AAU-1
Maximum lead coplanarity 0.008 inches (0.20 mm)
Weight 14.6 g
Moisture sensitivity level Printed on moisture barrier bag
Table 13–14. 1,508-Pin FineLine BGA Package Outline Dimensions
Symbol Millimeters
Min. Nom. Max.
A––3.50
A1 0.30 – –
A2 0.25 – 3.00
A3 – – 2.50
D 40.00 BSC
E 40.00 BSC
b 0.50 0.60 0.70
e 1.00 BSC
Altera Corporation 13–15
July 2005 Stratix Device Handbook, Volume 2
Package Information for Stratix Devices
Figure 13–6 shows a package outline for the 1,508-pin FineLine BGA
packaging.
Figure 13–6. 1,508-Pin FineLine BGA Package Outline
Pin A1
Corner
b
e
E
D
Pin A1 ID
A2
A3
A1
A
e
TOP VIEW BOTTOM VIEW
13–16 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Package Outlines
Altera Corporation 14–1
January 2005
14. Designing with
1.5-V Devices
Introduction The CycloneTM FPGA family prov ides the best solution for high-volume,
cost-sensitive applications. Stratix® and Cyclone devices are fabricated on
a leading-edge 1.5-V, 0.13-µm, all-layer copper SRAM process.
Using a 1.5-V operating voltage provides the following advantages:
■Lower power consumption compared to 2.5-V or 3.3-V devices.
■Lower operating temperature.
■Less need fo r fa ns and other t emperatu re-cont rol elements.
Since many existing designs are based on 5.0-V, 3.3-V and 2.5-V power
supplies, a voltage regulator may be required to lo wer the voltage supply
level to 1.5-V. This document provides guidelines for designing with
Stratix and Cyclone devices in mixed-voltage and single-voltage systems
and provides examples using voltage regulators. This document also
includes information on:
■Power Sequencing & Hot Socketing
■Using MultiVolt I/O Pins
■Voltage Regulators
■1.5-V Regulator Application Examples
■Board Layout
Power
Sequencing &
Hot Socketing
Because 1.5-V Cyclone FPGAs can be us ed in a mi xed-voltage
environment, they have been designed specifically to tolerate any
possible power-up sequence. Therefore, the VCCIO and VCCINT power
supplies may be powered in any order.
You can dri v e signals into Cyclone FPGAs before and during power up
without damaging the device. In addition, Cyclone FPGAs do not drive
out during power up since they are tri-stated du ring power up. Once the
device reaches operating condition s and is configured, Cyclone FPGAs
operate as specified by the user.
fSee the Stratix FPGA Family Data Sheet and the Cyclone FPGA Family Data
Sheet for more information.
C51012-1.1
14–2 Altera Corporation
Stratix Device Handbook, Volume 2 January 2005
Using MultiVolt I/O Pins
Using MultiVolt
I/O Pins Cyclone FPGAs require a 1.5-V VCCINT and a 3.3-V, 2.5-V, 1.8-V, or 1.5-V
I/O supply voltage level (VCCIO). All pins, including dedicated inputs,
clock, I/O, and JTAG pins, ar e 3.3-V tolerant befor e and after VCCINT and
VCCIO are powered.
When VCCIO is connected to 1.5-V, the output is compatible with 1.5-V
logic levels. The output pins can be made 1.8-V, 2.5-V, or 3.3-V compatible
by using open-drain outputs pulled up with external resistors. You can
use external re sistors to pull open-drain outputs up with a 1.8- V, 2.5-V, or
3.3-V VCCIO. Table 14–1 summarizes Cyclone MultiVolt I/O support.
Table 14–1. Cyclone MultiVolt I/O Support Note (1)
VCCIO (V) Input Signal Output Signal
1.5-V 1.8-V 2.5-V 3.3-V 5.0-V 1.5-V 1.8-V 2.5-V 3.3-V 5.0-V
1.5-V vv
v (2) v (2) v
1.8-V vvv v (3) v
2.5-V vv v (5) v (5) v
3.3-V v (4) vv (6) v (7) v (7) v (7) vv (8)
Notes to Table 14–1:
(1) The PCI clamping diode must be disabled to drive an input with voltages higher than VCCIO.
(2) When VCCIO = 1.5-V and a 2.5-V or 3.3-V input signal feeds an input pin, higher pin leakage current is expected.
(3) When VCCIO = 1.8-V, a Cyclone device can drive a 1.5-V device with 1.8-V tolerant inputs.
(4) When VCCIO = 3.3-V and a 2.5-V input signal feeds an input pin, the VCCIO supply current will be slightly larger
than expected.
(5) When VCCIO = 2.5-V, a Cyclone device can drive a 1.5-V or 1.8-V device with 2.5-V tolerant inputs.
(6) Cyclone devices can be 5.0-V tolerant with the use of an external resist or and the internal PCI c lamp diode.
(7) When VCCIO = 3.3-V, a Cyclone device can drive a 1.5-V, 1.8-V, or 2.5-V device with 3.3-V tolerant inputs.
(8) When VCCIO = 3.3-V, a Cyclone device can drive a device with 5.0-V LVTTL inputs but not 5.0-V LVCMOS inputs.
Altera Corporation 14–3
January 2005 Stratix Device Handbook, Volume 2
Designing with 1.5-V Devices
Figure 14–1 shows ho w Cycl one FPGAs interface with 3.3--V and 2.5-V
devices while operating with a 1.5-V VCCINT to increase performance and
save power.
Figure 14–1. Cyclone FPGAs Interface with 3.3-V & 2.5-V Devices
Voltage
Regulators This section explains how to generate a 1.5-V supply from another system
supply. Supplying power to the 1.5-V logic array and/or I/O pins
requires a 5.0-V- or 3.3-V-to-1.5-V voltage regulator. A linear regulator is
ideal for low-power applications because it minimizes device count and
has acceptable efficiency for most applications. A switching voltage
regulator provides optimal efficiency. Switching regulators are ideal for
high-power applications because of their high effici ency.
This section will help you decide which regulator to use in your sys tem ,
and how to implement the regulator in your design. There ar e several
companies that provide voltage regulators for low-voltage devices, such
as Linear Technology Corporation, Maxim Integrated Products, Intersil
Corporation (Elantec), and National Semiconductor Corporation.
3.3 V
2.5 V
1.5 V
3.3-V TTL
3.3-V CMOS
3.3-V Device 2.5-V Device
Cyclone Device
2.5-V TTL
2.5-V CMOS
VCCINT = 1.5 V
VCCIO1 = 2.5 V
VCCIO2 = 3.3 V
14–4 Altera Corporation
Stratix Device Handbook, Volume 2 January 2005
Voltage Regulators
Table 14–2 shows the terminology and specifications commonly
encountered with voltage regulators. Symbols are shown in par entheses.
If the symbols are diffe rent for linear and switc hing regulators, the l inear
regulator symbol is listed first.
Table 14–2. Voltage Regulator Specifications & Terminology (Part 1 of 2)
Specification/Terminology Description
Input voltage range (VIN,VCC) Minimum and maximum input v oltages define the input v oltage range , which
is determined by the regulator process voltage capabilities.
Line regulation
(line regulation, VOUT)Line regulation is the variation of the output voltage (VOUT) with changes in
the input voltage (VIN). Error amplifier gain, pass transistor gain, and output
impedance all influence line regulation. Higher gain results in better
regulation. Board layout and regulator pin-outs are also important because
stray resistance can introduce errors.
Load regulation
(load regulation, VOUT)Load regulation is a variation in the output voltage caused b y changes in the
input supply current. Linear Technology regulators are designed to minimize
load regulation, which is affected b y error amplifier gain, pass transistor gain,
and output impedance.
Output voltage selection Output voltage selection is adjustable by resistor voltage divider networks,
connected to the error amplifier input, that control the output voltage. There
are multiple output regulators that create 5.0-, 3.3-, 2.5-, 1.8- and 1.5-V
supplies.
Quiescent current Quiescent current is the supply current during no-load or quiescent state.
This current is sometimes used as a general term for a supply current used
by the regulator.
Dropout voltage Dropout voltage is the difference between the input and output voltages
when the input is low enough to cause the output to drop out of regulation.
The dropout voltage should be as low as possible for better efficiency.
Current limiting Voltage regulators are designed to limit the amount of output current in the
event of a failing load. A short in the load causes the output current and
voltage to decrease. This e vent cuts po wer dissipation in the regulator during
a short circuit.
Thermal overload protection This feature limits power dissipation if the regulator overheats. When a
specified temperature is reached, the regulator turns off the output drive
transistors, allowing the regulator to cool. Normal operation resumes once
the regulator reaches a normal operating temperature.
Rev erse current protection If the input power supply fails, large output capacitors can cause a substantial
reverse current to flow backward through the regulator, potentially causing
damage. To prevent damage , protection diodes in the regulator create a path
for the current to flow from VOUT to VIN.
Stability The dominant pole placed by the output capacitor influences stability.
Voltage regulator vendors can assist you in output capacitor selection for
regulator designs that differ from what is offered.
Altera Corporation 14–5
January 2005 Stratix Device Handbook, Volume 2
Designing with 1.5-V Devices
Linear Voltage Regulators
Linear voltage regulators generate a regulated output fr om a lar ger input
voltage using current pass elements in a linear mode. Ther e are two types
of linear regulators available: one using a series pass element and another
using a shunt element (e.g., a zener diode). Altera recommends using
series linear regulators because shunt regulators are less efficient.
Series linear re gulators use a series pass element (i .e., a bipolar transistor
or MOSFET) controlled by a feedback err or amplifier (see Figure 14–2) to
regulate the output voltage by comparing the output to a reference
voltage. The error amplifier drives the transistor further on or off
continuously to control the flow of current needed to sustain a steady
voltage level across the load.
Figure 14–2. Series Linear Regulator
Minimum load requirements A minimum lo ad from the voltage divider network is required for good
regulation, which also serves as the ground for the regulator’s current path.
Efficiency Efficiency is the division of the output power by the input power. Each
regulator model has a specific efficiency value. The higher the efficiency
value, the better the regulator.
Table 14–2. Voltage Regulator Specifications & Terminology (Part 2 of 2)
Specification/Terminology Description
–
+
Reference
Error
Amplifier
VOUT
VIN
14–6 Altera Corporation
Stratix Device Handbook, Volume 2 January 2005
Voltage Regulators
Table 14–3 shows the advantages and disadvantages of linear regulators
compared to switching regulators.
You can minimize the difference between the input and output voltages
to improve the efficiency of linear regulators. The dropout voltage is the
minimum allowable dif ference between the r egulator’s input and output
voltage.
Linear regulators are available with fixed, variable, single, or multi ple
outputs. Multiple-output regulators can generate multiple outputs (e.g.,
1.5- and 3.3-V outputs). If the board only has a 5.0-V power voltage
supply, you should use multiple-output regulators. The logic array
requires a 1.5-V power supply, and a 3.3-V power supply is required to
interface with 3.3- and 5.0-V devic es. However, fixed-output regulators
have fewer supporting components , reducing board space and cost.
Figure 14–3 shows an example of a three-terminal, fixed-output linear
regulator.
Figure 14–3. Three-Terminal, Fixed-Output Linear Regulator
Adjustable-output regulators contain a voltage divider network that
controls the r e gula tor’s output. Figure 14–4 shows how you can also us e
a three-terminal linear r egulato r in an adjustable-output configuration.
Table 14–3. Linear Regulator Advantages & Disadvantages
Advantages Disadvantages
Requires few supporting components
Low cost
Requires less board space
Quick transient response
Better noise and drift characteristics
No electromagnetic interference (EMI)
radiation from the switching
components
Tighter regulation
Less efficient (typically 60%)
Higher power dissipation
Larger heat sink requirements
Linear Regulator
IN OUT
ADJ
1.5 V
VIN
Altera Corporation 14–7
January 2005 Stratix Device Handbook, Volume 2
Designing with 1.5-V Devices
Figure 14–4. Adjustable-Output Linear Regulator
Switching Voltage Regulators
Step-down switching regulators can provide 3.3-V-to-1.5-V conversion
with up to 95% efficiencies. This high efficiency comes from minimizing
quiescent curr ent, us ing a low-r esistance power MOSFET switch, and, in
higher-cur r ent appl ications, using a sy nchr onous s witch to r educe diode
losses.
Switching regulators supply power by pulsing the output voltage and
current to the loa d. Table 14–4 shows the advantages and disadvantages
of switching regulators compared to linear regulators. For more
information on switching regulators, see Application Note 35: Step Down
Switching Regulators from Linear Technology.
There are two types of switching regulators, asynchronous and
synchr onou s. Asynchr onou s switching reg u lators have one field effect
transistor (FET) and a diode to pr ov ide the current path while the FET is
off (see Figure 14–5).
Linear Regulator
IN OUT
ADJ
VIN +C1
+
VREF R1
R2
C2
IADJ
VOUT = [VREF × (1 + )] + (IADJ × R1)
R1
R2
Table 14–4. Switching Regulator Advantages & Disadvantages
Advantages Disadvantages
Highly efficient (typically >80%)
Reduced power dissipation
Smaller heat sink requirements
Wider input voltage range
High power density
Generates EMI
Complex to design
Requires 15 or more supporting
components
Higher cost
Requires more board space
14–8 Altera Corporation
Stratix Device Handbook, Volume 2 January 2005
Voltage Regulators
Figure 14–5. Asynchronous Switching Regu lator
Synchronous switching regulators have a voltage- or current-controlled
oscillator that controls the on and off time of the two MOSFET devices
that supply the current to the circuit (see Figure 14–6).
Figure 14–6. Voltage-Controlled Syn chrono us Switching Regulator
Maximum Output Current
Select an external MOSFET switching transistor (optional) based on the
maximum output current that it can supply. Use a MOSFET with a low
on-resistance and a voltage rating high enough to avoid avalanche
breakdown. For gate-drive voltages less than 9-V, use a logic-level
MOSFET. A logic-level MOSFET is onl y required for topologies with a
contro ller IC and an external MOSFET.
High-Frequency
Circulating Path LOAD
Switch Node
MOSFET
VOUT
VIN
VIN
VOUT
Voltage-Controlled
Oscillator (VCO)
Altera Corporation 14–9
January 2005 Stratix Device Handbook, Volume 2
Designing with 1.5-V Devices
Selecting Voltage Regulators
Your design requirements determine which voltage regulator you need.
The key to selecting a voltage regulator is understanding the regulator
parameters and how they relate to the design.
The following checklist ca n help you sel ect the pr oper r egu lator for you r
design:
■Do you require a 3.3-V, 2.5-V, and 1.5-V output (VOUT)?
■What precision is requir ed on the regulated 1.5-V supplies (line and
load regula tion)?
■What supply voltages (VIN or VCC) are available on the board?
■What voltage variance (input voltage range) is expected on VIN or
VCC?
■What is the maximum ICC (IOUT) required by your Altera® device?
■What is the maximum current surge (IOUT(MAX)) that the regulator
will need to supply instantaneously?
Choose a Regulator Type
If required, select either a linear, asy nchronous switching, or
synchronous switching regulator based on your output current, r egulator
efficiency, cost, and board-space requir ements. DC-to-DC conv erters
have output current capabilities from 1 to 8 A. You can use a controller
with an external MOSFET rated for higher current for higher-output-
current applications.
Calculate the Maximum Input Current
Use the following equation to estimate the maximum input current based
on the output power requirements at the maximum input voltage:
Where η is nominal efficiency: typically 90% for switching regu lators,
60% for linear 2.5-V-to-1.5-V conversion, 45% for linear 3.3-V-to-1.5-V
conversion, and 30% for linear 5.0-V-to-1.5-V conversion.
Once you identify the design requirements, select the vol tage regulator
that is best for your design. Tables 14–5 and 14–6 list a few Linear
Technology and Elantec regulators available at the time this document
I
IN,DC(MAX)
= V
OUT
× I
OUT(MAX)
η × V
IN(MAX)
14–10 Altera Corporation
Stratix Device Handbook, Volume 2 January 2005
Voltage Regulators
was published. Ther e may be mor e r egula tors to choose fr om depe nding
on your design specification. Contact a regulator manufacturer for
availability.
Voltage Divider Network
Design a voltage divider network if you are using an adjustable output
regulator. Follow the controller or converter IC’s instructions to adjust
the output voltage.
1.5-V Regulator Circuits
This section co ntains the circuit diagrams for the voltage regulators
discussed in this chapter. You can use the voltage regulators in this
section to generate a 1.5-V power supply. See the voltage regulator data
sheet to find detailed speci fications. If you require further information
that is not shown in the data sheet, contact the regulator’s vendor.
Table 14–5. Linear Technology 1.5-V Output Voltage Regulators
Voltage Regulator Regulator Type Total Number of
Components VIN (V) IOUT (A) Special Features
LT1573 Linear 10 2.5 or 3.3 (1) 6–
LT1083 Linear 5 5.0 7.5 –
LT1084 Linear 5 5.0 5 –
LT1085 Linear 5 5.0 3 Inexpensive solution
LTC1649 Switching 22 3.3 15 Selectable output
LTC1775 Switching 17 5.0 5 –
Note to Table 14–5:
(1) A 3.3-V VIN requires a 3.3-V supply to the regulator’s input and 2.5-V supply to bias the transistors.
Table 14–6. Elantec 1.5-V Output Voltage Regulators
Voltage Regulator Regulator Type Total Number of
Components VIN (V) IOUT (A) Special Features
EL7551C Switching 11 5.0 1 –
EL7564CM Switching 13 5.0 4 –
EL7556BC Switching 21 5.0 6 –
EL7562CM Switching 17 3.3 or 5.5 2 –
EL7563CM Switching 19 3.3 4 –
Altera Corporation 14–11
January 2005 Stratix Device Handbook, Volume 2
Designing with 1.5-V Devices
Figures 14–7 through 14–12 show the circuit diagrams of Linear
Technology voltage regul ators listed in Table 14–5.
The LT1573 linear voltage r egulator converts 2.5-V to 1.5-V with an
output current of 6A (see Figure 14–7).
Figure 14–7. LT1573: 2.5-V-to-1.5-V/6.0-A Linear Voltage Regulator
Notes to Figure 14–7:
(1) CIN1 and COUT are AVX 100-μF/10-V surface-mount tantalum capacitors.
(2) Use SHDN (active high) to shut down the reg ulator.
(3) CTIME is a 0.5-μF capacitor for 100-ms time out at room temperature.
(4) CIN2 is an AVX 15-μF/10-V surface-mount tantalum capacitor.
Use adjustable 5.0- to 1.5-V regulators (shown in Figures 14–8 thro ugh
14–10) for 3.0- to 7.5-A low-cost, low-device-count, board-space-ef f icient
solutions.
LT1573
FB
LATCH
SHDN (2)
GND
COMP
VOUT
VIN
DRIVE
LOAD
VOUT
R2 1k
1/8 W
R1
186 Ω
1/8 W
CTIME
0.5 μF
COUT
CIN1
Motorola
D45H11
+
+
V
3.3 V
IN2
V
2.5 V
1.5 V
IN1
CIN2 +
R
6 Ω
1/2 W
DR
200Ω
1/8 W
B
+
(1)
(4)
(3)
(1)
14–12 Altera Corporation
Stratix Device Handbook, Volume 2 January 2005
Voltage Regulators
Figure 14–8. LT1083: 5.0-V-to-1.5-V/7.5-A Linear V oltage Regulator
Note to Figure 14–8:
(1) This capacitor is necessary to maintain the voltage level at the input regulator.
There could be a voltage drop at the input if the voltage supply is too far away.
Figure 14–9. LT1084: 5.0-V-to-1.5-V/5.0-A Linear V oltage Regulator
Note to Figure 14–9:
(1) This capacitor is necessary to maintain the voltage level at the input regulator.
There could be a voltage drop at the input if the voltage supply is too far away.
LT1083
ADJ
OUTIN
C1
VIN
+
C2+
R1
5 kΩ
R2
1 kΩ
10 μF10 μF
(1)
VOUT = 1.25 V × (1 + )
R2
R1
LT1083
ADJ
OUTIN
C1
VIN
+
C2+
R1
5 kΩ
R2
1 kΩ
10 μF10 μF
(1)
VOUT = 1.25 V × (1 + )
R2
R1
Altera Corporation 14–13
January 2005 Stratix Device Handbook, Volume 2
Designing with 1.5-V Devices
Figure 14–10. LT1085: 5.0-V-to-1.5-V/3-A Linear Voltage Regulator
Note to Figure 14–10:
(1) This capacitor is necessary to maintain the voltage level at the input regulator.
There could be a voltage drop at the input if the voltage supply is too far away.
Figure 14–11 shows a high-efficiency switching regulator circuit diagram.
A selectable resistor network contr ols the output voltage. The resistor
values in Figure 14–11 are selected for 1.5-V output operation.
Figure 14–11. LT1649: 3.3-V-to-1.5-V/15-A Asynchronous Switching Regulator
Notes to Figure 14–11:
(1) MBR0530 is a Motorola device.
(2) IRF7801 is a International Rectifier device.
(3) See the Panasonic 12TS-1R2HL device.
LT1084
ADJ
OUTIN
C1
VIN
+
C2+
R1
5 kΩ
R2
1 kΩ
10 μF10 μF
(1)
VOUT = 1.25 V × (1 + )
R2
R1
PVCC1
PVCC2
VCC
IMAX
SHDN
COMP
SS
GND
G1
IFB
G2
FB
VIN
C+
C–
CP OUT
LTC1649
++
+
+0.33 μF10 μF
1 μF
1 μF
1 kΩ
MBR05300.1 μF
10 μF
22 kΩ
RIMAX
50 kΩ
R1
2.16 kΩ
R2
12.7 kΩ
COUT
4,400 μF
VOUT
1.5 V
(15 A)
SHUTDOWN
MBR0530 (1)
Q3
IRF7801
RC
7.5 kΩ
CC
0.01 μF
C1
220 pF
Q1, Q2
IRF7801
Two in
Parallel (2)
CIN
3,300 μF
VIN
3.3 V
LEXT (3) 1.2 μH
14–14 Altera Corporation
Stratix Device Handbook, Volume 2 January 2005
Voltage Regulators
Figure 14–12 shows synchronous switching regulator with adjustable
outputs.
Figure 14–12. LTC1775: 5.0-V-to-1.5-V/5-A Synchronous Switching Regulator
Notes to Figure 14–12:
(1) This is a KEMETT495X15 6M035AS capacitor.
(2) This is a Sumida CDRH127-6R1 inductor.
(3) This is a KEMETT510X68 7K 004AS capacitor.
EXTVCC
ITH
VOSENSE
VPROG
SGND
SYNC
RUN/SS
FCB
VIN
BOOST
BG
PGND
INTVCC
TK
SW
TG
CC2
220 pF
CC1
2.2 nF INTVCC
OPEN
M1
1/2 FDS8936A
M2
1/2 FDS8936A
DB
CMDSH-3
VIN
5 V
VOUT
1.5 V
5 A
RF
1 Ω
RC
10 kΩ
R2
2.6 kΩ
R1
10 kΩ
CIN (1)
15 μF
35 V
×3
COUT (3
)
680 μF
4 V
×2
CB
0.22 μF
CVCC
4.7 μF
CSS
0.1 μF
CF
0.1 μF
L1 (2)
6.1 μH
D1
MBRS140
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Altera Corporation 14–15
January 2005 Stratix Device Handbook, Volume 2
Designing with 1.5-V Devices
Figures 14–13 thr ough 14–17 show the circuit diagrams of Elantec voltage
regulators listed in Table 14–6.
Figures 14–13 through 14–15 show the switching regulator that converts
5.0-V to 1.5-V with different output current.
Figure 14–13. EL7551C: 5.0-V-to-1.5-V/1-A Synchronous Switching Regulator
C5
0.1 μF
C6
0.1 μF
C3
0.1 μF
C1
10 μF
Ceramic
C4
270 pF
C7
47 μF
V0
1.5 V
1 A
VIN
5.0 V
L1
10 μH
R2
539 Ω
R3
39 kΩ
R1
1 kΩ
PGND
PGND
FB
LX
LX
VREF
VDRV
VHI
SGND
EN
VDD
PGND
VIN
COSC
PGND
VIN
EL7551C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
14–16 Altera Corporation
Stratix Device Handbook, Volume 2 January 2005
Voltage Regulators
Figure 14–14. EL7564CM: 5.0-V -to-1.5-V/4-A Synchronous Switching Regulator
C3
0.22 μF
C5
0.1 μF
C4
390 pF
C2
2.2 nF
C1
330 μF
C7
330 μF
V0
1.5 V
4 A
VIN
5.0 V
L1
4.7 μH
R4
22 Ω
R1
1 kΩ
R2
539 Ω
C10
100 pF
D1
C6
0.22 μF
PGND
LX
PGND
PGND
VIN
STP
STN
FB
VDRV
VHI
EN
PG
LX
PGND
SGND
VDD
VTJ
VREF
COSC
PGND
EL7564CM
8
9
10
13
12
11
1
2
3
4
5
6
7
20
19
18
17
16
15
14
Altera Corporation 14–17
January 2005 Stratix Device Handbook, Volume 2
Designing with 1.5-V Devices
Figure 14–15. EL7556BC: 5.0-V-to-1.5-V/6-A Synchronous Switching Regulator
Notes to Figures 14–13 to 14–15:
(1) These capacitors are ceramic capacitors.
(2) These capacitors are ceramic or tantalum capacitor.
(3) These are BAT54S fast diodes.
(4) D4 is only required for EL7556ACM.
(5) This is a Sprague 293D337X96R3 2X330μF capacitor.
(6) This is a Sprague 293D337X96R3 3X330μF capacitor.
C11 (2)
0.22 μF
C10 (6)
1.0 mF
C5 (2)
1 μF
C4 (1)
0.1 μF
C6 (1)
0.1 μF
C8 (1)
220 pF
C7 (1)
39 pF
C12
1.0 μF
C9 (5)
660 μF
VIN
TEST
PWRGD
OT
FB1
OUTEN
CSLOPE
VDD
VSSP
VSSP
VSSP
VSSP
VSSP
VCC2DET
VIN
VIN
CREF
COSC
FB2
C2V
VHI
LX
LX
VSSP
VSSP
LX
LX
CP
VSS
EL7556BC
R5
5.1 Ω
R4
100 Ω
L1
2.5 μH
R6
39.2 Ω
R1
20 Ω
D4
Optional (3), (4)
VOUT
= 1.5 V × (1 + )
R3
50 Ω
VIN
D3 (3)
D2 (3)
D1 (3)
R3
R4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
14–18 Altera Corporation
Stratix Device Handbook, Volume 2 January 2005
Voltage Regulators
Figures 14–16 and 14–17 show the switching r egulator that converts 3.3 V
to 1.5 V with different output currents.
Figure 14–16. EL7562CM: 3.3-V to 1.5-V/2-A Synchronous Switching Regulator
Figure 14–17. EL7563CM: 3.3-V to 1.5-V/4-A Synchronous Switching Regulator
VOUT
1.5 V
2 A
VIN
3.3 V
SGND
VDD
PGND
VIN
VIN
EN
COSC
PGND
PGND
FB
LX
VHI
LX
PGND
VREF
VDRV
EL7562CM
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
R3
39 Ω
C5
0.1 μF
C6
0.1 μF
C8
0.1 μF
C2
0.1 μF
C3
0.1 μF
C4
270 pF
C1
100 μF
C9
0.1 μF
C7
100 μF
L1
2.5 μH
R2
539 Ω
R1
1 kΩ
D2D3D4
VOUT
1.5 V
4 A
VIN
3.3 V
VREF
COSC
VTJ
PGND
PGND
VIN
SGND
VDD
EN
PG
VHI
LX
LX
PGND
FB
VDRV
EL7563CM
20
19
18
17
16
15
14
13
PGND
PGND
STP
STN
12
11
9
10
1
2
3
4
5
6
7
8
R4
22 Ω
C7
330 μF
L1
2.5 μH
R2
513 Ω
R1
1 kΩ
C3
0.22 μF
C6
0.22 μF
C10
2.2 nF
C1
330 μF
C9
0.1 μF
C8
0.22 μF
C2
2.2 nF
C4
390 pF
C5
0.1 μF
D1
D3
D2D4
Altera Corporation 14–19
January 2005 Stratix Device Handbook, Volume 2
Designing with 1.5-V Devices
1.5-V Regulator
Application
Examples
The following sections show the pr ocess used to select a voltage regulator
for three sa mple d esigns. The r egu lator s ele ction is base d on the am ount
of power that the Cyclone device consumes. There are 14 variables to
consider when selecting a voltage regulator. The following variabl es
apply to Cyclone device power consumption:
■fMAX
■Output and bidirectional pins
■Average toggle rate for I/O pins (togIO)
■Average toggle rate for logic elements (LEs) (togLC)
■User-mode ICC consumption
■Maximum power-up ICCINT requirement
■Utilization
■VCCIO supply level
■VCCINT supply level
The following variables apply to the voltage regulator:
■Output voltage precision requirement
■Supply voltage on the board
■Voltage supply output current
■Variance of board supply
■Efficiency
Different designs have different power consumpti ons based on the
variables listed. Once you calculate the Cyclone device’s power
consumption, you must consider how much current the Cyclone device
needs. You can use the Cyclone power calculator (available at
www.altera.com) or the PowerGaugeTM tool in the Quartus II software to
determine the current needs. Also check the maximum power -up current
requirement listed in the Power Consumption section of the Cyclone
FPGA Family Data Sheet because the power-up curr ent requirement may
exceed the user-mode current consumption for a specific design.
Once you determine the minim um current the Cyclone device requires,
you must select a voltage regulator that can generate the desired output
current with the voltage and curr ent supply that is available on the boar d
using the variables listed in this section. An example is shown to illustrate
the voltage regulator selection process.
14–20 Altera Corporation
Stratix Device Handbook, Volume 2 January 2005
1.5-V Regulator Application Examples
Synchronous Switching Regulator Example
This example shows a worst-case scenario for power consumption where
the design uses all the LEs and RAM. Table 14–7 shows the design
requirements for 1.5-V design using a Cyclone EP1C12 FPGA.
Table 14–8 uses the checklist on page 14–9 to help select the appropriate
voltage regulator.
Table 14–7. Design Requirements for the Example EP1C12F324C
Design Requirement V alue
Output voltage precision requirement ±5%
Supply voltages available on the board 3.3 V
Voltage supply output current available for this
section (IIN, DC(MAX))2 A
Variance of board supply (VIN)±5%
fMAX 150 MHz
Average togIO 12.5%
Average togLC 12.5%
Utilization 100%
Output and bidirectional pins 125
VCCIO supply level 3.3 V
VCCINT supply level 1.5 V
Efficiency ≥90%
Table 14–8. Voltage Regulator Selection Process for EP1C12F324C Desig n (Part 1 of 2)
Output voltage requirements VOUT = 1.5 V
Supply voltages VIN OR VCC = 3.3 V
Supply variance from Linear Technology data sheet Supply variance = ±5%
Estimated ICCINT
Use Cyclone Power Calculator ICCINT = 620 mA
Estimated ICCIO if regulator powers VCCIO
Use Cyclone Power Calculator (not applicable in this example
because VCCIO = 3.3 V)
ICCIO = N/A
Total user-mode current consumption
ICC = ICCINT + ICCIO
ICC = 620 mA
Altera Corporation 14–21
January 2005 Stratix Device Handbook, Volume 2
Designing with 1.5-V Devices
Board Layout Laying out a printed circuit board (PCB) pr operly is extr emely important
in high-frequency (≥100 kHz) switching regulator designs. A poor PCB
layout results in increased EMI and ground bounce, which affects the
reliability of the voltage regul ator by obscuring important voltage and
current feed back signals. Altera recommends using Gerber fil es ⎯pre-
designed layout files⎯supplied by the regulator vendor for your board
layout.
If you cannot use the supplied layout files, contact the voltage regulator
vendor for help on re-designing the board to fit your design r equirements
while maintaining the proper functionality.
Altera recommends that you use separate layers for signals, the ground
plane, and voltage supply planes. You can support separate layers by
using multi-layer PCBs, assuming you are using two signal layers.
EP1C12 maximum power-up current requirement
See Power Consumption section of the Cyclone FPGA Family
Data Sheet for other densities
IPUC(MAX) = 900 mA
Maximum output current required
Compare ICC with IPUC(MAX)
IOUT(MAX) = 900 mA
Voltage regulator selection
See Linear Technology LTC 1649 data sheet
See Intersil (Elantec) EL7562C data sheet LTC1649 IOUT(MAX) =
EL7562C IOUT(MAX) = 15 A
2 A
LTC1649
Nominal efficiency (η) Nominal efficiency (η) = > 90%
Line and load regulation
Line regulation + load regulation = (0.17 mV + 7 mV)/ 1.5 V × 100% Line and Load
Regulation = 0.478% < 5%
Minimum input voltage (VIN(MIN))
(VIN(MIN)) = VIN(1 – ΔVIN) = 3.3V(1 – 0.05) (VIN(MIN)) = 3.135 V
Maximum input current
IIN, DC(MAX) = (VOUT × IOUT(MAX))/(η × VIN(MIN)) IIN, DC(MAX) = 478 mA < 2 A
EL7562C
Nominal efficiency (η) Nominal efficiency (η) = > 95%
Line and load regulation
Line regulation + load regulation = (0.17 mV + 7 mV)/ 1.5 V × 100% Line and Load
Regulation = 0.5% < 5%
Minimum input voltage (VIN(MIN))
(VIN(MIN)) = VIN(1 – ΔVIN) = 3.3V(1 – 0.05) (VIN(MIN)) = 3.135 V
Maximum input current
IIN, DC(MAX) = (VOUT × IOUT(MAX))/(η × VIN(MIN)) IIN, DC(MAX) = 453 mA < 2 A
Table 14–8. Voltage Regulator Selection Process for EP1C12F324C Desig n (Part 2 of 2)
14–22 Altera Corporation
Stratix Device Handbook, Volume 2 January 2005
Board Layout
Figure 14–18 shows how to use regulators to generate 1.5-V and 2.5-V
power supplies if the system needs two power supply systems. One
regulator is used for each power supply.
Figure 14–18. Two Regulator Solution for Systems that Require 5.0-V, 2.5-V & 1.5-V Supply Levels
Figure 14–19 shows ho w to use a single regulator to generate two
different power supplies (1.5-V and 2. 5-V). The use of a single regulator
to generate 1.5-V and 2.5-V supplies from the 5.0-V power supply can
minimize the board size and thus save cost.
Figure 14–19. Single Regulator Solution for Systems that Require 5.0-V, 2.5-V & 1.5-V Supply Levels
Regulator
Regulator 2.5-V
Device
1.5-V
Device
Altera
Cyclone
FPGA
1.5 V
5.0 V
2.5 V
PCB
Regulator
2.5-V
Device
1.5-V
Device
Altera
Cyclone
FPGA
1.5 V
5.0 V 2.5 V
PCB
Altera Corporation 14–23
January 2005 Stratix Device Handbook, Volume 2
Designing with 1.5-V Devices
Split-Plane Method
The split-plane design method re duces the number of planes requir ed by
placing two power supply planes in one plane (see Figure 14–20). For
example, the layout for this method can be structured as follows:
■One 2.5-V plane, covering the entire boar d
■One plane split between 5.0-V and 1.5-V
This technique assumes that the majority of devices are 2.5-V. To support
MultiVolt I/O, Altera devices must have access to 1.5-V a nd 2.5-V planes.
Figure 14–20. Split Board Layout for 2.5-V Systems With 5.0-V & 1.5-V Devices
Conclusion With the proliferation of multiple voltage levels in systems, it is
important to design a voltage system that can support a low-power
device like Cycl one devices. Designers must cons ider key elements of the
PCB, such as power supplies, regulators, power consumption, and board
layout when successfully designi ng a system th at incorporates the low-
voltage Cyclone family of devices.
2.5-V
Device
2.5-V
Device
2.5-V
Device
5.0-V
Device
5.0-V
Device 1.5-V
Device
1.5-V
Device 2.5-V
Device
Altera
Cyclone
FPGA
(1.5 V)
1.5 V
PCB 5.0 V
Regulator
14–24 Altera Corporation
Stratix Device Handbook, Volume 2 January 2005
References
References Linear Technology Corporation. Application Note 35 (Step Down Switching
Regulators). Milpitas: Linear Technology Corporation, 1989.
Linear Technology Corporation. LT1573 Data Sheet (Low Dropout
Regulator Driver). Milpitas: Linear Technology Corporation, 1997.
Linear Technology Corporation. LT1083/LT1084/LT1085 Data Sheet (7.5 A,
5 A, 3 A Low Dropout Positive Adjustable Regulators). Milpitas: Linear
Technology Corporation, 1994.
Linear Technology Corporation. LTC1649 Data Sheet (3.3V Input High
Power Step-Down Switching Regulator Controller). Milpitas: Linear
Technology Corporation, 1998.
Linear Technology Corporation. LTC1775 Data Sheet (High Power No
Rsense Current Mode Synchronous Step-Down Switching Regulator).
Milpitas: Linear Tech nology Corporation, 1999.
Intersil Corporation. EL7551C Data Sheet (Monolithic 1 Amp DC:DC Step-
Down Regulator). Milpitas: Intersil Corporation, 2002.
Intersil Corporation. EL7564C Data Sheet (Monolithic 4 Amp DC:DC Step-
Down Regulator). Milpitas: Intersil Corporation, 2002.
Intersil Corporation. EL7556BC Data Sheet (Integrated Adjustable 6 Amp
Synchronous Switcher). Milpitas: Intersil Corporation, 2001.
Intersil Corporation. EL7562C Data Sheet (Monolithic 2 Amp DC:DC Step-
Down Regulator). Milpitas: Intersil Corporation, 2002.
Intersil Corporation. EL7563C Data Sheet (Monolithic 4 Amp DC:DC Step-
Down Regulator). Milpitas: Intersil Corporation, 2002.
