AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 1
AL5DS9xx9V Data Sheets
3.3V Synchronous Dual-Port SRAM
AL5DS9349V/59V/69V/79V
4K/8K/16K/32K x 18 bits
AL5DS9269/79V
16K/32K x 16 bits
AL5DS9149/59/69/79/89V
4K/8K/16K/32K/64K x 9 bits
AL5DS9069/79/89V
16K/32K/64K x 8 bits
Preliminary
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 2
Amendments (Since January 4, 2002)
02.01.04 Preliminary version 0.1
02.01.10 Preliminary version 0.2:
(1) Modifies truth table and note descriptions in paragraph 7
(2) Modifies Absolute Maximum Ratings in paragraph 8.1
(3) Modifies CIN and COUT DC characteristics in paragraph 8.3
(4) Modifies Bank Select Pipelined Read and Counter Rest in Pipelined Mode timing
diagrams
02.04.09 Preliminary version 0.3:
(1) Modifies features in paragraph 2
(2) Modifies ordering information in paragraph 4.1
(3) Modifies AC characteristics in paragraph 8.5
02.05.07 Preliminary version 0.4:
(1) Modifies marking information in paragraphs 4 and 6
(2) Modifies the font type in paragraphs 6 and 9
02.09.25 Preliminary version 0.5:
(1) Split the datasheets to two parts: AL5DS9389V/9289V/9199V/9099V for 1M bit
density and other parts for less than 1M bit density
(2) Modifies the pin-out diagram in paragraph 6
(3) Modifies the truth table of address control in paragraph 7
02.11.01 Preliminary version 0.6:
Modifies the DC characteristics in paragraph 8.3
THE INFORMATION CONTAINED HEREIN IS SUBJECT TO CHANGE WIHOUT NOTICE.
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 3
AL5DS9XX9V 3.3V Synchronous Dual-Port SRAM
Contents:
1 General Description ...............................................................................................4
2 Features ..................................................................................................................4
3 Applications ............................................................................................................5
4 Chip Information....................................................................................................5
4.1 Marking Information.............................................................................................................5
4.2 Ordering Information............................................................................................................5
5 Function Block Diagram .......................................................................................7
6 Pin-out Diagram.....................................................................................................8
7 Pin Definition and Description..............................................................................9
8 Electrical Characteristics.....................................................................................16
8.1 Absolute Maximum Ratings................................................................................................16
8.2 Recommended Operating Conditions ................................................................................16
8.3 DC Characteristics ...............................................................................................................17
8.4 AC Test Loads ......................................................................................................................18
8.5 AC Characteristics ...............................................................................................................18
9 Timing Diagrams .................................................................................................21
10 Mechanical Drawing............................................................................................27
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 4
1 General Description
A Dual-port RAM is a static RAM with a dual-ported cell. There are separate address, data and
control signals for each port to access a common SRAM array. A dual-port RAM is generally
classified with FIFOs as a “specialty” memory. They are most commonly used in communications
that include the exchange of data between processors, processes and systems.
Each port contains an internal counter for fast memory access applications. The initial address of the
internal counter is loaded with the port’s Address Strobe (/ADS). It also allows the Counter Enable
(/CNTEN) to increment the internal counter on each Low to High transition of that port’s clock
signal. The counter can address the entire memory array and will loop back to start (address 0). The
internal counter will be reset to zero while asserting Counter Reset (/CNTRST).
The AL5DS9xx9V is a high speed, 3.3V, synchronous, CMOS, dual-ported SRAM series. The
AL5DS9389V is configured as 64K x 18-bit, AL5DS9289V as 64K x 16-bit, AL5DS9199V as
128K x 9-bit and AL5DS9099V as 128K x 8-bit. All these parts support both Pipelined and Flow-
Through modes that are selected via the Pipe/FT pin. In the Pipelined mode, two cycles are required
to reactivate the data outputs. The AL5DS9xx9V series features dual Chip Enables that allow
simple depth and width expansion without external control logic.
All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. AL5DS9289V and
AL5DS9389V are also available in 128-pin TQFP packages.
2Features
zTrue dual ported memory cells
z4 Flow-Through/Pipelined devices:
-- 64K x 18-bit organization (AL5DS9389V)
-- 64K x 16-bit organization (AL5DS9289V)
-- 128K x 9-bit organization (AL5DS9199V)
-- 128K x 8-bit organization (AL5DS9099V)
zSupports byte write/read for 16/18 bit devices
zSeparate upper-byte and lower-byte controls for bus matching (only for 16/18 bit devices)
z3 modes supported:
-Pipelined
-Flow-Through
-Burst
zCounter enable and reset
zFast 100-MHz operation on both ports in Pipelined output mode
zSupports depth and width expansion
z0.25-micron CMOS for optimum speed/power
zHigh speed clock to data access
z3.3V low operating power
zPin-compatible and functionally equivalent to IDT or Cypress
zAvailable in 100 or 128 pin TQFP
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 5
3 Applications
zCellular Base Stations
zCellular Phones
zMulti-protocol Routers
zLAN/WAN Switches
zPBXs
zRAIDs (Storage Networks)
zSet-top Boxes
zAudio/Video Editing
zGraphics Accelerators
zSatellite Encoders
zCable Modems
zFlight Simulators
zHigh-end Printing Servers
zUltrasound Imaging
4 Chip Information
4.1 Marking Information
˔˟ˈ˗˦ˌ˫˫ˌ˩
˫ˀˀ˫˫
˫˫˫˫
˫˫˫˫˫˫ˁ˫
ˣ˴ʳˡ˵˸ˍʳ˫˫ʳːʳʳʳ˃ˌʿʳ˄ˌʿʳ˅ˋʿʳˆˋ
ˣ˴˶˾˴˺˸ˍʳ˫˫ː
ˣ˙˄˅ˋˍ ˄˅ˋˀ˼ʳ˧ˤ˙ˣ
ˣ˙˄˃˃ˍ ˄˃˃ˀ˼ʳ˧ˤ˙ˣ
˦˸˸˷ʳ˚˴˷˸ˍʳʳːʳ˄˃˃ʿʳˋˆ
˩˸˼ʳˡ˵˸ˍʳ˫ʳːʳ˔ʿʳ˕ʿʳ˖ˁˁ
˟ʳˡ˵˸
˗˴˸ʳ˖˷˸
4.2 Ordering Information
Two packages are available for AL5DS9xx9V series Synchronous Dual-Port SRAM.
Part number Speed
(MHz)
Package Power
Supply
Word
Length
Bus
Width
AL5DS9069V (A-100-PF100) 100 100 pin TQFP 3.3Vr10% 16K 8 bits
AL5DS9069V (A-83-PF100) 83 100 pin TQFP 3.3Vr10% 16K 8 bits
AL5DS9079V (A-100-PF100) 100 100 pin TQFP 3.3Vr10% 32K 8 bits
AL5DS9079V (A-83-PF100) 83 100 pin TQFP 3.3Vr10% 32K 8 bits
AL5DS9089V (A-100-PF100) 100 100 pin TQFP 3.3Vr10% 64K 8 bits
AL5DS9089V (A-83-PF100) 83 100 pin TQFP 3.3Vr10% 64K 8 bits
AL5DS9149V (A-100-PF100) 100 100 pin TQFP 3.3Vr10% 4K 9 bits
AL5DS9149V (A-83-PF100) 83 100 pin TQFP 3.3Vr10% 4K 9 bits
AL5DS9159V (A-100-PF100) 100 100 pin TQFP 3.3Vr10% 8K 9 bits
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 6
Part number Speed
(MHz)
Package Power
Supply
Word
Length
Bus
Width
AL5DS9159V (A-83-PF100) 83 100 pin TQFP 3.3Vr10% 8K 9 bits
AL5DS9169V (A-100-PF100) 100 100 pin TQFP 3.3Vr10% 16K 9 bits
AL5DS9169V (A-83-PF100) 83 100 pin TQFP 3.3Vr10% 16K 9 bits
AL5DS9179V (A-100-PF100) 100 100 pin TQFP 3.3Vr10% 32K 9 bits
AL5DS9179V (A-83-PF100) 83 100 pin TQFP 3.3Vr10% 32K 9 bits
AL5DS9189V (A-100-PF100) 100 100 pin TQFP 3.3Vr10% 64K 9 bits
AL5DS9189V (A-83-PF100) 83 100 pin TQFP 3.3Vr10% 64K 9 bits
AL5DS9269V (A-100-PF100) 100 100 pin TQFP 3.3Vr10% 16K 16 bits
AL5DS9269V (A-83-PF100) 83 100 pin TQFP 3.3Vr10% 16K 16 bits
AL5DS9279V (A-100-PF100) 100 100 pin TQFP 3.3Vr10% 32K 16 bits
AL5DS9279V (A-83-PF100) 83 100 pin TQFP 3.3Vr10% 32K 16 bits
AL5DS9269V (A-100-PF128) 100 128 pin TQFP 3.3Vr10% 16K 16 bits
AL5DS9269V (A-83-PF128) 83 128 pin TQFP 3.3Vr10% 16K 16 bits
AL5DS9279V (A-100-PF128) 100 128 pin TQFP 3.3Vr10% 32K 16 bits
AL5DS9279V (A-83-PF128) 83 128 pin TQFP 3.3Vr10% 32K 16 bits
AL5DS9349V (A-100-PF100) 100 100 pin TQFP 3.3Vr10% 4K 18 bits
AL5DS9349V (A-83-PF100) 83 100 pin TQFP 3.3Vr10% 4K 18 bits
AL5DS9359V (A-100-PF100) 100 100 pin TQFP 3.3Vr10% 8K 18 bits
AL5DS9359V (A-83-PF100) 83 100 pin TQFP 3.3Vr10% 8K 18 bits
AL5DS9369V (A-100-PF100) 100 100 pin TQFP 3.3Vr10% 16K 18 bits
AL5DS9369V (A-83-PF100) 83 100 pin TQFP 3.3Vr10% 16K 18 bits
AL5DS9379V (A-100-PF100) 100 100 pin TQFP 3.3Vr10% 32K 18 bits
AL5DS9379V (A-83-PF100) 83 100 pin TQFP 3.3Vr10% 32K 18 bits
AL5DS9379V (A-100-PF128) 100 128 pin TQFP 3.3Vr10% 32K 18 bits
AL5DS9379V (A-83-PF128) 83 128 pin TQFP 3.3Vr10% 32K 18 bits
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 7
5 Function Block Diagram
˧˸ʳ˗˴˿ˀˣ˸˷ʳ˦˥˔ˠ
˟˸˹
˔˷˷˸
˖˿
˥˼˺˻
˔˷˷˸
˖˿
˟˸˹ʳ˜˂ˢ
˖˿
˥˼˺˻ʳ˜˂ˢ
˖˿
˔˗˦˟
˖ˡ˧˘ˡ˟
˖ˡ˧˥˦˧˟
˖˟˞˟
˄˅˄ˊ
˔˃˟˄ˉ˟
˔˗˦˥
˖ˡ˧˘ˡ˥
˖ˡ˧˥˦˧˥
˖˟˞˥
˄˅˄ˊ ˔˃˥˄ˉ˥
ˋ˂ˌ
ˋ˂ˌ
˜˂ˢ˃˥ˊ˂ˋ˥
˜˂ˢˋ˂ˌ˥˄ˈ˂˄ˊ˥
˥˂˪˥
˟˕˥
˨˕˥
ˢ˘˥
˖˘˄˥
˖˘˃˥
ˣ˜ˣ˘˂˙˧˥
ˋ˂ˌ
ˋ˂ˌ
˜˂ˢ˃˟ˊ˂ˋ˟
˜˂ˢˋ˂ˌ˟˄ˈ˂˄ˊ˟
˥˂˪˟
˟˕˟
˨˕˟
ˢ˘˟
˖˘˄˟
˖˘˃˟
ˣ˜ˣ˘˂˙˧˟
ˡ˸ʳ˄ˍʳ˟˕˥ʳ˴˷ʳ˨˕˥ʳ˴˸ʳ˹ʳ˄ˉ˂˄ˋʳ˵˼ʳ˷˸˼˶˸ʳ˿ˁ
ˡ˸ʳ˅ˍʳ˜˂ˢ˃ˊʳ˹ʳʳˋ˂˄ˉʳ˵˼ʳ˷˸˼˶˸ʿʳ˜˂ˢ˃ˋʳ˹ʳʳˌ˂˄ˋʳ˵˼ʳ˷˸˼˶˸ʿʳ˜˂ˢˋ˄ˈʳ˹ʳ˄ˉʳ˵˼ʳ˷˸˼˶˸ʿʳ˴˷ʳ˜˂ˢˌ˄ˊʳ˹ʳʳ˄ˋʳ˵˼ʳ˷˸˼˶˸ˁ
ˡ˸ʳˆˍʳ˔˃˄ˈʳ˹ʳˉˇ˞ʿʳ˴˷ʳ˔˃˄ˉʳ˹ʳ˄˅ˋ˞ʳ˷˸˼˶˸
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 8
6 Pin-out Diagram
128 pin 14mm*20mm*1.4mm TQFP package-1:
˄
˄˄
˄˃
ˌ
ˋ
ˊ
ˉ
ˈ
ˇ
ˆ
˅
ˆ˄
ˆ˃
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˅ˈ
˅ˇ
˅ˆ
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˅˄
˅˃
˄ˌ
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˄ˊ
˄ˉ
˄ˈ
˄ˇ
˄ˆ
˄˅
ˆˋ
ˆˊ
ˆˉ
ˆˈ
ˆˇ
ˆˆ
ˆ˅
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ˌˆ
ˌˇ
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ˊˆ
ˊˇ
ˊˈ
ˊˉ
ˊˊ
ˊˋ
ˊˌ
ˋ˃
ˋ˄
ˋ˅
ˋˆ
ˋˇ
ˋˈ
ˋˉ
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ˋˋ
ˋˌ
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ˈˇ
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ˈ˅
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˄˄˄
˄˄˅
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˄˅˄
˄˅˅
˄˅ˆ
˄˅ˇ
˄˅ˈ
˄˅ˉ
˄˅ˊ
˄˅ˋ
˄˅ˋˀˣ˼ʳ˧ˤ˙ˣʳʻ˧ʳ˩˼˸ʼ
˔˟ˈ˗˦ˌˆˊˌ˩ʻ˔ˀ˄˃˃ˀˣ˙˄˅ˋʼˍʳˆ˅˞ʳʽʳ˄ˋ
˔˟ˈ˗˦ˌˆˊˌ˩ʻ˔ˀˋˆˀˣ˙˄˅ˋʼˍʳˆ˅˞ʳʽʳ˄ˋ
˜˂ˢ˄ˆ˥
˩˖˖
˩˖˖
˩˖˖
˜˂ˢ˄ˈ˥
˜˂ˢ˄ˇ˥
˜˂ˢ˄ˊ˥
˜˂ˢ˄ˉ˥
ˣ˜ˣ˘˂˙˧˥
˚ˡ˗
˚ˡ˗
ˢ˘˥
˥˂˪˥
˟˕˥
˨˕˥
˖˘˃˥
˖˘˄˥
˖ˡ˧˥˦˧˥
ˡ˖
ˡ˖
˔˄˃˥
ˡ˖
˔˄ˇ˥
˔˄ˆ˥
˔˄˅˥
˔˄˄˥
ˡ˖
ˡ˖
ˡ˖
˔ˌ˥
ˡ˖
ˡ˖
ˡ˖
ˡ˖
ˡ˖
˔ˋ˥
˔ˊ˥
˔ˉ˥
˔ˈ˥
˔ˇ˥
˔ˆ˥
˔˅˥
˔˄˥
˔˃˥
ˡ˖
˖ˡ˧˘ˡ˥
˖˟˞˥
˔˗˦˥
˚ˡ˗
˩˖˖
˔˗˦˟
˖˟˞˟
˖ˡ˧˘ˡ˟
ˡ˖
˔˃˟
˔˄˟
˔˅˟
˔ˆ˟
˔ˇ˟
˔ˈ˟
˔ˉ˟
˔ˊ˟
˔ˋ˟
˔ˌ˟
˜˂ˢ˄˅˥
ˡ˖
ˡ˖
˚ˡ˗
˜˂ˢ˄˄˥
˚ˡ˗
˩˖˖
˜˂ˢ˄˃˥
˜˂ˢˌ˥
˜˂ˢˋ˥
˜˂ˢˊ˥
˜˂ˢˉ˥
˜˂ˢˈ˥
˜˂ˢˇ˥
˩˖˖
˚ˡ˗
˜˂ˢˆ˥
˜˂ˢ˅˥
˜˂ˢ˄˥
˜˂ˢ˃˥
˩˖˖
˚ˡ˗
˚ˡ˗
˩˖˖
˩˖˖
˜˂ˢ˃˟
˜˂ˢˉ˟
˜˂ˢˈ˟
˜˂ˢˇ˟
˜˂ˢˆ˟
˜˂ˢ˅˟
˜˂ˢ˄˟
˜˂ˢˊ˟
˜˂ˢˌ˟
˜˂ˢˋ˟
˜˂ˢ˄˃˟
˜˂ˢ˄˅˟
˜˂ˢ˄˄˟
˔˄˃˟
ˡ˖
˔˄ˇ˟
˔˄ˆ˟
˔˄˅˟
˔˄˄˟
ˡ˖
ˡ˖
˟˕˟
˨˕˟
˖˘˃˟
˖˘˄˟
˖ˡ˧˥˦˧˟
˚ˡ˗
˩˖˖
˥˂˪˟
ˢ˘˟
ˣ˜ˣ˘˂˙˧˟
˚ˡ˗
˚ˡ˗
˩˖˖
˜˂ˢ˄ˊ˟
˜˂ˢ˄ˉ˟
˜˂ˢ˄ˈ˟
˜˂ˢ˄ˇ˟
˜˂ˢ˄ˆ˟
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 9
128 pin 14mm*20mm*1.4mm TQFP package-2:
˄
˄˄
˄˃
ˌ
ˋ
ˊ
ˉ
ˈ
ˇ
ˆ
˅
ˆ˄
ˆ˃
˅ˌ
˅ˋ
˅ˊ
˅ˉ
˅ˈ
˅ˇ
˅ˆ
˅˅
˅˄
˅˃
˄ˌ
˄ˋ
˄ˊ
˄ˉ
˄ˈ
˄ˇ
˄ˆ
˄˅
ˆˋ
ˆˊ
ˆˉ
ˆˈ
ˆˇ
ˆˆ
ˆ˅
ˌ˅
ˌˆ
ˌˇ
ˊ˅
ˊˆ
ˊˇ
ˊˈ
ˊˉ
ˊˊ
ˊˋ
ˊˌ
ˋ˃
ˋ˄
ˋ˅
ˋˆ
ˋˇ
ˋˈ
ˋˉ
ˋˊ
ˋˋ
ˋˌ
ˌ˃
ˌ˄
ˉˈ
ˉˉ
ˉˊ
ˉˋ
ˉˌ
ˊ˃
ˊ˄
ˆˌ
ˇ˃
ˇˇ
ˇˆ
ˇ˅
ˇ˄
ˈ˃
ˈˇ
ˈˆ
ˈ˅
ˈ˄
ˉ˃
ˉˆ
ˉ˅
ˉ˄
ˉˇ
ˈˈ
ˈˌ
ˈˋ
ˈˊ
ˈˉ
ˇˈ
ˇˌ
ˇˋ
ˇˊ
ˇˉ
˄˃˃
˄˃˄
˄˃˅
ˌˈ
ˌˉ
ˌˊ
ˌˋ
ˌˌ
˄˃ˆ
˄˃ˇ
˄˃ˈ
˄˃ˉ
˄˃ˊ
˄˃ˋ
˄˃ˌ
˄˄˃
˄˄˄
˄˄˅
˄˄ˆ
˄˄ˇ
˄˄ˈ
˄˄ˉ
˄˄ˊ
˄˄ˋ
˄˄ˌ
˄˅˃
˄˅˄
˄˅˅
˄˅ˆ
˄˅ˇ
˄˅ˈ
˄˅ˉ
˄˅ˊ
˄˅ˋ
˄˅ˋˀˣ˼ʳ˧ˤ˙ˣʳʻ˧ʳ˩˼˸ʼ
˔˟ˈ˗˦ˌ˅ˊˌ˩ʻ˔ˀ˄˃˃ˀˣ˙˄˅ˋʼˍʳˆ˅˞ʳʽʳ˄ˉ
˔˟ˈ˗˦ˌ˅ˊˌ˩ʻ˔ˀˋˆˀˣ˙˄˅ˋʼˍʳˆ˅˞ʳʽʳ˄ˉ
˔˟ˈ˗˦ˌ˅ˉˌ˩ʻ˔ˀ˄˃˃ˀˣ˙˄˅ˋʼˍʳ˄ˉ˞ʳʽʳ˄ˉ
˔˟ˈ˗˦ˌ˅ˉˌ˩ʻ˔ˀˋˆˀˣ˙˄˅ˋʼˍʳ˄ˉ˞ʳʽʳ˄ˉ
ˡ˸ʳ˄ˍʳ˼ʳˇˆʳ˴˷ʳ˄˅ˇʳ˴˸ʳˡ˖ʳ˹ʳ˔˟ˈ˗˦ˌ˅ˉˌ˩
ˡ˖
ˡ˖
ˡ˖
˔ˌ˥
ˡ˖
ˡ˖
ˡ˖
ˡ˖
ˡ˖
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˔ˉ˥
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˔ˇ˥
˔ˆ˥
˔˅˥
˔˄˥
˔˃˥
ˡ˖
˖ˡ˧˘ˡ˥
˖˟˞˥
˔˗˦˥
˚ˡ˗
˩˖˖
˔˗˦˟
˖˟˞˟
˖ˡ˧˘ˡ˟
ˡ˖
˔˃˟
˔˄˟
˔˅˟
˔ˆ˟
˔ˇ˟
˔ˈ˟
˔ˉ˟
˔ˊ˟
˔ˋ˟
˔ˌ˟
ˡ˖
ˡ˖
˚ˡ˗
˚ˡ˗
˩˖˖
˜˂ˢ˄˃˥
˜˂ˢˌ˥
˜˂ˢˋ˥
˜˂ˢˊ˥
˜˂ˢˉ˥
˜˂ˢˈ˥
˜˂ˢˇ˥
˩˖˖
˚ˡ˗
˜˂ˢˆ˥
˜˂ˢ˅˥
˜˂ˢ˄˥
˜˂ˢ˃˥
˩˖˖
˚ˡ˗
˚ˡ˗
˩˖˖
˩˖˖
˜˂ˢ˃˟
˜˂ˢˉ˟
˜˂ˢˈ˟
˜˂ˢˇ˟
˜˂ˢˆ˟
˜˂ˢ˅˟
˜˂ˢ˄˟
˜˂ˢˊ˟
˜˂ˢˌ˟
˜˂ˢˋ˟
˜˂ˢ˄˃˟
ˡ˖
ˡ˖
ˡ˖
ˡ˖
˜˂ˢ˄ˆ˥
˩˖˖
˩˖˖
˩˖˖
˜˂ˢ˄ˈ˥
˜˂ˢ˄ˇ˥
˜˂ˢ˄˅˥
˜˂ˢ˄˄˥
ˣ˜ˣ˘˂˙˧˥
˚ˡ˗
˚ˡ˗
ˢ˘˥
˥˂˪˥
˟˕˥
˨˕˥
˖˘˃˥
˖˘˄˥
˖ˡ˧˥˦˧˥
ˡ˖
ˡ˖
˔˄˃˥
ˡ˖
˔˄ˇ˥ˮˡ˖˰
˔˄ˆ˥
˔˄˅˥
˔˄˄˥
˔˄˃˟
ˡ˖
ˮˡ˖˰˔˄ˇ˟
˔˄ˆ˟
˔˄˅˟
˔˄˄˟
ˡ˖
ˡ˖
˟˕˟
˨˕˟
˖˘˃˟
˖˘˄˟
˖ˡ˧˥˦˧˟
˚ˡ˗
˩˖˖
˥˂˪˟
ˢ˘˟
ˣ˜ˣ˘˂˙˧˟
˚ˡ˗
˚ˡ˗
˩˖˖
˜˂ˢ˄ˈ˟
˜˂ˢ˄ˇ˟
˜˂ˢ˄ˆ˟
˜˂ˢ˄˅˟
˜˂ˢ˄˄˟
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 10
100 pin 14mm*14mm*1.4mm TQFP package-1:
100-Pin TQFP (Top View)
AL5DS9379V(A-100-PF100): 32K * 18
AL5DS9379V(A-83-PF100): 32K * 18
AL5DS9369V(A-100-PF100): 16K * 18
AL5DS9369V(A-83-PF100): 16K * 18
AL5DS9359V(A-100-PF100): 8K * 18
AL5DS9359V(A-83-PF100): 8K * 18
AL5DS9349V(A-100-PF100): 4K * 18
AL5DS9349V(A-83-PF100): 4K * 18
Note 1: pins 6 and 69 are NC for AL5DS9369V/59V/49V
Note 2: pins 5 and 70 are NC for AL5DS9359V/49V
Note 3: pins 4 and 71 are NC for AL5DS9349V
GND
GND
A8L
A3L
A4L
A5L
A6L
A7L
A0L
A1L
A2L
ADSL
CLKL
CNTENL
ADSR
CLKR
CNTENR
A0R
A3R
A4R
A5R
A1R
A2R
A6R
A7R
GND
GND
VCC
I/O9L
I/O8L
I/O7L
I/O6L
I/O3L
I/O2L
I/O1L
I/O0L
I/O5L
I/O4L
VCC
I/O1R
I/O0R
I/O3R
I/O2R
I/O5R
I/O4R
I/O7R
I/O6R
I/O9R
I/O8R
I/O10R
72
73
74
75
68
69
70
71
64
65
66
67
60
61
62
63
56
57
58
59
52
53
54
55
51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
11
10
9
8
7
6
5
4
3
2
25
24
23
22
21
20
19
18
17
16
15
14
13
12
39
40
44
43
42
41
50
45
49
48
47
46
26
27
31
30
29
28
37
32
36
35
34
33
38
GND
GND
I/O11R
PIPE/FTR
OER
R/WR
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O17R
LBR
UBR
CE0R
CE1R
CNTRSTR
A9R
A10R
A11R
A14R[NC]
A8R
A13R[NC]
NC
A12R[NC]
A9L
A10L
A11L
[NC]A12L
[NC]A13L
[NC]A14L
GND
I/O16L
LBL
UBL
CE0L
CE1L
CNTRSTL
VCC
R/WL
OEL
PIPE/FTL
I/O17L
NC
I/O14L
I/O15L
I/O12L
I/O13L
I/O10L
I/O11L
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 11
100 pin 14mm*14mm*1.4mm TQFP package-2:
100-Pin TQFP (Top View)
AL5DS9279V(A-100-PF100): 32K * 16
AL5DS9279V(A-83-PF100): 32K * 16
AL5DS9269V(A-100-PF100): 16K * 16
AL5DS9269V(A-83-PF100): 16K * 16
Note 1: pins 6 and 70 are NC for AL5DS9269V
A9L
A10L
A11L
A12L
A13L
[NC]A14L
GND
LBL
NC
CE0L
CE1L
CNTRSTL
VCC
R/WL
OEL
PIPE/FTL
NC
I/O14L
I/O15L
I/O12L
I/O13L
I/O10L
I/O11L
GND
GND
I/O11R
PIPE/FTR
OER
R/WR
I/O15R
I/O14R
I/O13R
I/O12R
LBR
UBR
CE0R
CE1R
CNTRSTR
A9R
A10R
A11R
A12R
A13R
A14R[NC]
GND
A8L
A3L
A4L
A5L
A6L
A7L
A0L
A1L
A2L
ADSL
CLKL
CNTENL
ADSR
CLKR
CNTENR
A0R
A3R
A4R
A5R
A1R
A2R
A6R
A7R
GND
GND
VCC
I/O9L
I/O8L
I/O7L
I/O6L
I/O3L
I/O2L
I/O1L
I/O0L
I/O5L
I/O4L
VCC
I/O1R
I/O0R
I/O3R
I/O2R
I/O5R
I/O4R
I/O7R
I/O6R
I/O9R
I/O8R
NC
72
73
74
75
68
69
70
71
64
65
66
67
60
61
62
63
56
57
58
59
52
53
54
55
51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
11
10
9
8
7
6
5
4
3
2
25
24
23
22
21
20
19
18
17
16
15
14
13
12
39
40
44
43
42
41
50
45
49
48
47
46
26
27
31
30
29
28
37
32
36
35
34
33
38
LBL
NC
I/O10R
NC
NC
A8R
NC
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 12
100 pin 14mm*14mm*1.4mm TQFP package-3:
100-Pin TQFP (Top View)
AL5DS9189V(A-100-PF100): 64K * 9
AL5DS9189V(A-83-PF100): 64K * 9
AL5DS9179V(A-100-PF100): 32K * 9
AL5DS9179V(A-83-PF100): 32K * 9
AL5DS9169V(A-100-PF100): 16K * 9
AL5DS9169V(A-83-PF100): 16K * 9
AL5DS9159V(A-100-PF100): 8K * 9
AL5DS9159V(A-83-PF100): 8K * 9
AL5DS9149V(A-100-PF100): 4K * 9
AL5DS9149V(A-83-PF100): 4K * 9
Note 1: pins 11 and 65 are NC for AL5DS9179V/69V/59V/49V
Note 2: pins 10 and 66 are NC for AL5DS9169V/59V/49V
Note 3: pins 9 and 67 are NC for AL5DS9159V/49V
Note 4: pins 8 and 68 are NC for AL5DS9149V
NC
A7L
A8L
[NC]A12L
[NC]A13L
[NC]A14L
NC
NC
CE0L
CE1L
CNTRSTL
VCC
R/WL
OEL
PIPE/FTL
[NC]A15L
GND
GND
PIPE/FTR
OER
R/WR
CE0R
CE1R
CNTRSTR
A9R
A10R
A11R
A12R[NC]
A13R[NC]
GND
NC
A3L
A4L
A5L
A6L
NC
A0L
A1L
A2L
ADSL
CLKL
CNTENL
ADSR
CLKR
CNTENR
A0R
A3R
A4R
A5R
A1R
A2R
A6R
GND
GND
VCC
GND
I/O8L
I/O7L
I/O6L
I/O3L
I/O2L
I/O1L
I/O0L
I/O5L
I/O4L
VCC
I/O1R
I/O0R
I/O3R
I/O2R
I/O5R
I/O4R
I/O7R
I/O6R
NC
I/O8R
NC
72
73
74
75
68
69
70
71
64
65
66
67
60
61
62
63
56
57
58
59
52
53
54
55
51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
11
10
9
8
7
6
5
4
3
2
25
24
23
22
21
20
19
18
17
16
15
14
13
12
39
40
44
43
42
41
50
45
49
48
47
46
26
27
31
30
29
28
37
32
36
35
34
33
38
NC
NC
NC
GND
NC
NC
NC
NC
NC
NC
A9L
A10L
A11L
NC
NC
NC
NC
NC
A8R
A7R
A14R[NC]
A15R[NC]
NC
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 13
100 pin 14mm*14mm*1.4mm TQFP package-4:
100-Pin TQFP (Top View)
AL5DS9089V(A-100-PF100): 64K * 8
AL5DS9089V(A-83-PF100): 64K * 8
AL5DS9079V(A-100-PF100): 32K * 8
AL5DS9079V(A-83-PF100): 32K * 8
AL5DS9069V(A-100-PF100): 16K * 8
AL5DS9069V(A-83-PF100): 16K * 8
Note 1: pins 11 and 65 are NC for AL5DS9079V/69V
Note 2: pins 10 and 66 are NC for AL5DS9069V
NC
A7L
A8L
A12L
A13L
[NC]A14L
NC
NC
CE0L
CE1L
CNTRSTL
VCC
R/WL
OEL
PIPE/FTL
[NC]A15L
GND
GND
PIPE/FTR
OER
R/WR
CE0R
CE1R
CNTRSTR
A9R
A10R
A11R
A12R
A13R
GND
NC
A3L
A4L
A5L
A6L
NC
A0L
A1L
A2L
ADSL
CLKL
CNTENL
ADSR
CLKR
CNTENR
A0R
A3R
A4R
A5R
A1R
A2R
A6R
GND
GND
VCC
GND
NC
I/O7L
I/O6L
I/O3L
I/O2L
I/O1L
I/O0L
I/O5L
I/O4L
VCC
I/O1R
I/O0R
I/O3R
I/O2R
I/O5R
I/O4R
I/O7R
I/O6R
NC
NC
NC
72
73
74
75
68
69
70
71
64
65
66
67
60
61
62
63
56
57
58
59
52
53
54
55
51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
11
10
9
8
7
6
5
4
3
2
25
24
23
22
21
20
19
18
17
16
15
14
13
12
39
40
44
43
42
41
50
45
49
48
47
46
26
27
31
30
29
28
37
32
36
35
34
33
38
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A9L
A10L
A11L
NC
NC
NC
NC
NC
A8R
A7R
A14R[NC]
A15R[NC]
NC
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 14
7 Pin Definition and Description
The pin-out definitions are described as follows:
Left Port Right Port I/O
type
Description
A0L~A16L A
0R~A16R I Address bus.
/ADSL /ADSR I
A
ddress Strobe. Low active. Asserting this signal LOW
w
hile using an external address will access the port. /ADS
i
s only dependent of /CNTRST control signal.
/CNTENL /CNTENR I Counter Enable. Low active. When counter is enabled, the
i
nternal address counter increments one on each rising
edge of CLK regardless of Chip Enable and Lower Byte
or Upper Byte Selects.
/CNTRSTL /CNTRSTR I Counter Reset. Low active. Resets the internal address
counter to zero. This signal is independent of all other
control signals.
/CE0L, CE1L /CE0R, CE1R I Chip Enable. Low active for Chip Enable 0 and High
active for Chip Enable 1.
CLKL CLKR I Clock input.
I/O0L~I/O17L I/O0R~I/O17R I/O
D
ata bus.
/LBL /LBR I
L
ower Byte Select. Low active. Enables the read and
w
rite operations to the lower byte (I/O0-I/O8 for 18 bit
devices, I/O0-I/O7 for 16 bit devices) while asserting this
signal Low. Not available for 8/9 bit devices.
/UBL /UBR I
U
pper Byte Select. Low active. Enables the read and write
opera
t
ions to the upper byte (I/O9-I/O17 for 18 bit devices,
I
/O8-I/O15 for 16 bit devices) while asserting this signal
L
ow. Not available for 8/9 bit devices.
/OEL /OER I Output Enable. Low active. Asynchronous input signal.
R/WL R/WR I
R
ead/Write Enable. High active for read operations and
L
ow active for write operations.
PIPE/FTL PIPE/FTR I
P
ipelined and Flow-Through Mode Select. High active for
P
ipelined mode and Low active for Flow-Through mode.
NC - No connection
Digital Power
VCC DP Digital power
GND DP Digital ground
Note: For I/O type, I, O, and DP indicate input, output, and digital power respectively.
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 15
For 18 or 16 bit devices, the truth table of read/write and enable control is as follows:
/CE0 CE1 CLK R/W /UB /LB /OE Upper byte Lower byte Note
X X X X X X H High-Z High-Z Outputs disabled
L H nH H L L High-Z Data output Read Lower byte only
L H nH L H L Data output High-Z Read Upper byte only
L H nH L L L Data output Data output Read both bytes
L H nL H L X High-Z Data input Write to Lower byte
L H nL L H X Data input High-Z Write to Upper byte
L H nL L L X Data input Data input Write to both bytes
X X nX H H X High-Z High-Z Both bytes disabled
H X nX X X X High-Z High-Z Chip disabled (Note 2)
X L nX X X X High-Z High-Z Chip disabled (Note 2)
Note 1: H, L, X, and n denote VIH, VIL, Don’t Care and Rising-Edge Trigger, respectively.
Note 2: For Pipelined mode, chip is disabled on the following clock cycle if /CE changes state.
For 9 or 8 bit devices, the truth table of read/write and enable control is as follows:
/CE0 CE1 CLK R/W /OE Data I/O Note
X X X X H High-Z Outputs disabled
L H nH L Data output Read operation
L H nL X Data input Write operation
H X nX X High-Z Chip disabled (Note 2)
X L nX X High-Z Chip disabled (Note 2)
Note 1: H, L, X, and n denote VIH, VIL, Don’t Care and Rising-Edge Trigger, respectively.
Note 2: For Pipelined mode, chip is disabled on the following clock cycle if /CE changes state.
The truth table of address counter control is as follows:
/CNTRST /ADS /CNTEN CLK Address
input
Previous
address
Internal
address Data I/O Note
L X X
nX X 0 Q0
Reset internal address
counter to 0
H L X
nAn X An Q
n
Load external address into
internal address counter
H H L
nX AP A
P+1 Q
P+1
Enable internal address
counter
H H L
nX Amax A
0 Q
0
Enable internal address
counter (Note 4)
H H H
nX AP A
P Q
P
Disable internal address
counter
Note 1: H, L, X, and n denote VIH, VIL, Don’t Care and Rising-Edge Trigger, respectively.
Note 2: Assuming /CE0, /UB, /LB, and /OE = VIL and assuming CE1 and R/W = VIH.
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 16
Note 3: Data I/O is configured in Flow-Through mode. For Pipelined mode, the data output will be
delayed by one cycle.
Note 4: Because the internal address counter will be larger than the maximum memory address, it
will not reset the internal address counter to 0 on the next clock cycle when the previous
internal address has encountered the maximum memory address. Therefore, the application
software should remember to load a new address into the internal address counter or to
invoke the /CNTRST signal to reset the internal address counter to 0 if the internal address
has encountered the maximum memory address.
8 Electrical Characteristics
8.1 Absolute Maximum Ratings
(Exceeding the rating can be harmful to product life. These are only user guidelines and are not
tested.)
Parameter 3.3V Rating Unit
VCC Supply Voltage -0.3 ~ +3.8 V
VP Input Pin Voltage -0.3 ~ +(VCC+0.3) V
IO Output Current -20 ~ +20 mA
TAMB Ambient Op. Temperature 0 ~ +85 °C
Tstg Storage Temperature -40 ~ +125 °C
TVSOL Vapor Phase Soldering
Temperature (15 Sec.)
220 °C
8.2 Recommended Operating Conditions
3.3V Rating
Parameter
Min. Typical Max.
Unit
VCC Supply Voltage +3.0 +3.3 +3.6 V
VIH High Level Input Voltage 0.7 VCC V
CC V
VIL Low Level Input Voltage 0 0.3 VCC V
TAMB Ambient Op. Temperature 0 +70 °C
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 17
8.3 DC Characteristics
(VCC = 3.3V, GND=0V. TAMB = 0 to 70°C) Note: Some parameters are guaranteed by
design only and are not production tested.
3.3V Rating
Parameter
Min. Typical Max.
Unit
VIH Hi-level Input Voltage 0.7 VCC - VCC V
VIL Lo-level Input Voltage 0 0.3 VCC V
VOH Hi-level Output Voltage (VCC =
Min., IOH = -4 mA)
2.4 - VCC V
VOL Lo-level Output Voltage (VCC =
Min., IOH = +4 mA)
- - +0.4 V
CIN Input Capacitance at VCC=3.3V,
TA=25°C and f=1MHz
10 pF
COUT Output Capacitance at VCC=3.3V,
TA=25°C and f=1MHz
10 pF
ILI Input Leakage Current (VCC =
3.6V, VIN = 0V~ VCC)
+5
PA
ILO Output Leakage Current (CE1 =
VIL, VOUT = 0V~ VCC)
+5
PA
IOZ 3-state Current (/OE = VIH) TBD PA
ICC Operating Current (VCC = Max.,
IOUT = 0 mA, outputs disabled)
TBD TBD mA
ISB1 Standby Current (Both ports are
TTL level inputs )
TBD TBD mA
ISB2 Standby Current (One port is TTL
level inputs )
TBD TBD mA
ISB3 Standby Current (Both ports are
CMOS level inputs )
TBD TBD PA
ISB4 Standby Current (One port is
CMOS level inputs )
TBD TBD mA
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 18
8.4 AC Test Loads
8.4.1 Normal Load (Load 1)
˜˂ˢˢ˨˧
ˈˌ˃:
ˇˆˈ:ˆ˃˙
ˆˁˆ˩
8.4.2 3-State Load (Load 2)
˜˂ˢˢ˨˧
:
ˇˆˈ:ˈ˙
ˆˁˆ˩
8.5 AC Characteristics
(VCC = 3.3V, GND=0V, TAMB = 0 to 70°C) Note: Some parameters are guaranteed by design
only and are not production tested.
3.3V Rating
-100 -83 Parameter
Min Max Min Max
Unit
Address Control
tADDRS Setup time for Address 3.5 4 ns
tADDRH Hold time for Address 0 0 ns
tINr Rising time for all control inputs 3 3 ns
tINf Falling time for all control inputs 3 3 ns
tADSS Setup time for /ADS 3.5 4 ns
tADSH Hold time for /ADS 0 0 ns
tCENS Setup time for /CNTEN 3.5 4.5 ns
tCENH Hold time for /CNTEN 0 0 ns
tCRSTS Setup time for /CNTRST 3.5 4 ns
tCRSTH Hold time for /CNTRST 0 0 ns
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 19
3.3V Rating
-100 -83 Parameter
Min Max Min Max
Unit
I/O Control
tINr Rising time for all control inputs 3 3 ns
tINf Falling time for all control inputs 3 3 ns
tCES Setup time for Chip Enable 3.5 4 ns
tCEH Hold time for Chip Enable 0 0 ns
tRWS Setup time for R/W 3.5 4 ns
tRWH Hold time for R/W 0 0 ns
tBS
Setup time for /UB and /LB (not for 8/9 bit
devices) 3.5 4 ns
tBH
Hold time for /UB and /LB (not for 8/9 bit
devices) 0 0 ns
tDAIS Setup time for input data 3.5 4 ns
tDAIH Hold time for input data 0 0 ns
tOE Output Enable to data valid 8 9 ns
tOELZ Output Enable to Low Z [1] 2 2 ns
tOEHZ Output Enable to High Z [1] 1 7 1 7 ns
tCDFT Clock to data valid of Flow-Through 15 18 ns
tCDPIPE Clock to data valid of Pipelined 6.5 7.5 ns
tCKLZ Clock High to Low Z [1] 2 2 ns
tCKHZ Clock High to High Z [1] 2 9 2 9 ns
tDAOH Data output hold time after Clock High 2 2 ns
tCWDD Write port Clock High to Read data delay 28 30 ns
Clock
fFT Frequency of Flow-Through 53 45
MHz
tFT Clock cycle time of Flow-Through 19 22 ns
GFT Duty Factor for Flow-Through (tFTH * fFT) 40 60 40 60 %
fPIPE Frequency of Pipelined 100 83
MHz
tPIPE Clock cycle time of Pipelined 10 12 ns
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 20
3.3V Rating
-100 -83 Parameter
Min Max Min Max
Unit
GPIPE Duty Factor for Pipelined (tPIPEH * fPIPE) 40 60 40 60 %
tr Rising time for Clock 3 3 ns
tf Falling time for Clock 3 3 ns
tCCS Setup time for Clock to Clock 9 10 ns
Note 1: The above parameters that use 3-State load (load 2) under test conditions are
guaranteed by design only.
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 21
9 Timing Diagrams
˖˗˙˧
ˢ˘
˖˞˟˭
˖˘˃
˖˘˄
˨˕ʿʳ˟˕
˥˂˪
˔˫˔ˬ˔˭˔
˔˷˷˸
˔˗˗˥˦ ˔˗˗˥˛
ˤ˫ˤˬˤ˭
ʳ˗˔˧˔ʳ˜˂ˢ
˗˔ˢ˛ ˖˞˛˭
ˢ˘
ˢ˘˛˭ ˢ˘˟˭
˖˘˦ ˖˘˛
˕˦ ˕˛
˥˪˦ ˥˪˛
˖˘˦ ˖˘˛
˕˦ ˕˛
˖˟˞ ˙˧˛
˙˧˟
˙˧
˥˸˴˷ʳ˖˶˿˸ʳ˹ʳ˙˿ˀ˧˻˺˻ʳˠ˷˸
ˡ˸ʳ˄ˍʳˣ˜ˣ˘˂˙˧ʳ˴˷ʳ˔˗˦ː˩˜˟ʿʳ˖ˡ˧˘ˡʳ˴˷ʳ˖ˡ˧˥˦˧ʳːʳ˩˜˛
ˡ˸ʳ˅ˍʳ˨˕ʳ˴˷ʳ˟˕ʳ˴˸ʳ˿ʳ˴˴˼˿˴˵˿˸ʳ˹ʳ˄ˉ˂˄ˋʳ˵˼ʳ˷˸˼˶˸ˁ
˹
˜ˡ ˜ˡ˹
˜ˡ
˜ˡ˹
˜ˡ
˜ˡ˹
˜ˡ
˜ˡ˹
˥˸˴˷ʳ˖˶˿˸ʳ˹ʳˣ˼˸˿˼˸˷ʳˠ˷˸
˖˗ˣ˜ˣ˘
ˢ˘
˖˘˃
˖˘˄
˨˕ʿʳ˟˕
˥˂˪
˔˫˔ˬ˔˭˔
˔˷˷˸
˔˗˗˥˦ ˔˗˗˥˛
ˤ˫ˤˬˤ˭
ʳ˗˔˧˔ʳ˜˂ˢ
˗˔ˢ˛
ˢ˘
ˢ˘˛˭ ˢ˘˟˭
˖˘˦ ˖˘˛
˕˦ ˕˛
˥˪˦ ˥˪˛
˖˘˦ ˖˘˛
˕˦ ˕˛
˖˟˞ ˣ˜ˣ˘˛
ˣ˜ˣ˘˟
ˣ˜ˣ˘ ˹
˖˞˟˭
ʳʳʳʳʳʳʳʳʳʳʳʳ˄ʳ˟˴˸˶
ˡ˸ʳ˄ˍʳ˔˗˦ː˩˜˟ʿʳˣ˜ˣ˘˂˙˧ʳʿʳ˖ˡ˧˘ˡʳ˴˷ʳ˖ˡ˧˥˦˧ʳːʳ˩˜˛
ˡ˸ʳ˅ˍʳˤ˭ʳ˿˷ʳ˵˸ʳ˷˼˴˵˿˸˷ʳ˼˹ʳ˨˕ʳ˴˷˂ʳ˟˕ʳ˴ʳ˛˼˺˻ˁʳ˨˕ʳ˴˷ʳ˟˕ʳ˴˸ʳ˿ʳ˹ʳ˄ˉ˂˄ˋʳ˵˼ʳ˷˸˼˶˸ˁ
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 22
˟˸˹ʳˣʳ˪˼˸ʳʳ˙˿ˀ˧˻˺˻ʳ˥˼˺˻ʳˣʳ˥˸˴˷
˥˂˪˟˥˪˦ ˥˪˛
˖˟˞˟
ˡ
ˠ˴˶˻
˔˷˷˸˟
ʳ˗˔˧˔ˀ˜˟
ˠ˴˶˻
˔˗˗˥˦ ˔˗˗˥˛
˩˴˿˼˷
˗˔˜˦ ˗˔˜˛
˖˟˞˥
˖˖˦
˖˪˗˗
˖˗˙˧
˥˂˪˥
˔˷˷˸˥
ʳ˗˔˧˔ˀˢ˥
˥˪˦ ˥˪˛
ˠ˴˶˻
˔˗˗˥˦ ˔˗˗˥˛
˗˔ˢ˛
˩˴˿˼˷
ˡ
ˠ˴˶˻
˗˔ˢ˛
˩˴˿˼˷
˖˗˙˧
ˡ˸˄ˍʳʳ˜˹ʳ˧˖˖˦ʳˑʳ˴˼ʳ˸˶˼˹˼˸˷ʿʳ˻˸ʳ˷˴˴ʳ˼ʳʳ˴˿˼˷ʳ˼˿ʳ˧˖˖˦ʾ˧˖˗˙˧ʳ˴˷ʳ˼˺˸ʳ˧˖˪˗˗ˁ
ˡ˸˅ˍʳˢ˘˥ʿʳ˖˘˃ʳʿʳ˨˕ʿʳ˟˕ʿʳˣ˜ˣ˘˂˙˧ʳ˴˷ʳ˔˗˦ː˩˜˟ʿʳˢ˘˟ʿʳ˖˘˄ʿʳ˖ˡ˧˘ˡʳ˴˷ʳ˖ˡ˧˥˦˧ʳːʳ˩˜˛
˕˴˾ʳ˦˸˿˸˶ʳˣ˼˸˿˼˸˷ʳ˥˸˴˷
˖˘˛
˖˟˞ ˣ˜ˣ˘˛
ˣ˜ˣ˘˟
ˣ˜ˣ˘ ˹
˖˘˦
˖˘˦ ˖˘˛
˔˫˔ˬ˔
˔˗˗˥˦ ˔˗˗˥˛
ˤˬ
˖˞˛˭
˔˫˔ˬ˔
˔˷˷˸ʻ˔ʼ
˔˗˗˥˦ ˔˗˗˥˛
ʳ˗˔˧˔ʳ˜˂ˢʻ˔ʼ
˖˗ˣ˜ˣ˘
˖˞˛˭
ˤ˫
˖˘˃ʻ˔ʼ
˗˔ˢ˛
ˤ˭
˖˞˟˭
˖˗ˣ˜ˣ˘
˖˘˃ʻ˕ʼ
˔˷˷˸ʻ˕ʼ
ʳ˗˔˧˔ʳ˜˂ˢʻ˕ʼ
˖˘˛
˖˘˦
˖˘˛
˖˘˦
˖˞˟˭
˖˗ˣ˜ˣ˘
ˡ˸ʳ˄ˍʳ˨˕ʿʳ˟˕ʿʳˢ˘ʳ˴˷ʳ˔˗˦ː˩˜˟ʿʳ˖˘˄ʻ˔ʼʿʳ˖˘˄ʻ˕ʼʿʳ˥˂˪ʿʳˣ˜ˣ˘˂˙˧ʿʳ˖ˡ˧˘ˡʳ˴˷ʳ˖ˡ˧˥˦˧ʳːʳ˩˜˛
ˡ˸ʳ˅ˍʳ˘˴˶˻ʳ˵˴˾ʳ˶˼ʳ˹ʳ˸ʳ˔˸˟˺˼˶ʳ˷˴˿ʳʳ˦˥˔ˠʳ˹ʳ˻˼ʳ˴˸˹ˁʳ˔˷˷˸ʻ˔ʼʳːʳ˔˷˷˸ʻ˕ʼ
˔˭
˔˭
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 23
ˣ˼˸˿˼˸˷ʳ˥˸˴˷ˀˀ˪˼˸ˀˀ˥˸˴˷ʳˠ˷˸ʳʻˢ˘ʳːʳ˩˜˟ʼ
ˡ˸ʳ˄ˍʳ˖˘˃ʿʳ˨˕ʿʳ˟˕ʳ˴˷ʳ˔˗˦ː˩˜˟ʿʳ˖˘˄ʿʳˣ˜ˣ˘˂˙˧ʳʿʳ˖ˡ˧˘ˡʳ˴˷ʳ˖ˡ˧˥˦˧ʳːʳ˩˜˛
ˡ˸ʳ˅ˍʳˢʳ˴˸ʳ˼ʳ˷˸˸˼˸˷ʳ˵ʳ˻˸ʳ˸˼ʳ˶˶˿˸ʳ˶˿ʳ˼˺˴˿ˁ
ˡ˸ʳˆˍʳ˗˴˴ʳ˼ʳ˸ʳ˴ʳ˻˸ʳ˸˿˸˶˸˷ʳ˴˷˷˸ʳ˻˿˷ʳ˵˸ʳ˸ˀ˼˸ʳʳ˸˸ʳ˷˴˴ʳ˼˸˺˼ʳ˷˼˺ʳˡʳˢ˸˴˼ʳ˶˶˿˸ˁ
˥˂˪
˔˔ʾ˄ ˔ʾ˅
˔˷˷˸
˔˗˗˥˦ ˔˗˗˥˛
˥˪˦
˥˪˛
˖˟˞ ˣ˜ˣ˘˛
ˣ˜ˣ˘˟
ˣ˜ˣ˘ ˹
˔ʾ˅
˥˪˦ ˥˪˛
˔ʾˆ ˔ʾˇ
ʳ˗˔˧˔˜ˡ
˗˔˜˦
ˤˤʾˆ
˗˔˧˔ˢ˨˧
˖˞˟˭
˗ʾ˅
˗˔˜˛
˖˗ˣ˜ˣ˘ ˖˞˛˭
˖˗ˣ˜ˣ˘
ˡʳˢ˸˴˼ ˪˼˸˥˸˴˷ ˥˸˴˷
ˣ˼˸˿˼˸˷ʳ˥˸˴˷ˀˀ˪˼˸ˀˀ˥˸˴˷ʳˠ˷˸ʳʻˢ˘ʳʳ˶˿˿˸˷ʼ
ˡ˸ʳ˄ˍʳ˖˘˃ʿʳ˨˕ʿʳ˟˕ʳ˴˷ʳ˔˗˦ː˩˜˟ʿʳ˖˘˄ʿʳˣ˜ˣ˘˂˙˧ʳʿʳ˖ˡ˧˘ˡʳ˴˷ʳ˖ˡ˧˥˦˧ʳːʳ˩˜˛
ˡ˸ʳ˅ˍʳˢʳ˴˸ʳ˼ʳ˷˸˸˼˸˷ʳ˵ʳ˻˸ʳ˸˼ʳ˶˶˿˸ʳ˶˿ʳ˼˺˴˿ˁ
˥˂˪
˔˔ʾ˄ ˔ʾ˅
˔˷˷˸
˔˗˗˥˦ ˔˗˗˥˛
˥˪˦
˥˪˛
˖˟˞ ˣ˜ˣ˘˛
ˣ˜ˣ˘˟
ˣ˜ˣ˘ ˹
˔ʾˆ
˥˪˦ ˥˪˛
˔ʾˇ ˔ʾˈ
ʳ˗˔˧˔˜ˡ
ˤˤʾˇ
˗˔˧˔ˢ˨˧
˖˞˟˭
˗ʾˆ
˖˗ˣ˜ˣ˘
ˢ˘˛˭
˖˗ˣ˜ˣ˘
˗ʾ˅
˗˔˜˦ ˗˔˜˛
˗˔˜˦ ˗˔˜˛
˪˼˸˥˸˴˷ ˥˸˴˷
ˢ˘
˜ˡ ˜ˡ˹
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 24
˙˿ˀ˧˻˺˻ʳ˥˸˴˷ˀˀ˪˼˸ˀˀ˥˸˴˷ʳˠ˷˸ʳʻˢ˘ʳːʳ˩˜˟ʼ
ˡ˸ʳ˄ˍʳ˖˘˃ʿʳ˨˕ʿʳ˟˕ʿʳˣ˜ˣ˘˂˙˧ʿʳ˴˷ʳ˔˗˦ː˩˜˟ʿʳ˖˘˄ʿʳ˖ˡ˧˘ˡʳ˴˷ʳ˖ˡ˧˥˦˧ʳːʳ˩˜˛
ˡ˸ʳ˅ˍʳˢʳ˴˸ʳ˼ʳ˷˸˸˼˸˷ʳ˵ʳ˻˸ʳ˸˼ʳ˶˶˿˸ʳ˶˿ʳ˼˺˴˿ˁ
ˡ˸ʳˆˍʳ˗˴˴ʳ˼ʳ˸ʳ˴ʳ˻˸ʳ˸˿˸˶˸˷ʳ˴˷˷˸ʳ˻˿˷ʳ˵˸ʳ˸ˀ˼˸ʳʳ˸˸ʳ˷˴˴ʳ˼˸˺˼ʳ˷˼˺ʳˡʳˢ˸˴˼ʳ˶˶˿˸ˁ
˥˂˪
˔˔ʾ˄ ˔ʾ˅
˔˷˷˸
˔˗˗˥˦ ˔˗˗˥˛
˥˪˦
˥˪˛
˖˟˞ ˙˧˛
˙˧˟
˙˧ ˹
˔ʾ˅
˥˪˦ ˥˪˛
˔ʾˆ ˔ʾˇ
ʳ˗˔˧˔˜ˡ
˗˔˜˦
ˤʾˆ
˗˔˧˔ˢ˨˧
˖˞˟˭
˗ʾ˅
˗˔˜˛
˖˗˙˧ ˖˞˛˭ ˖˗˙˧
ˡʳˢ˸˴˼ ˪˼˸˥˸˴˷ ˥˸˴˷
ˤ
˗˔ˢ˛
˖˗˙˧
ˤʾ˄
˗˔ˢ˛
˖˗˙˧
˙˿ˀ˧˻˺˻ʳ˥˸˴˷ˀˀ˪˼˸ˀˀ˥˸˴˷ʳˠ˷˸ʳʻˢ˘ʳʳ˶˿˿˸˷ʼ
ˡ˸ʳ˄ˍʳ˖˘˃ʿʳ˨˕ʿʳ˟˕ʿʳˣ˜ˣ˘˂˙˧ʳ˴˷ʳ˔˗˦ː˩˜˟ʿʳ˖˘˄ʿʳ˖ˡ˧˘ˡʳ˴˷ʳ˖ˡ˧˥˦˧ʳːʳ˩˜˛
ˡ˸ʳ˅ˍʳˢʳ˴˸ʳ˼ʳ˷˸˸˼˸˷ʳ˵ʳ˻˸ʳ˸˼ʳ˶˶˿˸ʳ˶˿ʳ˼˺˴˿ˁ
˥˂˪
˔˔ʾ˄ ˔ʾ˅
˔˷˷˸
˔˗˗˥˦ ˔˗˗˥˛
˥˪˦
˥˪˛
˖˟˞ ˙˧˛
˙˧˟
˙˧ ˹
˔ʾˆ
˥˪˦ ˥˪˛
˔ʾˇ ˔ʾˈ
ʳ˗˔˧˔˜ˡ
ˤˤʾˇ
˗˔˧˔ˢ˨˧
˖˞˟˭
˗ʾˆ
˖˗˙˧
ˢ˘˛˭
˖˗˙˧
˗ʾ˅
˗˔˜˦ ˗˔˜˛
˗˔˜˦ ˗˔˜˛
˪˼˸˥˸˴˷ ˥˸˴˷
ˢ˘
˜ˡ
˗˔ˢ˛
˜ˡ˹
˖˗˙˧
ˢ˘
˗˔ˢ˛
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 25
ˣ˼˸˿˼˸˷ʳ˥˸˴˷ʳ˼˻ʳ˜˸˴˿ʳ˔˷˷˸ʳ˖˸ʳ˘˴˵˿˸
ˡ˸ʳ˄ˍʳ˖˘˃ʿʳ˨˕ʿʳ˟˕ʳ˴˷ʳˢ˘ː˩˜˟ʿʳ˖˘˄ʿʳˣ˜ˣ˘˂˙˧ʳʿʳ˥˂˪ʳ˴˷ʳ˖ˡ˧˥˦˧ʳːʳ˩˜˛
˔
˔˷˷˸
˔˗˗˥˦ ˔˗˗˥˛
˖˟˞ ˣ˜ˣ˘˛
ˣ˜ˣ˘˟
ˣ˜ˣ˘ ˹
ˤˤʾˆ
˗˔˧˔ˢ˨˧
˔˗˦˛
˖˗ˣ˜ˣ˘
˗˔ˢ˛
˥˸˴˷ʳ˼˻ʳ˖˸ ˖˸
˛˿˷
˥˸˴˷
˘˸˴˿
˔˷˷˸
˥˸˴˷ʳ˼˻
˖˸
˔˗˦
˔˗˦˦
˔˗˦˛
˔˗˦˦
˖ˡ˧˘ˡ
˖˘ˡ˦
˖˘ˡ˛
˖˘ˡ˦
˖˘ˡ˛
ˤˤˤʾ˄ ˤʾ˅
˙˿ˀ˧˻˺˻ʳ˥˸˴˷ʳ˼˻ʳ˜˸˴˿ʳ˔˷˷˸ʳ˖˸ʳ˘˴˵˿˸
ˡ˸ʳ˄ˍʳ˖˘˃ʿʳ˨˕ʿʳ˟˕ʿʳˣ˜ˣ˘˂˙˧ʳ˴˷ʳˢ˘ː˩˜˟ʿʳ˖˘˄ʿʳ˥˂˪ʳ˴˷ʳ˖ˡ˧˥˦˧ʳːʳ˩˜˛
˔
˔˷˷˸
˔˗˗˥˦ ˔˗˗˥˛
˖˟˞ ˙˧˛
˙˧˟
˙˧ ˹
ˤˤʾˇ
˗˔˧˔ˢ˨˧
˔˗˦˛
˖˗˙˧
˗˔ˢ˛
˥˸˴˷ʳ˼˻ʳ˖˸ ˖˸
˛˿˷
˥˸˴˷
˘˸˴˿
˔˷˷˸
˥˸˴˷ʳ˼˻
˖˸
˔˗˦
˔˗˦˦
˔˗˦˛
˔˗˦˦
˖ˡ˧˘ˡ
˖˘ˡ˦
˖˘ˡ˛
˖˘ˡ˦
˖˘ˡ˛
ˤˤʾ˄ ˤʾ˅ ˤʾˆ
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 26
ˣ˼˸˿˼˸˷˂˙˿ˀ˧˻˺˻ʳ˪˼˸ʳ˼˻ʳ˜˸˴˿ʳ˔˷˷˸ʳ˖˸ʳ˘˴˵˿˸
ˡ˸ʳ˄ˍʳ˖˘˃ʿʳ˨˕ʿʳ˟˕ʿʳ˴˷ʳ˥˂˪ʳː˩˜˟ʿʳˢ˘ʿʳ˖˘˄ʿʳ˴˷ʳ˖ˡ˧˥˦˧ʳːʳ˩˜˛
ˡ˸ʳ˅ˍʳˣ˼˸˿˼˸˷ʳ˷˸ʳ˼ʳ˻˸ʳ˴˸ʳ˴ʳ˙˿ˀ˧˻˺˻ʳ˷˸ˁ
˔
˔˷˷˸
˔˗˗˥˦ ˔˗˗˥˛
˖˟˞ ˙˧˛
˙˧˟
˙˧ ˹
˔˗˦˛
˔˗˦
˔˗˦˦
˔˗˦˛
˔˗˦˦
˖ˡ˧˘ˡ
˖˘ˡ˦
˖˘ˡ˛
˖˘ˡ˦
˖˘ˡ˛
˗˔˜˦
˪˼˸ʳ˼˻ʳ˖˸ ˖˸
˛˿˷
˪˼˸
˘˸˴˿
˔˷˷˸
˪˼˸ʳ˼˻
˖˸
˗ʾˈ
ʳ˗˔˧˔˜ˡ
˗˔˜˛
˗˗ʾ˄ ˗ʾ˅ ˗ʾˇ
˔ʾˇ
˜˸˴˿
˔˷˷˸ ˔˔ʾ˄ ˔ʾ˅ ˔ʾˆ
˗ʾ˅ ˗ʾˆ
˖˸ʳ˥˸˸ʳ˼ʳˣ˼˸˿˼˸˷ʳˠ˷˸
ˡ˸ʳ˄ˍʳ˖˘˃ʿʳ˨˕ʿʳ˟˕ʳ˴˷ʳˢ˘ʳː˩˜˟ʿʳ˖˘˄ʳ˴˷ʳˣ˜ˣ˘˂˙˧ʳːʳ˩˜˛
ˡ˸ʳ˅ˍʳ˧˻˸˸ʳ˸˼ʳʳ˷˸˴˷ʳ˶˶˿˸ʳ˷˼˺ʳ˶˸ʳ˸˸ˁ
˔˗˦˛
˔˗˦
˔˗˦˦ ˔˗˦˛
˔˗˦˦
˖˘ˡ˛
˔ʾ˄
˜˸˴˿
˔˷˷˸ ˔˫˃˄ ˔
ˤ
˗˔˧˔ˢ˨˧ ˤ˄
ˤ˃
ʳ˗˔˧˔˜ˡ ˗˃
˗˔˜˦ ˗˔˜˛
˔˗˗˥˦ ˔˗˗˥˛
˖˟˞ ˣ˜ˣ˘˛
ˣ˜ˣ˘˟ ˹
˔˷˷˸ ˔˔ʾ˄
ˣ˜ˣ˘
˖˥˦˧˦
˖ˡ˧˘ˡ
˖˘ˡ˦ ˖˘ˡ˦
˖˘ˡ˛
˖ˡ˧˥˦˧
˖˥˦˧˛
˥˂˪
˪˼˸ʳ˼˻
˖˸ʳ˥˸˸
˪˼˸
˔˷˷˸ʳ˃
˥˸˴˷
˔˷˷˸ʳ˃
˥˸˴˷
˔˷˷˸ʳ˄
˥˸˴˷
˔˷˷˸ʳ
˥˸˴˷
˔˷˷˸
ʾ˄
˥˪˛
˥˪˦
˥˪˛
˥˪˦
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 27
10 Mechanical Drawing
128 PIN 14mm*20mm*1.4mm TQFP:
MILLIMETER INCH
SYMBOL
MIN. NOM. MAX. MIN. NOM. MAX.
b0.17 0.20 0.27 0.007 0.008 0.011
e0.50 BSC. 0.020 BSC.
D2 18.50 0.728
E2 12.50 0.492
TOLERANCES OF FORM AND POSITION
aaa 0.20 0.008
bbb 0.20 0.008
ccc 0.08 0.003
ddd 0.08 0.003
NOTES:
1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per
side. D1 and E1 are maximum plastic body size dimensions that include mold mismatch.
2. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not
cause the lead width to exceed the maximum “b” dimension by more than 0.08mm. Dambar
cannot be located on the lower radius or the foot. Minimum space between protrusion and an
adjacent lead is 0.07mm (for 0.4mm and 0.5mm pitch packages).
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 28
100 PIN 14mm*14mm*1.4mm TQFP:
MILLIMETER INCH
SYMBOL
MIN. NOM. MAX. MIN. NOM. MAX.
b0.17 0.20 0.27 0.007 0.008 0.011
e0.50 BSC. 0.020 BSC.
D2 12.00 0.472
E2 12.00 0.472
TOLERANCES OF FORM AND POSITION
aaa 0.20 0.008
bbb 0.20 0.008
ccc 0.08 0.003
ddd 0.08 0.003
NOTES:
1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per
side. D1 and E1 are maximum plastic body size dimensions that include mold mismatch.
2. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not
cause the lead width to exceed the maximum “b” dimension by more than 0.08mm. Dambar
cannot be located on the lower radius or the foot. Minimum space between protrusion and an
adjacent lead is 0.07mm (for 0.4mm and 0.5mm pitch packages).
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.6 29
CONTACT INFORMATION
Averlogic Technologies Corp.
4F, No. 514, Sec. 2, Cheng Kung Rd., Nei-Hu Dist., Taipei, Taiwan
Tel: +886 2-27915050
Fax: +886 2-27912132
E-mail: sales@averlogic.com.tw
URL: http://www.averlogic.com.tw
Averlogic Technologies, Inc.
90 Great Oaks Blvd. #204, San Jose, CA 95119,U.S.A.
Tel: 1 408 361-0400
Fax: 1 408 361-0404
E-mail: sales@averlogic.com
URL: http://www.averlogic.com
