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SLRS049C − FEBRUAR Y1997 − REVISED AUGUST 2004
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D500-mA Rated Collector Current (Single
Output)
DHigh-Voltage Outputs ...50 V
DOutput Clamp Diodes
DInputs Compatible With Various Types of
Logic
DRelay Driver Applications
DCompatible with ULN2800A Series
description/ordering information
The ULN2803A is a high-voltage, high-current Darlington
transistor array. The device consists of eight npn Darlington pairs
that feature high-voltage outputs with common-cathode clamp
diodes for switching inductive loads. The collector-current rating of
each Darlington pair is 500 mA. The Darlington pairs may be
connected in parallel for higher current capability.
Applications include relay drivers, hammer drivers, lamp drivers, display drivers (LED and gas discharge), line
drivers, and logic buffers. The ULN2803A has a 2.7-kseries base resistor for each Darlington pair for operation
directly with TTL or 5-V CMOS devices.
ORDERING INFORMATION
TAPACKAGEORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP (N) Tube of 20 ULN2803AN ULN2803AN
−40°C to 85°C
SOIC (DW)
Tube of 40 ULN2803ADW
ULN2803A
−40 C to 85 C
SOIC (DW)
Reel of 2000 ULN2003ADWR
ULN2803A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
1B
2B
3B
4B
5B
6B
7B
8B
GND
1C
2C
3C
4C
5C
6C
7C
8C
COM
DW OR N PACKAGE
(TOP VIEW)
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SLRS049C − FEBRUAR Y1997 − REVISED AUGUST 2004
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram
8C
7C
6C
5C
4C
3C
2C
7
6
5
4
3
2
1
7B
6B
5B
4B
3B
2B
1B
11
12
13
14
15
16
17
COM
8
8B 10
1C
18
schematic (each Darlington pair)
2.7 k
7.2 k3 k
COM
Output C
E
Input B
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SLRS049C − FEBRUAR Y1997 − REVISED AUGUST 2004
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)
Collector-emitter voltage 50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous collector current 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp diode current 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total substrate-terminal current −2.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Notes 2 and 3): DW package TBD°C/W. . . . . . . . . . . . . . . . . . . . . . . .
N package TBD°C/W. . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, unless otherwise noted, are with respect to the emitter/substrate terminal GND.
2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can af fect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
electrical characteristics at 25°C free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICEX Collector cutoff current VCE = 50 V,
See Figure 1 II = 0, 50 µA
II(off) Off-state input current VCE = 50 V,
TA = 70°C, IC = 500 µA,
See Figure 2 50 65 µA
II(on) Input current VI = 3.85 V, See Figure 3 0.93 1.35 mA
VCE = 2 V,
IC = 200 mA 2.4
V
I(on)
On-state input voltage VCE = 2 V,
See Figure 4
IC = 250 mA 2.7 V
VI(on)
On-state input voltage
See Figure 4
IC = 300 mA 3
V
II = 250 µA,
See Figure 5 IC = 100 mA, 0.9 1.1
VCE(sat
)
Collector-emitter saturation voltage II = 350 µA,
See Figure 5 IC = 200 mA, 1 1.3 V
II = 500 µA,
See Figure 5 IC = 350 mA, 1.3 1.6
IRClamp diode reverse current VR = 50 V, See Figure 6 50 µA
VFClamp diode forward voltage IF = 350 mA, See Figure 7 1.7 2 V
CiInput capacitance VI = 0 V, f = 1 MHz 15 25 pF
switching characteristics at 25°C free-air temperature
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output
VS = 50 V,
RL = 163
,
130
ns
tPHL Propagation delay time, high- to low-level output
VS = 50 V,
CL = 15 pF,
RL = 163 ,
See Figure 8 20 ns
VOH High-level output voltage after switching VS = 50 V,
See Figure 9 IO 300 mA, VS − 20 mV
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SLRS049C − FEBRUAR Y1997 − REVISED AUGUST 2004
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 1. ICEX Test Circuit
Open VCE
ICEX
Open
Figure 2. II(off) Test Circuit
Open VCE
IC
II(off)
Figure 3. II(on) Test Circuit
Open
II
OpenVI
Figure 4. VI(on) Test Circuit
Open
VCE
IC
VI
Figure 5. hFE, VCE(sat) Test Circuit
Open
VCE
IC
II
hFE = IC
II
Figure 6. IR Test Circuit
VR
Open
IR
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SLRS049C − FEBRUAR Y1997 − REVISED AUGUST 2004
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PARAMETER MEASUREMENT INFORMATION
Figure 7. VF Test Circuit
Open
VF
IF
NOTES: A. The pulse generator has the following characteristics: PRR = 1 MHz, ZO = 50 .
B. CL includes probe and jig capacitance.
C. VIH = 3 V Figure 8. Propagation Delay Times
Pulse
Generator
(see Note A)
Input Open VS = 50 V
RL = 163
CL = 15 pF
(see Note B)
Output
tPHL tPLH
0.5 µs
<5 ns <10 ns
90%
50%
10% 10%
90% 50%
50% 50%
VIH
(see Note C)
Input
Output
0
Test Circuit
Voltage Waveforms
VOH
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SLRS049C − FEBRUAR Y1997 − REVISED AUGUST 2004
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PARAMETER MEASUREMENT INFORMATION
NOTES: A. The pulse generator has the following characteristics: PRR = 12.5 KHz, ZO = 50 .
B. CL includes probe and jig capacitance.
C. VIH = 3 V Figure 9. Latch-Up Test
Pulse
Generator
(see Note A)
Input
VS
163
CL = 15 pF
(see Note B)
Output
40 µs
<5 ns <10 ns
90%
1.5 V
10% 10%
90% 1.5 V
VIH
(see Note C)
Input
Output
0
2 mH
VOH
Test Circuit
Voltage Waveforms
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SLRS049C − FEBRUAR Y1997 − REVISED AUGUST 2004
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