PE29102
High-speed FET Driver
Page 8 DOC-81227-4 – (10/2017)
www.psemi.com
Theory of Operation
General
The PE29102 is intended to drive both the high-side (HS) and the low-side (LS) gates of external power FETs,
such as enhancement mode GaN FETs, for power management applications. The PE29102 is suited for applica-
tions requiring higher switching speeds due to the reduced parasitic properties of the high resistivity insulating
substrate inherent with Peregrine’s UltraCMOS process.
The driver uses a single-ended pulse width modulation (PWM) input that feeds a dead-time controller, capable
of generating a small and accurate dead-time. The dead-time circuit prevents shoot-through current in the
output stage. The propagation delay of the dead-time controller must be small to meet the fast switching require-
ments when driving GaN FETs. The differential outputs of the dead-time controller are then level-shifted from a
low-voltage domain to a high-voltage domain required by the output drivers.
Each of the output drivers includes two separate pull-up and pull-down outputs allowing independent control of
the turn-on and turn-off gate loop resistance. The low impedance output of the drivers improves external power
FETs switching speed and efficiency, and minimizes the effects of the voltage rise time (dv/dt) transients.
Under-voltage Lockout
An internal under-voltage lockout (UVLO) feature prevents the PE29102 from powering up before input voltage
rises above the UVLO threshold of 3.6V (typ), and 400 mV (typ) of hysteresis is built in to prevent false
triggering of the UVLO circuit. The UVLO must be cleared and the EN pin must be released before the part will
be enabled.
Dead-time Adjustment
The PE29102 features a dead-time adjustment that allows the user to control the timing of the LS and HS gates
to eliminate any large shoot-through currents, which could dramatically reduce the efficiency of the circuit and
potentially damage the GaN FETs. Two external resistors contro l the timing of outputs in the dead-time controller
block. The timing waveforms are illustrated in Figure 6.
The dead-time resistors only af fect the rising edge of the low-side gate (LSG) and high -side gate (HSG) outputs.
Dead-time resistor RDLH will delay the rising edge of HSG, thus providing the desired dead-time between LSG
falling and HSG rising. Likewise, dead-time resistor RDHL will delay the rising edge of LSG, thus providing the
desired dead-time between HSG falling and LSG rising. Figure 7 shows the resulting dead-time versus the
external resistor values with both HS and LS bias diode/capacitors installed as indicated in Figure 5. The LS
bias diode and capacitor are included for symmetry only and are not required for the part to function. Removing
the LS bias diode will in crease th e LSG voltag e by a pproximately 0.3V, resulting in a wider separation of the tDHL
and tDLH curves in Figure 7.
Phase Control
Pin 10 (PHCTL) controls the polarity of the gate driver outputs. When PHCTL is high, the HSG will be in phase
with the input signal. When PHCTL is low, the LSG will be in phase with the input signal. The PHCTL pin
includes an internal pull-down resistor and can be left floating.