CY8CTMG120
TrueTouch™ Multi-Touch Gesture
Touchscreen Controller
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document Number: 001-46929 Rev. *B Revised July 29, 2008
Features
■
TrueTouch
™
Capacitive Touchscreen Controller
❐
Supports Single-T ouch and Multi-T ouch T ouchscreen Control
❐
Supports up to 44 X/Y Sensor Inputs
❐
Supports Screen Sizes 8.4” and Below
❐
Fast Scan Rates: T ypical 0.5 ms per Sensor
❐
High Resolution: Typical 480 x 360 for 3.5” Screen
❐
Available in 56-Pin QFN Package
❐
Seamless Transition up to Higher Function Multi - Touch
All-Point Device
■
Lowest Noise TrueTouch Device
■
Highly Configurable Sensing Circuitry
❐
Allows Maximum Design Flexibility
❐
Allows Trade-Off Between Scan Time and Noise Perfor-
mance
■
Includes Gesture Detection Library
■
Develop Customized User Defined Ge stures
■
Provides Maximum EMI Immunity
❐
Selectable Sp read-Spectrum Clock Source
■
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds to 24 MHz
❐
Two 8x8 Multiply, 32-Bit Accumulate
❐
Low Power at High Speed
❐
3V to 5.25V Operating Voltage
❐
Industrial Temperature Range: –40°C to +85°C
❐
USB Temperature Range: –10°C to +85°C
■
Full-Speed USB (12 Mbps)
❐
Four Uni-Directional Endpoints
❐
One Bi-Directional Control Endpoint
❐
USB 2.0 Compli an t
❐
Dedicated 256 Byte Buffer
❐
No External Crystal Required
■
Flexible On -C h ip Memory
❐
16K Flash Program Storage, 50000 Erase/Write Cycles
❐
1K SRAM Data Storage
❐
In-System Serial Programming (ISSP)
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
EEPROM Emulation in Flash
■
Precision, Programmable Clocking
❐
Internal ±4% 24 and 48 MHz Oscillator
❐
Internal Oscillator for Watchdog and Sleep
❐
0.25% Accuracy for USB with no External Components
■
Additional System Resources
❐
I
2
C™ Slave, Master, and Multi-Master to 40 0 kHz
❐
Watchdog and Sleep Timers
❐
User-Configurable Low Voltage Detection
❐
Integrated Supervisory Circuit
❐
On-Chip Precision Voltage Reference
■
Complete Development Tools
❐
Free Development Software (PSoC Designer™)
❐
TrueTouch
Touchscreen T uner
❐
Full-Featured, In-Circuit Emulator and Programmer
❐
Full Speed Emulation
❐
Complex Breakpoint Structure
❐
128K Bytes Trace Memory
■
Programmable Pin Configurations
❐
25 mA Sink, 10 mA Drive on All GPIO
❐
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐
Configurable Interrupt on All GPIO
Logic Block Diagram
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CY8CTMG120
Document Number: 001-46929 Rev. *B Page 2 of 33
TrueTouch Functional Overview
The TrueT ouch family provides the fastest and most efficient way
to develop and tune a capacitive touchscreen application. A
TrueTouch device includes the configurable TrueTouch block,
configurable analog and digital logic, programmable inter-
connect, and an 8-bit CPU to run custom firmware. This archi-
tecture enables the user to create flexible, customized touch-
screen configurations to match the requirements of each
individual touchscreen application. Various configurations of
Flash program memory, SRAM data memory, and configurable
IO are included in a range of convenient pinouts.
The Tr ueTouch architecture is comprised of four main areas: the
Core, Digital System, the TrueTouch Analog System, and
System Resources including a full-speed USB port. Configurable
global busing allows all the device resources to be combined into
a complete custom touchscreen system. The CY8CTMG120
device can have up to seven IO ports that connect to the global
digital and analog interconnects, providing access to four digital
blocks and six analog blocks. Implementation of touchscreen
application all ows additional digital and analog resources to be
used, depending on the touchscreen design. The CY8CTMG120
is offered in a 56-pin QFN package, with up to 48 general
purpose IO (GPIO), and support of up to 44 X/Y sensors.
When designing to uchscreen applications, refer to the UM data
sheet for performance requirements to meet and detailed design
process explanation.
The TrueTouch Core
The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture micropro-
cessor. The CPU uses an interrupt controller with up to 20
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog T imers (WDT).
Memory encompasses 16K of Flash for program sto rage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash uses four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
The T rueTouch device incorporates flexible internal clock gener-
ators, including a 24 MHz IMO (internal main oscillator) a ccurate
to 8% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. The clocks, together with programmable
clock dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the PSoC device. In
USB systems, the IMO self-tunes to ± 0.25% accuracy for USB
communication.
The GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external inter-
facing. Every pin also has the capability to generate a system
interrupt on high level, low level, and change from last read.
The Digital System
The Digital System is composed of 4 digi tal PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.
Figure 1. Digital System Block Diagram
Digital peripheral configurations include those listed below.
■
Full-Speed USB (12 Mbps)
■
PWMs (8 to 32 bit)
■
PWMs with dead band (8 to 24 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UAR T 8 bi t w ith selectab l e parity
■
SPI master and slave
■
I2C slave and multi-master
■
Pseudo random sequence generators (8 to 32 bit)
The digital blocks are connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow signal multiplexing and performing logic operations.
This configurability frees your designs from the cons traints of a
fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by TrueTouch device family. This allows optimum
choice of system resources for your applica tion. Fa mily charac-
teristics are shown in Table 1 on page 4.
DIGITAL SYSTEM
To System Bus
Digital Clocks
From Core
Digital PSoC Block Array
To Analog
System
8
Row Inp u t
Configuration
Row Out put
Configuration
88
8
Row 0
DBB00 DBB01 DCB02 DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 1
Port 0
Port 3
Port 2
Port 5
Port 4
Port 7
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CY8CTMG120
Document Number: 001-46929 Rev. *B Page 3 of 33
The Analog System
The Analog System is composed of 6 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are listed below.
■
Analog-to-digital converters (up to 2, with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
■
Filters (2 and 4 pole band-pass, low pass, and notch)
■
Amplifiers (up to 2, with selectable gain to 48x)
■
Instrumentation amplifiers (1 with selectable gain to 93x)
■
Comparators (up to 2, with 16 selectable thresholds)
■
DACs (up to 2, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 2, with 6- to 9-bit resol ution)
■
High current output drivers (two with 30 mA drive as a PSoC
Core Resource)
■
1.3V reference (as a System Resource)
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown Figure 2.
The Analog Multiplexer System
The Analog Mux Bus connects to every GPIO pin in ports 0-5.
Pins are connected to the bus individually or in any combination.
The bus also connects to the analog system for capacitive
sensing with the TrueTouch block comparator. It can be split into
two sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.
Switch control logic enables selected pins to switch dynamically
under hardware control. This allows capacitive measurement for
the touchscreen applications. Other multiplexer applications
include:
■
Chip-wide mux that allows analog input from up to 48 IO pins.
■
Electrical connection between any IO pin combinations.
Figure 2. Analog System Block Diagra m
Additional System Resources
System Resources, provide additional capability useful to
complete systems. Additional resources include a multiplier,
decimator , low voltage detection, and power on reset. Brief state-
ments describing the merits of each resource follow.
■
Full-S peed USB (12 Mbp s) with 5 configurable endpoints and
256 bytes of RAM. No external components required except
two series resistors. Wider than commercial temperature USB
operation (-10°C to +85°C).
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
T wo multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math and
digital filters.
ACB00 ACB01
Block
Array
Array Input
Configuration
ACI1[1:0]
ASD20
ACI0[1:0]
P0[6]
P0[4]
P0[2]
P0[0]
P2[2]
P2[0]
P2[6]
P2[4]
RefIn
AGNDIn
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Reference
Generators AGNDIn
RefIn
Bandgap
RefHi
RefLo
AGND
ASD11
ASC21
ASC10
Inte rface to
Digital System
M 8C Inte rface (Add ress Bus, Data Bus, Etc.)
Ana log Reference
All IO
(Excep t Port 7)
Analog
Mux Bus
[+] Feedback
CY8CTMG120
Document Number: 001-46929 Rev. *B Page 4 of 33
■
Decimator provides a custom hardware filter for digital signal
processing applications including creation of Del ta Sigma
ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, multi-master are supported.
■
Low Voltage Detectio n (LVD) interrupts signal the application
of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
Versatile analog multiplexer system.
Getting Started
To understand the PSoC silicon, read this data sheet and use the
PSoC Designer Integrated Development Environment (IDE).
This data sheet is an overview of the PSoC integrated circuit and
presents general silicon and electrical specifications. For in
depth touchscreen application information, including touch-
screen specific specifications, read the touchscreen user module
data sheet that is supported by this specific device.
TrueTouch Device Characteristics
Depending on the TrueTouch device selected for a touchscreen
application, characteristics and capabilities of each device
change. Table 1 lists the touchscreen sensing capabilities
available for specific T rueTouch devices. The TrueTouch device
covered by this data sheet is highlighted in this table.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accesso ries for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page, and cl ick PSoC (Program-
mable System-on-Chip) to view a current list of available items.
Technical Training Modules
Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced analog and CapSense. Go to
http://www.cypress.com/training.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located on the left side of the web page, and select
CYPros Consultants.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They are available with a four hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Application Notes
A long list of application notes assist you in every aspect of your
design effort. To view the PSoC application notes, go to the
http://www.cypress.com web site and select Application Notes
under the Design Resources list located in the center of the web
page. Application notes are listed by date as default.
Development Tools
PSoC Designer is a Microsoft
®
Windows based, integrated
development environment for the Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 200 0, Windows
Millennium (Me), or Windows XP (see Figure 3 on page 5).
PSoC Designer helps the customer to select an operating config-
uration for the PSoC, write application code that uses the PSoC,
and debug the application. This system provides design
database management by project, an integ rated debugger with
In-Circuit Emulator (ICE), i n-system programming support, and
the CYASM macro assembler for the CPUs.
PSoC Designer also supports a high level C language compiler
developed specifically for the devices in the family.
Table 1. True Touch Device Characteristics
TrueTouch Part
Number
Sensor
Inputs
Max Screen
Size (Inches)
Single-Touch
Multi-Touch
Gesture
Multi-Touch
All-Point
Scan
Speed (ms)
[1]
Current
Consumption
[2]
Flash Size
SRAM
Size
CY8CTST110 up to
24 4.3” Y N N 0.5 3 8K 512
Bytes
CY8CTST120 up to
44 8.4” Y N N 0.5 16 16K 1K
CY8CTMG110 up to
24 4.3” Y Y N 0.5 38K 512
Bytes
CY8CTMG120 up to
44 8.4 Y Y N 0.5 16 16K 1K
CY8CTMA120 up to
37 7.3” Y Y Y 0.12 16 16K 1K
Notes
1. Per sensor typical. Depends on touchscreen panel. For MA120 per X/Y crossing Vcc = 3.3V.
2. Average mA supply current. Based on 8 ms report rate, except for MA120.
[+] Feedback
CY8CTMG120
Document Number: 001-46929 Rev. *B Page 5 of 33
Figure 3. PSoC Designer Subsystems
PSoC Designer Software Subsystems
Device Editor
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, amplifiers, and filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configu-
ration allows changing configurations at ru n time.
PSoC Designer sets up power-on initialization tables for selected
PSoC block configurations and creates source code for an appli-
cation framework. The framework contains software to operate
the selected components. If the project uses more than one
operating configuration, then it contains routines to switch
between different sets of PSoC block configurations at run time.
PSoC Designer prints out a configuration sheet for a given
project configuration for use du ring application programming in
conjunction with the device data sheet. After the framework is
generated, the user can add application-specific code to flesh
out the framework. It is also possible to change the selected
components and regenerate the framework.
Design Browser
The Design Browser allows users to select and import precon-
figured designs into the user’s project. Users can easily browse
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tools include a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader .
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
Assembler. The macro assembler allows the assembly code to
be merged seamlessly with C code. The link libraries a utomati-
cally use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Co mpiler. A C language compiler is available that
supports the PSoC family of devices. Even if you have never
worked in the C language before, the product quickly allows you
to create complete C programs for the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended ma th functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the desig ner to test the program in
a physical system while provid ing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQ s and an Online
Support Forum to aid the designer in gettin g started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE is available for development
support. This hardware has the capability to program single
devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
TrueTouch Touchscreen Tuner
The TrueTouch tuner is a Microsoft
®
Windows based graphical
user interface allowing developers to set critical parameters and
observe changes to the touchscreen application in real time.
Optimal configuration from the tuner can be immediately applied
to the TrueTouch user module settings.
Commands
Results
PSoC
Designer
Core
Engine
PSoC
Configuration
Sheet
Manufacturing
Information
File
Device
Database
Importable
Design
Database
Device
Programmer
Graphical Designer
Interface
Context
Sensitive
Help
Emulation
Pod In-Circuit
Emulator
Project
Database
Application
Database
User
Modules
Library
PSoC
Designer
[+] Feedback
CY8CTMG120
Document Number: 001-46929 Rev. *B Page 6 of 33
Designing with User Modules
The development p rocess for the PSoC de vice differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the
hardware and software. This substantially lowers the risk of
having to select a different part to meet the fin al design require-
ments.
To speed the development process, the PSoC Designer IDE
provides a library of pre-built, pre-tested hardware peripheral
functions, called “User Modules.” User modules make se lecting
and implementing peripheral devices simple, and come in
analog, digital, and mixed signal varieties. The standard user
module library contains over 50 common peripherals such as
ADCs, DACs timers, counters, UARTs, and other not so common
peripherals such as DTMF generators and Bi-Quad analog filter
sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more di gital PSoC blocks, one for ea ch 8 b its
of resolution. The user module parameters permit to establish
the pulse width and duty cycle. User modules also provide tested
software to cut development time. The user module appl ication
programming interface (API) provides high level functions to
control and respond to hardware events at run-time. The API
also provides optional interrupt service routines that are adapted
as needed.
The API functions are document ed in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each d ata sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. Pick the user modules you need for
your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, build signal chains by intercon-
necting user modules to each other and the IO pins. At this stage,
also configure the clock source connections and enter parameter
values directly or by selecting values from drop-down menus.
When you are re ady to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the high level user module API
functions.
Figure 4. User Module and Source Code Development Flows
The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open th e project source code files (inclu ding
all generated code files) from a hierarchal view . The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilitie s include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project level options control optimization strategies
used by the compiler and linker . Syntax errors are displayed in a
console window. Double click the error message to view the
offending line of source code. When all is correct, the linker
builds a HEX file image suitable for programming.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you define complex breakpoint events that
include monitoring address and data bus values, memory
locations and external signals.
Debugger
Interface
to I CE
Appl icati on Edi t or
Device Editor
Project
Manager
Source
Code
Editor
Storage
Inspector
User
Module
Selection
Placement
and
Parameter
-ization
Generate
Application
Build
All
Event &
Breakpoint
Manager
Build
Manager
Source
Code
Generator
[+] Feedback
CY8CTMG120
Document Number: 001-46929 Rev. *B Page 7 of 33
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 4 on page 11 lists all the abbreviations used to
measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘0x’, or ‘b’ are
decimal.
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-to-analog converter
DC direct current
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only
memory
FSR full scale range
GPIO general purpose IO
GUI graphical user interface
HBM human body model
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision power on reset
PSoC® Programmable System-on-Chip™
PWM pulse width modulator
SC switched capacitor
SRAM static random access memory
[+] Feedback
CY8CTMG120
Document Number: 001-46929 Rev. *B Page 8 of 33
Pinouts
This section describes, lists, and illustrates the CY8CTMG120 TrueTouch family pins and pinout configura tion. The CY8CTMG120
TrueTouch device is availabl e in the fo llowing packages, all of which a re shown on the follo wing pages. Every port pin (l abeled with
a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.
56-Pin Part Pinout
Table 2. 56-Pin Part Pinout (QFN)
Pin
No. Type Name Description
Figure 5. CY8CTMG120 56-Pin PSoC Device
Digital Analog
1IO I, M P2[3] Direct switched capacitor block input.
2IO I, M P2[1] Direct switched capacitor block input.
3IO MP4[7]
4IO MP4[5]
5IO MP4[3]
6IO MP4[1]
7IO MP3[7]
8IO MP3[5]
9IO MP3[3]
10 IO MP3[1]
11 IO MP5[7]
12 IO MP5[5]
13 IO MP5[3]
14 IO MP5[1]
15 IO MP1[7] I2C Serial Clock (SCL).
16 IO MP1[5] I2C Serial Data (SDA).
17 IO MP1[3]
18 IO M P1[1] I2C Serial Clock (SCL), IS SP SC LK
[3]
.
19 Power Vss Ground. Connect to circuit ground.
20 USB D+
21 USB D-
22 Power Vdd Supply voltage. Byp ass to ground with
0.1 uF capacitor.
23 IO P7[7]
24 IO P7[0]
25 IO MP1[0] I2C Serial Data (SDA), ISSP SDA T A
[3]
.
26 IO MP1[2]
27 IO MP1[4]
28 IO MP1[6]
29 IO MP5[0] Pin
No. Type Name Description
30 IO MP5[2] Digital Analog
31 IO MP5[4] 44 IO M P2[6] External Voltage Reference (VREF) input.
32 IO MP5[6] 45 IO I, M P0[0] Analog column mux input.
33 IO MP3[0] 46 IO I, M P0[2] Analog column mux input.
34 IO MP3[2] 47 IO I, M P0[4] Analog column mux input VREF.
35 IO MP3[4] 48 IO I, M P0[6] Analog column mux input.
36 Input XRES Active high exter n al rese t with inter n al
pull down. 49 Power Vdd Supply voltage. Bypass to grou nd with 0.1 uF
capacitor.
37 IO MP4[0] 50 Power Vss Ground. Connect to circuit ground.
38 IO MP4[2] 51 IO I, M P0[7] Analog column mux input,.
39 IO MP4[4] 52 IO IO, M P0[5] Analog column mux input and column output.
40 IO MP4[6] 53 IO IO, M P0[3] Analog column mux input and column output.
41 IO I, M P2[0] Direct switched capacitor block inpu t. 54 IO I, M P0[1] Analog column mux input.
42 IO I, M P2[2] Direct switched capacitor block inpu t. 55 IO MP2[7]
43 IO MP2[4] External Analo g Ground (A GND) input . 56 IO MP2[5]
EP Power Vss Exposed Pad is internally connected to ground.
Connect to circuit ground.
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
QFN
(Top View)
A, I, M, P2[3]
A, I, M, P2[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
M, I2C SCL, P1[7]
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
Vss
D+
D-
Vdd
P7[7]
P7[0]
M, I2C SDA, P1[0]
M, P1[2]
M, P1[4]
M, P1[6]
15
16
17
18
19
20
21
22
23
24
25
26
27
28 P2[4], M
P2[6], M
P0[0], A, I, M
P0[2], A, I, M
P0[4], A, I, M
P0[6], A, I, M
Vdd
Vss
P0[7], A, I, M
P0[5], A, IO, M
P0[3], A, IO, M
P0[1], A, I, M
P2[7], M
P2[5], M
43
44
45
46
47
48
49
50
51
52
53
54
55
56
P2[2], A, I, M
P2[0], A, I, M
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Note
3. These are the ISSP pins, which are not High Z at POR.
[+] Feedback
CY8CTMG120
Document Number: 001-46929 Rev. *B Page 9 of 33
100-Pin Part Pinout (On-Chip Debug)
The 100-pin TQFP part is the CY8CTMG12 0 On-Chip Debug (OCD) TrueTouch device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Figure 6. CY8CTMG120 OCD
Table 3. 100-Pin Part Pinout (TQFP)
Pin
No.
Digital
Analog
Name Description Pin
No.
Digital
Analog
Name Description
1NC No connection. Leave floating. 51 IO MP1[6]
2NC No connection. Leave floating. 52 IO MP5[0]
3IO I, M P0[1] Analog column mux input. 53 IO MP5[2]
4IO M P2[7] 54 IO M P5[4]
5IO M P2[5] 55 IO M P5[6]
6IO I, M P2[3] Direct switched capacitor block input. 56 IO MP3[0]
7IO I, M P2[1] Direct switched capacitor block input. 57 IO MP3[2]
8IO M P4[7] 58 IO M P3[4]
9IO M P4[5] 59 IO M P3[6]
10 IO M P4[3] 60 HCLK OCD high-speed clock output.
11 IO M P4[1] 61 CCLK OCD CPU clock output.
12 OCDE OCD even data IO. 62 Input XRES Active high pin reset with internal pull
down.
13 OCD
OOCD odd data output. 63 IO M P4[0]
14 NC No connection. Leave floating. 64 IO MP4[2]
15 Power Vss Ground. Connect to circuit ground. 65 Power Vss Ground. Connect to circuit ground.
16 IO M P3[7] 66 IO M P4[4]
17 IO M P3[5] 67 IO M P4[6]
TQFP
NC
NC
AI, M, P0[1]
M, P2[7]
M, P2[5]
AI, M, P2[3]
AI, M, P2[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
OCDE
OCDO
NC
Vss
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SC L, P1[ 7]
NC
NC
D-
P7[3]
NC
NC
I2C SDA, M, P1[5]
M, P1[3]
I2C SCL, M , P1[1]
NC
Vss
D+
Vdd
P7[7]
P7[6]
P7[5]
P7[4]
P7[2]
P7[1]
P7[0]
NC
NC
NC
I2C SDA, M, P1[0]
M, P1[2]
M, P1[4]
NC
P0[0], M, AI
NC
P2[6], M, External VREF
NC
P2[4], M, External AGND
P2[2], M, AI
P2[0], M, AI
P4[6], M
P4[4], M
Vss
P4[2], M
P4[0], M
XRES
CCLK
HCLK
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
NC
P0[3], M , AI
NC
P0[5], M , AI
NC
P0[7], M , AI
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Vss
NC
Vdd
P0[6], M , AI
NC
P0[4], M , AI
NC
P0[2], M , AI
NC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
50
49
[+] Feedback
CY8CTMG120
Document Number: 001-46929 Rev. *B Page 10 of 33
Pin
No.
Digital
Analog
Name Description Pin
No.
Digital
Analog
Name Description
19 IO M P3[1] 69 IO I, M P2[2] Direct switched capacitor block input.
20 IO M P5[7] 70 IO P2[4] External Analog Ground (AGND) input.
21 IO M P5[5] 71 NC No connection. Leave floating.
22 IO M P5[3] 72 IO P2[6] External Voltage Reference (VREF)
input.
23 IO M P5[1] 73 NC No connection. Leave floating.
24 IO M P1[7] I2C Serial Clock (SCL). 74 IO I P0[0] Analog column mux input.
25 NC No connection. Leave floating. 75 NC No connection. Leave floating.
26 NC No connection. Leave floating. 76 NC No connection. Leave floating.
27 NC No connection. Leave floating. 77 IO I, M P0[2] Analog column mux input and column
output.
28 IO P1[5] I2C Serial Data (SDA) 78 NC No connection. Leave floating.
29 IO P1[3] 79 IO I, M P0[4] Analog column mux input and column
output.
30 IO P1[1] Crystal (XTALin), I2C Serial Clock
(SCL), ISSP SCLK
[3]
.80 NC No connection. Leave floating.
31 NC No connection. Leave floating. 81 IO I, M P0[6] Analog column mux input.
32 Power Vss Ground. Connect to circuit ground. 82 Power Vdd Supply voltage. Bypass to ground with
0.1 uF capacitor.
33 USB D+ 83 NC No connection. Leave floating.
34 USB D- 84 Power Vss Ground. Connect to circuit ground .
35 Power Vdd Supply voltage. Bypass to ground with
0.1 uF capacitor. 85 NC No connection. Leave floating.
36 IO P7[7] 86 NC No connection. Leave floating.
37 IO P7[6] 87 NC No connection. Leave floating.
38 IO P7[5] 88 NC No connection. Leave floati ng.
39 IO P7[4] 89 NC No connection. Leave floati ng.
40 IO P7[3] 90 NC No connection. Leave floating.
41 IO P7[2] 91 NC No connection. Leave floating.
42 IO P7[1] 92 NC No connection. Leave floati ng.
43 IO P7[0] 93 NC No connection. Leave floati ng.
44 NC No connection. Leave floating. 94 NC No connection. Leave floating.
45 NC No connection. Leave floating. 95 IO I, M P0[7] Analog column mux input.
46 NC No connection. Leave floating. 96 NC No conn ection. Leave floating.
47 NC No connection. Leave floating. 97 IO IO, M P0[5] Analog column mux input and column
output.
48 IO P1[0] Crystal (XTALout), I2C Serial Data
(SDA), ISSP SDATA
[3]
.98 NC No connection. Leave floating.
49 IO P1[2] 99 IO IO, M P0[3] Analog column mux input and column
output.
50 IO P1[4] Optional External Clock Input
(EXTCLK). 100 NC No connection. Leave floating.
LEGEND A = Analog, I = Input, O = Output, NC = No Con nection, M = Analog Mu x Input, OCD = On-Chip Debugger.
Table 3. 100-Pin Part Pinout (TQFP) (continued)
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CY8CTMG120
Document Number: 001-46929 Rev. *B Page 11 of 33
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8CTMG120 T rueTouch device family. For the most up to date
electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
S pecifications are valid for -40
o
C ≤ T
A
≤ 85
o
C and T
J
≤ 100
o
C, except where noted. S pecifications for devices running at greater than
12 MHz are valid for -40
o
C ≤ T
A
≤ 70
o
C and T
J
≤ 82
o
C.
Figure 7. Voltage versus CPU Freque ncy
Table 4 lists the units of measure that are used in this section
Table 4. Units of Measure
Symbol Unit of Measure Symbol Unit of Measure
o
Cdegree Celsius μWmicrowatts
dB decibels mA milli-ampere
fF femto farad ms milli-second
Hz hertz mV milli-volts
KB 1024 bytes nA nanoampere
Kbit 1024 bits ns nanosecond
kHz kilohertz nV nanovolts
kΩkilohm Ωohm
MHz megahertz pA picoampere
MΩmegaohm pF picofarad
μAmicroampere pp peak-to-peak
μFmicrofarad ppm parts per million
μHmicrohenry ps picosecond
μsmicrosecond sps samples per second
μVmicrovolts ssigma: one standard deviation
μVrms microvolts root-mean-square Vvolts
5.25
4.75
3.00
93 kHz 12 MHz 24 MHz
CPU Frequency
Vdd Voltage
Valid
Operating
Region
[+] Feedback
CY8CTMG120
Document Number: 001-46929 Rev. *B Page 12 of 33
Absolute Maximum Ratings
Operating Temperature
Table 5. Absolute Maximum Ratings
Symbol Description Min Typ Max Units Notes
T
STG
Storage Temperature -55 25 +100
o
CHigher storage temperatures
reduces data retention time.
Recommended storage temper-
ature is +25
o
C ± 25
o
C. Extended
duration storage temperatures
above 65
o
C degrades reliability.
T
A
Ambient Temperature with Power Appl ied -40 –+85
o
C
Vdd Supply Voltage on Vdd Relative to Vss -0.5 –+6.0 V
V
IO
DC Input Voltage Vss - 0.5 –Vdd + 0.5 V
V
IO2
DC Voltage Applied to Tri-state Vss - 0.5 –Vdd + 0.5 V
I
MIO
Maximum Current into any Port Pin -25 –+50 mA
I
MAIO
Maximum Current into any Port Pin
Configur ed as Analog Driv er -50 –+50 mA
ESD Electro Static Discharge Voltage
[4]
.
2000 – – V Human Body Model ESD.
LU Latch Up Current – – 200 mA
Table 6. Operating Temperature
Symbol Description Min Typ Max Units Notes
T
A
Ambient Temperature
[5]
.
-40 –+85
o
C
T
AUSB
Ambient Temperature using USB -10 –+85
o
C
T
J
Junction Temperature -40 –+100
o
CThe temperature rise from ambient
to junction is package specific. See
Thermal Impedance for the Package
on page 30. The user must limit the
power consumption to comply with
this requirement.
Notes
4. See the user module data sheet for touchscreen application related ESD testing
5. See the user module dat a sheet for touchscreen application related temperature testing.
[+] Feedback
CY8CTMG120
Document Number: 001-46929 Rev. *B Page 13 of 33
DC Electrical Characteristics
The below electrical characteristics are for proper CPU core and I/O operation. For capacitive touchscreen electrical characteristics,
refer to the touchscreen user module data sheet.
DC Chip Level Specifications
Table 7 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤
T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively . T ypical parameters apply to 5V and 3.3V at 25°C. These are for design
guidance only.
Table 7. DC Chip Level Specifications
Symbol Description Min Typ Max Units Notes
Vdd Supply Voltage 3.0 –5.25 VSee DC POR and LVD specifications,
Table 19 on page 20.
I
DD5
Supply Current, IMO = 24 MHz (5V) –14 27 mA Conditions are Vdd = 5.0V , T
A
= 25
o
C,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 93.75 kHz, analog power
= off.
I
DD3
Supply Current, IMO = 24 MHz (3.3V) – 8 14 mA Conditions are Vdd = 3.3V , T
A
= 25
o
C,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 0.367 kHz, analog power
= off.
I
SB
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT.
[6]
.
– 3 6.5 μAConditions are with internal slow
speed oscillator , Vdd = 3.3V, -40
o
C ≤
T
A
≤ 55
o
C, analog power = off.
I
SBH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT at High Temperature.
[6]
.
– 4 25 μAConditions are with internal slow
speed oscillator, Vdd = 3.3V, 55
o
C <
T
A
≤ 85
o
C, analog power = off.
Note
6. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be comp ared with devices that have similar
functions enabled.
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CY8CTMG120
Document Number: 001-46929 Rev. *B Page 14 of 33
DC General Purpo se IO Specificat io n s
Table 8 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤
T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively . T ypical parameters apply to 5V and 3.3V at 25°C. These are for design
guidance only.
DC Full-Speed USB Specifications
Table 9 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -10°C ≤
T
A
≤ 85°C, or 3.0V to 3.6V and -10°C ≤ T
A
≤ 85°C, respectively . T ypical parameters apply to 5V and 3.3V at 25°C. These are for design
guidance only.
Table 8. DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
R
PU
Pull Up Resistor 4 5.6 8 kΩ
R
PD
Pull Down Resistor 4 5.6 8 k Ω
V
OH
High Output Level Vdd -
1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])). 80
mA maximum combined IOH budget.
V
OL
Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])). 200
mA maximum combined IOL budget.
V
IL
Input Low Level – – 0.8 V Vdd = 3.0 to 5.25.
V
IH
Input High Level 2.1 – V Vdd = 3.0 to 5.25.
V
H
Input Hysterisis –60 –mV
I
IL
Input Leakage (Absolute Value) –1–nA Gross tested to 1 μA.
C
IN
Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent. Temp =
25
o
C.
C
OUT
Capacitive Load on Pins as Output –3.5 10 pF Package and pin dependent. Temp =
25
o
C.
Table 9. DC Full Speed (12 Mbps) USB Sp ecifications
Symbol Description Min Typ Max Units Notes
USB Interface
V
DI
Differential Input Sensitivity 0.2 – – V | (D+) - (D-) |
V
CM
Differential Input Common Mode Range 0.8 – 2.5 V
V
SE
Single Ended Receiver Threshold 0.8 – 2.0 V
C
IN
Transceiver Capacitance – – 20 pF
I
IO
High-Z State Data Line Leakage -10 – 10 μA0V < V
IN
< 3.3V.
R
EXT
External USB Series Resistor 23 – 25 WIn series with each USB pin.
V
UOH
Static Output High, Driven 2.8 – 3.6 V15 kΩ ± 5% to Ground. Internal pull-up
enabled.
V
UOHI
Static Output High, Idle 2.7 – 3.6 V15 kΩ ± 5% to Ground. Internal pull-up
enabled.
V
UOL
Static Output Low – – 0.3 V15 kΩ ± 5% to Ground. Internal pull-up
enabled.
Z
O
USB Driver Output Impedance 28 – 44 WIncluding R
EXT
Resistor.
V
CRS
D+/D- Crossover Voltage 1.3 – 2.0 V
[+] Feedback
CY8CTMG120
Document Number: 001-46929 Rev. *B Page 15 of 33
DC Operational Amplifier Specifications
Table 10 and Table 11 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively . Typical parameters apply to 5V and 3.3V at 25°C. These
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.
Table 10. 5V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
V
OSOA
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–1.6
1.3
1.2
10
8
7.5
mV
mV
mV
TCV
OSOA
Average Input Offset Voltage Drift – 7.0 35.0 μV/
o
C
I
EBOA
Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 μA.
C
INOA
Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent.
Temp = 25
o
C.
V
CMOA
Common Mode Vol tage Range
Common Mode V oltage Range (high power
or high opamp bias)
0.0 – Vdd
Vdd - 0.5 V The common-mode input voltage
range is measured through an
analog output buffer. The spec ifi-
cation includes the limitations
imposed by the characteristics of
the analog output buffer.
0.5 –
G
OLOA
Open Loop Gain
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
60
60
80
–– dB
V
OHIGHOA
High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
V
OLOWOA
Low Output V oltage Swing (internal signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
I
SOA
Supply Current (including associated AGND
buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
–
400
500
800
1200
2400
4600
800
900
1000
1600
3200
6400
μA
μA
μA
μA
μA
μA
PSRR
OA
Supply Vol tage Rejection Ratio 65 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd -
1.25V) ≤ VIN ≤ Vdd.
[+] Feedback
CY8CTMG120
Document Number: 001-46929 Rev. *B Page 16 of 33
Table 11. 3.3V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
V
OSOA
Input Offset Voltag e (Absolute Value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5V Only
–
–1.65
1.32 10
8 mV
mV
TCV
OSOA
Average Input Offset Voltage Drift – 7.0 35.0 μV/
o
C
I
EBOA
Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 μA.
C
INOA
Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin depende nt.
Temp = 25
o
C.
V
CMOA
Common Mode Voltage Range 0.2 – Vdd - 0.2 V The common-mode input voltage
range is measured through an analog
output buffer. The specification
includes the limitations imposed by
the characteristics of the analo g
output buffer.
G
OLOA
Open Loop Gain
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
60
60
80
–– dB
V
OHIGHOA
High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High is 5V only
Vdd - 0.2
Vdd - 0.2
Vdd - 0.2
–
–
–
–
–
–
V
V
V
V
OLOWOA
Low Output V oltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
I
SOA
Supply Current (including associated AGND
buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
–
400
500
800
1200
2400
4600
800
900
1000
1600
3200
6400
μA
μA
μA
μA
μA
μA
PSRR
OA
Supply Voltage Rejectio n Ratio 65 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd -
1.25V) ≤ VIN ≤ Vdd.
[+] Feedback
CY8CTMG120
Document Number: 001-46929 Rev. *B Page 17 of 33
DC Low Power Comparator Specifications
Table 12 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5 .25V and -40 °C
≤ T
A
≤ 85°C, 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to
5V at 25°C. These are for design guidan ce only.
DC IDAC Resolution
Table 13 lists IDAC typical resolution. Typical parameters apply to 5V at 25°C. These are for design guidance only.
DC Analog Output Buffer Specifications
Table 14 and Table 15 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively . Typical parameters apply to 5V and 3.3V at 25°C. These
are for design guidance only.
Table 12. DC Low Power Co mparator Specifications
Symbol Description Min Typ Max Units Notes
V
REFLPC
Low Power Comparator (LPC) Reference
Voltage Range 0.2 – Vdd - 1 V
I
SLPC
LPC Supply Cu rre nt – 10 40 μA
V
OSLPC
LPC Voltage Offset – 2.5 30 mV
Table 13. DC Low Power Co mparator Specifications
Symbol Description Min Typ Max Units Notes
I
DAC
Current Output of 1 LSB (1x Setting) - 75 - nA
Table 14. 5V DC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
V
OSOB
Input Offset Voltage (Absolute Value) – 3 12 mV
TCV
OSO
B
Average Input Offset Voltage Drift –+6 –μV/°C
V
CMOB
Common-Mode Input Voltage Range 0.5 –Vdd - 1.0 V
R
OUTOB
Output Resistance
Power = Low
Power = High –
–0.6
0.6 –
–W
W
V
OHIGHO
B
High Output Voltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low
Power = High 0.5 x Vdd
+ 1.1
0.5 x Vdd
+ 1.1 –
––
–V
V
V
OLOWOB
Low Output V oltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low
Power = High –
––
–0.5 x Vdd
- 1.3
0.5 x Vdd
- 1.3 V
V
I
SOB
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High –
–1.1
2.6 5.1
8.8 mA
mA
PSRR
OB
Supply Voltage Rejection Ratio 53 64 –dB (0.5 x Vdd - 1.3) ≤ V
OUT
≤ (Vdd - 2.3).
[+] Feedback
CY8CTMG120
Document Number: 001-46929 Rev. *B Page 18 of 33
DC Analog Reference Specifications
Table 16 and Table 17 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively . Typical parameters apply to 5V and 3.3V at 25°C. These
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous T ime PSoC blocks. The power levels for AGND refer to
the power of the Analog C ontinuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 15. 3.3V DC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
V
OSOB
Input Offset Voltage (Absolute Value) – 3 12 mV
TCV
OSOB
Average Input Offset Voltage Drift –+6 –μV/°C
V
CMOB
Common-Mode Input Voltage Range 0.5 -Vdd - 1.0 V
R
OUTOB
Output Resistance
Power = Low
Power = High –
–1
1–
–W
W
V
OHIGHOB
High Output Voltage Swing (Load = 1K
ohms to Vdd/2)
Power = Low
Power = High 0.5 x Vdd
+ 1.0
0.5 x Vdd
+ 1.0 –
––
–V
V
V
OLOWOB
Low Output Voltage Swing (Load = 1K
ohms to Vdd/2)
Power = Low
Power = High –
––
–0.5 x Vdd
- 1.0
0.5 x Vdd
- 1.0 V
V
I
SOB
Supply Current Including Bias Cell (No
Load)
Power = Low
Power = High –0.8
2.0 2.0
4.3 mA
mA
PSRR
OB
Supply Voltage Rejecti on Ratio 34 64 –dB (0.5 x Vdd - 1.0) ≤ V
OUT
≤
(0.5 x Vdd + 0.9).
Table 16. 5V DC Analog Referenc e Specifications
Symbol Description Min Typ Max Units
BG Bandgap Voltage Reference 1.28 1.30 1.32 V
–AGND = Vdd/2
[7]
Vdd/2 - 0.04 Vdd/2 - 0.01 Vdd/2 + 0.007 V
–AGND = 2 x BandGap
[7]
2 x BG - 0.048 2 x BG - 0.030 2 x BG + 0.024 V
–AGND = P2[4] (P2[4] = Vdd/2)
[7]
P2[4] - 0.011 P2[4] P2[4] + 0.011 V
–AGND = BandGap
[7]
BG - 0.009 BG + 0.008 BG + 0.016 V
–AGND = 1.6 x BandGap
[7]
1.6 x BG - 0.022 1.6 x BG - 0.010 1.6 x BG + 0.018 V
–AGND Block to Block Variation (AGND = Vdd/2)
[7]
-0.034 0.000 0.034 V
–RefHi = Vdd/2 + BandGap
Vdd
/2 + BG - 0.10
Vdd
/2 + BG
Vdd
/2 + BG + 0.10 V
–RefHi = 3 x BandGap 3 x BG - 0.06 3 x BG 3 x BG + 0.06 V
–RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] -
0.113 2 x BG + P2[6] -
0.018 2 x BG + P2[6] +
0.077 V
–RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098 V
–RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4 ] + P2[ 6] -
0.133 P2[4] + P2[6] -
0.016 P2[4] + P2[6]+
0.100 V
Note
7. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.0 2V.
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CY8CTMG120
Document Number: 001-46929 Rev. *B Page 19 of 33
–RefHi = 3.2 x BandGap 3.2 x BG - 0.112 3.2 x BG 3.2 x BG + 0.076 V
–RefLo = Vdd/2 – BandGap
Vdd
/2 - BG - 0.04
Vdd
/2 - BG
+
0.024
Vdd
/2 - BG + 0.04 V
–RefLo = BandGap BG - 0.06 BG BG + 0.06 V
–RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] -
0.084 2 x BG - P2[6] +
0.025 2 x BG - P2[6] +
0.134 V
–RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107 V
–RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] -
0.057 P2[4] - P2[6] +
0.026 P2[4] - P2[6 ] +
0.110 V
Table 16. 5V DC Analog Referenc e Specifications (continued)
Symbol Description Min Typ Max Units
Table 17. 3.3V DC Analog Reference Specifications
Symbol Description Min Typ Max Units
BG Bandgap Voltage Reference 1.28 1.30 1.32 V
–AGND = Vdd/2
[7]
Vdd/2 - 0.03 Vdd/2 - 0.01 Vdd/2 + 0.005 V
–AGND = 2 x BandGap
[7]
Not Allowed
–AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.008 P2[4] + 0.001 P2[4] + 0.009 V
–AGND = BandGap
[7]
BG - 0.009 BG + 0.005 BG + 0.015 V
–AGND = 1.6 x BandGap
[7]
1.6 x BG - 0.027 1.6 x BG - 0.010 1.6 x BG + 0.018 V
–AGND Column to Column Variation (AGND =
Vdd/2)
[7]
-0.034 0.000 0.034 V
–RefHi = Vdd/2 + BandGap Not Allowed
–RefHi = 3 x BandGap Not Allowed
–RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allo wed
–RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed
–RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] -
0.075 P2[4] + P2[6] -
0.009 P2[4] + P2[6] +
0.057 V
–RefHi = 3.2 x BandGap Not Allowed
–RefLo = Vdd/2 - BandGap Not Allo wed
–RefLo = BandGap Not Allowed
–RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed
–RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed
–RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] -
0.048 P2[4]- P2[6] +
0.022 P2[4] - P2[6] +
0.092 V
[+] Feedback
CY8CTMG120
Document Number: 001-46929 Rev. *B Page 20 of 33
DC Analog PSoC Bloc k Spec ifications
Table 18 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5 .25V and -40 °C
≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C. These are for
design guid an ce on ly.
DC POR and L VD Specifications
Table 19 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5 .25V and -40 °C
≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively . T ypical parameters apply to 5V or 3.3V at 25°C. These are for design
guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT _CR register.
Table 18. DC Analog PSoC Block Specifications
Symbol Description Min Typ Max Units Notes
R
CT
Resistor Unit Value (Continuous Time) –12.2 – kΩ
C
SC
Capacitor Unit Value (Switched Capacitor) –80 –fF
Table 19. DC POR and LVD Specifications
Symbol Description Min Typ Max Units Notes
V
PPOR0R
V
PPOR1R
V
PPOR2R
Vdd Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b –2.91
4.39
4.55 –V
V
V
V
PPOR0
V
PPOR1
V
PPOR2
Vdd Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b –2.82
4.39
4.55 –V
V
V
V
PH0
V
PH1
V
PH2
PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
–
–
92
0
0
–
–
–
mV
mV
mV
V
LVD0
V
LVD1
V
LVD2
V
LVD3
V
LVD4
V
LVD5
V
LVD6
V
LVD7
Vdd Value for LV D Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
2.98
[8]
3.08
3.20
4.08
4.57
4.74
[9]
4.82
4.91
V
V
V
V
V
V
V
V
Notes
8. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
9. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
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CY8CTMG120
Document Number: 001-46929 Rev. *B Page 21 of 33
DC Programming Specifications
Table 20 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5 .25V and -40 °C
≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C. These are for
design guid an ce on ly.
Table 20. DC Programming Specifications
Symbol Description Min Typ Max Units Notes
I
DDP
Supply Current During Programming or V erify –15 30 mA
V
ILP
Input Low Voltage During Programming or
Verify – – 0.8 V
V
IHP
Input High Voltage During Programmi ng or
Verify 2.1 – – V
I
ILP
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify – – 0.2 mA Driving internal pull-down
resistor.
I
IHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify – – 1.5 mA Driving internal pull-down
resistor.
V
OLV
Output Low Voltage During Programming or
Verify – – Vss + 0.75 V
V
OHV
Output High Voltage During Programming or
Verify Vdd
- 1.0 –Vdd V
Flash
ENP
B
Flash Endurance (per block) 50,000 – – – Erase/write cycles per block.
Flash
ENT
Flash Endurance (total)
[10]
1,800,000 – – – Erase/write cycles.
Flash
DR
Flash Data Retention 10 – – Years
Note
10.A maximum of 36 x 50,000 block endurance cycles is al lowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks
of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees
more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs App lication Note AN2015 at http://www.cypress.com under Application Notes for more inf ormation.
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Document Number: 001-46929 Rev. *B Page 22 of 33
AC Electrical Characteristics
AC Chip Level Specifications
Table 21 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5 .25V and -40 °C
≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C. These are for
design guid an ce on ly.
Figure 8. 24 MHz Period Jitter (IMO) Timing Diagram
Table 21. AC Chip Level Specifications
Symbol Description Min Typ Max Units Notes
F
IMO245V
Internal Main Oscillator Frequency for 24 MHz
(5V) 23.04 24 24.96
[11,12]
MHz Trimmed for 5V operation using
factory trim values.
F
IMO243V
Internal Main Oscillator Frequency for 24 MHz
(3.3V) 22.08 24 25.92
[12, 13]
MHz Trimmed for 3.3V operation using
factory trim values.
F
IMOUSB5V
Internal Main Oscillator Frequency with USB
(5V)
Frequency locking enabled and USB traffic
present.
23.94 24 24.06
[12]
MHz -10°C ≤ T
A
≤ 85°C
4.35 ≤ Vdd ≤ 5.15
F
IMOUSB3V
Internal Main Oscillator Frequency with USB
(3.3V)
Frequency locking enabled and USB traffic
present.
23.94 24 24.06
[12]
MHz -0°C ≤ T
A
≤ 70°C
3.15 ≤ Vdd ≤ 3.45
F
CPU1
CPU Frequency (5V Nominal) 0.93 24 24.96
[11, 12]
MHz
F
CPU2
CPU Frequency (3.3V Nominal) 0.93 12 12.96
[12, 13]
MHz
F
BLK5
Digital PSoC Block Frequency (5V Nominal) 048 49.92
[1 1, 12,
14]
MHz Refer to the AC digital block speci-
fications.
F
BLK3
Digital PSoC Block Frequency (3.3V
Nominal) 024 25.92
[12, 14]
MHz
F
32K1
Internal Low S peed Oscillator Frequency 15 32 64 kHz
Jitter32k 32 kHz Period Jitter –100 ns
Step24M 24 MHz Trim Step Size – 50 – kHz
Fout48M 48 MHz Output Frequency 46.08 48.0 49.92
[11, 13]
MHz Trimmed. Utilizing factory trim
values.
Jitter24M1 24 MHz Period Jitter (IMO) Peak-to-Peak –300 ps
F
MAX
Maximum Frequency of Signal on Row Input
or Row Output. – – 12.96 MHz
T
RAMP
Supply Ramp Time 0 – – μs
Jitter24M1
F
24M
Notes
11. 4.75V < Vdd < 5.25V.
12.Accuracy derived from Intern al Main Oscillator with appropriate trim for Vdd rang e.
13.3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Micro controller T r ims for Dual Voltage-Range Operati on” for i nformation on t rimming f or ope rat ion
at 3.3V.
14.See the individual user module data sheets for information on maximum frequencies for user modules.
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CY8CTMG120
Document Number: 001-46929 Rev. *B Page 23 of 33
AC General Purpose IO Specifications
Table 22 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5 .25V and -40 °C
≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C. These are for
design guidance only.
Figure 9. GPIO Timing Diagram
AC Full-Speed USB Specifications
Table 23 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5 .25V and -10 °C
≤ T
A
≤ 85°C, or 3.0V to 3.6V and -10°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C. These are for
design guidance only.
Table 22. AC GPIO Specifications
Symbol Description Min Typ Max Units Notes
F
GPIO
GPIO Operating Frequency 0–12 MHz Normal Strong Mode
TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.5 to 5.25V , 10% - 90%
TFallF Fall Time, Normal S trong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90%
TRiseS R ise Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25V, 10% - 90%
TFallS Fall Time, Slow Stro ng Mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25V, 10% - 90%
TFallF
TFallS
TRiseF
TRiseS
90%
10%
GPIO
Pin
Output
Voltage
Table 23. AC Full-Speed (12 Mbps) USB Specifications
Symbol Description Min Typ Max Units Notes
T
RFS
Transition Rise Time 4 – 20 ns For 50 pF load.
T
FSS
Transition Fall Time 4 – 20 ns For 50 pF load.
T
RFMFS
Rise/Fall Time Matching: (T
R
/T
F
)90– 111 % For 50 pF load.
T
DRATEF
S
Full-Speed Data Rate 12 -
0.25% 12 12 +
0.25% Mbps
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CY8CTMG120
Document Number: 001-46929 Rev. *B Page 24 of 33
AC Operational Amplifier Specifi c ations
Table 24 and Table 25 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively . Typical parameters apply to 5V and 3.3V at 25°C. These
are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V
.
Table 24. 5V AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units
T
ROA
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Hig h
Power = High, Opamp Bias = High –
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
T
SOA
Falling Settling T ime from 20% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Hig h
Power = High, Opamp Bias = High –
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
SR
ROA
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Hig h
Power = High, Opamp Bias = High
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
SR
FOA
Falling Slew Rate (20% to 80 %)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Hig h
Power = High, Opamp Bias = High
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
BW
OA
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Hig h
Power = High, Opamp Bias = High
0.75
3.1
5.4
–
–
–
–
–
–
MHz
MHz
MHz
E
NOA
Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-H
z
Table 25. 3.3V AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units
T
ROA
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Hig h –
––
–3.92
0.72 μs
μs
T
SOA
Falling Settling T ime from 20% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Hig h –
––
–5.41
0.72 μs
μs
SR
ROA
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Hig h 0.31
2.7 –
––
–V/μs
V/μs
SR
FOA
Falling Slew Rate (20% to 80 %)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Hig h 0.24
1.8 –
––
–V/μs
V/μs
BW
OA
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Hig h 0.67
2.8 –
––
–MHz
MHz
E
NOA
Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz
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Document Number: 001-46929 Rev. *B Page 25 of 33
AC Low Power Comparator Specifications
Table 26 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5 .25V and -40 °C
≤ T
A
≤ 85°C, 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to
5V at 25°C. These are for design guidan ce only.
AC Digital Block Specifications
Table 27 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5 .25V and -40 °C
≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C. These are for
design guid an ce on ly.
Table 26. AC Low Power Co mparator Specifications
Symbol Description Min Typ Max Units Notes
T
RLPC
LPC Response Time – – 50 μs≥ 50 mV overdrive comparator
reference set within V
REFLPC
.
Table 27. AC Digital Block Specifications
Function Description Min Typ Max Units Notes
Timer Capture Pulse Width 50
[15]
– – ns
Maximum Frequency, No Capture – – 49.92 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, With Capture – – 25.92 MHz
Counter Enable Pulse Width 50
[15]
– – ns
Maximum Frequency, No Enable In put – – 49.92 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, Enable Input – – 25.92 MHz
Dead
Band Kill Pulse Width:
Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode 50
[15]
– – ns
Disable Mo de 50
[15]
– – ns
Maximum Frequency – – 49.92 MHz 4.75V < Vdd < 5.25V.
CRCPRS
(PRS
Mode)
Maximum Input Clock Frequency – – 49.92 MHz 4.75V < Vdd < 5.25V.
CRCPRS
(CRC
Mode)
Maximum Input Clock Frequency – – 24.6 MHz
SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz due to
2 x over clocking.
SPIS Maximum Input Clock Frequency – – 4.1 MHz
Width of SS_ Negated Between Transmis-
sions 50
[15]
– – ns
Trans-
mitter Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz due
to 8 x over clocking.
Receiver Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz due
to 8 x over clocking.
Note
15.50 ns minimum input pulse width is based on the input synchronizer s running at 24 MHz (42 ns nominal period).
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CY8CTMG120
Document Number: 001-46929 Rev. *B Page 26 of 33
AC External Clock Specifications
Table 28 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5 .25V and -40 °C
≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C. These are for
design guid an ce on ly.
AC Analog Output Buffer Specifications
Table 29 and Table 30 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively . Typical parameters apply to 5V and 3.3V at 25°C. These
are for design guidance only.
Table 28. AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
F
OSCEXT
Frequency for USB Applications 23.94 24 24.06 MHz
– Duty Cycle 47 50 53 %
– Power up to IMO Switch 150 – – μs
Table 29. 5V AC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units
T
ROB
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High –
––
–2.5
2.5 μs
μs
T
SOB
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High –
––
–2.2
2.2 μs
μs
SR
ROB
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Power = Low
Power = High 0.65
0.65 –
––
–V/μs
V/μs
SR
FOB
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High 0.65
0.65 –
––
–V/μs
V/μs
BW
OBSS
Small Signal Bandwidth, 20mV
pp
, 3dB BW, 100pF Load
Power = Low
Power = High 0.8
0.8 –
––
–MHz
MHz
BW
OBLS
Large Signal Bandwidth, 1V
pp
, 3dB BW, 100pF Load
Power = Low
Power = High 300
300 –
––
–kHz
kHz
Table 30. 3.3V AC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units
T
ROB
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High –
––
–3.8
3.8 μs
μs
T
SOB
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High –
––
–2.6
2.6 μs
μs
SR
ROB
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Power = Low
Power = High 0.5
0.5 –
––
–V/μs
V/μs
SR
FOB
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High 0.5
0.5 –
––
–V/μs
V/μs
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CY8CTMG120
Document Number: 001-46929 Rev. *B Page 27 of 33
AC Programming Specifications
Table 31 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5 .25V and -40 °C
≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C. These are for
design guidance only.
BW
OBSS
Small Signal Bandwidth, 20mV
pp
, 3dB BW , 100pF Load
Power = Low
Power = High 0.7
0.7 –
––
–MHz
MHz
BW
OBLS
Large Signal Bandwidth, 1V
pp
, 3dB BW, 100pF Loa d
Power = Low
Power = High 200
200 –
––
–kHz
kHz
Table 31. AC Programming Specifications
Symbol Description Min Typ Max Units Notes
T
RSCLK
Rise Time of SCLK 1 – 20 ns
T
FSCLK
Fall Time of SCLK 1 – 20 ns
T
SSCLK
Data Setup Time to Falling Edge of SCLK 40 ––ns
T
HSCLK
Data Hol d Time from Falling Edge of SCLK 40 ––ns
F
SCLK
Frequency of SCLK 0–8MHz
T
ERASE
B
Flash Erase Time (Block) –10 –ms
T
WRITE
Flash Block Write Time –30 –ms
T
DSCLK
Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6
T
DSCLK3
Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6
Table 30. 3.3V AC Analog Output Buffer Specifications (continued)
Symbol Description Min Typ Max Units
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CY8CTMG120
Document Number: 001-46929 Rev. *B Page 28 of 33
AC I
2
C Specifications
Table 32 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5 .25V and -40 °C
≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C. These are for
design guidance only.
Figure 10. Definition for Timing for Fast/Standard Mode on the I
2
C Bus
Table 32. AC Characte ristics of the I
2
C SDA and SCL Pins for Vdd
Symbol Description Standard Mode Fast Mode Units Notes
Min Max Min Max
F
SCLI2C
SCL Clock Frequency 0 100 0 400 kHz
T
HDSTAI2
C
Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated. 4.0 –0.6–μs
T
LOWI2C
LOW Period of the SCL Clock 4.7 –1.3–μs
T
HIGHI2C
HIGH Period of the SCL Clock 4.0 –0.6–μs
T
SUSTAI2
C
Setup Time for a Repeated START Condition 4.7 –0.6–μs
T
HDDATI2
C
Data H ol d Time 0 –0–μs
T
SUDATI2
C
Data Setup Time 250 –100
[16]
–ns
T
SUSTOI2
C
Setup Time for STOP Condition 4.0 –0.6–μs
T
BUFI2C
Bus Free Time Between a STOP and START
Condition 4.7 –1.3–μs
T
SPI2C
Pulse Width of Spikes are Supp ressed by the
Input Filter. –– 0 50 ns
SDA
SCL
SSr SP
T
BUFI2C
T
SPI2C
T
HDSTAI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
Note
16.A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but th e re quire ment t
SU;DAT
≥
250 ns must then be me t. This is automa tical ly th e case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line t
rmax
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) bef ore the SCL line is released.
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CY8CTMG120
Document Number: 001-46929 Rev. *B Page 29 of 33
Packaging Information
This section illustrates the package specification for the CY8CTMG120 TrueTouch devices, along with the thermal impedance for the
package and solder reflow peak temperatures.
It is important to note that emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed
description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
For information on the preferred dimensions for mounting Q FN packages, see the following Applicati on Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Pinned vias for thermal conduction are not requ ired for the low power PSoC device.
Figure 11. 56-Lea d (8x8 mm) QFN
001-12921 **
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CY8CTMG120
Document Number: 001-46929 Rev. *B Page 30 of 33
Figure 12. I100-Lead (14x14 x 1.4 mm) TQFP
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Thermal Impedance for the Package
Package Typical θ
JA [17]
56 QFN
[18]
12.93
o
C/W
100 TQFP 51
o
C/W
Table 33. Solder Reflow Peak Temp erature
Package Minimum Peak Temperature
[19]
Maximum Peak Temperature
56 QFN 240
o
C260
o
C
51-85048 *C
Notes
17.T
J
= T
A
+ Power x θ
JA.
18.To achieve the thermal impedance specified for the ** package, the center thermal pad is soldered to the PCB ground plane.
19.Higher temperatures is requ ired based on the solder melting point. T yp ical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste. Refer
to the solder manufacturer specification s.
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CY8CTMG120
Document Number: 001-46929 Rev. *B Page 31 of 33
Development Tool Selection
Software
PSoC Designer
At the core of the PSoC development software suite is PSoC
Designer. Used by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for half a decade.
PSoC Designer is available free of charge at
http://www.cypress.com under Design Resources > Software
and Drivers.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free of charge at http://www.cypress.com/psocpro-
grammer.
Hi-Tech C Lite C omp i ler
Hi-Tech C Lite is an ANSI C compiler optimized for PSoC to
deliver dense, efficient executable code for a smaller-than-eve r
footprint. Hi-Tech C Lite is available for download at
http://www.cypress.htsoft.com. To install the HI-TECH Lite
version, download the complier installation file from HI-TECH
and choose the Lite option when prompted for a registration key.
The Lite version can be upgraded to the 45-day full featured
evaluation version or the PRO version at any time, however the
PRO version can only be enab led with a pu rch ased re gistration
key.
Hi-Tech C Pro Compil e r
Hi-Tech C Pro is an optional upgrade to PSoC Designer that
offers all of the benefits of Hi-Tech C Lite with additional features.
Hi-Tech C Pro is available for purchase either at the Cypress
Online Store or at http://www.cypress.htsoft.com. Hi-Tech C Pro
is recommended for touchscreen applications using the
Multi-Touch All-Point CY8CTMA120 device.
CY3202-C iMAGEcraft C Compiler
CY3202 is the optio nal upgrade to PSoC Designer that enables
the iMAGEcraft C compiler. It can be purchased from the
Cypress Online Store. At http://www.cypress.com, click the
Online Store shopping cart icon at the bottom of the web page,
and click PSoC (Programmable System-on-Chip) to view a
current list of available items.
Evaluation Tools
All evaluation tools can be pu rchased from the Cypress Online
Store.
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC
devices through the MiniProg1 programming unit. The MiniProg
is a small, compact prototyping programmer that connects to the
PC through a provided USB 2.0 cable. The kit includes:
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■
PSoC Designer Software CD
■
Getting S tarted Guide
■
USB 2.0 Cable
Device Programmers
All device programmers can be purchased from the Cypress
Online Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
Modular Programmer Base
■
3 Programming Module Cards
■
MiniProg Programming Unit
■
PSoC Designer Software CD
■
Getting S tarted Guide
■
USB 2.0 Cable
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note: CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
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CY8CTMG120
Document Number: 001-46929 Rev. *B Page 32 of 33
Accessories (Emulation and Programming)
Third Party Tools
Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during devel-
opment and producti on. Specific details for each of these tool s
can be found at http://www.cypress.com under Design
Resources > Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see application note AN2323 “Debugging - Build a PSoC
Emulator into Your Board”.
Ordering Information.
Ordering Code Definitions
Package
Ordering
Code
Flash
(Bytes)
SRAM
(Bytes)
Temperature
Range
Single-Touch
Enabled
Multi-Touch
Gesture
Enabled
Multi-Touch
All-Point
Enabled
X/Y
Sensor
Inputs
56-Pin (8x8 mm) QFN CY8CTMG120-56LFXI 16K 1K -40C to +85C Y Y N Up to 44
56-Pin (8x8 mm) QFN
(Tape and Reel) CY8CTMG120-56LFXIT 16K 1K -40C to +85C Y Y N Up to 44
100-Pin OCD TQFP CY8CTMG120-00AXI 16K 1K -40C to +85C Y Y N Up to 44
CY 8 C TMG xxx-56xx
Package Type:Thermal Rating:
PX = PDIP Pb-FreeC = Commercial
SX = SOIC Pb-FreeI = Industrial
PVX = SSOP Pb-FreeE = Extended
LFX/LKX = QFN Pb-Free
AX = TQFP Pb-Free
BVX = VFBGA Pb-Free
Pin Count: 56-Pin
Part Number
Family Code: TMG = Multi-Touch Touchscreen
Controller
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
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Document Number: 001-46929 Rev. *B Revised July 29, 2008 Page 33 of 33
TrueTouch™, PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Sem icon ductor Corp . Al l ot her trad emarks
or registered tra dema rks refer enced herei n are pr oper ty of the respe ctive co rp oratio ns. Pur chase of I2 C comp onen t s from C ypress or on e of it s subli censed Associat ed Comp an ies conveys a l icen se
under the Philips I2C Patent Rights to use these components in an I2C system, pr ovided that the system conform s to the I2C Standard Specification as defined by Philips. All products and company
names mentioned in this document may be the trademarks of their respective holders.
CY8CTMG120
© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress p roducts are not warranted nor int ended to be used for med ical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypr ess does no t author ize its products fo r use as critica l
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyr igh t laws and internati onal tr eaty pr ovision s. Cypr ess here by gra nt s to lic ensee a p erson al, no n-exclu sive , non- transfer abl e license to copy, use, modify, create derivative works of ,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of lice nsee product to be used on ly in conjunction wit h a Cypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, m odification, transl ation, compilatio n, or represent ation of this S ource Code exce pt as specified above is prohib ited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liabil ity ar ising ou t of t he app licati on or us e of an y product or circ uit de scrib ed herei n. Cypr ess does n ot auth orize it s product s for use a s critical componen ts in life-suppo rt systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC psoc.cypress.com
Clocks & Buffers clocks.cypress.com
Wireless wireless.cypress.com
Memories memory.cypress.com
Image Sensors image.cypress.com
PSoC Solutions
General psoc.cypress.com/solutions
Low Power/Low Voltage psoc.cypress.com/low-power
Precision Analog psoc.cypress.com/precision-analog
LCD Drive psoc.cypress.com/lcd-drive
CAN 2.0b psoc.cypress.com/can
USB psoc.cypress.com/usb
Document Title: CY8CTMG120 TrueTouch™ Multi- To uch Gesture Touch screen Controller
Document Number: 001-46929
Revision ECN Orig. of
Change Submission
Date Description of Change
** 2518134 DSO/AESA 06/18/08 New data sheet
*A 2523303 DSO/PYRS 06/30/08 Updated X/Y sensor inputs to 44 and supporte d screen sizes to 8.4” and below
*B 2549257 YOM/PYRS 08/06/08 Added other sections based on PSoC data sheets
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