SCANSTA111MTNOPB - NATIONAL SEMICONDUCTOR

SCAN92LV090

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN

Literature Number: SNLS058H

December 2006

SCAN92LV090

9 Channel Bus LVDS Transceiver w/ Boundary SCAN

General Description

The SCAN92LV090A is one in a series of Bus LVDS

transceivers designed specifically for the high speed, low

power proprietary backplane or cable interfaces. The device

operates from a single 3.3V power supply and includes nine

differential line drivers and nine receivers. To minimize bus

loading, the driver outputs and receiver inputs are internally

connected. The separate I/O of the logic side allows for loop

back support. The device also features a flow through pin out

which allows easy PCB routing for short stubs between its

pins and the connector.

The driver translates 3V TTL levels (single-ended) to differ-

ential Bus LVDS (BLVDS) output levels. This allows for high

speed operation, while consuming minimal power with re-

duced EMI. In addition, the differential signaling provides

common mode noise rejection of ±1V.

The receiver threshold is less than ±100 mV over a ±1V com-

mon mode range and translates the differential Bus LVDS to

standard (TTL/CMOS) levels.

This device is compliant with IEEE 1149.1 Standard Test Ac-

cess Port and Boundary Scan Architecture with the incorpo-

ration of the defined boundary-scan test logic and test access

port consisting of Test Data Input (TDI), Test Data Out (TDO),

Test Mode Select (TMS), Test Clock (TCK), and the optional

Test Reset (TRST).

Features

■IEEE 1149.1 (JTAG) Compliant

■Bus LVDS Signaling

■Low power CMOS design

■High Signaling Rate Capability (above 100 Mbps)

■0.1V to 2.3V Common Mode Range for VID = 200mV

■±100 mV Receiver Sensitivity

■Supports open and terminated failsafe on port pins

■3.3V operation

■Glitch free power up/down (Driver & Receiver disabled)

■Light Bus Loading (5 pF typical) per Bus LVDS load

■Designed for Double Termination Applications

■Balanced Output Impedance

■Product offered in 64 pin LQFP package and BGA

package

■High impedance Bus pins on power off (VCC = 0V)

Simplified Functional Diagram

10124201

Connection Diagrams

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN

10124202

Top View

Order Number SCAN92LV090VEH

See NS Package Number VEH064DB

10124216

Top View

Order Number SCAN92LV090SLC

See NS Package Number SLC64A

www.national.com 2

SCAN92LV090

Pinout Description

Pin Name TQFP Pin # BGA Pin # Input/Output Descriptions

DO+/RI+ 27, 31, 35, 37, 41, 45,

47, 51, 55

A7, B8, C6, D5, D8, E6,

F7, G5, G6

I/O True Bus LVDS Driver Outputs and Receiver Inputs.

DO−/RI− 26, 30, 34, 36, 40, 44,

46, 50, 54

B5, B6, C7, D6, E5, E8,

F6, G8, H7

I/O Complimentary Bus LVDS Driver Outputs and Receiver

Inputs.

DIN 2, 6, 12, 18, 20, 22, 58,

60, 62

A2, A4, C3, C4, D2, E3,

G3, G4, H3

I TTL Driver Input.

RO 3, 7, 13, 19, 21, 23, 59,

61, 63

A3, B3, C1, C2, D4, E4,

F4, G1, H2

O TTL Receiver Output.

RE 17 H1 I Receiver Enable TTL Input (Active Low).

DE 16 G2 I Driver Enable TTL Input (Active High).

GND 4, 5, 9, 14, 25, 56 B1, B4, D3, E1, F2, H5 Power Ground for digital circuitry (must connect to GND on PC

board). These pins connected internally.

VCC 10, 15, 24, 57, 64 A1, A5, F1, F3, H4 Power VCC for digital circuitry (must connect to VCC on PC

board). These pins connected internally.

AGND 28, 33, 43, 49, 53 A8, C5, D7, F5, G7 Power Ground for analog circuitry (must connect to GND on PC

board). These pins connected internally.

AVCC 29, 32, 42, 48, 52 A6, B7, C8, H6, H8 Power Analog VCC (must connect to VCC on PC board). These

pins connected internally.

TRST 39 F8 I Test Reset Input to support IEEE 1149.1 (Active Low)

TMS 38 E7 I Test Mode Select Input to support IEEE 1149.1

TCK 1 B2 I Test Clock Input to support IEEE 1149.1

TDI 8 D1 I Test Data Input to support IEEE 1149.1

TDO 11 E2 O Test Data Output to support IEEE 1149.1

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SCAN92LV090

Absolute Maximum Ratings (Notes 2, 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (VCC)4.0V

Enable Input Voltage

(DE, RE) −0.3V to (VCC +0.3V)

Driver Input Voltage (DIN) −0.3V to (VCC +0.3V)

Receiver Output Voltage

(ROUT) −0.3V to (VCC +0.3V)

Bus Pin Voltage (DO/RI±) −0.3V to +3.9V

ESD (HBM 1.5 kΩ, 100 pF) >4.5 kV

Driver Short Circuit Duration momentary

Receiver Short Circuit Duration momentary

Maximum Package Power Dissipation at 25°C

LQFP 1.74 W

Derate LQFP Package 13.9 mW/°C

θja 71.7°C/W

θjc 10.9°C/W

Junction Temperature +150°C

Storage Temperature Range −65°C to +150°C

Lead Temperature

(Soldering, 4 sec.) 260°C

Recommended Operating

Conditions

Min Max Units

Supply Voltage (VCC) 3.0 3.6 V

Receiver Input Voltage 0.0 2.4 V

Operating Free Air Temperature −40 +85 °C

Maximum Input Edge Rate

(Note 6)(20% to 80%) Δt/ΔV

Data 1.0 ns/V

Control 3.0 ns/V

DC Electrical Characteristics

Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3)

Symbol Parameter Conditions Pin Min Typ Max Units

VOD Output Differential Voltage RL = 27Ω, Figure 1 DO+/RI+,

DO−/RI−

240 300 460 mV

ΔVOD VOD Magnitude Change 27 mV

VOS Offset Voltage 1.1 1.3 1.5 V

ΔVOS Offset Magnitude Change 5 10 mV

VOH Driver Output High Voltage RL = 27Ω 1.4 1.65 V

VOL Driver Output Low Voltage RL = 27Ω 0.95 1.1 V

IOSD Output Short Circuit Current

(Note 10)

VOD = 0V, DE = VCC, Driver outputs

shorted together |36| |65| mA

VOH Voltage Output High (Note

11)

VID = +300 mV IOH = −400 µA ROUT VCC−0.2 V

Inputs Open VCC−0.2 V

Inputs Terminated,

RL = 27Ω

VCC−0.2 V

VOL Voltage Output Low IOL = 2.0 mA, VID = −300 mV 0.05 0.075 V

IOD Receiver Output Dynamic

Current (Note 10)

VID = 300mV, VOUT = VCC−1.0V −110 |75| mA

VID = −300mV, VOUT = 1.0V |75| 110 mA

VTH Input Threshold High DE = 0V, VCM = 1.5V DO+/RI+,

DO−/RI−

+100 mV

VTL Input Threshold Low −100 mV

VCMR Receiver Common Mode

Range

|VID|/2 2.4 − |

VID|/2 V

IIN Input Current DE = 0V, RE = 2.4V,

VIN = +2.4V or 0V −25 ±1 +25 µA

VCC = 0V, VIN = +2.4V or 0V −20 ±1 +20 µA

VIH Minimum Input High

Voltage

DIN, DE,

RE, TCK,

TRST,

TMS, TDI

2.0 VCC V

VIL Maximum Input Low

Voltage

GND 0.8 V

IIH Input High Current VIN = VCC or 2.4V DIN, DE, RE −20 ±10 +20 µA

IIL Input Low Current VIN = GND or 0.4V −20 ±10 +20 µA

VCL Input Diode Clamp Voltage ICLAMP = −18 mA −1.5 −0.8 V

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SCAN92LV090

Symbol Parameter Conditions Pin Min Typ Max Units

IIH Input High Current VIN = VCC TDI, TMS,

TCK, TRST

-20 +20 µA

IILR Input Low Current VIN = GND, VCC = 3.6v TDI, TMS,

TRST

-25 -115 µA

IIL Input Low Current VIN = GND TCK -20 +20 µA

ICCD Power Supply Current

Drivers Enabled, Receivers

Disabled

No Load, DE = RE = VCC,

DIN = VCC or GND

VCC

50 80 mA

ICCR Power Supply Current

Drivers Disabled, Receivers

Enabled

DE = RE = 0V, VID = ±300mV

50 80 mA

ICCZ Power Supply Current,

Drivers and Receivers TRI-

STATE®

DE = 0V; RE = VCC,

DIN = VCC or GND 50 80 mA

ICC Power Supply Current,

Drivers and Receivers

Enabled

DE = VCC; RE = 0V,

DIN = VCC or GND,

RL = 27Ω

160 210 mA

ICCS Power Supply Current

(SCAN Test Mode), Drivers

and Receivers Enabled

DE = VCC; RE = 0V,

DIN = VCC or GND,

RL = 27Ω, TAP in any state other than

Test-Logic-Reset

180 230 mA

IOFF Power Off Leakage Current VCC = 0V or OPEN,

DIN, DE, RE = 0V or OPEN,

VAPPLIED = 3.6V (Port Pins)

DO+/RI+,

DO−/RI− −20 +20 µA

COUTPUT Capacitance @ Bus Pins DO+/RI+,

DO−/RI− 5 pF

COUTPUT Capacitance @ ROUT ROUT 7 pF

AC Electrical Characteristics

Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6)

Symbol Parameter Conditions Min Typ Max Unit

DIFFERENTIAL DRIVER TIMING REQUIREMENTS

tPHLD Differential Prop. Delay High to Low (Note 8) RL = 27Ω,

Figure 2, Figure 3

CL = 10 pF

1.0 1.8 2.6 ns

tPLHD Differential Prop. Delay Low to High (Note 8) 1.0 1.8 2.6 ns

tSKD1 Differential Skew |tPHLD–tPLHD| (Note 9) 120 ps

tSKD2 Chip to Chip Skew (Note 12) 1.6 ns

tSKD3 Channel to Channel Skew (Note 13) 0.25 0.55 ns

tTLH Transition Time Low to High 0.5 1.2 ns

tTHL Transition Time High to Low 0.5 1.2 ns

tPHZ Disable Time High to Z RL = 27Ω,

Figure 4, Figure 5

CL = 10 pF

3 8 ns

tPLZ Disable Time Low to Z 3 8 ns

tPZH Enable Time Z to High 3 8 ns

tPZL Enable Time Z to Low 3 8 ns

DIFFERENTIAL RECEIVER TIMING REQUIREMENTS

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SCAN92LV090

Symbol Parameter Conditions Min Typ Max Unit

tPHLD Differential Prop. Delay High to Low (Note 8) Figure 6, Figure 7

CL = 35 pF

2.0 2.4 3.9 ns

tPLHD Differential Prop Delay Low to High (Note 8) 2.0 2.4 3.9 ns

tSDK1 Differential Skew |tPHLD–tPLHD| (Note 9) 210 ps

tSDK2 Chip to Chip Skew (Note 12) 1.9 ns

tSDK3 Channel to Channel skew (Note 13) 0.35 0.7 ns

tTLH Transition Time Low to High 1.5 2.5 ns

tTHL Transition Time High to Low 1.5 2.5 ns

tPHZ Disable Time High to Z RL = 500Ω,

Figure 8, Figure 9

CL = 35 pF

4.5 10 ns

tPLZ Disable Time Low to Z 3.5 8 ns

tPZH Enable Time Z to High 3.5 8 ns

tPZL Enable Time Z to Low 3.5 8 ns

SCAN CIRCUITRY TIMING REQUIREMENTS

fMAX Maximum TCK Clock Frequency RL = 500Ω, CL = 35 pF 25.0 75.0 MHz

tSTDI to TCK, H or L 1.5 ns

tHTDI to TCK, H or L 1.5 ns

tSTMS to TCK, H or L 2.5 ns

tHTMS to TCK, H or L 1.5 ns

tWTCK Pulse Width, H or L 10.0 ns

tWTRST Pulse Width, L 2.5 ns

tREC Recovery Time, TRST to TCK 2.0 ns

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.

Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified

except VOD, ΔVOD and VID.

Note 3: All typicals are given for VCC = +3.3V and TA = +25°C, unless otherwise stated.

Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) > 4.5 kV EIAJ (0Ω, 200 pF) > 300V.

Note 5: CL includes probe and fixture capacitance.

Note 6: Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50Ω, tr, tf = <1.0 ns (0%–100%). To ensure fastest propagation delay and

minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge

rate, the better the AC performance.

Note 7: The DS92LV090A functions within datasheet specification when a resistive load is applied to the driver outputs.

Note 8: Propagation delays are guaranteed by design and characterization.

Note 9: tSKD1 |tPHLD–tPLHD| is the worse case skew between any channel and any device over recommended operation conditions.

Note 10: Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity.

Note 11: VOH failsafe terminated test performed with 27Ω connected between RI+ and RI− inputs. No external voltage is applied.

Note 12: Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.

Note 13: Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device, common edge.

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SCAN92LV090

Applications Information

General application guidelines and hints may be found in the

following application notes: AN-808, AN-1108, AN-977,

AN-971, and AN-903.

There are a few common practices which should be implied

when designing PCB for Bus LVDS signaling. Recommended

practices are:

•Use at least 4 PCB board layer (Bus LVDS signals,

ground, power and TTL signals).

•Keep drivers and receivers as close to the (Bus LVDS port

side) connector as possible.

•Bypass each Bus LVDS device and also use distributed

bulk capacitance between power planes. Surface mount

capacitors placed close to power and ground pins work

best. Two or three high frequency, multi-layer ceramic

(MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in parallel

should be used between each VCC and ground. The

capacitors should be as close as possible to the VCC pin.

Multiple vias should be used to connect VCC and Ground

planes to the pads of the by-pass capacitors.

In addition, randomly distributed by-pass capacitors

should be used.

•Use the termination resistor which best matches the

differential impedance of your transmission line.

•Leave unused Bus LVDS receiver inputs open (floating).

Limit traces on unused inputs to <0.5 inches.

•Isolate TTL signals from Bus LVDS signals

MEDIA (CONNECTOR or BACKPLANE) SELECTION:

•Use controlled impedance media. The backplane and

connectors should have a matched differential

impedance.

TABLE 1. Functional Table

MODE SELECTED DE RE

DRIVER MODE H H

RECEIVER MODE L L

TRI-STATE MODE L H

LOOP BACK MODE H L

TABLE 2. Transmitter Mode

INPUTS OUTPUTS

DE DIN DO+ DO−

H L L H

H H H L

H 0.8V< DIN <2.0V X X

L X Z Z

TABLE 3. Receiver Mode

INPUTS OUTPU

RE (RI+) – (RI−)

L L (< −100 mV) L

L H (> +100 mV) H

L−100 mV < VID < +100

H X Z

X = High or Low logic state

L = Low state

Z = High impedance state

H = High state

Test Circuits and Timing Waveforms

10124203

FIGURE 1. Differential Driver DC Test Circuit

10124204

FIGURE 2. Differential Driver Propagation Delay and Transition Time Test Circuit

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SCAN92LV090

10124205

FIGURE 3. Differential Driver Propagation Delay and Transition Time Waveforms

10124206

FIGURE 4. Driver TRI-STATE Delay Test Circuit

10124207

FIGURE 5. Driver TRI-STATE Delay Waveforms

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SCAN92LV090

10124208

FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit

10124214

FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms

10124215

FIGURE 8. Receiver TRI-STATE Delay Test Circuit

10124211

FIGURE 9. Receiver TRI-STATE Delay Waveforms

Typical Bus Application Configurations

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SCAN92LV090

10124212

Bi-Directional Half-Duplex Point-to-Point Applications

10124213

Multi-Point Bus Applications

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SCAN92LV090

Description of Boundary-Scan

Circuitry

The SCAN92LV090 features two unique Scan test modes,

each which requires a unique BSDL model depending on the

level of test access and fault coverage goals. In the first mode

(Mode0), only the TTL Inputs and Outputs of each transceiver

are accessible via a 1149.1 compliant protocol. In the second

mode (Mode1), both the TTL Inputs and Outputs and the dif-

ferential LVDS I/Os are included in the Scan chain.

All test modes are handled by the ATPG software, and BSDL

selection should be invisible to the user.

The BYPASS register is a single bit shift register stage iden-

tical to scan cell TYPE1. It captures a fixed logic low.

Bypass Register Scan Chain Definition

Logic 0

10124209

The INSTRUCTION register is an eight-bit register which

captures the value 00111101.

Instruction Register Scan Chain Definition

10124210

MSB → LSB (Mode0)

Instruction Code Instruction

00000000 EXTEST

10000010 SAMPLE/PRELOAD

10000111 CLAMP

00000110 HIGHZ

All Others BYPASS

MSB → LSB (Mode1)

Instruction Code Instruction

10011001 EXTEST

10010010 SAMPLE/PRELOAD

10001111 CLAMP

00000110 HIGHZ

All Others BYPASS

10124221

Mode 0 Boundary Scan Register Configuration

(Refer to the BSDL for exact register order)

10124220

Mode 1 Boundary Scan Register Configuration

(Refer to the BSDL for exact register order)

11 www.national.com

SCAN92LV090

Physical Dimensions inches (millimeters) unless otherwise noted

64-Lead Molded LQFP Package

Order Number SCAN92LV090VEH

NS Package Number VEH064DB

64-Lead Ball Grid Array Package

Order Number SCAN92LV090SLC

NS Package Number SLC64A

www.national.com 12

SCAN92LV090

Notes

13 www.national.com

SCAN92LV090

Notes

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN

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