1PS8551 07/31/01
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PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger with 3-State Outputs
Logic Block Diagram
Product Features
PI74AVC+16268 is designed for low-voltage operation,
VCC = 1.65V to 3.6V
True ±24mA Balanced Drive @ 3.3V
IOFF supports partial power-down operation
3.6 I/O Tolerant Inputs and Outputs
All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
Industrial operation: 40°C to +85°C
Available Packages:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductors PI74AVC+ series of logic circuits are
produced using the Companys advanced submicron CMOS
technology, achieving industry leading speed.
The PI74AVC+16268, a 12-bit to 24-bit registered bus exchanger
designed for 1.65V to 3.6V VCC operation, is used for applications
in which data must be transferred from a narrow high-speed bus to
a wide, lower frequency bus. It provides synchronous data exchange
between the two ports. Data is stored in internal registers on the low-
to-high transition of the clock (CLK) input when appropriate clock-
enable (CLKEN) inputs are low. The select (SEL) line is synchronous
with CLK and selects 1B or 2B input data for the A outputs.
For data transfer in the A-to-B direction, a two-stage pipeline is
provided in the A-to-1B path, with a single storage register in the
A-to-2B path. Proper control of these inputs allows two sequential
12-bit words to be presented synchronously as a 24-bit word on the
B-port. Data flow is controlled by the active-low output enables
(OEA, OEB). These control terminals are registered so bus direction
changes are synchronous with CLK.
To ensure the high-impedance state during power up or power
down, a clock pulse should be applied as soon as possible and OE
should be tied to VCC through a pullup resistor, the minimum value
of the resistor is determined by the current-sinking capability of the
driver. Because OE is being routed through a register, the active
state of the outputs cannot be determined prior to the arrival of the
first clock pulse.
G1
C1
1D
1
B
1
OEB
CLK
CLKEN1B
SEL
1
1
C1
1D C1 1D
CE
C1
2
B
1
23
6
A1 8
28
56
55
30
27
2
29
CLKEN2B
CLKENA1
CLKENA2
CE
1D
V
V
CE
V
1D
V
CE
C1
1D
CE
C1
1D
VV
C1
V
OEA 1
1 of 12 Channels
C1
1D
V