Fractional-N PLL with Integrated VCO
25 MHz to 3000 MHz
Data Sheet HMC832
FEATURES
RF bandwidth:
25 MHz to 3000 MHz
3.3 V supply
Maximum phase detector rate: 100 MHz
Ultralow phase noise
−110 dBc/Hz in band, typical
Fractional figure of merit (FOM): −226 dBc/Hz
24-bit step size, resolution 3 Hz typical
Exact frequency mode with 0 Hz frequency error
Fast frequency hopping
40-lead 6 mm × 6 mm SMT package: 36 mm2
APPLICATIONS
Cellular infrastructure
Microwave radio
WiMax, WiFi
Communications test equipment
CATV equipment
DDS replacement
Military
Tunable reference source for spurious-free performance
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The HMC832 is a 3.3 V, high performance, wideband, frac-
tional-N, phase-locked loop (PLL) that features an integrated
voltage controlled oscillator (VCO) with a fundamental
frequency of 1500 MHz to 3000 MHz, and an integrated VCO
output divider (divide by 1/2/4/6/…60/62), that enables the
HMC832 to generate continuous frequencies from 25 MHz to
3000 MHz. The integrated phase detector (PD) and delta-sigma
(Δ-Σ) modulator, capable of operating at up to 100 MHz, permit
wider loop bandwidths and faster frequency tuning with
excellent spectral performance.
Industry leading phase noise and spurious performance, across
all frequencies, enable the HMC832 to minimize blocker effects,
and to improve receiver sensitivity and transmitter spectral
purity. A low noise floor (−160 dBc/Hz) eliminates any contri-
bution to modulator/mixer noise floor in transmitter applications.
The HMC832 is footprint-compatible to the market leading
HMC830 PLL with integrated VCO. It features 3.3 V supply and
an innovative programmable performance technology that enables
the HMC832 to tailor current consumption and corresponding
noise floor performance to individual applications by selecting
either a low current consumption mode or a high performance
mode for an improved noise floor performance.
Additional features of the HMC832 include 12 dB of RF output
gain control in 1 dB steps; output mute function to automatically
mute the output during frequency changes when the device is
not locked; selectable output return loss; programmable
differential or single-ended outputs, with the ability to select
either output in single-ended mode; and a Δ-Σ modulator exact
frequency mode that enables users to generate output frequencies
with 0 Hz frequency error.
CP
EN
EN
VTUNE
RF_N
RF_P
SEN
CP PFD
÷R
÷N
÷1, 2, 4, 6, ...62
MODULATOR
XREFP
LD/SDO SCK SDI
CAL
VCO
LOCK
DETECT
HMC832
SPI
PROGRAMMING
INTERFACE
CONTROL
12827-001
Rev. A Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
HMC832 Data Sheet
Rev. A | Page 2 of 48
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 6
Recommended Operating Conditions ...................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 14
PLL Subsystem Overview .......................................................... 14
VCO Subsystem Overview ........................................................ 14
SPI (Serial Port Interface) Configuration of PLL and VCO
Subsystems ................................................................................... 14
VCO Subsystem .......................................................................... 16
PLL Subsystem ............................................................................ 20
Soft Reset and Power-On Reset ................................................ 28
Power-Down Mode .................................................................... 29
General-Purpose Output (GPO) Pin ....................................... 29
Chip Identification ..................................................................... 29
Serial Port .................................................................................... 29
Applications Information .............................................................. 33
Power Supply ............................................................................... 34
Programmable Performance Technology................................ 34
Loop Filter and Frequency Changes ........................................ 34
RF Programmable Output Return Loss ................................... 35
Mute Mode .................................................................................. 35
PLL Register Map ........................................................................... 36
ID, Read Address, and RST Registers ...................................... 36
Reference Divider, Integer, and Fractional Frequency
Registers ....................................................................................... 36
VCO SPI Register ....................................................................... 37
Delta-Sigma Configuration ....................................................... 37
Lock Detect Register .................................................................. 38
Analog Enable (EN) Register .................................................... 38
Charge Pump Register ............................................................... 39
Autocalibration Register ............................................................ 39
Phase Detector (PD) Register ................................................... 40
Exact Frequency Mode Register ............................................... 40
General-Purpose, Serial Port Interface, and Reference
Divider (GPO_SPI_RDIV) Register ........................................ 41
VCO Tune Register .................................................................... 42
SAR Register ............................................................................... 42
General-Purpose 2 Register ...................................................... 42
Built-In Self Test Register .......................................................... 42
VCO Subsystem Register Map ...................................................... 43
VCO Enable Register ................................................................. 43
VCO Output Divider Register .................................................. 44
VCO Configuration Register .................................................... 44
VCO Calibration/Bias, CF Calibration, and MSB Calibration
Registers ....................................................................................... 45
VCO Output Power Control ..................................................... 45
Evaluation Printed Circuit Board (PCB) ..................................... 46
Changing Evaluation Board Reference Frequency and CP
Current Configuration .............................................................. 46
Evaluation Kit Contents ............................................................ 46
Outline Dimensions ....................................................................... 47
Ordering Guide .......................................................................... 48
REVISION HISTORY
11/14—Rev. 0 to Rev. A
This Hittite Microwave Products data sheet has been reformatted
to meet the styles and standards of Analog Devices, Inc.
Updated Format .................................................................. Universal
Moved Endnotes from Typical Performance Characteristics
Section to the Applications Information Section ....................... 34
Changes to Ordering Guide .......................................................... 48
Data Sheet HMC832
SPECIFICATIONS
VPPCP, VDDLS, VCC1, VCC2 = 3.3 V; RVDD, AVDD, DVDD, VCCPD, VCCHF, VCCPS = 3.3 V minimum and maximum specified
across the temperature range of −40°C to +85°C.
Table 1.
Parameter
Test Conditions/Comments
Min Typ Max Unit
RF OUTPUT CHARACTERISTICS
Output Frequency
25
3000
MHz
VCO Frequency at PLL Input 1500 3000 MHz
RF Output Frequency at fVCO 1500 3000 MHz
OUTPUT POWER
RF Output Power at Fundmental
Frequency
2000 MHz across all frequencies (see Figure 25)
Maximum gain setting: VCO_REG 0x07[3:0] = 11d
single-ended
7 dBm
Gain Setting 6: VCO_REG 0x07[3:0] = 6d differential 2 dBm
Output Power Control Range 1 dB steps 12 dB
HARMONICS FOR FUNDAMENTAL
MODE
fo Mode at 2 GHz 2nd/3rd/4th −20/−29/−45 dBc
fo/2 Mode at 2 GHz/2 = 1 GHz 2nd/3rd/4th −26/−10/−34 dBc
fo/30 Mode at 3 GHz/30 = 100 MHz 2nd/3rd/4th −33/−10/−40 dBc
fo/62 Mode at 1550 MHz/62 = 25 MHz 2nd/3rd/4th −40/−6/−43 dBc
VCO OUTPUT DIVIDER
VCO RF Divider Range
1, 2, 4, 6, 8, … 62
1
62
PLL RF DIVIDER CHARACTERISTICS
19-Bit N-Divider Range (Integer) Maximum = 219 − 1 16 524,287
19-Bit N-Divider Range (Fractional) Fractional nominal divide ratio varies (±4) dynamically
maximum
20 524,283
REFERENCE (XREFP PIN) INPUT
CHARACTERISTICS
Maximum XREFP Input Frequency 350
MHz
XREFP Input Level AC-coupled1 −6
+12 dBm
XREFP Input Capacitance 5 pF
14-Bit R-Divider Range 1 16,383
PHASE DETECTOR (PD)2
PD Frequency Fractional Mode3
DC 100 MHz
PD Frequency Integer Mode DC 100 MHz
CHARGE PUMP
Output Current 0.02
2.54 mA
Charge Pump Gain Step Size 20 µA
PD/Charge Pump SSB Phase Noise 50 MHz reference, input referred
1 kHz −143 dBc/Hz
10 kHz Add 2 dB for fractional mode −150 dBc/Hz
100 kHz Add 3 dB for fractional mode −152 dBc/Hz
LOGIC INPUTS
VSW 40
50 60 % DVDD
LOGIC OUTPUTS
Output High Voltage (VOH ) DVDD V
Output Low Voltage (VOL ) 0 V
Output Impedance 100 200 Ω
Maximum Load Current 1.5 mA
POWER SUPPLY VOLTAGES
3.3 V Supplies AVDD, VCCHF, VCCPS, VCCPD, RVDD, DVDD, VPPCP,
VDDLS, VCC1, VCC2
3.1
3.3 3.5 V
Rev. A | Page 3 of 48
HMC832 Data Sheet
Parameter
Test Conditions/Comments
Min Typ Max Unit
POWER SUPPLY CURRENTS
High Performance Mode
2500 MHz, Gain 11 219 mA
800 MHz, Gain 11 230 mA
2500 MHz, Gain 6 226 mA
800 MHz, Gain 6 237 mA
2500 MHz, Gain 1 210 mA
800 MHz, Gain 1 221 mA
Low Current Mode
2500 MHz, Gain 6
195
mA
800 MHz, Gain 6 205 mA
2500 MHz, Gain 1 180 mA
800 MHz, Gain 1
VCO_REG 0x03[1:0] = 3d4
Gain 11 (VCO_REG 0x07[3:0] = 11d) single-ended
output (VCO_REG 0x03[3:2] = 2d)
Single-ended output
Gain 6 (VCO_REG 0x07[3:0] = 6d) differential output
(VCO_REG 0x03[3:2] = 3d)
Differential output
Gain 1 (VCO_REG 0x07[3:0] = 1d) differential output
(VCO_REG 0x03[3:2] = 3d)
Differential output
VCO_REG 0x03[1:0] = 1d4
Gain 6 (VCO_REG 0x07[3:0] = 6d), differential output
(VCO_REG 0x03[3:2] = 3d)
Differential output
Gain 1 (VCO_REG 0x07[3:0] = 1d), differential output
(VCO_REG 0x03[3:2] = 3d)
Differential output 192 mA
Power-Down
Crystal Off Register 0x01 = 0, crystal not clocked 10 µA
Crystal On, 100 MHz Register 0x01 = 0, crystal clocked 100 MHz 5 mA
POWER-ON RESET
Typical Reset Voltage on DVDD 700 mV
Minimum DVDD Voltage for No Reset 1.5 V
Power-On Reset Delay 250 µs
VCO OPEN-LOOP PHASE NOISE
fo @ 2 GHz5
10 kHz Offset −88 dBc/Hz
100 kHz Offset −116 dBc/Hz
1 MHz Offset
−139
dBc/Hz
10 MHz Offset −157 dBc/Hz
100 MHz Offset −162 dBc/Hz
fo @ 2 GHz/2 = 1 GHz5
10 kHz Offset −93 dBc/Hz
100 kHz Offset
−122
dBc/Hz
1 MHz Offset −145 dBc/Hz
10 MHz Offset −159 dBc/Hz
100 MHz Offset
−162
dBc/Hz
fo @ 3 GHz/30 = 100 MHz5
10 kHz Offset −110 dBc/Hz
100 kHz Offset −139 dBc/Hz
1 MHz Offset −160 dBc/Hz
10 MHz Offset
−163
dBc/Hz
100 MHz Offset −163 dBc/Hz
FIGURE OF MERIT (FOM)
Floor Integer Mode (Figure 24) Normalized to 1 Hz −229 dBc/Hz
Floor Fractional Mode (Figure 24)
Normalized to 1 Hz
−226
dBc/Hz
Flicker (Both Modes) (Figure 24) Normalized to 1 Hz −268 dBc/Hz
Rev. A | Page 4 of 48
Data Sheet HMC832
Parameter
Test Conditions/Comments
Min Typ Max Unit
VCO CHARACTERISTICS
VCO Tuning Sensitivity
2800 MHz Measured with 1.5 V on VTUNE; see Figure 29 24.6 MHz/V
2400 MHz Measured with 1.5 V on VTUNE; see Figure 29 25.8 MHz/V
2000 MHz Measured with 1.5 V on VTUNE; see Figure 29 25.2 MHz/V
1600 MHz Measured with 1.5 V on VTUNE; see Figure 29 24.3 MHz/V
VCO Supply Pushing Measured with 1.5 V on VTUNE 2.8 MHz/V
1 Measured with 100 Ω external termination. See Reference Input Stage section for more details.
2 Slew rate of ≥0.5 ns/V is recommended, see Reference Input Stage section for more details. Frequency is guaranteed across process voltage and temperature from
−40°C to +85°C.
3 This maximum PD frequency can only be achieved if the minimum N value is respected. For example, in the case of fractional mode, the maximum PD frequency =
fVCO/20 or 100 MHz, whichever is less.
4 For detailed current consumption information, refer to Figure 33 and Figure 36.
5 Gain setting = 6 (VCO_REG 0x07[3:0] = 6d) in high performance mode (VCO_REG 0x03[1:0] = 3d).
TIMING SPECIFICATIONS
SPI Write Timing Characteristics
AVDD = DVDD = 3 V, AGND = DGND = 0 V.
Table 2. SPI Write Timing Characteristics, See Figure 47
Parameter Test Conditions/Comments Min Typ Max Unit
t1 SDI setup time to SCLK rising edge 3 ns
t2 SCLK rising edge to SDI hold time 3 ns
t3 SEN low duration 10 ns
t4 SEN high duration 10 ns
t5 SCLK 32nd rising edge to SEN rising edge 10 ns
t6 Recovery time 20 ns
Maximum serial port clock speed 50 MHz
Table 3. SPI Read Timing Characteristics, See Figure 48
Parameter Test Conditions/Comments Min Typ Max Unit
t1 SDI setup time to SCK rising edge 3 ns
t2 SCK rising edge to SDI hold time 3 ns
t3 SEN low duration 10 ns
t4 SEN high duration 10 ns
t5 SCK rising edge to SDO time 8.2 ns + 0.2 ns/pF ns
t6 Recovery time 10 ns
t7 SCK 32nd rising edge to SEN rising edge 10 ns
Rev. A | Page 5 of 48
HMC832 Data Sheet
Rev. A | Page 6 of 48
ABSOLUTE MAXIMUM RATINGS
Table 4. Absolute Maximum Ratings
Parameter Rating
AVDD, RVDD, DVDD, VCCPD, VCCHF, VCCPS−0.3 V to +3.6 V
VPPCP, VDDLS, VCC1 −0.3 V to +3.6 V
VCC2 −0.3 V to +3.6 V
Operating Temperature −40°C to +85°C
Storage Temperature −65°C to +150°C
Maximum Junction Temperature 150°C
Thermal Resistance (θJC) (Junction to Case (Ground
Paddle))
9°C/W
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
ESD Sensitivity (HBM) Class 1B
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
RECOMMENDED OPERATING CONDITIONS
Table 5. Recommended Operating Conditions
Parameter Min Typ Max Units
Temperature
Junction Temperature1 125 °C
Ambient Temperature −40 +85 °C
Supply Voltage
AVDD, RVDD, DVDD, VCCPD, VCCHF,
VCCPS, VPPCP, VDDLS, VCC1, VCC2
3.1 3.3 3.5 V
1 Layout design guidelines set out in Qualification Test Report are strongly
recommended.
ESD CAUTION
Data Sheet HMC832
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
AVDD
DC Power Supply for Analog Circuitry.
2, 5, 6, 8, 9, 11 to
14, 18 to 22, 24, 26,
34, 37, 38
NC No Connect. These pins are not connected internally; however, it is recommended to connect these
pins to RF/dc ground externally.
3 VPPCP Power Supply for Charge Pump Analog Section.
CP
Charge Pump Output.
7 VDDLS Power Supply for the Charge Pump Digital Section.
10 RVDD Reference Supply.
15 XREFP Reference Oscillator Input.
16 DVDD DC Power Supply for Digital (CMOS) Circuitry.
17 CEN PLL Subsystem Enable. Note that there is no effect on the VCO subsystem. Connect to logic high for
normal operation.
23 VTUNE VCO Varactor. Tuning port input.
25 VCC2 VCO Analog Supply 2.
27 VCC1 VCO Analog Supply 1.
28 RF_N RF Negative Output.
RF_P
RF Positive Output.
SEN
PLL Serial Port Enable (CMOS) Logic Input.
31 SDI PLL Serial Port Data (CMOS) Logic Input.
32 SCK PLL Serial Port Clock (CMOS) Logic Input.
33 LD/SDO Lock Detect, or Serial Data, or General-Purpose (CMOS) Logic Output (GPO).
35 VCCHF DC Power Supply for Analog Circuitry.
36 VCCPS DC Power Supply for Analog Prescaler.
39 VCCPD DC Power Supply for Phase Detector.
40 BIAS External Bypass Decoupling for Precision Bias Circuits. Note: 1.920 V ± 20 mV reference voltage (BIAS) is
generated internally and cannot drive an external load. It must be measured with a 10 GΩ meter, such
as the Agilent 34410A; a normal 10 MΩ DVM reads erroneously.
EP Exposed Pad. The exposed pad must be connected to RF/dc ground.
NOTES
1. NC = NO CO NNE C T. DO NO T CO NNE CT TO THIS PIN.
2. T HE E X P OSE D GRO UND PAD MUST BE
CONNECTED TO RF/ DC GROUND.
1AVDD 2NC 3VPPCP 4CP 5NC 6NC 7VDDLS 8NC 9NC 10RVDD
23 VTUNE
24 NC
25 VCC2
26 NC
27 VCC1
28 RF_N
29 RF_P
30 SEN
22 NC
21 NC
11NC 12NC 13NC
15XREFP
17CEN 16DVDD
18NC 19NC 20NC
14NC
33 LD/SDO
34 NC
35 VCCHF
36 VCCPS
37 NC
38 NC
39 VCCPD
40 BIAS
32 SCK
31 SDI
HMC832
TOP VIEW
(No t t o Scal e)
12827-002
Rev. A | Page 7 of 48
HMC832 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. Typical Closed-Loop Integer Phase Noise, 50 MHz PD Frequency, Output
Gain = 6 (VCO_REG 0x07[3:0] = 6d), High Performance Mode (VCO_REG 0x03[1:0]
= 3d), Phase Noise Integrated from 1 kHz to 100 MHz, See Table 12
Figure 4. Open-Loop VCO Phase Noise at 1800 MHz
Figure 5. Free Running VCO Phase Noise at 3000 MHz
Figure 6. Typical Closed-Loop Fractional Phase Noise, 50 MHz PD Frequency,
Output Gain = 6 (VCO_REG 0x07[3:0] = 6d), High Performance Mode (VCO_REG
0x03[1:0] = 3d), Phase Noise Integrated from 1 kHz to 100 MHz, See Table 12
Figure 7. Closed-Loop Phase Noise at 1800 MHz, Divided by 1 to 62, PD
Frequency, Loop Filter Bandwidth = 75 kHz (Type 2 from Table 12), High Perfor-
mance Mode (VCO_REG 0x03[1:0] = 3d), Subset of Available Output Divide Ratios
is Shown; Full Range of Output Divide Values Includes 1, 2, 4, 6, 8, … 58, 60, 62
Figure 8. Closed-Loop Phase Noise at 3000 MHz, Divided by 1 to 62, PD
Frequency, Loop Filter Bandwidth = 75 kHz (Type 2 from Table 12), High Perfor-
mance Mode (VCO_REG 0x03[1:0] = 3d), Subset of Available Output Divide Ratios
is Shown; Full Range of Output Divide Values Includes 1, 2, 4, 6, 8, … 58, 60, 62
–170 1k 10k 100k 1M 10M 100M
–160
–150
–140
–130
–120
–110
–100
OFF SET (Hz)
PHASE NOISE (dBc/Hz)
750MHz, EVM = –62.5d B, O R 0.075%
1600MHz, EVM = –57dB O R 0.141%
2500MHz, EVM = –53.3d B OR 0. 216%
875MHz, EVM = –64.8d B OR 0. 058%
1600MHz, EVM = –59.8d B OR 0. 102%
2500MHz, EVM = –55.8d B OR 0. 168%
LOOP BW = 127kHz
LOOP BW = 75kHz
12827-003
1k 10k 100k 1M 10M 100M
OFF SET (Hz)
–180
–160
–140
–120
–100
–80
–60
PHASE NOISE (dBc/Hz)
LOW CURRE NT MODE
(VCO_REG 0x03[ 10] = 1d)
HIG H P E RFO RM ANCE M ODE
(VCO_REG 0x03[ 10] = 3d)
12827-004
PHASE NOISE (dBc/Hz)
1k 10k 100k 1M 10M 100M
OFF SET (Hz)
–180
–160
–140
–120
–100
–80
–40
–60
LOW CURRE NT MODE
(VCO_REG 0x03[ 10] = 1d)
HIG H P E RFO RM ANCE M ODE
(VCO_REG 0x03[ 10] = 3d)
12827-005
–170 1k 10k 100k 1M 10M 100M
–160
–150
–140
–130
–120
–110
–100
OFF SET (Hz)
PHASE NOISE (dBc/Hz)
LOOP BW = 127kHz
880MHz, EVM = –61.3d B OR 0. 086%
1605MHz, EVM = –57.5d B OR 0. 133%
2505MHz, EVM = –52dB O R 0.251%
880MHz, EVM = –61.8d B OR 0. 081%
1605MHz, EVM = –57.2d B OR 0. 138%
2505MHz, EVM = –53.9d B OR 0. 204%
LOOP BW = 75kHz
12827-006
1k 10k 100k 1M 10M 100M
–170
–160
–150
–140
–130
–120
–110
–100
OFF SET (Hz)
PHASE NOISE (dBc/Hz)
÷16
÷32
÷62
÷1
÷2
÷8
÷4
12827-007
1k 10k 100k 1M 10M 100M
–170
–160
–150
–140
–130
–120
–110
–100
OFF SET (Hz)
PHASE NOISE (dBc/Hz)
÷16
÷32
÷62
÷1
÷2
÷8
÷4
12827-008
Rev. A | Page 8 of 48
Data Sheet HMC832
Figure 9. Fractional Spurious Performance at 904 MHz, Exact Frequency
Mode On, 122.88 MHz XTAL, PFD = 61.44 MHz, Channel Spacing = 200 kHz,
Loop Filter Type 2 (See Table 12)
Figure 10. Fractional Spurious Performance at 2118.24 MHz,
Exact Frequency Mode On, 122.88 MHz XTAL, PFD = 61.44 MHz, Channel
Spacing = 240 kHz, Loop Filter Type 2 (See Table 12)
Figure 11. Fractional Spurious Performance at 2646.96 MHz, Exact Frequency
Mode On, 122.88 MHz XTAL, PFD = 61.44 MHz, Channel Spacing = 240 kHz,
Loop Filter Type 2 (See Table 12)
Figure 12. Fractional Spurious Performance at 1804 MHz, Exact Frequency
Mode On, 122.88 MHz XTAL, PFD = 61.44 MHz, Channel Spacing = 200 kHz,
Loop Filter Type 2 (See Table 12)
Figure 13. Fractional Spurious Performance at 2118.24 MHz, Identical
Configuration to Figure 10 with Exact Frequency Mode Off
Figure 14. Fractional Spurious Performance at 2646.96 MHz, Identical
Configuration to Figure 11 with Exact Frequency Mode Off
–180
–160
–140
–120
–100
–80
–60
PHASE NOISE (dBc/Hz)
OFF SET (Hz)
1k 10k 100k 1M 10M 100M
LO W CURRENT M ODE (VCO_REG0 x0 3 [10 ] = 1d )
SSB INTEGRATED PHASE NOI SE = –64 . 3 dBc
INTEGRATION BANDW IDTH = 1 k Hz TO 100MHz
SNR = 61.3dB, EVM = 0. 0 86 % , PHASE NO I SE
INTEGRATION BANDW IDTH 1k Hz TO 100M Hz
HIGH PERF ORM ANCE MODE ( VCO_ REG0x 0 3[10 ] = 3 d)
SSB INTEGRATED PHASE NOI SE = –65 . 5 dBc
INTEGRATION BANDW IDTH = 1 k Hz TO 100MHz
SNR = 62.5dB, EVM = 0. 0 75 % PHASE NO ISE
INTEGRATION BANDW IDTH 1k Hz TO 100M Hz
12827-009
–180
–160
–140
–120
–100
–80
–60
PHASE NOISE (dBc/Hz)
OFFSET (Hz)
1k 10k 100k 1M 10M 100M
HIGH PERF ORM ANCE MODE ( VCO_ REG0x 0 3[10 ] = 3 d)
SSB INTEGRATED PHASE NOI SE = –57 . 4 5d Bc
INTEGRATION BANDW IDTH = 1 k Hz TO 100MHz
SNR = 54.45dB, EVM = 0. 189% , PHASE NOISE
INTEGRATION BANDW IDTH 1k Hz TO 100M Hz
LO W CURRENT M ODE (VCO_REG0 x0 3 [10 ] = 1d )
SSB INTEGRATED PHASE NOI SE = –57 dBc
INTEGRATION BANDW IDTH = 1 k Hz TO 100MHz
SNR = 54d B, EVM = 0.19 9% , PHASE NO I SE
INTEGRATION BANDW IDTH 1k Hz TO 100M Hz
12827-010
–180
–160
–140
–120
–100
–80
–60
PHASE NOISE (dBc/Hz)
OFF SET (Hz)
1k 10k 100k 1M 10M 100M
LO W CURRENT MO DE (VCO_REG0 x0 3 [10 ] = 1d )
SSB INTEGRATED PHASE NOI SE = –55 .6dBc
INTEGRATION BANDW IDTH = 1 k Hz TO 100MHz
SNR = 52.6dB, EVM = 0. 2 34 % , PHASE NO I SE
INTEGRATION BANDW IDTH 1k Hz TO 100M Hz
HIGH PERF ORM ANCE MODE ( VCO_ REG0x 0 3[1 0] = 3 d )
SSB INTEGRATED PHASE NOI SE = –56 dBc
INTEGRATION BANDW IDTH = 1 k Hz TO 100MHz
SNR = 53d B, EVM = 0.22 4% , PHASE NO ISE
INTEGRATION BANDW IDTH 1k Hz TO 100M Hz
12827-011
–180
–160
–140
–120
–100
–80
–60
PHASE NOISE (dBc/Hz)
OFF SET (Hz)
1k 10k 100k 1M 10M 100M
LO W CURRENT MO DE (VCO_REG0 x0 3 [10 ] = 1d )
SSB INTEGRATED PHASE NOI SE = –58 .7dBc
INTEGRATION BANDW IDTH = 1 k Hz TO 100MHz
SNR = 55.7dB, EVM = 0. 1 64 % , PHASE NO I SE
INTEGRATION BANDW IDTH 1k Hz TO 100M Hz
HIGH PERF ORM ANCE MODE ( VCO_ REG0x 0 3[1 0] = 3 d )
SSB INTEGRATED PHASE NOI SE = –59 dBc
INTEGRATION BANDW IDTH = 1 k Hz TO 100MHz
SNR = 56d B, EVM = 0.15 8% , PHASE NO ISE
INTEGRATION BANDW IDTH 1k Hz TO 100M Hz
12827-012
–180
–160
–140
–120
–100
–80
–60
PHASE NOISE (dBc/Hz)
OFF SET (Hz)
1k 10k 100k 1M 10M 100M
LO W CURRENT MO DE (VCO_REG0 x0 3 [10 ] = 1d )
SSB INTEGRATED PHASE NOI SE = –57 dBc
INTEGRATION BANDW IDTH = 1 k Hz TO 100MHz
SNR = 54, EVM = 0. 1 99 % , PHASE NO I SE
INTEGRATION BANDW IDTH 1k Hz TO 100M Hz
HIGH PERF ORM ANCE MODE ( VCO_ REG0x 0 3[1 0] = 3 d )
SSB INTEGRATED PHASE NOI SE = –57 .45dBc
INTEGRATION BANDW IDTH = 1 k Hz TO 100MHz
SNR = 54.45dB, EVM = 0. 189% , PHASE NOISE
INTEGRATION BANDW IDTH 1k Hz TO 100M Hz
12827-013
–180
–160
–140
–120
–100
–80
–60
PHASE NOISE (dBc/Hz)
OFF SET (Hz)
1k 10k 100k 1M 10M 100M
LO W CURRENT MO DE (VCO_REG0 x0 3 [10 ] = 1d )
SSB INTEGRATED PHASE NOI SE = –55 .6dBc
INTEGRATION BANDW IDTH = 1 k Hz TO 100MHz
SNR = 52.6dB, EVM = 0. 2 34 % , PHASE NO I SE
INTEGRATION BANDW IDTH 1k Hz TO 100M Hz
HIGH PERF ORM ANCE MODE ( VCO_ REG0x 0 3[1 0] = 3 d )
SSB INTEGRATED PHASE NOI SE = –56 dBc
INTEGRATION BANDW IDTH = 1 k Hz TO 100MHz
SNR = 53d B, EVM = 0.22 4% , PHASE NO ISE
INTEGRATION BANDW IDTH 1k Hz TO 100M Hz
12827-014
Rev. A | Page 9 of 48
HMC832 Data Sheet
Figure 15. Low Frequency Performance, 100 MHz XTAL, PD Frequency =
50 MHz, Loop Filter Type 3 (See Table 12), Integer Mode, 50 MHz Low-Pass
Filter at the Output of HMC832 for the 25 MHz Curve Only, Charge Pump Set to
Maximum Value
Figure 16. Typical Spurious Emissions at 2000.1 MHz, Tunable Reference,
Loop Filter Type 2 (see Table 12 and the Loop Filter and Frequency Changes
Section)
Figure 17. Open-Loop Phase Noise
Figure 18. Typical Spurious Emissions at 2000.1 MHz, 50 MHz Fixed
Reference, 50 MHz PD Frequency, Integer Boundary Spur Inside the Loop
Filter Bandwidth (See the Loop Filter and Frequency Changes Section)
Figure 19. Typical Spurious vs. Offset from 2 GHz, Fixed 50 MHz Reference vs.
Tunable 47.5 MHz Reference (See the Loop Filter and Frequency Changes
Section)
Figure 20. Open-Loop Phase Noise vs. Frequency at Various Temperatures
–170
–160
–150
–140
–130
–120
PHASE NOISE (dBc/Hz)
OFF SET (Hz)
100 1k 10k 100k 1M 10M 100M
12827-015
100MHz OUTP UT
55.55M Hz OUTP UT
25MHz OUTP UT
–180
–160
–140
–120
–100
–80
–60
PHASE NOISE (dBc/Hz)
OFF SET (Hz)
1k 10k 100k 1M 10M 100M
12827-016
–180
–160
–140
–120
–100
–80
–40
–60
PHASE NOISE (dBc/Hz)
OFF SET (Hz)
1k 10k 100k 1M 10M 100M
HIG H P E RFO RM ANCE M ODE ON
(VCO_REG 0x03[ 1: 0] = 3d)
2854MHz
2453MHz
2013MHz
1587MHz
12827-017
–180
–160
–140
–120
–100
–80
–60
PHASE NOISE (dBc/Hz)
OFF SET (Hz)
1k 10k 100k 1M 10M 100M
12827-018
–120
–110
–100
–90
–80
–70
–60
PHASE NOISE (dBc/Hz)
OUTPUT FREQUENCY (kHz )
2000.01 2000.1 2001
TYPICAL SPURIOUS VS. OFFSET FROM 2GHz,
TUNABLE REFERE NCE ~ 47.5MHz
TYPICAL SPURIOUS VS. OFFSET FROM 2GHz,
FIXED RE FERE NCE = 50M Hz
12827-019
–170
–160
–150
–140
–130
–120
–110
–100
1000100
PHASE NOISE (dBc/Hz)
FREQUENCY (MHz)
300 300030
100kHz OFFSET
ALL M ODES
1MHz OFFSET
ALL M ODES
100MHz OFFSET
HIGH PERF ORM ANCE
MODE
100MHz OFFSET
LO W CURRENT MO DE
–40°C
+27°C
+85°C
12827-020
Rev. A | Page 10 of 48
Data Sheet HMC832
Figure 21. Single Sideband Integrated Phase Noise, High Performance Mode,
Loop Filter Type 2 (See Table 12)
Figure 22. Typical Single-Ended Output Power vs. Frequency (Mid Gain
Setting 6)
Figure 23. Typical RF Output Power at 2 GHz (Single-Ended) vs. Temperature
Figure 24. Figure of Merit
Figure 25. Typical Output Power vs. Frequency and Gain (Single-Ended)
Figure 26. RF Output Return Loss
–90
–85
–80
–75
–70
–65
–60
–55
–50
SSB INTEGRATED PHASE NOISE (dBc)
OUTPUT FREQUENCY (MHz)
0.0141
0.0447
0.1410
0.4460
100 1000
0.0045
EVM (%)
+85°C
+27°C
–40°C
PHASE NOISE INTEGRATED FRO M 10kHz TO 20M Hz
12827-021
–15
–10
–5
0
5
10
15
OUTPUT P OW E R ( dBm)
FREQUENCY (MHz)
10025 30001000
PHASE NOISE INTEGRATED FRO M 10kHz TO 20MHz
HIG H P E RFO RM ANCE M ODE
(VCO_REG 0x03[ 1: 0] = 3d)
LOW CURRE NT MODE
(VCO_REG 0x03[ 1: 0] = 1d)
RET URN LOS S ( V CO_REG0x03[5] = 0)
RET URN LOS S ( V CO_REG0x03[5] = 1)
12827-022
–6
–4
–2
0
2
4
6
8
10
0246810
OUTPUT P OW E R ( dBm)
GAIN SETTING
+85°C
+27°C
–40°C
12827-023
–240
–230
–220
–210
–200
100 1k 10k 100k 1M
NORM ALIZED P HAS E NOI S E ( dBc/ Hz )
OFF SET (Hz)
FOM FLOOR
TYP FOM VS OF F SET
FOM 1/f NOISE
12827-024
10025 30001000
–20
–15
–10
–5
0
5
10
15
20
FREQUENCY (MHz)
OUTPUT P OW E R ( dBm)
GAIN SETTING = 11
(VCO_REG 0x07[ 3: 0] = 11d)
HIGH PERFORMANCE MODE
LOW CURRE NT MODE
GAIN SETTING = 5
(VCO_REG 0x07[ 3: 0] = 5d)
GAIN SETTING = 0
(VCO_REG 0x07[ 3: 0] = 0d)
12827-025
–30
–25
–20
–15
–10
–5
0
OUTPUT FREQUENCY (MHz)
RET URN LOS S ( dB)
10025 80001000
RET URN LOS S 0 ( V CO_REG0x03[5] = 0)
RET URN LOS S 1 ( V CO_REG0x03[5] = 1)
12827-026
Rev. A | Page 11 of 48
HMC832 Data Sheet
Figure 27. Frequency Settling After Frequency Change, Autocalibration
Enabled, Loop Filter BW = 127 kHz (Type 1, See Table 12)
Figure 28. Frequency Settling After Frequency Change, Manual Calibration,
Loop Filter BW = 127 kHz (Type 1 in Table 12)
Figure 29. Typical VCO Sensitivity
Figure 30. Phase Settling After Frequency Change, Autocalibration Enabled,
Loop Filter BW = 127 kHz (Type 1, See Table 12)
Figure 31. Phase Settling After Frequency Change, Manual Calibration
Figure 32. Typical Tuning Voltage After Calibration (See the Loop Filter and
Frequency Changes Section)
2.2
2.4
2.6
2.8
3.0
3.2
TIME (µs)
020 40 60 80 100 120 140 160
FREQUENCY (GHz)
SETTLING TIM E TO < 1 0 DEGREES
PHASE ERRO R
12827-027
TIME (µs)
020 40 60 80 100 120 140 160
2.495
2.500
2.505
2.510
FREQUENCY (GHz)
SETTLING TIMETO < 10 DEG RE E S
PHASE E RROR
NOTE: LOOP FILTER BANDWIDTH = 127kHz, LOOP
FILTER PHASE MARGIN = 61 DEGREES. THIS RESULT IS
DIRECTLY AFFECTED BY LOOP FILTER DESIGN. FASTER
SETTLING TIME IS POSSIBLE WITH WIDER LOOP FILTER
BANDWIDTH AND LOWER PHASE MARGIN.
12827-028
10
20
30
40
50
60
70
80
90
00.66 1.30 2.00 3.30
TUNING V OLTAGE (V)
kVCO (MHz/V)
2.60
1587MHz
2013MHz
2854MHz
TUNING CA P 15 2453MHz
12827-029
–200
–150
–100
–50
0
50
100
150
200
PHASE E RROR (Degrees)
TIME (µs)
020 40 60 80 100 120 140 160
SETTLING TIM E TO < 1 0 DEGREES
PHASE ERRO R
12827-030
–200
–150
–100
–50
0
50
100
150
200
PHASE E RROR (Degrees)
TIME (µs)
020 40 60 80 100 120 140 160
SETTLING TIM E TO < 1 0 DEGREES
PHASE ERRO R
NOTE: LOOP FILTE R BANDW IDTH = 12 7k Hz ,
LOOP FILTER PHASE M ARGIN = 6 1 DE GREES.
THIS RESULT IS DIRECTLY AFFECTED BY LOOP
FILTER DESI GN. FASTER SETTLING TIM E IS
POSSIBLE WITH W IDER LO O P FILTER
BANDWIDTH AND LOW ER PHAS E MARG IN.
12827-031
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
CALIBRATED AT + 85 ° C, M E ASURED AT –40°C
1330 1710 1900 2090 2280 2470 2660 2850 30401520
TUNE VOLTAGE AFTE R CALI BR ATION (V)
VCO FREQUENC Y (MHz)
CALIBRATED AT + 27 ° C, M E ASURED AT +27°C
CALIBRATED AT –40 ° C, M E ASURED AT + 85°C
CALIBRATED AT + 85 ° C, M E ASURED AT +85°C
CALIBRATED AT –40 ° C, M E ASURED AT –40°C
12827-032
f
MAX
f
MIN
Rev. A | Page 12 of 48
Data Sheet HMC832
Figure 33. Current Consumption in Single-Ended Output Configuration,
Output Gain Configured in VCO_REG 0x07[3:0], Differential or Single-Ended
Mode Programmed in VCO_REG 0x03[3:2]
Figure 34. Reference Input Sensitivity, Square Wave, Measured from a 50 Ω
Source with a 100 Ω External Resistor Termination
Figure 35. Mute Mode Isolation, Measured at Output
Figure 36. Current Consumption in Differential Output Configuration,
Output Gain Configured in VCO_REG 0x07[3:0], Differential or Single-Ended
Mode Programmed in VCO_REG 0x03[3:2]
Figure 37. Reference Input Sensitivity, Sinusoidal Wave, Measured from a
50 Ω Source with a 100 Ω External Resistor Termination
160
170
180
190
200
210
220
230
240
CURRENT CO NS UM P TI ON (mA)
OUTPUT FREQUENCY (MHz)
fO
fO
/2
fO
/62
50001000 1500 2000 2500 3000
HIG H P E RFO RM ANCE M ODE
(VCO_REG 0x03[ 1: 0] = 3d)
LOW CURRE NT
CONSUM P TI ON MODE
(VCO_REG 0x03[ 1: 0] = 1d)
fO
/4
OUTPUT GAIN 0dB
OUTPUT GAIN 6dB
12827-033
220
222
224
226
228
230
232
14MHz S QUARE WAVE
25MHz S QUARE WAVE
50MHz S QUARE WAVE
100MHz S QUARE WAVE
FOM (dBc/Hz)
–12 –9 –6 –3 0 3
–15
REF ERE NCE P OW E R ( dBm)
12827-034
–110
–90
–70
–50
–30
–10
1000100
FRQUENCY (MHz)
ISOLATION (dB)
3000
MUTE ON (VCO_REG0x03[8:7] = 3d)
SIGNAL ON RF_N PIN WHEN RF_N PIN OFF,
RF_P PIN ON (VCO_REG0x03[3:2] = 1d),
MUTE OFF (ON ONLY DURING VCO
CALIBRATION VCO_REG0x03[8:7] = 1d)
BOTH RF_N AND RF_P PINS OFF,
(VCO_REG0x03[3:2] = 0d),
MUTE OFF (ON ONLY DURING VCO
CALIBRATION VCO_REG0x03[8:7] = 1d)
12827-035
180
200
220
240
260
CURRENT CONSUM P TI ON (mA)
OUTPUT FREQUENCY (MHz)
f
O
f
O/2
f
O/4
f
O/62
500
01000 1500 2000 2500 3000
OUTPUT GAIN 0dB
OUTPUT GAIN 6dB
HIG H P E RFO RM ANCE M ODE
(VCO_REG 0x03[ 1: 0] = 3d)
LOW CURRE NT
CONSUMPT IO N M ODE
(VCO_REG 0x03[ 1: 0] = 1d)
12827-036
200
205
210
215
220
225
230
235
–20 –15 –10 –5 0 5
14MHz S INUSO IDAL
25MHz S INUSO IDAL
50MHz S QUARE
100MHz S QUARE
REF ERE NCE P OW E R ( dBm)
FOM (dBc/Hz)
12827-038
Rev. A | Page 13 of 48
HMC832 Data Sheet
THEORY OF OPERATION
Figure 38. PLL and VCO Subsystems
The HMC832 PLL with integrated VCO is comprised of two
subsystems; PLL subsystem and VCO subsystem, as shown in
Figure 38.
PLL SUBSYSTEM OVERVIEW
The PLL subsystem divides down the VCO output to the
desired comparison frequency via the N-divider (integer value
set in Register 0x03, fractional value set in Register 0x04),
compares the divided VCO signal to the divided reference
signal (reference divider set in Register 0x02) in the phase
detector (PD), and drives the VCO tuning voltage via the charge
pump (CP) (configured in Register 0x09) to the VCO
subsystem. Some of the additional PLL subsystem functions
include
• Delta-sigma configuration (Register 0x06).
• Exact frequency mode (configured in Register 0x0C,
Register 0x03, and Register 0x04).
• Lock detect (LD) configuration (use Register 0x07 to
configure LD and Register 0x0F to configure the LD_SDO
output pin).
• External CEN pin used for the hardware PLL enable pin.
CEN pin does not affect the VCO subsystem.
Typically, only writes to the divider registers (integer part uses
Register 0x03, fractional part uses Register 0x04) of the PLL
subsystem are required for HMC832 output frequency changes.
Divider registers of the PLL subsystem (Register 0x03 and
Register 0x04), set the fundamental frequency (1500 MHz to
3000 MHz) of the VCO subsystem. Output frequencies ranging
from 25 MHz to 1500 MHz are generated by tuning to the
appropriate fundamental VCO frequency (1500 MHz to
3000 MHz) by programming the N divider (Register 0x03 and
Register 0x04) and programming the output divider (divide by
1/2/4/6 … /60/62, in VCO_REG 0x02) in the VCO subsystem.
For detailed frequency tuning information and example, see the
Frequency Tuning section.
VCO SUBSYSTEM OVERVIEW
The VCO subsystem consists of a capacitor switched step tuned
VCO and an output stage. In typical operation, the VCO
subsystem is programmed with the appropriate capacitor switch
setting that is executed automatically by the PLL subsystem
autocalibration state machine when autocalibration is enabled
(Register 0x0A[11] = 0, see the VCO Calibration section for
more information). The VCO tunes to the fundamental
frequency (1500 MHz to 3000 MHz), and is locked by the CP
output from the PLL subsystem. The VCO subsystem controls
the output stage of the HMC832 enabling configuration of
• User defined performance settings (see the Programmable
Performance Technology section) that are configured via
VCO_REG 0x03[1:0].
• VCO output divider settings that are configured in the
VCO_REG 0x02 (divide by 2/4/6 … 60/62 to generate
frequencies from 25 MHz to 1500 MHz, or divide by 1 to
generate fundamental frequencies between 1500 MHz and
3000 MHz).
• Output gain settings (VCO_REG 0x07[3:0]).
• Output return loss setting (VCO_REG 0x03[5]). See
Figure 26 for more information.
• Single-ended or differential output operation
(VCO_REG 0x03[3:2]).
• Mute (VCO_REG 0x03[8:7]).
SPI (SERIAL PORT INTERFACE) CONFIGURATION
OF PLL AND VCO SUBSYSTEMS
The two subsystems (PLL subsystem and VCO subsystem) have
their own register maps as shown in the PLL Register Map and
VCO Subsystem Register Map sections. Typically, writes to both
register maps are required for initialization and frequency
tuning operations.
As shown in Figure 38, the PLL subsystem is connected directly
to the SPI of the HMC832, whereas the VCO subsystem is
connected indirectly through the PLL subsystem to the
RF_N
RF_P
VTUNE
REF BUFF
RF BUFFE R E N
PLL BUFF
PLL BUFF E N
VSPI
VSPICAL
CONTROL
4
MODULATOR
CHARGE
PUMP
PHASE
FREQUENCY
DETECTOP
R
DIVIDER
PLL ONLY
XREFP
CEN
CP
SEN
SDI
SCK
LD_SDO
N
DIVIDER
CALVCO EN
CNTRL
f
O
OR ÷N OR ×2
3
12827-043
Rev. A | Page 14 of 48
Data Sheet HMC832
Rev. A | Page 15 of 48
HMC832 SPI. As a result, writes to the PLL Register Map are
written directly and immediately, whereas the writes to the
VCO Subsystem Register Map are written to the PLL subsystem
Register 0x05 and forwarded via the internal VCO SPI (VSPI)
to the VCO subsystem. This is a form of indirect addressing.
Note that VCO subsystem registers are write only and cannot be
read. More information is available in the VCO Serial Port
Interface (VSPI) section.
VCO Serial Port Interface (VSPI)
The HMC832 communicates with the internal VCO subsystem
via an internal 16-bit VCO SPI. The internal serial port controls
the step tuned VCO and other VCO subsystem functions.
Note that the internal VCO subsystem SPI (VSPI) runs at
the rate of the autocalibration FSM clock, tFSM, (see the VCO
Autocalibration section) where the FSM clock frequency
cannot be greater than 50 MHz. The VSPI clock rate is set
by Register 0x0A[14:13].
Writes to the control registers of the VCO are handled indirectly
via writes to Register 0x05 of the HMC832. A write to HMC832
Register 0x05 causes the internal PLL subsystem to forward the
packet, MSB first, across its internal serial link to the VCO
subsystem, where it is interpreted.
VSPI Use of Register 0x05
The packet data written into Register 0x05 is subparsed by logic
at the VCO subsystem into the following three fields:
Field 1—Bits[2:0]: 3-bit VCO_ID, target subsystem address =
000b.
Field 2—Bits[6:3]: 4-bit VCO_REGADDR, the internal register
address inside the VCO subsystem.
Field 3—Bits[15:7]: 9-bit VCO_DATA, data field to write to the
VCO register.
For example, to write 0_1111_1110 into Register 2 of the VCO
subsystem (VCO_ID = 000b), and set the VCO output divider
to divide by 62, the following needs to be written to
Register 0x05 = 0_1111_1110b, 0010b, 000b or equivalently,
Register 0x05 = 7F10.
During autocalibration, the autocalibration controller writes
into the VCO register address specified by the VCO_ID
and VCO_REGADDR, as stored in Register 0x05[2:0] and
Register 0x05[6:3], respectively. Autocalibration requires that
these values be zero (Register 0x05[6:0] = 0); otherwise, when
they are not zero (Register 0x05[6:0] ≠ 0), autocalibration does
not function.
To ensure that the autocalibration functions, it is critical to
write Register 0x05[6:0] = 0 after the last VCO subsystem write
prior to an output frequency change triggered by a write to
either Register 0x03 or Register 0x04.
However, it is impossible to write only Register 0x05[6:0] = 0
(VCO_REGADDR) without writing Register 0x05[15:7]
(VCO_DATA). Therefore, to ensure that the VCO_DATA
(Register 0x05[15:7]) in VCO_REGADDR 0x00 is not changed,
it is required to read the switch settings provided in Regis-
ter 0x10[7:0], and then rewrite them to Register 0x05[15:7], as
shown in the following example:
1. Read Register 0x10
2. Write to Register 0x05 the following:
a. Register 0x05[15:14] = Register 0x10[7:6]
b. Register 0x05[13] = 1, reserved bit
c. Register 0x05[12:8] = Register 0x10[4:0]
d. Register 0x05[7:0] = 0
Changing the VCO subsystem configuration (VCO Subsystem
Register Map section) without following this procedure results
in a failure to lock to the desired frequency.
For applications not using the read functionality of the
HMC832 SPI, in which Register 0x10 cannot be read, it is
possible to write Register 0x05 = 0x0 to set Register 0x05[6:0] =
0, which also sets the VCO subband setting equal to zero
(Register 0x05[15:7] = 0), effectively programming incorrect
VCO subband settings and causing the HMC832 to lose lock.
This procedure is then immediately followed by a write to:
Register 0x03, if in integer mode.
Register 0x04, if in fractional mode.
This write effectively retriggers the autocalibration state
machine, forcing the HMC832 to relock whether in integer or
fractional mode.
This procedure causes the HMC832 to lose lock and relock after
every VCO subsystem change. Typical output frequency and
lock time is shown in Figure 27 and Figure 30, and is typically
in the order of 100 μs for a phase settling of 10°, and is also
dependent on loop filter design (loop filter bandwidth and loop
filter phase margin).
HMC832 Data Sheet
VCO SUBSYSTEM
Figure 39. PLL and VCO Subsystems
The HMC832 contains a VCO subsystem that can be
configured to operate in:
• Fundamental frequency (fo) mode (1500 MHz to
3000 MHz).
• Divide by N mode, where N = 2, 4, 6, 8 … 58, 60, 62
(25 MHz to 1500 MHz).
All modes are VCO register programmable, as shown in
Figure 39. One loop filter design can be used for the entire
frequency of operation of the HMC832.
VCO Calibration
VCO Autocalibration
The HMC832 uses a step tuned type VCO. A simplified step
tuned VCO is shown in Figure 41. A step tuned VCO is a VCO
with a digitally selectable capacitor bank allowing the nominal
center frequency of the VCO to be adjusted or stepped by
switching in and out of the VCO tank capacitors. Note that
more than one capacitor can be switched in at a time.
A step tuned VCO allows the user to center the VCO on the
required output frequency while keeping the varactor tuning
voltage optimized near the mid voltage tuning point of the
HMC832 charge pump. This enables the PLL charge pump to
tune the VCO over the full range of operation with both a low
tuning voltage and a low tuning sensitivity (kVCO).
The VCO switches are normally controlled automatically by the
HMC832 using the autocalibration feature. The autocalibration
feature is implemented in the internal state machine. It manages
the selection of the VCO subband (capacitor selection) when a
new frequency is programmed. The VCO switches may also be
controlled directly via Register 0x05 for testing or for other
special purpose operations. Other control bits specific to the
VCO are also sent via Register 0x05.
To use a step tuned VCO in a closed loop, the VCO must be
calibrated such that the HMC832 knows which switch position
on the VCO is optimum for the desired output frequency. The
HMC832 supports autocalibration of the step tuned VCO. The
autocalibration fixes the VCO tuning voltage at the optimum
midpoint of the charge pump output, then measures the free
running VCO frequency while searching for the setting which
results in the free running output frequency that is closest to the
desired phase-locked frequency. This procedure results in a
phase-locked oscillator that locks over a narrow voltage range
on the varactor. A typical tuning curve for a step tuned VCO is
shown in Figure 40. Note that the tuning voltage stays in a
narrow range over a wide range of output frequencies.
SPI LD_SDO
VCO_REG0x01[0]
VCO_REG0x01[3]
EN
EN
÷1, ÷2, ÷4, ÷6, ... ÷62
VCO_REG0x01[2]
VCO _RE G0x01[1] , EN
VCO_REG0x00[8:1] VCO_REG0x00[0]
LOOP
FILTER
VCO
VCO CA L
VOLTAGE
EN
VCO_REG0x07[3:0]
VCO_REG0x02[5:0]
VCO
CONTROL
VSPI
VTUNE
RF_N
RF_P
VDD
MASTER E NABLE
VCO SUBSYSTEM
VCO_REG0x03[1:0]
VCO_REG0x03[3]
VCO_REG0x03[2]
VCO_REG0x01[5]
VCO SUBSYST EM
PERFORMANCE
TUNING
CONTROL
MODULATOR
N
DIVIDER
CP
PHASE
FREQUENCY
DETECTOR CHARGE
PUMP
R
DIVIDER
XREFP
CAL
12827-044
Rev. A | Page 16 of 48
Data Sheet HMC832
Figure 40. Typical VCO Tuning Voltage After Calibration
The calibration is normally run automatically, once for every
change of frequency. This ensures optimum selection of VCO
switch settings vs. time and temperature. The user does not
normally need to be concerned about which switch setting is
used for a given frequency because this is handled by the
autocalibration routine.
The accuracy required in the calibration affects the amount of
time required to tune the VCO. The calibration routine searches
for the best step setting that locks the VCO at the current
programmed frequency and ensures that the VCO stays locked
and performs well over its full temperature range without
additional calibration, regardless of the temperature at which
the VCO was calibrated.
Autocalibration can also be disabled, thereby allowing manual
VCO tuning. Refer to the Manual VCO Calibration for Fast
Frequency Hopping section for a description of manual tuning.
Figure 41. Simplified Step Tuned VCO
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
1330 1520 1900 2090 3040
28502660
2470
2280
1710
TUNE VOLTAGE AFTE R CALI BR ATION (V)
VCO FREQUENC Y (MHz)
CALIBRATED AT +85°C, M E AS URE D AT +85°C
CALIBRATED AT +85°C, M E AS URE D AT –40°C
CALIBRATED AT –40°C, M E AS URE D AT –40°C
CALIBRATED AT –40°C, M E AS URE D AT + 85°C
CALIBRATED AT + 27°C, M E AS URE D AT +27°C
12827-046
f
MIN
f
MAX
HOST
SCK
SYNTHESIZER
SDI
CP
VCO
RF
OUT
VCO
SUB-BAND
SELECT
VCO
VSPI
LOOP
FILTER
VCOIP
VTUNE
DTUNE
VSCK
VSDO
VSLE
SEN
12827-045
Rev. A | Page 17 of 48
HMC832 Data Sheet
Autocalibration Using Register 0x05
Autocalibration transfers switch control data to the VCO
subsystem via Register 0x05. The address of the VCO subsystem
in Register 0x05 is not altered by the autocalibration routine.
The address and ID of the VCO subsystem in Register 0x05
must be set to the correct value before autocalibration is
executed. For more information see the VCO Serial Port
Interface (VSPI) section.
Automatic Relock on Lock Detect Failure
It is possible by setting Register 0x07[13] to have the VCO
subsystem automatically rerun the calibration routine and
relock itself if lock detect indicates an unlocked condition for
any reason. With this option the system attempts to relock only
once.
VCO Autocalibration on Frequency Change
Assuming Register 0x0A[11] = 0, the VCO calibration starts
automatically whenever a frequency change is requested. If it is
desired to rerun the autocalibration routine for any reason at
the same frequency, rewrite the frequency change with the same
value and the autocalibration routine executes again without
changing the final frequency.
VCO Autocalibration Time and Accuracy
The VCO frequency is counted for tMMT, the period of a single
autocalibration measurement cycle.
tMMT = tXTAL × R × 2n (1)
where:
n is set by Register 0x0A[2:0] and results in measurement
periods which are multiples of the PD period, tXTALR.
R is the reference path division ratio currently in use,
Register 0x02.
tXTAL is the period of the external reference (crystal) oscillator.
The VCO autocalibration counter, on average, expects to
register N counts, rounded down (floor) to the nearest integer,
for every PD cycle.
N is the ratio of the target VCO frequency, fVCO, to the
frequency of the PD, fPD, where N can be any rational number
supported by the N divider.
N is set by the integer (NINT = Register 0x03) and fractional
(NFRAC = Register 0x04) register contents by Equation 2.
N = NINT + NFRAC/224 (2)
The autocalibration state machine and the data transfers to the
internal VCO subsystem SPI (VSPI) run at the rate of the FSM
clock, tFSM, where the FSM clock frequency cannot be greater
than 50 MHz.
tFSM = tXTAL × 2m (3)
where m is 0, 2, 4, or 5 as determined by Register 0x0A[14:13].
The expected number of VCO counts, V, is given by
V = floor (N × 2n) (4)
The nominal VCO frequency measured, fVCOM, is given by
fVCOM = V × fXTAL/(2n × R) (5)
where the worst case measurement error, fERR , is
fERR ≈ ±fPD/2n + 1 (6)
A 5-bit step tuned VCO, for example, nominally requires five
measurements for calibration or in the worst case, six
measurements, and hence, seven VSPI data transfers of 20 clock
cycles each. The measurement has a programmable number of
wait states, k, of 128 FSM cycles defined by Register 0x0A[7:6] =
k. Total calibration time, worst case, is given by
tCAL = k128 tFSM + 6tPD 2n + 7 × 20 tFSM (7)
or equivalently
tCAL = tXTAL (6R × 2n + (140+(k × 128)) × 2m) (8)
For guaranteed hold of lock, across temperature extremes, the
resolution should be better than 1/8th the frequency step caused
by a VCO subband switch change. Better resolution settings
show no improvement.
Figure 42. VCO Calibration
Table 7. Autocalibration Example with fXTAL = 50 MHz, R = 1, m = 0
Control Value Register 0x0A[2:0] n 2n tMMT (µs) tCAL (µs) fERR Maximum
0 0 1 0.02 4.92 ±25 MHz
1 1 2 0.04 5.04 ±12.5 MHz
2
2
4
0.08
5.28
±6.25 MHz
3 3 8 0.16 5.76 ±3.125 MHz
4 5 32 0.64 8.64 ±781 kHz
XREF
CALIBRATION WINDOW
REG0x02
START
V
VCO CTR
FSM
50MHz M AX FOR
FSM + VSPI CLOCKS
REGA[14:13]
m = [0, 2, 4, 5] REGA[2:0]
n = [ 0, 1, 2, 3, 5, 6, 7, 8]
STOP
t
MMT
= RT
XTAL
× 2
n
12827-047
t
PD
÷ 2
n
÷ 2
m
÷ R
Rev. A | Page 18 of 48
Data Sheet HMC832
Control Value Register 0x0A[2:0] n 2n tMMT (µs) tCAL (µs) fERR Maximum
5 6 64 1.28 12.48 ±390 kHz
6 7 128 2.56 20.16 ± 95 kHz
7 8 256 5.12 35.52 ±98 kHz
VCO Autocalibration Example
The VCO subsystem must satisfy the maximum fPD limited by
the two following conditions:
N ≥ 16 (fINT), N ≥ 20.0 (fFRAC)
where N = fVCO/ fPD.
fPD ≤ 100 MHz
For example, if the VCO subsystem output frequency is to
operate at 2.01 GHz and the crystal frequency is fXTAL = 50 MHz,
R = 1, and m = 0 (see Figure 42), then tFSM = 20 ns (50 MHz).
Note that when using autocalibration, the maximum autocali-
bration finite state machine (FSM) clock cannot exceed 50 MHz
(see Register 0x0A[14:13]). The FSM clock does not affect the
accuracy of the measurement, it only affects the time to produce
the result. This same clock is used to clock the 16-bit VCO
serial port.
If time to change frequencies is not a concern, then the
calibration time for maximum accuracy can be set, and
therefore, the measurement resolution is of no concern.
Using an input crystal of 50 MHz (R = 1 and fPD = 50 MHz) the
times and accuracies for calibration using Equation 6 and
Equation 8 are listed in Table 7, where minimal tuning time is
1/8th of the VCO band spacing.
Across all VCOs, a measurement resolution better than 800 kHz
produces correct results. Setting m = 0 and n = 5, provides
781 kHz of resolution and adds 8.6 μs of autocalibration time to
a normal frequency hop. After the autocalibration sets the final
switch value, 8.64 μs after the frequency change command, the
fractional register is loaded, and the loop locks with a normal
transient predicted by the loop dynamics. Therefore, as shown
in this example, autocalibration typically adds about 8.6 μs to
the normal time to achieve frequency lock. Use autocalibration
for all but the most extreme frequency hopping requirements.
Manual VCO Calibration for Fast Frequency Hopping
When switching frequencies quickly is needed, it is possible to
eliminate the autocalibration time by calibrating the VCO in
advance and storing the switch number vs. frequency infor-
mation in the host. This is accomplished by initially locking the
HMC832 on each desired frequency using autocalibration, then
reading and storing the selected VCO switch settings. The VCO
switch settings are available in Register 0x10[7:0] after every
autocalibration operation. The host must then program the
VCO switch settings directly when changing frequencies.
Manual writes to the VCO switches are executed immediately as
are writes to the integer and fractional registers when
autocalibration is disabled. Therefore, frequency changes with
manual control and autocalibration disabled requires a
minimum of two serial port transfers to the PLL, once to set the
VCO switches and once to set the PLL frequency.
When autocalibration is disabled, Register 0x0A[11] = 1, the
VCO updates its registers immediately with the value written
via Register 0x05. The VCO internal transfer requires 16 VSCK
clock cycles after the completion of a write to Register 0x05.
VSCK and the autocalibration controller clock are equal to the
input reference divided by 0, 4, 16, or 32 as controlled by
Register 0x0A[14:13].
Registers Required for Frequency Changes in Fractional
Mode
In fractional mode (Register 0x06[11] = 1), a large change of
frequency may require main serial port writes to one of the
three following registers
• The integer register, INTG, Register 0x03. This is required
only if the integer part changes.
• The VCO SPI register, Register 0x05. This is required only
for manual control of VCO if Register 0x0A[11] = 1,
autocalibration is disabled, or to change the VCO output
divider value (VCO_REG 0x02), see Figure 39 for more
information.
• The fractional register, Register 0x04. The fractional register
write triggers autocalibration when Register 0x0A[11] = 0,
and it is loaded into the modulator automatically after the
autocalibration runs. If autocalibration is disabled, Regis-
ter 0x0A[11] = 1, the fractional frequency change is loaded
immediately into the modulator when the register is
written with no adjustment to the VCO.
Small steps in frequency in fractional mode, with autocalibration
enabled (Register 0x0A[11] = 0), usually require only a single
write to the fractional register. In a worst-case scenario, three
main serial port transfers to the HMC832 could be required to
change frequencies in fractional mode. If the frequency step is
small and the integer part of the frequency does not change,
then the integer register is not changed. In all cases, in frac-
tional mode, it is necessary to write to the fractional register,
Register 0x04, for frequency changes.
Rev. A | Page 19 of 48
HMC832 Data Sheet
Registers Required for Frequency Changes in Integer
Mode
In integer mode (Register 0x06[11] = 0), a change of frequency
requires main serial port writes to the following registers:
• VCO SPI register, Register 0x05. This is required for
manual control only of the VCO when Register 0x0A[11] =
1 (autocalibration disabled) or when the VCO output
divider value must change (VCO_REG 0x02).
• Integer register, Register 0x03. In integer mode, an
integer register write triggers autocalibration when
Register 0x0A[11] = 0 and it is loaded into the prescaler
automatically after autocalibration runs. If autocalibration
is disabled, Register 0x0A[11] = 1, the integer frequency
change is loaded into the prescaler immediately when
written with no adjustment to the VCO. Normally, changes
to the integer register cause large steps in the VCO
frequency; therefore, the VCO switch settings must be
adjusted. Autocalibration enabled is the recommended
method for integer mode frequency changes. If auto-
calibration is disabled (Register 0x0A[11] = 1), a priori
knowledge of the correct VCO switch setting and the
corresponding adjustment to the VCO is required before
executing the integer frequency change.
VCO Output Mute Function
The HMC832 features an intelligent output mute function with
the capability to disable the VCO output while maintaining
fully functional PLL and VCO subsystems. The mute function is
automatically controlled by the HMC832 and provides a
number of mute control options including
• Automatic mute. This option automatically mutes the
outputs during VCO calibration during output frequency
changes. This mode can be useful in eliminating any out of
band emissions during frequency changes, and ensuring
that the system emits only the desired frequencies. It is
enabled by writing VCO_REG 0x03[8:7] = 1d.
• Always mute (VCO_REG 0x03[8:7] = 3d). This mode is
used for manual mute control.
Typical isolation when the HMC832 is muted is always better
than 50 dB, and is ~40 dB better than disabling the individual
outputs of the HMC832 via VCO_REG 0x03[3:2], as shown in
Figure 35.
Also note that the VCO subsystem registers are not directly
accessible. They are written to the VCO subsystem via PLL
Register 0x05. See Figure 39 and the VCO Serial Port Interface
(VSPI) section for more information about the VCO subsystem
SPI.
VCO Built-In Test (BIST) with Autocalibration
The frequency limits of the VCO can be measured using the
BIST features of the autocalibration machine by setting Regis-
ter 0x0A[10] = 1, which freezes the VCO switches in one position.
VCO switches may then be written manually with the varactor
biased at the nominal midrail voltage used for autocalibration.
For example, to measure the VCO maximum frequency use
Switch 0, written to the VCO subsystem via Register 0x05 =
000000001 0000 VCO_ID, where VCO_ID = 000b.
When autocalibration is enabled (Register 0x0A[11] = 0), and a
new frequency is written, autocalibration runs. The VCO
frequency error relative to the command frequency is measured
and the results are written to Register 0x11[19:0], where
Register 0x11[19] is the sign bit. The result is written in terms of
VCO count error (see Equation 4).
For example, if the expected VCO is 2 GHz, the reference is
50 MHz, and n is 6, expect to measure 2000/(50/26) = 2560
counts. If a difference of −5 counts is measured in Register 0x11,
then it means 2555 counts were actually measured. Hence, the
actual frequency of the VCO is 5/2560 low, or 1.99609375 GHz,
±1 count ~ ±781 kHz.
PLL SUBSYSTEM
Charge Pump (CP) and Phase Detector (PD)
The phase detector (PD) has two inputs, one from the reference
path divider and one from the RF path divider. When in lock,
these two inputs are at the same average frequency and are fixed
at a constant average phase offset with respect to each other.
The frequency of operation of the PD is fPD. Most formulae
related to step size, Δ-Σ modulation, timers, and so forth are
functions of the operating frequency of the PD, fPD. fPD is also
referred to as the comparison frequency of the PD.
The PD compares the phase of the RF path signal with that of
the reference path signal and controls the charge pump output
current as a linear function of the phase difference between the
two signals. The output current varies linearly over a full ±2π
radians (±360°) of input phase difference.
Charge Pump
A simplified diagram of the charge pump is shown in Figure 43.
The CP consists of four programmable current sources, two con-
trolling the CP gain (Up Gain Register 0x09[13:7], and Down
Gain Register 0x09[6:0]) and two controlling the CP offset,
where the magnitude of the offset is set by Register 0x09[20:14],
and the direction is selected by Register 0x09[21] = 1 for up and
Register 0x09[22] = 1 for down offset.
CP gain is used at all times, whereas CP offset is recommended
for fractional mode of operation only. Typically, the CP up and
down gain settings are set to the same value (Register 0x09[13:7] =
Register 0x09[6:0]).
Rev. A | Page 20 of 48
Data Sheet HMC832
Charge Pump Gain
Charge pump up and down gains are set by Register 0x09[6:0]
and Register 0x09[13:7], respectively. The current gain of the
pump in amps/radian is equal to the gain setting of this register
(Register 0x09) divided by 2π.
Typical CP gain setting is set to 2 mA to 2.5 mA; however, lower
values can also be used. Note that values less than 1 mA may
result in degraded phase noise performance.
For example, if both Register 0x09[13:7] and Register 0x09[6:0]
are set to 50 decimal, the output current of each pump is 1 mA,
and the phase frequency detector gain is kP = 1 mA/2π radians,
or 159 μA/rad. See the Charge Pump (CP) and Phase Detector
(PD) section for more information.
Figure 43. Charge Pump Gain and Offset Control
UP
PD
REF PATH
VCO PATH LOOP
FILTER
UP GAIN
REG0x09[13:7]
UP OFFSE T REG0x09[21]
0µA TO 635µA
5µA STEP
REG0x09[20:14]
DN OFFS E T REG0x09[22]
0µA TO 635µA
5µA STEP
REG0x09[20:14]
0mA TO 2.54mA
20µA STEP
0mA TO 2.54mA
20µA STEP
DN GAI N
REG0x09[6:0]
DN
12827-048
Rev. A | Page 21 of 48
HMC832 Data Sheet
Charge Pump Phase Offset
In integer mode, the phase detector operates with zero offset.
The divided reference signal and the divided VCO signal arrive
at the phase detector inputs at the same time. Integer mode
does not require any CP offset current. When operating in
integer mode, disable CP offset in both directions (up and
down) by writing Register 0x09[22:21] = 00b, and set the CP
offset magnitude to zero by writing Register 0x09[20:14] = 0.
In fractional mode, CP linearity is of paramount importance.
Any nonlinearity degrades phase noise and spurious perfor-
mance. These nonlinearities are eliminated by operating the PD
with an average phase offset, either positive or negative (either
the reference or the VCO edge always arrives first at the PD,
that is, leads).
A programmable CP offset current source is used to add dc
current to the loop filter and to create the desired phase offset.
Positive current causes the VCO to lead, negative current causes
the reference to lead.
The CP offset is controlled via Register 0x09. The phase offset is
scaled from 0° to 360°, where they arrive a full cycle late.
The specific level of charge pump offset current (Register 0x09,
Bits[20:14]) is provided in Equation 9 and plotted in Figure 44.
Required CP Offset =
min [(4.3 × 10−9 × fPD × ICP), 0.25 × ICP] (9)
where:
fPD is the comparison frequency of the phase detector (Hz).
ICP is the full-scale current setting (A) of the switching charge
pump (set in Register 0x09[6:0] and Register 0x09[13:7]).
Figure 44. Recommended CP Offset Current vs. PD Frequency for Typical CP
Gain Currents, Calculated Using Equation 9
Do not allow the required CP offset current to exceed 25% of
the programmed CP current. It is recommended to enable the
up offset and disable the down offset by writing Register 0x09,
Bits[22:21] = 01b.
Operation with CP offset influences the required configuration
of the lock detect function. See the description of the lock
detect function in the Lock Detect section.
Phase Detector Functions
Register 0x0B, the phase detector register, allows manual access
to control special phase detector features.
Setting Register 0x0B[5] = 0 masks the PD up output, which
prevents the charge pump from pumping up.
Setting Register 0x0B[6] = 0, masks the PD down output, which
prevents the charge pump from pumping down.
Clearing both Register 0x0B[5] and Register 0x0B[6] tristates
the charge pump while leaving all other functions operating
internally.
PD force up (Register 0x0B[9] = 1) and PD force down
(Register 0x0B[10] = 1) allows the charge pump to be forced up
or down, respectively. This forces the VCO to the ends of the
tuning range, which is useful in testing the VCO.
Reference Input Stage
Figure 45. Reference Path Input Stage
The reference buffer provides the path from an external
reference source (generally crystal-based) to the R divider, and
eventually to the phase detector. The buffer has two modes of
operation controlled by Register 0x08[21]. High gain (Regis-
ter 0x08[21] = 0) is recommended below 200 MHz, and high
frequency (Register 0x08[21] = 1) for 200 MHz to 350 MHz
operation. The buffer is internally dc biased with 100 Ω internal
termination. For a 50 Ω match, add an external 100 Ω resistor
to ground followed by an ac coupling capacitor (impedance less
than 1 Ω).
At low frequencies, a relatively square reference is recommended to
maintain a high input slew rate. At higher frequencies, use a
square or sinusoid.
Table 8 shows the recommended operating regions for different
reference frequencies. If operating outside these regions, the
device usually still operates, but with degraded reference path
phase noise performance.
When operating at 50 MHz, the input referred phase noise of
the PLL is between −148 dBc/Hz and −150 dBc/Hz at a 10 kHz
offset, depending upon the mode of operation. To avoid degra-
dation of the PLL noise contribution, the input reference signal
should be 10 dB better than this floor. Note that such low levels
are only necessary if the PLL is the dominant noise contributor
and these levels are required for the system goals.
0
100
200
300
400
500
600
700
020 40 60 80 100
RECOMMENDE D OF FSE T CURRENT (µ A)
PHASE DETECTOR FREQUENC Y (MHz)
CP CURRENT = 2.5mA
CP CURRENT = 2mA
CP CURRENT = 1mA
12827-049
XREFP
80Ω
V
b
20Ω
AC COUPLE
100Ω
RVDD
12827-050
Rev. A | Page 22 of 48
Data Sheet HMC832
Table 8. Reference Sensitivity
Reference Input
Frequency (MHz)
Square Input Sinusoidal Input
Slew > 0.5 V/ns Recommended Swing (V p-p) Recommended Power Range (dBm)
Recommended Minimum Maximum Recommended Minimum Maximum
<10 Yes 0.6 2.5 No No No
10 Yes 0.6 2.5 No No No
25 Yes 0.6 2.5 Okay 8 15
50 Yes 0.6 2.5 Yes 6 15
100 Yes 0.6 2.5 Yes 5 15
150 Okay 0.9 2.5 Yes 4 12
200 Okay 1.2 2.5 Yes 3 8
Reference Path, R Divider
The reference path, R divider is based on a 14-bit counter and
can divide input signals by values from 1 to 16,383 and is
controlled via Register 0x02.
RF Path, N Divider
The main RF path divider is capable of average divide ratios
between 219 − 5 (524,283) and 20 in fractional mode, and 219 − 1
(524,287) to 16 in integer mode. The VCO frequency range
divided by the minimum N divider value places practical
restrictions on the maximum usable PD frequency. For
example, a VCO operating at 1.5 GHz in fractional mode with a
minimum N divider value of 20 has a maximum PD frequency
of 75 MHz.
Lock Detect
The lock detect (LD) function verifies that the HMC832 is
generating the desired frequency. It is enabled by writing
Register 0x07[3] = 1. The HMC832 provides an LD indicator in
one of two ways
• As an output available on the LD_SDO pin of the
HMC832, (configuration is required to use the LD_SDO
pin for LD purposes, for more information, see the Serial
Port and Configuring the LD_SDO Pin for LD Output
sections).
• Or reading from Register 0x12[1], where Bit 1 = 1 indicates
a locked condition and Bit 1 = 0 indicates an unlocked
condition.
The LD circuit expects the divided VCO edge and the divided
reference edge to appear at the PD within a user specified time
period (window), repeatedly. Either signal may arrive first, only
the difference in arrival times is significant. The arrival of the
two edges within the designated window increments an internal
counter. When the count reaches and exceeds a user specified
value (Register 0x07[2:0]) the HMC832 declares lock.
Failure in registering the two edges in any one window resets
the counter and immediately declares an unlocked condition.
Lock is deemed to be reestablished when the counter reaches
the user specified value (Register 0x07[2:0]) again.
The HMC832 supports two lock detect modes:
• Analog LD, that only supports a fixed window size of 10 ns.
Analog LD mode is selected by writing Register 0x07[6] = 0.
• Digital LD, that supports a user configurable window size,
programmed in Register 0x07[11:7]. Digital LD is selected
by writing Register 0x07[6] = 1.
Lock Detect Configuration
Optimal spectral performance in fractional mode requires CP
current and CP offset current configuration discussed in detail
in the Charge Pump (CP) and Phase Detector (PD) section.
These settings in Register 0x09 impact the required LD window
size in fractional mode of operation. To function, the required
lock detect window size is provided by Equation 10 in fractional
mode and Equation 11 in integer mode.
LD Window (sec) =
2
)Hz(
1
(sec)1066.2
(A) (Hz)
(A) 9
+×+
×
−
PD
CP
PD
OffsetCP
fIf
I
(10)
PD
f
secWindowLD ×
=2
1
)
(
(11)
where:
fPD is the comparison frequency of the phase detector.
ICP Offset is the charge pump offset current (Register 0x09[20:14]).
ICP is the full-scale current setting of the switching charge pump
(Register 0x09[6:0] or Register 0x09[13:7]).
If the result provided by Equation 10 is equal to 10 ns, analog
LD can be used (Register 0x07[6] = 0); otherwise, digital LD is
necessary (Register 0x07[6] = 1).
Table 9 lists the required Register 0x07 settings to appropriately
program the digital LD window size. From Table 9, select the
closest value in the digital LD window size columns to the ones
calculated in Equation 10 and Equation 11, and program
Register 0x07[11:10] and Register 0x07[9:7] accordingly.
Rev. A | Page 23 of 48
HMC832 Data Sheet
Table 9. Typical Digital Lock Detect Window
LD Timer Speed
Register 0x07
Bits[11:10] Digital Lock Detect Window Size Nominal Value (ns)
Fastest 00 6.5 8 11 17 29 53 100 195
01 7 8.9 12.8 21 36 68 130 255
10 7.1 9.2 13.3 22 38 72 138 272
Slowest 11 7.6 10.2 15.4 26 47 88 172 338
LD Timer Divide
Setting
Register 0x07,
Bits[9:7]
000 001 010 011 100 101 110 111
Digital Window Configuration Example
Assuming, fractional mode, with a 50 MHz PD and a
• Charge pump gain of 2 mA (Register 0x09[13:7] = 0x64,
Register 0x09[6:0] = 0x64),
• Up offset (Register 0x09[22:21] = 01b)
• Offset current magnitude of +400 μA (Register 0x09[20:14]
= 0x50)
Applying Equation 10, the required LD window size is:
LD Window (sec) =
ns33.13
2
)Hz(1050
1
(sec)1066.2
)A(102)Hz(1050
)A(104.0
6
9
36
3
=
×
+×+
×××
×
−
−
−
Locating the Table 9 value that is closest to this result is, in this
case, 13.3 ≈ 13.33. To set the digital LD window size, program
Register 0x07[11:10] = 10b and Register 0x07[9:7] = 010b,
according to Table 9.
There is always a good solution for the lock detect window for a
given operating point. The user should understand, however,
that one solution does not fit all operating points. As observed
from Equation 10 and Equation 11, if the charge pump offset or
PD frequency is changed significantly, then the lock detect
window may need to be adjusted.
Configuring the LD_SDO Pin for LD Output
Setting Register 0x0F[7] = 1 and Register 0x0F[4:0] = 1 displays
the lock detect flag on the LD_SDO pin of the HMC832. When
locked, LD_SDO is high. As the name suggests, LD_SDO pin is
multiplexed between the LD and the serial data output (SDO)
signals. Therefore, LD is available on the LD_SDO pin at all
times except when a serial port read is requested, in which case
the pin reverts temporarily to the serial data output pin, and
returns to the lock detect flag after the read is completed.
LD can be made available on LD_SDO pin at all times by
writing Register 0x0F[6] = 1. In that case, the HMC832 does
not provide any readback functionality because the SDO signal
is not available.
Cycle Slip Prevention (CSP)
When changing VCO frequency and the VCO is not yet locked
to the reference, the instantaneous frequencies of the two PD
inputs are different, and the phase difference of the two inputs
at the PD varies rapidly over a range much greater than ±2π
radians. Because the gain of the PD varies linearly with phase
up to ±2π, the gain of a conventional PD cycles from high gain,
when the phase difference approaches a multiple of 2π, to low
gain, when the phase difference is slightly larger than a multiple
of 0 radians. The output current from the charge pump cycles
from maximum to minimum, even though the VCO has not yet
reached its final frequency.
The charge on the loop filter small capacitor may actually
discharge slightly during the low gain portion of the cycle. This
can make the VCO frequency reverse temporarily during
locking. This phenomenon is known as cycle slipping. Cycle
slipping causes the pull-in rate during the locking phase to vary
cyclically. Cycle slipping increases the time to lock to a value
greater than that predicted by normal small signal Laplace
transform analysis.
The HMC832 PD features an ability to reduce cycle slipping
during acquisition. The cycle slip prevention (CSP) feature
increases the PD gain during large phase errors. The specific
phase error that triggers the momentary increase in PD gain is
set via Register 0x0B[8:7].
Frequency Tuning
The HMC832 VCO subsystem always operates in fundamental
frequency of operation (1500 MHz to 3000 MHz). The HMC832
generates frequencies below its fundamental frequency (25 MHz to
1500 MHz) by tuning to the appropriate fundamental frequency
and selecting the appropriate output divider setting (divide by
2/4/6/ … 60/62) in VCO_REG 0x02[5:0].
The HMC832 automatically controls frequency tuning in the
fundamental band of operation, for more information see the
VCO Autocalibration section.
To tune to frequencies below the fundamental frequency range
(<1500 MHz) it is required to tune the HMC832 to the appropriate
fundamental frequency, then select the appropriate output divider
setting (divide by 2/4/6/ … 60/62) in VCO_REG 0x02[5:0].
Integer Mode
The HMC832 is capable of operating in integer mode. For
integer mode, set the following registers:
• Disable the fractional modulator, Register 0x06[11] = 0
• Bypass the modulator circuit, Register 0x06[7] = 1
In integer mode, the VCO step size is fixed to that of the PD
frequency. Integer mode typically has a 3 dB lower phase noise
than fractional mode for a given PD operating frequency.
Integer mode, however, often requires a lower PD frequency to
meet step size requirements. The fractional mode advantage is
that higher PD frequencies can be used; therefore, lower phase
noise can often be realized in fractional mode. Disable charge
pump offset when in integer mode.
Rev. A | Page 24 of 48
Data Sheet HMC832
Integer Frequency Tuning
In integer mode the digital Δ-Σ modulator is shut off and the N
divider (Register 0x03) may be programmed to any integer
value in the range of 16 to 219 − 1. To run in integer mode,
configure Register 0x06 (as described in the Integer Mode
section), then program the integer portion of the frequency as
explained by Equation 12, ignoring the fractional part.
1. Disable the fractional modulator, Register 0x06[11] = 0
2. Bypass the Δ-Σ modulator Register 0x06[7] = 1
3. To tune to frequencies (<1500 MHz), select the appropriate
output divider value VCO_REG 0x02[5:0].
Writing to VCO subsystem registers (VCO_REG 0x02[5:0] and
VCO_REG 0x03[0] in this case) is accomplished indirectly through
PLL Register 5 (Register 0x05). More information on communi-
cating with the VCO subsystem through PLL Register 0x05 is
available in the VCO Serial Port Interface (VSPI) section.
Fractional Mode
The HMC832 is placed in fractional mode by setting the
following registers:
• Enable the fractional modulator, Register 0x06[11] = 1.
• Connect the Δ-Σ modulator in circuit, Register 0x06[7] = 0.
Fractional Frequency Tuning
This is a generic example, with the goal of explaining how to
program the output frequency. Actual variables are dependant
upon the reference in use.
The HMC832 in fractional mode can achieve frequencies at
fractional multiples of the reference. The frequency of the
HMC832, fVCO, is given by
FRAC
INT
FRAC
INT
XTAL
VCO
ffNN
R
f
f+=+= )(
(12)
fOUT = fVCO/k (13)
where:
fOUT is the output frequency after any potential dividers.
k is 1 for fundamental, or k = 2, 4, 6, … 58, 60, 62 depending on
the selected output divider value (Register 0x05[5:0] indirectly
to VCO_REG 0x02[5:0]).
NINT is the integer division ratio, Register 0x03, an integer
number between 20 and 524,284.
NFRAC is the fractional part, from 0.0 to 0.99999..., NFRAC =
Register 0x04/224.
R is the reference path division ratio, Register 0x02.
fXTAL is the frequency of the reference oscillator input.
fPD is the PD operating frequency, fXTAL/R.
For example:
fOUT = 1402.5 MHz
k = 2
fvco = 2,805 MHz
fXTAL = 50 MHz
R = 1
fPD = 50 MHz
NINT = 56
NFRAC = 0.1
Register 0x04 = round(0.1 × 224) = round(1,677,721.6) =
1,677,722.
errorzf
VCO
Hz192.1MH2805
2
1677722
56
1
1050
24
6
+=
+
×
(14)
error
f
fVCO
OUT Hz596.0MHz5.1402
2+==
(15)
In this example, the output frequency of 1402.5 MHz is achieved by
programming the 19-bit binary value of 56d = 0x38 into the
INTG_REG bit in Register 0x03, and the 24-bit binary value of
1677722d = 0x19999A into the FRAC bit in Register 0x04. The
0.596 Hz quantization error can be eliminated using the exact
frequency mode, if required. In this example, the output
fundamental is divided by 2. Specific control of the output
divider is required. See the VCO Subsystem Register Map
section and description for details.
Exact Frequency Tuning
Due to quantization effects, the absolute frequency precision of
a fractional PLL is normally limited by the number of bits in the
fractional modulator. For example, a 24-bit fractional modulator
has frequency resolution set by the phase detector (PD) compari-
son rate divided by 224. The value 224 in the denominator is
sometimes referred to as the modulus. Analog Devices PLLs use
a fixed modulus, which is a binary number. In some types of
fractional PLLs the modulus is variable, allowing exact frequency
steps to be achieved with decimal step sizes. Unfortunately,
small steps using small modulus values result in large spurious
outputs at multiples of the modulus period (channel step size).
For this reason, Analog Devices PLLs use a large fixed modulus.
Normally, the step size is set by the size of the fixed modulus. In
the case of a 50 MHz PD rate, a modulus of 224 would result in a
2.98 Hz step resolution, or 0.0596 ppm. In some applications it is
necessary to have exact frequency steps, and even an error of
3 Hz cannot be tolerated.
Fractional PLLs are able to generate exact frequencies (with
zero frequency error) if N can be exactly represented in binary
(for example, N = 50.0, 50.5, 50.25, 50.75, and so forth). Note
that, some common frequencies cannot be exactly represented.
For example, NFRAC = 0.1 = 1/10 must be approximated as
round((0.1 x 224)/224 ) ≈ 0.100000024. At fPD = 50 MHz, this
Rev. A | Page 25 of 48
HMC832 Data Sheet
translates to a 1.2 Hz error. The exact frequency mode of the
HMC832 addresses this issue and can eliminate quantization
error by programming the channel step size to fPD/10 in
Register 0x0C to 10 (in this example). More generally, this
feature can be used whenever the desired frequency, fVCO, can be
exactly represented on a step plan where there are an integer
number of steps (<214) across integer-N boundaries.
Mathematically, this situation is satisfied if
≥=
=
14
1
2
and)
,
(where
0
)mod(
PD
GCD
PD
VCO
GCD
GCD
VCOk
f
fff
GCD
f
ff
(16)
where:
GCD means greatest common divisor.
fPD = frequency of the phase detector.
fVCOk is the channel step frequency where 0 < k < 224−1, as shown
in Figure 46.
Some fractional PLLs are able to achieve these exact frequencies
by adjusting (shortening) the length of the phase accumulator
(the denominator or the modulus of the Δ-Σ modulator) so that
the Δ-Σ modulator phase accumulator repeats at an exact
period related to the interval frequency (fVCOk − fVCO(k−1)) in
Figure 46. Consequently, the shortened accumulator results in
more frequent repeating patterns and as a result often leads to
spurious emissions at multiples of the repeating pattern period,
or at harmonic frequencies of fVCOk − fVCO(k−1). For example, in
some applications, these intervals might represent the spacing
between radio channels, with the spurious occurring at
multiples of the channel spacing.
In comparison, the Analog Devices method is able to generate
exact frequencies between adjacent integer-N boundaries while
still using the full 24-bit phase accumulator modulus, thus
achieving exact frequency steps with a high phase detector
comparison rate, which allows Analog Devices PLLs to maintain
excellent phase noise and spurious performance in the exact
frequency mode.
Figure 46. Exact Frequency Tuning
INTEGER
BOUNDARY INTEGER
BOUNDARY
f
N + 1
–
f
N
=
f
PD
f
N
f
VCO1
f
VCO2
f
VCO3
f
VCO
=
f
VCO2
f
VCO4
f
N + 1
f
VCO
14
f
VCO
14
– 1
f
VCO
14
– 2
12827-051
Rev. A | Page 26 of 48
Data Sheet HMC832
Using Exact Frequency Mode
If the constraint in Equation 16 is satisfied, the HMC832 is able
to generate signals with zero frequency error at the desired
VCO frequency. Exact frequency mode can be reconfigured for
each target frequency, or be setup for a fixed fGCD that applies to
all channels.
Configuring Exact Frequency Mode for a Particular
Frequency
1. Calculate and program the integer register setting
Register 0x03 = NINT = floor(fVCO/fPD)
where the floor function is the rounding down to the
nearest integer.
2. Then calculate the integer boundary frequency
fN = NINT × fPD.
3. Calculate and program the exact frequency register value
Register 0x0C = fPD/fGCD
where fGCD = GCD(fVCO,fPD).
4. Calculate and program the fractional register setting
Register 0x04
−
=
PD
NVCOk
FRAC fff
ceilN )(
224
where ceil is the ceiling function meaning round up to the
nearest integer.
Example: to configure the HMC832 for exact frequency mode
at fVCO = 2800.2 MHz, where the PD rate (fPD) = 61.44 MHz,
proceed as follows:
1. Check Equation 16 to confirm that the exact frequency
mode for this fVCO is possible.
≥=
14
2
),(
PD
GCD
PD
VCOGCD
f
fandffGCDf
fGCD = GCD(2800.2 × 106, 61.44 × 106) =
120 × 103 >
14
6
2
1044.61 ×
= 3750
Because Equation 16 is satisfied, the HMC832 can be
configured for exact frequency mode at fVCO = 2800.2 MHz by
continuing with the remaining steps.
2. Calculate NINT
NINT = Register 0x03 =
D2x0d45
1044.61
102.2800
6
6
1==
×
×
=
floor
f
f
floor
PD
VCO
3. Calculate the value for Register 0x0C
Register 0x0C =
00xC0d3072
20000
1044.61
)1044.61,10100(
1044.61
)),((
6
63
6
1
==
×
=
××
×
=
−
+
GCD
fffGCD
f
PD
VCOkVCOk
PD
4. To program Register 0x04, the closest integer-N boundary
frequency (fN) that is less than the desired VCO frequency
(fVCO) must be calculated: fN = fPD × NINT. Using the current
example
fN = fPD × NINT = 45 × 61.44 × 106 = 2764.8 MHz, then
Register 0x04 =
938000x
0d9666560
1044
.61
)10
8.2764
10
2.2800
(2
)(2
6
6624
24
=
=
×
×−
×
=
−
ceil
f
ff
ceil
PD
N
VCO
Exact Frequency Channel Mode
When multiple, equally spaced, exact frequency channels are
needed that fall within the same interval (that is, fN ≤ fVCOk <
fN + 1) where fVCOk is shown in Figure 46 and 1 ≤ k ≤ 214, it is
possible to maintain the same integer-N (Register 0x03) and
exact frequency register (Register 0x0C) settings and only
update the fractional register (Register 0x04) setting. The exact
frequency channel mode is possible when Equation 16 is
satisfied for at least two equally spaced adjacent frequency
channels, that is, the channel step size.
To configure the HMC832 for exact frequency channel mode,
initially and only at the beginning, the integer (Register 0x03)
and exact frequency (Register 0x0C) registers need to be
programmed for the smallest fVCO frequency (fVCO1 in Figure 46),
as follows:
1. Calculate and program the integer register setting Regis-
ter 0x03 = NINT = floor(fVCO1/fPD), where fVCO1 is shown in
Figure 46 and corresponds to the minimum channel VCO
frequency. Then, the lower integer boundary frequency is
given by fN = NINT × fPD.
2. Calculate and program the exact frequency register value
Register 0x0C = fPD/fGCD, where fGCD = GCD((fVCOk + 1 − fVCOk),
fPD) = greatest common divisor of the desired equidistant
channel spacing and the PD frequency ((fVCOk + 1 − fVCOk)
and fPD).
Rev. A | Page 27 of 48
HMC832 Data Sheet
To switch between various equally spaced intervals (channels)
only the fractional register (Register 0x04) needs to be
programmed to the desired VCO channel frequency (fVCOk) in
the following manner:
Register 0x04 =
−
=
PD
NVCOk
FRAC fff
ceilN )(224
where fN = floor(fVCO1/fPD), and fVCO1, as shown in Figure 46,
represents the smallest channel VCO frequency that is greater
than fN.
Example: to configure the HMC832 for the exact frequency
mode for equally spaced intervals of 100 kHz, where the first
channel (Channel 1) = fVCO1 = 2800.200 MHz and the PD rate
(fPD) = 61.44 MHz, proceed as follows:
1. Check that the exact frequency mode for this fVCO1 =
2800.2 MHz (Channel 1) and fVCO2 = 2800.2 MHz +
100 kHz = 2800.3 MHz (Channel 2) is possible.
≥
=
≥
=
14
14
1
2
),(
2
),(
PD
GCD2
PD
VCO2
GCD2
PD
GCD1
PD
VCO
GCD1
f
fand
ff
GCDfand
f
f
andff
GCDf
(17)
3750
2
1044.61
10
120
)1044.61,10
2.2800(
14
6
3
66
=
×
>×
=×
×= GCDf
GCD1
3750
2
1044.61
1020
)1044.61,103.2800(
14
6
3
66
=
×
>×
=××= GCDfGCD2
2. If Equation 16 is satisfied for at least two of the equally
spaced interval (channel) frequencies fVCO1, fVCO2, fVCO3, ...
fVCON, as it is in Equation 17, HMC832 exact frequency
channel mode is possible for all desired channel
frequencies, and can be configured as follows:
Register 0x03 =
x2D0d45
1044.61
102.2800
6
6==
×
×
=
floor
f
f
floor
PD
VCO1
Register 0x0C =
0xC00d3072
20000
1044.61
)1044.61,10100(
1044.61
)),((
6
63
6
1
==
×
=
××
×
=
−
+
GCDfffGCD
f
PD
VCOkVCOk
PD
where (fVCOk+1 − fVCOk) is the desired channel spacing
(100 kHz in this example).
3. To program Register 0x04, the closest integer-N boundary
frequency, fN, that is less than the smallest channel VCO
frequency, fVCO1, must be calculated (fN = floor(fVCO1/fPD)).
Using the current example:
MHz8.27641044.6145
1044.61
102.2800
6
6
6
=××
=
×
×
×= floorff
PDN
Then, for Channel 1,
Register 0x04 = ceil
−
PD
N
VCO1
f
ff )(2
24
,
where fVCO1 = 2800.2 MHz.
938000x0d9666560
1044.61
)108.2764102.2800(2
6
6624
==
×
×−×
=ceil
4. To change from Channel 1 (fVCO1 = 2800.2 MHz) to
Channel 2 (fVCO2 = 2800.3 MHz), only Register 0x04 needs
to be programmed, as long as all of the desired exact
frequencies, fVCOk (Figure 46), fall between the same
integer-N boundaries (fN < fVCOk < fN + 1). In that case,
Register 0x04 =
.onsoand,EAAB93x0d9693867
1044.61
)108.2764103.2800(2
6
6624
=
=
×
×−×
ceil
Seed Register
The start phase of the fractional modulator digital phase
accumulator (DPA) can be set to one of four possible default
values via the seed register, Register 0x06[1:0]. The HMC832
automatically reloads the start phase (seed value) into the DPA
every time a new fractional frequency is selected. Certain zero
or binary seed values may cause spurious energy correlation at
specific frequencies. For most cases a random (not zero and not
binary) start seed is recommended (Register 0x06[1:0] = 2).
SOFT RESET AND POWER-ON RESET
The HMC832 features a hardware power-on reset (POR). All
chip registers are reset to default states approximately 250 μs
after power up.
The PLL subsystem SPI registers can also be soft reset by an SPI
write to Register 0x00. Note that the soft reset does not clear the
SPI mode of operation referred to in the Serial Port section.
Note that the VCO subsystem is not affected by the PLL soft
reset; the VCO subsystem registers can only be reset by
removing the power supply.
If external power supplies or regulators have rise times slower
than 250 μs, then it is advised to write to the SPI reset register
(Register 0x00[5] = 1) immediately after power up, before any
other SPI activity. This write procedure ensures starting from a
known state.
Rev. A | Page 28 of 48
Data Sheet HMC832
Rev. A | Page 29 of 48
POWER-DOWN MODE
Note that the VCO subsystem is not affected by the CEN or soft
reset. Therefore, device power-down is a two step process.
1. Power down the VCO by writing 0 to VCO Register 1 via
Register 0x05 .
2. Power-down the PLL by pulling the CEN pin (Pin 17) low
(assuming there are no SPI overrides (Register 0x01[0] = 1)).
Pulling the CEN pin low disables all analog functions and
internal clocks. Current consumption typically drops below
10 μA in the power-down state. The serial port still
responds to normal communication in power-down mode.
It is possible to ignore the CEN pin by setting Register 0x01[0]
= 0. Control of the power-down mode then comes from the
serial port register, Register 0x01[1].
It is also possible to leave various blocks turned on when in
power-down (see Register 0x01), as listed in Table 10.
Table 10. Bit and Block Assignments for Register 0x01
Bit Assignment Block Assignment
Bit 2 Internal bias reference sources
Bit 3 PD block
Bit 4 CP block
Bit 5 Reference path buffer
Bit 6 VCO path buffer
Bit 7 Digital I/O test pads
To mute the output but leave the PLL and VCO locked, see the
VCO Output Mute Function section.
GENERAL-PURPOSE OUTPUT (GPO) PIN
The PLL shares the LD_SDO (lock detect/serial data output)
pin to perform various functions. Although the pin is most
commonly used to read back registers from the chip via the SPI,
it is also capable of exporting a variety of signals and real-time
test waveforms (including lock detect). It is driven by a tristate
CMOS driver with ~200 Ω ROUT. It has logic associated with it
to dynamically select whether the driver is enabled, and to
decide which data to export from the chip.
In its default configuration, after power-on reset, the output
driver is disabled, and only drives during appropriately
addressed SPI reads. This allows it to share the output with
other devices on the same bus.
The pin driver is enabled if the chip is addressed; that is, the last
three bits of SPI cycle = 000b before the rising edge of SEN. If
SEN rises before SCK has clocked in an invalid (non zero) chip
address, the HMC832 starts to drive the bus.
To monitor any of the GPO signals, including lock detect, set
Register 0x0F[7] = 1 to keep the SDO driver always on. This
stops the LDO driver from tristating and means that the SDO
line cannot be shared with other devices.
The HMC832 naturally switches away from the GPO data and
exports the SDO during an SPI read. To prevent this automatic
data selection, and always select the GPO signal, set Bit 6 of
Register 0x0F to 1 to prevent automux of the SDO. The phase
noise performance at this output is poor and uncharacterized.
Also, the GPO output should not be toggling during normal
operation because it may degrade the spectral performance.
Note that there are additional controls available, which may be
helpful when sharing the bus with other devices.
To disable the driver completely, set Register 0x08[5] = 0 (it
takes precedence over all else).
To disable either the pull-up or pull-down sections of the
driver, Register 0x0F[8] = 1 or Register 0x0F[9] = 1,
respectively.
Example scenarios are listed in Table 11. The signals that are
available on the GPO are selected by changing the GPO Select
Register 0x0F[4:0].
Table 11. Driver Scenarios
Scenario Action
Drive SDO During Reads, Tristate
Otherwise (Allow Bus Sharing)
None required
Drive SDO During Reads, Lock
Detect Otherwise
Set GPO Select Register 0x0F[4:0]
= 00001b (default)
Set Register 0x0F[7] = 1, prevent
GPO driver disable
Always Drive Lock Detect Set Register 0x0F[6] = 1, prevent
automux of SDO
Set the GPO Select
Register 0x0F[4:0] = 00001
(default)
Set Register 0x0F[7] = 1, prevent
GPO driver disable
CHIP IDENTIFICATION
PLL subsystem version information may be read by reading the
content of read only register, chip_ID in Register 0x00. It is not
possible to read the VCO subsystem version.
SERIAL PORT
The SPI protocol has the following general features:
3-bit chip address, can address up to eight devices
connected to the serial bus.
Wide compatibility with multiple protocols from multiple
vendors.
Simultaneous write/read during the SPI cycle.
5-bit address space.
3-wire for write only capability, 4-wire for read/write
capability.
Typical serial port operation can be run with SCLK at speeds up
to 50 MHz.
Serial Port Initialization at Power-Up
At power-up, it is required that both SEN and SCK lines are
initially held low, and that the first rising edge occurs on the
SCK line before any rising edges occur on the SEN line.
HMC832 Data Sheet
If the first rising edge occurs on the SEN line before it does on
the SCK line the HMC832LP6GE SPI interface does not
function. In that case, it is necessary to cycle the power to the
off and on, and repeat the previous recommended sequence
(hold both signals low at power-up and ensure that the first
rising edge occurs on the SCK line).
Serial Port Write Operation
SPI write specifications are listed in the Table 2 in the SPI Write
Timing Characteristics section and a typical write cycle is
shown in Figure 47. The SPI write operation is as follows:
1. The master (host) places 24-bit data, D23:D0, MSB first, on
SDI on the first 24 falling edges of SCLK.
2. The slave (HMC832) shifts in data on SDI on the first 24
rising edges of SCLK.
3. The master places a 5-bit register address to be written to,
R4:R0, MSB first, on the next five falling edges of SCLK
(25th to 29th falling edges).
4. The slave shifts the register bits on the next five rising
edges of SCLK (25th to 29th rising edges).
5. The master places 3-bit chip address, A2:A0, MSB first, on
the next three falling edges of SCLK (30th to 32nd falling
edges). Analog Devices reserves Chip Address A2 to Chip
Address A0 = 000 for all RF PLLs with integrated VCOs.
6. The slave shifts the chip address bits on the next three
rising edges of SCLK (30th to 32nd rising edges).
7. The master asserts SEN after the 32nd rising edge of SCLK.
8. The slave registers the SDI data on the rising edge of SEN.
Figure 47. Serial Port Timing Diagram, Write
1
t
1
t
2
t
5
t
6
t
3
t
4
2 3 22 23 24 25 26
x x
D23 D22 D2 D1 D0 A2 A1 A0
R4 R3 R0
30 31 32
SCK
SDI
SEN
12827-052
Rev. A | Page 30 of 48
Data Sheet HMC832
Serial Port Read Operation
In general, the LD_SDO line is always active during the
write cycle. During any SPI cycle, LD_SDO contains the
data from the current address written in Register 0x0[4:0].
If Register 0x0[4:0] is not changed, the same data is always
present on LD_SDO during a SPI cycle.
If a read is required from a specific address, it is necessary to
write the required address to Register 0x0[4:0] in the first SPI
cycle, then in the next SPI cycle, the desired data becomes
available on LD_SDO. A typical read cycle is shown in Figure 48.
An example of the two cycle procedure to read from any
random address is as follows:
1. The master (host), on the first 24 falling edges of SCLK
places 24-bit data, D23:D0, MSB first, on SDI as shown in
Figure 48. Set D23:D5 to zero. D4:D0 = address of the
register to be read on the next cycle.
2. The slave (HMC832) shifts in data on SDI on the first 24
rising edges of SCK.
3. The master places the 5-bit register address , R4:R0, (the
read address register), MSB first, on the next five falling
edges of SCK (25th to 29th falling edges). R4:R0 = 00000.
4. The slave shifts the register bits on the next five rising
edges of SCK (25th to 29th rising edges).
5. The master places the 3-bit chip address, A2:A0, MSB first,
on the next three falling edges of SCK (30th to 32nd falling
edges). The chip address is always 000b.
6. The slave shifts the chip address bits on the next three
rising edges of SCK (30th to 32nd rising edges).
7. The master asserts SEN after the 32nd rising edge of SCK.
8. The slave registers the SDI data on the rising edge of SEN.
9. The master clears SEN to complete the the address transfer
of the two part read cycle.
10. If a write data to the chip is not needed at the same time as
the second cycle occurs, then it is recommended to simply
rewrite the same contents on SDI to Register 0x00 on the
readback portion of the cycle.
11. The master places the same SDI data as the previous cycle
on the next 32 falling edges of SCK.
12. The slave (HMC832) shifts the SDI data on the next 32
rising edges of SCK.
13. The slave places the desired read data (that is, data from
the address specified in Register 0x00[4:0] of the first
cycle) on LD_SDO, which automatically switches to SDO
mode from LD mode, disabling the LD output.
14. The master asserts SEN after the 32nd rising edge of SCK to
complete the cycle and revert back to lock detect on
LD_SDO.
Rev. A | Page 31 of 48
HMC832 Data Sheet
Figure 48. Serial Port Timing Diagram, Read
1
t1
t5
t4
t7t6
t2
18 19 20
READ ADDRESS REGISTER ADDRES S = 00000
FIRST CYCLE
CHIPADDRESS = 000
24 25 29 30 31 32
R0R3D0D4D5x x
x
LD/GPO
SCK
SDI
SEN
LD_SDO
OR
TRISTATE LD/GPO
x x x x x x x x x x
R4 A2 A1 A0
t3
1
t1t7t6
18 19 20
SECOND CYCLE
24 25 29 30 31 32
R0R3D0D4D5D23xx
D23
LD/GPO
SCK
SDI
SEN
LD_SDO LD/GPO
1
1
FOR MORE INFORMATION ON USING THE GPO PIN WHILE IN SPI OPEN MODE PLEASE SEE SERIAL PORT SECTION.
D22 D2 D1 D0 R4 R0 A2 A1 A0
R4 A2 A1 A0
t3
12827-053
Rev. A | Page 32 of 48
Data Sheet HMC832
APPLICATIONS INFORMATION
Large bandwidth (25 MHz to 3000 MHz), industry leading
phase noise and spurious performance, excellent noise floor
(−160 dBc/Hz), coupled with a high level of integration make
the HMC832 ideal for a variety of applications; as an RF or IF
stage local oscillator (LO).
Using the HMC832 with a tunable reference, as shown in Figure 51,
it is possible to drastically improve spurious emissions performance
across all frequencies.
Figure 49. HMC832 in a Typical Transmit Chain
Figure 50. HMC832 in a Typical Receive Chain
Figure 51. HMC832 Used as a Tunable Reference for HMC832
HMC1044LP3E
HMC900LP5E HMC795LP5E
HMC832
PLL ÷2
DAC
DAC
HMC832
PLL
12827-040
HMC597LP4E
HMC1044LP3E
HMC832
HMC832
HMC900LP5E
CMIO
CMQO
HMC960LP4E
90 0
PLL
PLL
HMCAD1520
ADC
HMCAD1520
ADC
12827-041
HMC832
CRYSTAL
OSCILLATOR
PLL
HMC832
TUNABL E RE FERE NCE
25MHz TO 100MHz PLL
12827-042
Rev. A | Page 33 of 48
HMC832 Data Sheet
POWER SUPPLY
The HMC832 is a high performance, low noise device. In some
cases, phase noise and spurious performance may be degraded
by noisy power supplies. To achieve maximum performance
and ensure that power supply noise does not degrade the per-
formance of the HMC832 it is recommended to use the Analog
Devices low noise, high power supply rejection ratio (PSRR)
regulator, the HMC1060LP3E. Using the HMC1060LP3E lowers
the design risk and cost, and ensures that the performance shown
in the Typical Performance Characteristics section can be achieved.
PROGRAMMABLE PERFORMANCE TECHNOLOGY
For low power applications that do not require maximum noise
floor performance, the HMC832 features the ability to reduce
current consumption by 50 mA (power consumption by 165 mW)
at the cost of decreasing phase noise floor performance by ~5 dB.
High performance is enabled by writing VCO_REG 0x03[1:0] =
3d, and it is disabled (low current consumption mode enabled)
by writing VCO_REG 0x03[1:0] = 1d. High performance mode
improves noise floor performance at the cost of increased current
consumption. Resulting current consumption and phase noise
floor performance are shown in Figure 33 and Figure 36.
LOOP FILTER AND FREQUENCY CHANGES
Figure 52. Loop Filter Design
All PLLs with integrated VCOs exhibit integer boundary spurs
at harmonics of the reference frequency. As seen in Figure 18,
the plot shows the worst case spurious scenario where the
harmonic of the reference frequency (50 MHz) is within the
loop filter bandwidth of the fundamental frequency of the
HMC832.
The tunable reference changes the reference frequency from
50 MHz in Figure 18 to 47.5 MHz in Figure 16 to distance the
harmonic of the reference frequency (spurious emissions) away
from the fundamental output frequency of the HMC832 so that
it is filtered by the loop filter. The internal HMC832 setup and
divide ratios are changed in the opposite direction accordingly
so that the HMC832 generates identical output frequency as
shown in Figure 18, without the spurious emissions inside the
loop bandwidth. Using these same procedures, in Figure 19, the
graph is generated by observing and plotting the magnitude of
the largest spur only, at any offset, at each output frequency,
while using a fixed 50 MHz reference and a tunable 47.5 MHz
reference.
The HMC832 features an internal autocalibration process that
seamlessly calibrates the HMC832 when a frequency change
is executed (see Figure 27 and Figure 30). Typical frequency
settling time that can be expected after any frequency change
(writes to Register 0x03 or Register 0x04 ) is shown in Figure 27
with autocalibration enabled (Register 0x0A[11] = 0). A fre-
quency hop of 5 MHz is shown in Figure 27; however the settling
time is independent of the size of the frequency change. Any size
frequency hop has a similar settling time with autocalibration
enabled. Figure 32 shows the typical tuning voltage after calibration
where once the HMC832 is calibrated at any temperature, the
calibration setting holds across the entire operating range of the
HMC832 (−40°C to +85°C). Figure 32 shows that the tuning
voltage is maintained within a narrow operating range for worst
case scenarios where calibration was executed at one temperature
extreme and the device is operating at the other extreme.
For applications that require fast frequency changes, the HMC832
supports manual calibration that enables faster settling times
(see Figure 28 and Figure 31). Manual calibration needs to be
executed only once for each individual HMC832, at any tempera-
ture, and is valid across all temperature operating ranges of the
HMC832. More information about manual calibration is available
in the Manual VCO Calibration for Fast Frequency Hopping
section. A Frequency hop of 5 MHz is shown in Figure 28 and
Figure 31; however, the settling time is independent of the size
of the frequency change. Any size frequency hop has a similar
settling time with autocalibration disabled (Register 0x0A[11] = 1).
Table 12. Loop Filter Designs Used in Typical Performance Characteristics Graphs
Loop Filter
Type
Loop Filter BW
(kHz)
Loop Filter Phase
Margin
C1
(pF)
C2
(nF)
C3
(pF)
C4
(pF)
R2
(Ω)
R3
(Ω)
R4
(Ω)
Loop Filter
Design
Type 11 127 61° 390 10 82 82 750 300 300 See Figure 52
Type 22 75 61° 270 27 200 390 430 390 390
Type 33 214 71° 56 1.8 NA NA 2200 0 0
1 Loop Filter Type 1 is for best integrated phase noise. Loop filter bandwidth is designed for 50 MHz PD frequency, CP = 1.6 mA at 2.2 GHz output in fractional mode.
2 Loop Filter Type 2 is suggested to use for best far out phase noise. Loop filter BW is designed for 50 MHz PD frequency, CP = 1.6 mA at 2.2 GHz output in fractional
mode.
3 Loop Filter Type 3 is suggested to use for best integrated phase noise at integer mode. Loop filter bandwidth is designed for 50 MHz PD frequency, CP = 2.5 mA at
3 GHz output in integer mode.
CP VTUNE
C4C3C1
C2
R2
R3 R4
12827-037
Rev. A | Page 34 of 48
Data Sheet HMC832
RF PROGRAMMABLE OUTPUT RETURN LOSS
The HMC832 features programmable RF output return loss
(VCO_REG 0x03[5]) and 12 dB of programmable gain
(VCO_REG 0x07[3:0]), as shown in Figure 26 and Figure 25.
Maximum output power is achieved with a high return loss
setting (VCO_REG 0x03[5] = 0), as shown in Figure 22. Setting
VCO_REG 0x03[5] = 1 improves return loss for applications
that require it at the cost of reduced RF output power (see
Figure 22).
MUTE MODE
The HMC832 features a configurable mute mode, along with the
ability to independently turn off outputs on both RF_N and
RF_P output pins. Figure 35 shows isolation measured at the
output when the mute mode is on (VCO_REG 0x03[8:7] = 3d),
and when the mute mode is off (VCO_REG 0x03[8:7] = 1d), with
either both outputs disabled (VCO_REG 0x03[3:2] = 0) or one
output enabled and the other disabled (VCO_REG 0x03[3:2] = 1d).
Rev. A | Page 35 of 48
HMC832 Data Sheet
PLL REGISTER MAP
ID, READ ADDRESS, AND RST REGISTERS
The ID register is read only, the read address/RST strobe register is write only, and the RST register is read/write.
Table 13. Register 0x00, ID Register (Read Only)
Bits Type Name Width Default Description
23:0 R CHIP_ID 24 A7975 HMC832LP6GE chip ID
Table 14. Register 0x00, Read Address/RST Strobe Register (Write Only)
Bits Type Name Width Default1 Description
4:0 W Read address 5 N/A Read address for next cycle, open mode only. This is a write only register.
5 W Soft reset 1 N/A Soft reset for both SPI modes (set to 0 for proper operation).
23:6
W
Not defined
18
N/A
Not defined (set to 0 for proper operation).
1 N/A means not applicable.
Table 15. Register 0x01, RST Register (Default 0x000002)
Bits Type Name Width Default Description
0 R/W RST_CHIPEN_PIN_SELECT 1 0 1 = take PLL enable via CEN pin, see the Power-Down Mode section
0 = take PLL enable via SPI (RST_CHIPEN_FROM_SPI) Register 0x01[1]
1 R/W RST_CHIPEN_FROM_SPI 1 1 PLL enable bit of the SPI
9:2 R/W Reserved 8 0 Reserved
REFERENCE DIVIDER, INTEGER, AND FRACTIONAL FREQUENCY REGISTERS
Table 16. Register 0x02, REFDIV Register (Default 0x000001)
Bits Type Name Width Default Description
13:0 R/W RDIV 14 1 Reference divider R value (see Equation 12). Using the divider requires the Analog EN
Register 0x08[3] = 1 and divider, minimum = 1d, maximum = 16,383d.
Table 17. Register 0x03, Frequency Register, Integer Part (Default 0x000019)
Bits Type Name Width Default Description
18:0 R/W INTG_REG 19 25d Integer divider register. These bits are the VCO divider integer part, used in
all modes, see Equation 12.
Fractional mode.
Maximum 219 − 4 = 0x7FFFC = 524,284d.
Integer mode.
Minimum 16d.
Maximum 219− 1 = 0x7FFFF = 524,287d.
Table 18. Register 0x04, Frequency Register, Fractional Part (Default 0x000000)
Bits Type Name Width Default Description
23:0
R/W
FRAC
24
0
VCO divider fractional part (24-bit unsigned), see the Fractional Frequency Tuning section.
These bits are used in fractional mode only (NFRAC = Register 0x04/224). Minimum = 0d;
maximum = 224 − 1.
Rev. A | Page 36 of 48
Data Sheet HMC832
VCO SPI REGISTER
Register 0x05 is a special register used for indirect addressing of
the VCO subsystem. Writes to Register 0x05 are automatically
forwarded to the VCO subsystem by the VCO SPI state
machine controller.
Register 0x05 is a read/write register. However, Register 0x05
holds only the contents of the last transfer to the VCO subsystem.
Therefore, it is not possible to read the full contents of the VCO
subsystem. Only the content of the last transfer to the VCO
subsystem can be read. Also note special considerations for
autocalibration related to Register 0x05.
Table 19. Register 0x05, VCO SPI Register (Default 0x000000)
Bits Type Name Width Default Description
2:0 R/W VCO_ID 3 0 Internal VCO subsystem ID.
6:3
R/W
VCO_REGADDR
4
0
VCO subsystem register address. These bits are for
interfacing with the VCO. See the VCO Serial Port Interface
(VSPI) section.
15:7
R/W
VCO_DATA
9
0
VCO subsystem data. These bits are for the data to be
written to the VCO subsystem.
DELTA-SIGMA CONFIGURATION
Table 20. Register 0x06, Delta-Sigma Configuration Register (Default 0x200B4A)
Bit Type Name Width Default Description
1:0 R/W Seed 2 2 Selects the seed in fractional mode. Writes to this register are stored in
theHMC832 and are loaded into the modulator only when a frequency change is
executed and if Register 0x06[8] = 1.
00: 0 seed.
01: LSB seed.
02: 0xB29D08 seed.
03: 0x50F1CD seed.
6:2 R/W Reserved 5 18d Reserved.
7 R/W FRAC_BYPASS 1 0 Bypass fractional mode. In the bypass fractional modulator, output is ignored, but
fractional modulator continues to be clocked when FRAC_RST = 1. This bit can be
used to test the isolation of the digital fractional modulator from the VCO output
in integer mode.
0: use modulator, required for fractional mode
1: bypass modulator, required for integer mode.
10:8 R/W Initialization 3 3d Program to 7d.
11
R/W
SD enable
This bit controls whether autocalibration starts on an integer or a fractional write.
1
1
0: disables fractional core, use for integer mode or integer mode with CSP.
1: enables fractional core, required for fractional mode, or integer isolation
testing.
20:12
R/W
Reserved
9
0
Reserved.
21 R/W Automatic clock
configuration
1 1 Program to 0.
22 R/W Reserved 1 0 Reserved.
Rev. A | Page 37 of 48
HMC832 Data Sheet
LOCK DETECT REGISTER
Table 21. Register 0x07, Lock Detect Register (Default 0x00014D)
Bit Type Name Width Default Description
2:0
R/W
LKD_WINCNT_MAX
3
5d
Lock detect window sets the number of consecutive counts of divided VCO
that must land inside the lock detect window to declare lock
0: 5
1: 32
2: 96
3: 256
4: 512
5: 2048
6: 8192
7: 65,535
3 R/W Enable internal lock
detect
1 1 See the Serial Port section
5:4 R/W Reserved 2 0 Reserved
6 R/W Lock detect window
type
1 1 Lock detection window timer selection
1: digital programmable timer
0: analog one shot, nominal 10 ns window
9:7 R/W LD digital window
duration
3 2 Lock detection, digital window duration
0: half cycle
1: one cycle
2: two cycles
3: four cycles
4: eight cycles
5: 16 cycles
6: 32 cycles
7: 64 cycles
11:10 R/W LD digital timer
frequency control
2 0 Lock detect digital timer frequency control, see the Lock Detect section for
more information
00: fastest
11: slowest
12 R/W Reserved 31 0 Reserved
13 R/W Automatic relock: one
try
1 0 1: attempts to relock if lock detect fails for any reason; tries one time only
ANALOG ENABLE (EN) REGISTER
Table 22. Register 0x08, Analog EN Register, (Default 0xC1BEFF)
Bit Type Name Width Default Description
4:0 R/W Reserved 5 31d Reserved
5 R/W GPO_PAD_EN 1 1 0: disables the LD/SDO pin
1: enables GPO port or allows a shared SPI
When Bit 5 = 1 and Register 0xF[7] = 1, the LD_SDO pin is always driven, which
is required for use of the GPO port
When Bit 5 = 1 and Register 0xF[7] = 0, SDO is off when an unmatched chip
address is seen on the SPI, allowing a shared SPI with other compatible devices
9:6 R/W Reserved 4 11d Reserved
10 R/W VCO buffer and
prescaler bias
enable
1 1 VCO buffer and prescaler bias enable
20:11 R/W Reserved 1 55d Reserved
Rev. A | Page 38 of 48
Data Sheet HMC832
Rev. A | Page 39 of 48
Bit Type Name Width Default Description
21 R/W
High frequency
reference
1 0 Program to 1 for XTAL > 200 MHz
23:22 R/W Reserved 2 3d Reserved
CHARGE PUMP REGISTER
Table 23. Register 0x09, Charge Pump Register (Default 0x403264)
Bit Type Name Width Default Description
6:0 R/W CP DN gain 7 100d
0x64
Charge pump DN gain control, 20 μA per step. Affects fractional phase
noise and lock detect settings.
0d = 0 μA
1d = 20 μA
2d = 40 μA
…
127d = 2.54 mA
13:7 R/W CP UP gain 7 100d
0x64
Charge pump up gain control, 20 μA per step. Affects fractional phase
noise and lock detect settings.
0d = 0 μA
1d = 20 μA
2d = 40 μA
…
127d = 2.54 mA
20:14 R/W Offset magnitude 7 0 Charge pump offset control, 5 μA per step. Affects fractional phase
noise and lock detect settings.
0d = 0 μA
1d = 5 μA
2d = 10 μA
…
127d = 635 μA
21 R/W Offset up enable 1 0 Recommended setting = 1 in fractional mode, 0 otherwise.
22 R/W Offset DN enable 1 1 Recommended setting = 0.
23 R/W Reserved 1 0 Reserved.
AUTOCALIBRATION REGISTER
Table 24. Register 0x0A, VCO Autocalibration Configuration Register (Default 0x002205)
Bit Type Name Width Default Description
2:0 R/W VTUNE resolution 3 5 R divider cycles
0: 1 cycle
1: 2 cycles
2: 4 cycles
…
7: 256 cycles
9:3 R/W Reserved 7 64d Program 8d
10 R/W Force curve 1 0 Program 0
11 R/W Autocalibration disable 1 0 Program 0 for normal operation using VCO autocalibration
12 R/W No VSPI trigger 1 0 0: normal operation
1: this bit disables the serial transfers to the VCO subsystem (via
Register 0x05)
HMC832 Data Sheet
Rev. A | Page 40 of 48
Bit Type Name Width Default Description
14:13 R/W FSM/VSPI clock select 2 1 These bits set the autocalibration FSM and VSPI clock (50 MHz
maximum)
0: input crystal reference
1: input crystal reference divide by 4
2: input crystal reference divide by 16
3: input crystal reference divide by 32
16:15 R/W Reserved 2 0 Reserved
PHASE DETECTOR (PD) REGISTER
Table 25. Register 0x0B, PD Register (Default 0x0F8061)
Bit Type Name Width Default Description
2:0 R/W PD_DEL_SEL 3 1 Sets PD reset path delay (recommended setting is 001).
4:3 R/W Reserved 2 0 Reserved.
5 R/W PD_UP_EN 1 1 Enables the PD up output.
6 R/W PD_DN_EN 1 1 Enables the PD down output.
8:7 R/W CSP mode 2 0 Cycle slip prevention mode. This delay varies by ±10% with temperature, and
±12% with process. Extra current is driven into the loop filter when the phase error
is larger than the following:
0 = disabled
1 = 5.4 ns
2 = 14.4 ns
3 = 24.1 ns
9 R/W Force CP up 1 0 Forces CP up output to turn on; use for test only.
10 R/W Force CP DN 1 0 Forces CP down output to turn on; use for test only.
23:11 R/W Reserved 13 496d
0x1F0
Reserved.
EXACT FREQUENCY MODE REGISTER
Table 26. Register 0x0C, Exact Frequency Mode Register (Default 0x000000)
Bit Type Name Width Default Description
13:0 R/W
Number of
Channels per fPD
14 0 The comparison frequency divided by the correction rate must be an integer.
Frequencies at exactly the correction rate have zero frequency error.
0: disabled.
1: disabled.
2:16383d (0x3FFF).
Data Sheet HMC832
GENERAL-PURPOSE, SERIAL PORT INTERFACE, AND REFERENCE DIVIDER (GPO_SPI_RDIV) REGISTER
Table 27. Register 0x0F, GPO_SPI_RDIV Register (Default 0x000001)
Bit Type Name Width Default Description
4:0
R/W
GPO_SELECT
5
1d
The signal selected here is an output to the SDO pin when the SDO
pin is enable via Register 0x08[5]
0: data from Register 0x0F[5]
1: lock detect output
2: lock detect trigger
3: lock detect window output
4: ring oscillator test
5: pull-up hard from CSP
6: pull-down hard from CSP
7: reserved
8: reference buffer output
9: reference divider output
10: VCO divider output
11: modulator clock from VCO divider
12: auxiliary clock
13: auxiliary SPI clock
14: auxiliary SPI enable
15: auxiliary SPI data output
16: PD down
17: PD up
18: SD3 clock delay
19: SD3 core clock
20: autostrobe integer write
21: autostrobe fractional write
22: autostrobe auxiliary SPI
23: SPI latch enable
24: VCO divider sync reset
25: seed load strobe
26 to 29: not used
30: SPI output buffer enable
31: soft reset, RST
5 R/W GPO test data 1 0 1: GPO test data
6 R/W Prevent automux SDO 1 0 1: outputs GPO data only
0: automuxes between SDO and GPO data
7 R/W LDO driver always on 1 0 1: LD_SDO pin driver always on
0: LD_SDO pin driver only on during SPI read cycle
8 R/W Disable PFET 1 0
9 R/W Disable NFET 1 0
Rev. A | Page 41 of 48
HMC832 Data Sheet
VCO TUNE REGISTER
The VCO tune register is a read only register.
Table 28. Register 0x10, VCO Tune Register (Default 0x000020)
Bit Type Name Width Default Description
7:0 R VCO switch
setting
8 32 Indicates the VCO switch setting selected by the autocalibration state machine to
yield the nearest free running VCO frequency to the desired operating frequency. Not
valid when Register 0x10[8] = 1, autocalibration busy. Note that when a manual
change is made to the VCO switch settings, this register does not indicate the current
VCO switch position. VCO subsystems may not use all the MSBs, in which case the
unused bits are don’t care.
0 = highest frequency.
1 = second highest frequency.
…
255 = lowest frequency.
8 R Autocalibration
busy
1 0 Busy when the autocalibration state machine is searching for the nearest switch
setting to the requested frequency.
SAR REGISTER
The SAR register is a read only register.
Register 0x11, SAR Register (Default 0x07FFFF)
Bit Type Name Width Default Description
18:0 R SAR error magnitude counts 19 219 to 1 SAR error magnitude counts
19 R SAR error sign 1 0 SAR error sign
0 = +ve
1 = −ve
GENERAL-PURPOSE 2 REGISTER
The GPO2 register is a read only register.
Table 29. Register 0x12, GPO2 Register (Default 0x000000)
Bit Type Name Width Default Description
0 R GPO 1 0 GPO state
1 R Lock detect 1 0 Lock detect status
1 = locked
0 = unlocked
BUILT-IN SELF TEST REGISTER
The BIST register is a read only register.
Table 30. Register 0x13, BIST Register (Default 0x001259)
Bit Type Name Width Default Description
16:0 R Reserved 17 4697d Reserved
Rev. A | Page 42 of 48
Data Sheet HMC832
VCO SUBSYSTEM REGISTER MAP
The VCO subsystem uses indirect addressing via Register 0x05. For more detailed information on how to write to the VCO subsystem,
see the VCO Serial Port Interface (VSPI) section.
The VCO tuning register is write only.
Table 31. VCO_REG 0x00 Tuning
Bit Type Name Width Default Description
0 W CAL 1 0 VCO tune voltage is redirected to a temperature compensated
calibration voltage
8:1
W
CAPS
8
16
VCO subband selection
0: maximum frequency
1111 1111: minimum frequency
VCO ENABLE REGISTER
The VCO enable register is a write only register.
Table 32. VCO_REG 0x01 Enable
Bit Type Name Width Default Description
0 W Master enable VCO subsystem 1 1 0: all VCO subsystem blocks are turned off.
1 W VCO enable 1 1 Enables VCOs.
2 W PLL buffer enable 1 1 Enables PLL buffer to N divider.
3 W Input/output master enable 1 1 Enables output stage and the output divider. It does not enable/disable
the VCO.
4 W Reserved 1 1 Reserved.
5 W Output stage enable 1 1 Output stage enable.
7:6 W Reserved 2 3 Reserved.
8 W Reserved 1 1 Reserved.
Example: Disabling the Output Stage of the VCO
Subsystem
To disable the output stage of the VCO subsystem of the
HMC832, clear Bit 5 in VCO_REG 0x01. If the other bits are
left unchanged, then write 1 1101 1111 into VCO_REG 0x01.
The VCO subsystem register is accessed via a write to PLL
subsystem Register 0x05 = 1 1101 1111 0001 00 = 0xEF88.
Register 0x05[2:0] = 000; VCO subsystem ID 0.
Register 0x05[6:3] = 0001; VCO subsystem register address.
Register 0x05[7] = 1; master enable.
Register 0x05[8] = 1; VCO enable.
Register 0x05[9] = 1; PLL buffer enable.
Register 0x05[10] = 1; I/O master enable.
Register 0x05[11] = 1; reserved.
Register 0x05[12] = 0; disable the output stage.
Register 0x05[14:13] = 11b.
Register 0x05[15] = 1; don’t care.
Rev. A | Page 43 of 48
HMC832 Data Sheet
VCO OUTPUT DIVIDER REGISTER
This is a write only register. Note that to write 0_1111_1110 into
VCO_REG 0x02 VCO subsystem (VCO_ID = 000b), and set
the VCO output divider to divide by 62, the following needs to
be written to Register 0x05 = 0_1111_1110, 0010, 000 b.
Register 0x05[2:0] = 000; Subsystem ID 0
Register 0x05[6:3] = 0010; VCO Register Address 2d.
Register 0x05[16:7] = 0_1111_1110; divide by 62, maximum
output RF gain.
Table 33. VCO_REG 0x02 VCO Output Divider
Bit Type Name Width Default Description
5:0 W RF divide ratio 6 1 0: mutes the output when VCO_REG 0x03[8:7] = 0d
1: fo
2: fo/2
3: invalid, defaults to 2
4: fo/4
5: invalid, defaults to 4
6: fo/6
…
60: fo/60
61: invalid, defaults to 60
62: fo/62 > 62 invalid, defaults to 62
8:6
W
Reserved
3
0
Reserved
VCO CONFIGURATION REGISTER
The VCO configuration register is a write only register.
Table 34. VCO_REG 0x03 Configuration
Bit Type Name Width Default Description
1:0
W
Programmable
performance mode
2
2
Selects output noise floor performance level at a cost of increased
current consumption.
01: low current consumption mode.
11: high performance mode.
Other states (00 and 10) not supported.
2 W RF_N output enable 1 0 Enables the output on RF_N pin. Required for differential operation, or
single-ended output on the RF_N pin.
3 W RF_P output enable 1 0 Enables the output on RF_P pin. Required for differential operation, or
single-ended output on the RF_P pin.
4 W Reserved 1 1 Reserved.
5 W Return loss 1 0 0: return loss = −5 dB typical (highest output power).
1: return loss = −10 dB typical.
6 W Reserved 1 0 Reserved.
8:7 W Mute mode 2 1 Defines when the mute function is enabled (the output is muted), see
the VCO Output Mute Function section, and Figure 35 for more
information.
00: enables mute when the divide ratio, VCO_REG 0x02[5:0] = 0. This
enables the HMC832 to be backwards compatible to the HMC830 mute
function.
01: during VCO calibration (see the VCO Calibration section for more
details).
10: not supported.
11: mute all RF outputs (unconditional).
Rev. A | Page 44 of 48
Data Sheet HMC832
VCO CALIBRATION/BIAS, CF CALIBRATION, AND MSB CALIBRATION REGISTERS
These registers are write only. Note that, specified performance is only guaranteed with the required settings in Table 35 only; other
settings are not supported.
Table 35. VCO_REG 0x04 CAL/Bias
Bit Type Name Width Default Description
0 W Initialization 9 201d Reserved
Table 36. VCO_REG 0x05 CF_CAL
Bit Type Name Width Default Description
8:0 W Reserved 9 170d Reserved
Table 37. VCO_REG 0x06 MSB Calibration
Bit Type Name Width Default Description
8:0 W Reserved 9 255d Reserved
VCO OUTPUT POWER CONTROL
The VCO power control register is write only.
Table 38. VCO_REG 0x07 Output Power Control
Bit Type Name Width Default Description
3:0 W Output stage gain control 4 1 Output stage gain control in 1 dB steps
0d: 0 dB gain
1d: 1 dB gain
2d: 2 dB gain
…
10d: 10 dB gain
11d: 11 dB gain
4 W Initialization 1 0 Program to 1d
8:5 W Reserved 4 4d Program 4d
Rev. A | Page 45 of 48
HMC832 Data Sheet
Rev. A | Page 46 of 48
EVALUATION PRINTED CIRCUIT BOARD (PCB)
Figure 53. Silk Screen and PCB Traces Top Layer
Figure 54. Silk Screen and PCB Traces Bottom Layer
The circuit board used in the application uses RF circuit design
techniques. Signal lines have 50 Ω impedance whereas the
package ground leads and exposed paddle are connected
directly to the ground plane similar to that shown in Figure 53
and Figure 54. Use a sufficient number of via holes to connect
the top and bottom ground planes. The evaluation circuit board
shown Figure 53 and Figure 54 is available from Analog Devices
upon request.
CHANGING EVALUATION BOARD REFERENCE
FREQUENCY AND CP CURRENT CONFIGURATION
The evaluation board is provided with a 50 MHz on board
reference oscillator, and Type 1 loop filter configuration, as
shown in Figure 52 (~127 kHz bandwidth, see Table 12).
The default register configuration file included in the Analog
Devices PLL evaluation software sets the comparison frequency
to 50 MHz (R = 1, that is, Register 0x02 = 1).
As with all PLLs and PLL with integrated VCOs, modifying the
comparison frequency or charge pump (CP) current results in
changes to the loop dynamics and ultimately, phase noise
performance. When making these changes there are several
items to keep in mind:
CP offset current setting: refer to the Charge Pump (CP)
and Phase Detector (PD) section.
LD configuration: refer to the Lock Detect section.
To redesign the loop filter for a particular application,
download the PLL design software tool by clicking on the
software download link on the HMC832 product page. Analog
Devices PLL design enables users to accurately model and
analyze performance of all Analog Devices PLLs, PLLs with
integrated VCOs, and clock generators. It supports various loop
filter topologies, and enables users to design custom loop filters
and accurately simulate resulting performance. For more
information, see the Loop Filter and Frequency Changes
section.
For evaluation purposes, the HMC832 evaluation board is
shipped with an on-board, low cost, low noise (100 ppm),
50 MHz VCXO, enabling evaluation of most parameters
including phase noise without any external references.
Exact phase or frequency measurements require the HMC832
to use the same reference as the measuring instrument. To
accommodate this requirement, the HMC832 evaluation board
includes the HMC1031MS8E; a simple low current integer-N
PLL that can lock the on-board VCXO to an external 10 MHz
reference input commonly provided by most test equipment. To
lock the HMC832 to an external 10 MHz reference, connect the
external reference output to the J5 input of the HMC832 evaluation
board and change the HMC1031MS8E integer divider value to
5 by changing the switch settings, D1 = 1 (SW1 to SW4 closed),
and D0 = 0 (SW2 to SW3 open), for more information see the
HMC1031MS8E data sheet.
EVALUATION KIT CONTENTS
The evaluation kit contains one HMC832LP6GE evaluation
PCB, a USB interface board, a six-foot USB A-male to USB
B-female cable, a CD ROM that contains the user manual,
evaluation PCB schematic, evaluation software, and Analog
Devices PLL design software. To order the evaluation kit, see
the Ordering Guide section for the product number.
12827-039
12827-139
Data Sheet HMC832
OUTLINE DIMENSIONS
Figure 55. 40-Lead Quad Flat No-Lead Package [QFN]
6 mm × 6 mm Body, Very Thin Quad
Dimensions shown in inches and [millimeters]
Figure 56. Tape and Reel Outline Dimensions
Dimensions shown in millimeters
11-10-2014-A
NOTES:
1. PACKAGE BODY MATERIAL: LOW STRESS INJECTION MOLDED PLASTIC SILICA
AND SILICON IMPREGNATED.
2. LEAD AND GROUND PADDLE MATERIAL: COPPER ALLOY.
3. LEAD AND GROUND PADDLE PLATING: 100% MATTE TIN.
4. DIMENSIONS ARE IN INCHES [MILLIMETERS].
5. LEAD SPACING TOLERANCE IS NON-CUMULATIVE.
6. PAD BURR LENGTH SHALL BE 0.15mm MAX. PAD BURR HEIGHT SHALL BE 0.25mm m ax.
7. PACKAGE WARP SHALL NOT EXCEED 0.05mm.
9. REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN.
FO R PROPER CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PI N CONFIGURATIO N AND
FUNCTI ON DESCRIPT IO NS
SECTI ON OF THIS DAT A SHEET .
BOTTOM VIEW
TOP VIEW
11-03-2014-A
Rev. A | Page 47 of 48
HMC832 Data Sheet
ORDERING GUIDE
Model1 Lead Finish
MSL
Rating Temperature Package Description Qty. Brand2
HMC832LP6GE 100% matte Sn MSL1 −40°C to +85°C 40-Lead Quad Flat No-Lead Package
[QFN], Low Stress Injection Molded Plastic
XXXX
832H
HMC832LP6GETR 100% matte Sn MSL1 −40°C to +85°C 40-Lead Quad Flat No-Lead Package
[QFN], Low Stress Injection Molded
Plastic, 7” Tape and Reel
500
XXXX
832H
EKIT01-HMC832LP6G Evaluation Kit
EVAL01-HMC832LP6G Evaluation Board
1 E = RoHS Compliant Part.
2 Four-digit lot number XXXX.
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12827-0-11/14(A)
Rev. A | Page 48 of 48