TPS74301RGWTG4 - Texas Instruments

TPS743xx

500mV/div

Time(20ms/div)

VPG

VTRACK

I =500mA

OUT

VOUT

COUT

Optional

OUT

BIAS

TRACK

GND

VIN

VBIAS

CIN

CBIAS

VTRACK

VPG

TPS74301

ADJUSTABLEVOLTAGEVERSION

VOUT

COUT

Optional

OUT

SNS

BIAS

TRACK

GND

VIN

VBIAS

CIN

CBIAS

VTRACK

VPG

TPS743xx

FIXEDVOLTAGEVERSION

TPS743xx

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SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

1.5A Ultra-LDO with Programmable Sequencing

Check for Samples: TPS743xx

1FEATURES DESCRIPTION

2• Track Pin Allows for Flexible Power-Up The TPS743xx low-dropout (LDO) linear regulators

Sequencing provide an easy-to-use robust power management

• 1% Accuracy Over Line, Load, and solution for a wide variety of applications. The

Temperature TRACK pin allows the output to track an external

• Supports Input Voltages as Low as 0.9V with supply. This feature is useful in minimizing the stress

External Bias Supply on ESD structures that are present between the

CORE and I/O power pins of many processors. The

• Adjustable Output (0.8V to 3.6V) enable input and power-good output allow easy

• Fixed Output (0.9V to 3.6V) sequencing with external regulators. This complete

• Ultra-Low Dropout: 55mV at 1.5A (typ) flexibility allows the user to configure a solution that

meets the sequencing requirements of FPGAs,

• Stable with Any or No Output Capacitor DSPs, and other applications with special start-up

• Excellent Transient Response requirements.

• Available in 5mm × 5mm × 1mm QFN and A precision reference and error amplifier deliver 1%

DDPAK-7 Packages accuracy over load, line, temperature, and process.

• Open-Drain Power-Good (5 × 5 QFN) Each LDO is stable with low-cost ceramic output

• Active High Enable capacitors and the family is fully specified from –40°C

to +125°C. The TPS743xx is offered in a small (5mm

× 5mm) QFN package, yielding a highly compact total

APPLICATIONS solution size. For applications that require additional

• FPGA Applications power dissipation, the DDPAK (KTW) package is also

• DSP Core and I/O Voltages available.

• Post-Regulation Applications

• Applications with Special Start-Up Time or

Sequencing Requirements

Figure 1. Tracking Response

Figure 2. Typical Application Circuit

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS743xx

SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION(1)

PRODUCT VOUT (2)

TPS743xx yyy z XX is nominal output voltage (for example, 12 = 1.2V, 15 = 1.5V, 01 = Adjustable).(3)

YYY is package designator.

Zis package quantity.

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Output voltages from 0.9V to 1.5V in 50mV increments and 1.5V to 3.3V in 100mV increments are available through the use of

innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability.

(3) For fixed 0.8V operation, tie FB to OUT.

ABSOLUTE MAXIMUM RATINGS(1)

At TJ= –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND.

TPS743xx UNIT

VIN, VBIAS Input voltage range –0.3 to +6 V

VEN Enable voltage range –0.3 to +6 V

VPG Power-good voltage range –0.3 to +6 V

IPG PG sink current 0 to +1.5 mA

VTRACK Track pin voltage range –0.3 to +6 V

VFB Feedback pin voltage range –0.3 to +6 V

VOUT Output voltage range –0.3 to VIN + 0.3 V

IOUT Maximum output current Internally limited

Output short circuit duration Indefinite

PDISS Continuous total power dissipation See Thermal Information Table

TJOperating junction temperature range –40 to +125 °C

TSTG Storage junction temperature range –55 to +150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for

extended periods may affect device reliability.

TPS743xx

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SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

THERMAL INFORMATION TPS743xx(2)

THERMAL METRIC(1) UNITS

RGW (20 PINS) KTW (7 PINS)

qJA Junction-to-ambient thermal resistance(3) 30.5 20.1

qJCtop Junction-to-case (top) thermal resistance(4) 27.6 2.1

qJB Junction-to-board thermal resistance(5) N/A N/A °C/W

yJT Junction-to-top characterization parameter(6) 0.37 4.2

yJB Junction-to-board characterization parameter(7) 10.6 6.1

qJCbot Junction-to-case (bottom) thermal resistance(8) 4.1 1.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.

(2) Thermal data for the RGW and KTW packages are derived by thermal simulations based on JEDEC-standard methodology as specified

in the JESD51 series. The following assumptions are used in the simulations:

(a) i. RGW: The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array.

-ii. KTW: The exposed pad is connected to the PCB ground layer through a 6x6 thermal via array.

(b) Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.

(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To

understand the effects of the copper area on thermal performance, refer to the Power Dissipation and Estimating Junction

Temperature sections.

(3) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(6) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).

(8) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

TPS743xx

SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

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ELECTRICAL CHARACTERISTICS

At VEN = 1.1V, VIN = VOUT + 0.3V, CIN = CBIAS = 0.1mF, COUT = 10mF, IOUT = 50mA, VBIAS = 5.0V, and TJ= –40°C to +125°C,

unless otherwise noted. Typical values are at TJ= +25°C. TPS743xx

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIN Input voltage range VOUT + VDO 5.5 V

VBIAS Bias pin voltage range 2.375 5.25 V

VREF Internal reference (Adj.) TJ= +25°C 0.796 0.8 0.804 V

Output voltage range VIN = 5V, IOUT = 1.5A, VBIAS = 5V VREF 3.6 V

VOUT 2.375V ≤VBIAS ≤5.25V, VOUT + 1.62V ≤VBIAS

Accuracy(1) –1 ±0.2 1 %

50mA ≤IOUT ≤1.5A

VOUT (NOM) + 0.3 ≤VIN ≤5.5V, QFN 0.0005 0.05

VOUT/VIN Line regulation %/V

VOUT (NOM) + 0.3 ≤VIN ≤5.5V, DDPAK 0.0005 0.06

0mA ≤IOUT ≤50mA 0.013 %/mA

VOUT/IOUT Load regulation 50mA ≤IOUT ≤1.5A 0.04 %/A

IOUT = 1.5A, VBIAS – VOUT (NOM) ≥1.62V, QFN 55 100

VIN dropout voltage(2) mV

VDO IOUT = 1.5A, VBIAS – VOUT (NOM) ≥1.62V, DDPAK 60 120

VBIAS dropout voltage(2) IOUT = 1.5A, VIN = VBIAS 1.4 V

ICL Current limit VOUT = 80% × VOUT (NOM) 1.8 4 A

IBIAS Bias pin current IOUT = 0mA to 1.5A 2 4 mA

ISHDN Shutdown supply current (VIN) VEN ≤0.4V 1 100 mA

IFB, ISNS Feedback, Sense pin IOUT = 50mA to 1.5A –250 68 250 nA

current(3)

1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V 73

Power-supply rejection dB

(VIN to VOUT)800kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V 42

PSRR 1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V 67

Power-supply rejection dB

(VBIAS to VOUT)800kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V 50

Noise Output noise voltage 100Hz to 100kHz, IOUT = 1.5A 25 × VOUT mVRMS

%VOUT droop during load

VTRAN IOUT = 50mA to 1.5A at 1A/ms, COUT = none 3.5 %VOUT

transient

tSTR Minimum startup time VTRACK > 0.8V 40 ms

TACC Track pin accuracy 0.2V ≤VTRACK ≤0.7V, VOUT = 0.8V –60 60 mV

ITR Track pin current VTRACK = 0.4V 0.1 1 mA

VEN, HI Enable input high level 1.1 5.5 V

VEN, LO Enable input low level 0 0.4 V

VEN, HYS Enable pin hysteresis 50 mV

VEN, DG Enable pin deglitch time 20 ms

IEN Enable pin current VEN = 5V 0.1 1 mA

VIT PG trip threshold VOUT decreasing 86.5 90 93.5 %VOUT

VHYS PG trip hysteresis 3 %VOUT

VPG, LO PG output low voltage IPG = 1mA (sinking), VOUT < VIT 0.3 V

IPG, LKG PG leakage current VPG = 5.25V, VOUT > VIT 0.3 1 mA

Operating junction

TJ–40 +125 °C

temperature

Shutdown, temperature increasing +155

Thermal shutdown

TSD °C

temperature Reset, temperature decreasing +140

(1) Adjustable devices tested at 0.8V; external resistor tolerance is not taken into account.

(2) Dropout is defined as the voltage from the input to VOUT when VOUT is 2% below nominal.

(3) IFB, ISNS current flow is out of the device.

Thermal

Limit

BIAS

TRACK

EN Hysteresis

andDe-Glitch

Current

Limit

UVLO

0.8V

Reference

0.9 V´REF

GND

V <V =1,V >V =0

TRACK REF TRACK REF

VOUT

V =0.8x( )

OUT 1+ R1

OUT

RSMALL

Thermal

Limit

BIAS

TRACK

EN Hysteresis

andDe-Glitch

Current

Limit

UVLO

0.8V

Reference

0.9 V´REF

GND

V <V =1,V >V =0

TRACK REF TRACK REF

VOUT

SNS

TPS743xx

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SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

BLOCK DIAGRAMS

Figure 3. Adjustable Voltage Version

Figure 4. Fixed Voltage Versions

TPS743xx

SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

www.ti.com

Table 1. Standard 1% Resistor Values for Programming the Output Voltage(1)

R1(kΩ) R2(kΩ) VOUT (V)

Short Open 0.8

0.619 4.99 0.9

1.13 4.53 1.0

1.37 4.42 1.05

1.87 4.99 1.1

2.49 4.99 1.2

4.12 4.75 1.5

3.57 2.87 1.8

3.57 1.69 2.5

3.57 1.15 3.3

(1) VOUT = 0.8 × (1 + R1/R2)

OUT

GND BIAS

FB/

SNS

1 2 3 4 56

BIAS

OUT

FB/SNS

TPS743xx

EN 11

GND 12

NC 13

NC 14

SS 15

NC4

NC3

NC2

OUT1

GND

TPS743xx

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SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

PIN CONFIGURATIONS

RGW PACKAGE KTW PACKAGE

5 × 5 QFN-20 DDPAK-7

(TOP VIEW) SURFACE-MOUNT

PIN DESCRIPTIONS

NAME KTW (DDPAK) RGW (QFN) DESCRIPTION

IN 5 5–8 Unregulated input to the device.

Enable pin. Driving this pin high enables the regulator. Driving this pin low puts

EN 7 11 the regulator into shutdown mode. This pin must not be left floating.

Tracking pin. Connect this pin to the center tap of a resistor divider off of an

TRACK 1 15 external supply to program the device to track an external supply.

BIAS 6 10 Bias input voltage for error amplifier, reference, and internal control circuits.

Power-Good (PG) is an open-drain, active-high output that indicates the status

of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a

high-impedance state. When VOUT is below this threshold the pin is driven to a

PG N/A 9 low-impedance state. A pull-up resistor from 10kΩto 1MΩshould be connected

from this pin to a supply up to 5.5V. The supply can be higher than the input

voltage. Alternatively, the PG pin can be left floating if output monitoring is not

necessary.

This pin is the feedback connection to the center tap of an external resistor

FB divider network that sets the output voltage. This pin must not be left floating.

(Adjustable version only.)

2 16 This pin is the sense connection to the load device. This pin must be connected

SNS to VOUT and must not be left floating. (Fixed versions only.)

OUT 3 1, 18–20 Regulated output voltage. No capacitor is required on this pin for stability.

No connection. This pin can be left floating or connected to GND to allow better

NC N/A 2–4, 13, 14, 17 thermal contact to the top-side plane.

GND 4 12 Ground

PAD/TAB Should be soldered to the ground plane for increased thermal performance.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

-0.1

010 20 30 40

ChangeinV (%)

OUT

I (mA)

OUT

+125 C°

+25 C°

-40 C°

ReferredtoI =50mA

OUT

0.050

0.025

-0.025

-0.050

-0.075

-0.100

-0.125

-0.150

50 500 1000

ChangeinV (%)

OUT

I (mA)

OUT

1500

+125 C°

+25 C°

- °40 C

ReferredtoI =50mA

OUT

0.05

0.04

0.03

0.02

0.01

-0.01

-0.02

-0.03

-0.04

-0.05

00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

ChangeinV (%)

OUT

V V-

IN OUT (V)

4.5

T = 40- °

TJ=+25°C

TJ=+125°C

100

00.5 1.0

DropoutVoltage(mV)

I (A)

OUT

1.5

+125 C°

+25 C°

- °40 C

200

180

160

140

120

100

0.9 1.4 1.9 2.4 2.9 3.4

DropoutVoltage(mV)

V V-

BIAS OUT (V)

3.9

+125 C°

+25 C°

-40°C

I =1.5A

OUT

0.9 1.4 1.9 2.4 2.9 3.4

DropoutVoltage(mV)

V-

BIAS VOUT (V)

3.9

+125 C°

+25 C°

-40°C

I =500mA

OUT

TPS743xx

SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

www.ti.com

TYPICAL CHARACTERISTICS

At TJ= +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, and COUT = 10mF,

unless otherwise noted. LOAD REGULATION LOAD REGULATION

Figure 5. Figure 6.

VIN DROPOUT VOLTAGE vs

LINE REGULATION IOUT AND TEMPERATURE (TJ)

Figure 7. Figure 8.

VIN DROPOUT VOLTAGE vs VIN DROPOUT VOLTAGE vs

VBIAS – VOUT AND TEMPERATURE (TJ) VBIAS – VOUT AND TEMPERATURE (TJ)

Figure 9. Figure 10.

1400

1300

1200

1100

1000

900

800

700

600

500

50 500 1000

DropoutVoltage(mV)

I (mA)

OUT

1500

+125 C°+25 C°

- °40 C

Power-SupplyRejection(dB)

10 100 1k 10k 100k 1M 10M

Frequency(Hz)

I =1.5A

OUT

100

10 100 1k 10k 100k 1M

Power-SupplyRejectionRatio(dB)

Frequency(Hz)

10M

V =1.8,V =1.5V

IN OUT OUT

,I =1.5A

C =0 F

OUT m

C =10 F

OUT m

C =100 F

OUT m

100

10 100 1k 10k 100k 1M

Power-SupplyRejectionRatio(dB)

Frequency(Hz)

10M

V =1.8,V =1.5V

IN OUT OUT

,I =100mA

C =10 F

OUT m

C =100 F

OUT m

C =0 F

OUT m

00.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25

Power-SupplyRejectionRatio(dB)

V V-

IN OUT (V)

2.50

1kHz

100kHz

300kHz

700kHz

I =1.5A

OUT

0.1

0.01

100 1k 10k

OutputSpectralNoiseDensity(mV/Ö)

Frequency(Hz)

100k

I =1.5A

OUT

V =1.1V

OUT

TPS743xx

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SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

TYPICAL CHARACTERISTICS (continued)

At TJ= +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, and COUT =

10mF, unless otherwise noted.

VBIAS DROPOUT VOLTAGE vs

IOUT AND TEMPERATURE VBIAS PSRR vs FREQUENCY

Figure 11. Figure 12.

VIN PSRR vs FREQUENCY VIN PSRR vs FREQUENCY

Figure 13. Figure 14.

VIN PSRR vs VIN – VOUT NOISE SPECTRAL DENSITY

Figure 15. Figure 16.

2.85

2.65

2.45

2.25

2.05

1.85

1.65

1.45

1.25

00.5 1.0

BiasCurrent(mA)

I (A)

OUT

1.5

+125 C°

+25 C°

- °40 C

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

2.0 2.5 3.0 3.5 4.0 4.5

BiasCurrent(mA)

V (V)

BIAS

5.0

+125 C°

+25 C°

- °40 C

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

-40 -20 0 20 40 60 80 100

BiasCurrent( A)m

JunctionTemperature( C)°

120

V =2.375V

BIAS

V =5.5V

BIAS

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

V Low-LevelPGVoltage(V)

02 4 6 8 10 12

PGCurrent(mA)

20mV/div

1V/div

Time(50 s/div)m

4.3V

C =2x470 F(OSCON)

OUT m

C =100 F(Cer.)

OUT m

C =10 F(Cer.)

OUT m

1V/ sm

3.3V

C =0 F

OUT m

4.3V

10mV/div

500mV/div

Time(50 s/div)m

C =2x470 F(OSCON)

OUT m

C =100 F(Cer.)

OUT m

C =10 F(Cer.)

OUT m

C =0 F

OUT m

2.5V

1.5V

V =1.2V

OUT

1V/ sm

TPS743xx

SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

www.ti.com

TYPICAL CHARACTERISTICS (continued)

At TJ= +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, and COUT =

10mF, unless otherwise noted.

IBIAS vs IOUT AND TEMPERATURE IBIAS vs VBIAS AND VOUT

Figure 17. Figure 18.

IBIAS SHUTDOWN vs TEMPERATURE LOW-LEVEL PG VOLTAGE vs PG CURRENT

Figure 19. Figure 20.

VBIAS LINE TRANSIENT VIN LINE TRANSIENT (1.5A)

Figure 21. Figure 22.

50mV/div

1A/div

Time(50 s/div)m

50mA

C =2x470 F(OSCON)

OUT m

C =100 F(Cer.)

OUT m

C =10 F(Cer.)

OUT m

1A/ sm

C =0 F

OUT m

1.5A

500mV/div

Time(20ms/div)

VPG

VTRACK

I =500mA

OUT

VOUT

1V/div

Time(20ms/div)

V (500mV/div)

VOUT

V =V

IN BIAS EN

=V

1V/div

Time(50 s/div)m

VOUT

1.1V

VEN

V =V

I =1.5A

TRACK IN

OUT

Time(20 s/div)m

VOUT

50mV/div

IOUT

500mA/div

OutputOpen

OutputShorted

TPS743xx

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SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

TYPICAL CHARACTERISTICS (continued)

At TJ= +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, and COUT =

10mF, unless otherwise noted.

OUTPUT LOAD TRANSIENT RESPONSE TRACKING RESPONSE

Figure 23. Figure 24.

POWER-UP/POWER-DOWN TURN-ON RESPONSE–QFN PACKAGE

Figure 25. Figure 26.

OUTPUT SHORT-CIRCUIT RECOVERY

Figure 27.

VOUT

COUT

Optional

OUT

SNS

BIAS

TRACK

GND

VIN

VBIAS

CIN

CBIAS

VTRACK

VPG

TPS743xx

VOUT

COUT

Optional

OUT

BIAS

TRACK

GND

VIN

VBIAS

CIN

CBIAS

VTRACK

VPG

TPS74301

V =0.8

OUT ´1+ R1

()

TPS743xx

SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

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APPLICATION INFORMATION

The TPS743xx belongs to a family of new generation R1and R2can be calculated for any output voltage

ultra-low dropout regulators that feature soft-start and using the formula shown in Figure 28. Refer to

tracking capabilities. These regulators use a low Table 1 for sample resistor values of common output

current bias input to power all internal control voltages. In order to achieve the maximum accuracy

circuitry, allowing the NMOS pass transistor to specifications, R2should be ≤4.99kΩ.

regulate very low input and output voltages. FIXED VOLTAGE AND SENSE PIN

The use of an NMOS-pass FET offers several critical

advantages for many applications. Unlike a PMOS Figure 29 illustrates a typical application circuit for the

topology device, the output capacitor has little effect TPS743xx fixed output device.

on loop stability. This architecture allows the

TPS743xx to be stable with any or even no output

capacitor. Transient response is also superior to

PMOS topologies, particularly for low VIN

applications.

The TPS743xx features a TRACK pin that allows the

output to track an external supply. This feature is

useful in minimizing the stress on ESD structures that

are present between the CORE and I/O power pins of

many processors. A power-good (PG) output is also

available to allow supply monitoring and sequencing

of follow-on supplies. To control the output turn-on, Figure 29. Typical Application Circuit for the

an enable (EN) pin with hysteresis and deglitch is TPS743xx (Fixed Voltage)

provided to allow slow-ramping signals to be utilized

for sequencing the device. The low VIN and VOUT

capability allows for inexpensive, easy-to-design, and A fixed voltage version of the TPS743xx has a sense

efficient linear regulation between the multiple supply pin (SNS) so that the device can monitor its output

voltages often present in processor intensive voltage at the load device pin(s) as closely as

systems. possible. Unlike other TI fixed-voltage LDOs,

however, this pin must not be left floating; it must be

ADJUSTABLE VOLTAGE PART AND connected to an output node. See the TI application

SETTING report, Ultimate Regulation of with Fixed Output

Versions of the TPS742xx, TPS743xx, and TPS744xx

Figure 28 is a typical application circuit for the (literature number SBVA024), available for download

TPS74301 adjustable device. from the TI web site.

INPUT, OUTPUT, AND BIAS CAPACITOR

REQUIREMENTS

The device does not require any output capacitor for

stability. If an output capacitor is needed, the device

is designed to be stable for all available types and

values of output capacitance. The device is also

stable with multiple capacitors in parallel, of any type

or value.

The capacitance required on the IN and BIAS pins is

strongly dependent on the input supply source

impedance. To counteract any inductance in the

input, the minimum recommended capacitor for VIN

and VBIAS is 1mF. If VIN and VBIAS are connected to

the same supply, the recommended minimum

capacitor for VBIAS is 4.7mF. Good quality, low ESR

Figure 28. Typical Application Circuit for the capacitors should be used on the input; ceramic X5R

TPS74301 (Adjustable Version) and X7R capacitors are preferred. These capacitors

should be placed as close the pins as possible for

optimum performance.

Reference

SimplifiedBlock Diagram

VOUT

OUT

BIAS

IN V =5V 5%

BIAS ±

V =1.8V

V =1.5V

I =1.5A

Efficiency=83%

OUT

Reference

SimplifiedBlock Diagram

BIAS

VIN

V =3.3V 5%

BIAS ±

V =3.3V 5%

V =1.5V

I =1.5A

Efficiency=45%

OUT

VOUT

OUT

TPS743xx

www.ti.com

SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

TRANSIENT RESPONSE

The TPS743xx was designed to have transient

response within 5% for most applications without any

output capacitor. In some cases, the transient

response may be limited by the transient response of

the input supply. This limitation is especially true in

applications where the difference between the input

and output is less than 300mV. In this case, adding

additional input capacitance improves the transient

response much more than just adding additional

output capacitance would do. With a solid input

supply, adding additional output capacitance reduces

undershoot and overshoot during a transient at the

expense of a slightly longer VOUT recovery time. Refer

to Figure 23 in the Typical Characteristics section. Figure 30. Typical Application of the TPS743xx

Since the TPS743xx is stable without an output Using an Auxiliary Bias Rail

capacitor, many applications may allow for little or no

capacitance at the LDO output. For these The second specification (shown in Figure 31),

applications, local bypass capacitance for the device referred to as VBIAS Dropout, is for users who wish to

under power may be sufficient to meet the transient tie IN and BIAS together. This option allows the

requirements of the application. This design reduces device to be used in applications where an auxiliary

the total solution cost by avoiding the need to use bias voltage is unavailable or low dropout is not

expensive high-value capacitors at the LDO output. required. Dropout is limited by BIAS in these

applications because VBIAS provides the gate drive to

DROPOUT VOLTAGE the pass FET, and therefore must be 1.4V above

VOUT. Because of this usage, IN and BIAS tied

The TPS743xx offers industry-leading dropout together easily consume huge power. Pay attention

performance, making it well-suited for high-current not to exceed the power rating of the IC package.

low VIN/low VOUT applications. The extremely low

dropout of the TPS743xx allows the device to be

used instead of a DC/DC converter and still achieve

good efficiencies. This efficiency allows users to

rethink the power architecture for their applications to

find the smallest, simplest, and lowest cost solution.

There are two different specifications for dropout

voltage with the TPS743xx. The first specification (as

shown in Figure 30) is referred to as VIN Dropout and

is for users wishing to apply an external bias voltage

to achieve low dropout. This specification assumes

that VBIAS is at least 1.62V above VOUT, which is the

case for VBIAS when powered by a 3.3V rail with 5%

tolerance and with VOUT = 1.5V. If VBIAS is higher than

3.3V × 0.95 or VOUT is less than 1.5V, VIN dropout is

less than specified.

Figure 31. Typical Application of the TPS743xx

Without an Auxiliary Bias

BIAS

OUT

TPS74201LDO1(1) DSP

I/O

CORE

BIAS

OUT

TRACK

TPS74301LDO2(1)

32.4kW

10kW

5V 3.3V

1.2V

NOTES:(1)CapacitorsonIN,BIAS,andOUTalongwiththeresistors

necessarytosettheoutputvoltagehavebeenomittedforsimplification.

(2)LowestvalueforV andhighestvalueforR shouldbeused

inthiscalculation.R mustbethecloseststandardvaluebelowthe

calculatedvalueforproperratiometricsequencing.

CORE 2

I/O

T mei

C REO

VOUT

SIMU TL A E USSEQUENCINGN O

RATIOMETRICSEQUENCING (2)

C REO

I/O

xR2

V CC IO -0.808

R1=0.808

xR2

V CC CORE -0.8

R1=0.8

TPS743xx

SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

www.ti.com

PROGRAMMABLE SEQUENCING WITH The maximum recommended value for R2is 100kΩ.

TRACK Once R2is selected, R1is calculated using one of the

equations given in Figure 32.

The TPS743xx features a track pin that allows the

output to track an external supply at start-up. While SEQUENCING REQUIREMENTS

the TRACK input is below 0.8V, the error amplifier

regulates the FB pin to the TRACK input. Properly The device can have VIN, VBIAS, VEN, and VTRACK

choosing the resistor divider network (R1and R2) as sequenced in any order without causing damage to

shown in Figure 32 enables the regulator output to the device. However, for the track function to work as

track the external supply to obtain a simultaneous or intended, certain sequencing rules must be applied.

ratiometric start-up. Once the TRACK input reaches VBIAS must be present and the device enabled before

0.8V, the error amplifier regulates the FB pin to the the track signal starts to ramp. VIN should ramp up

0.8V internal reference. Further increases to the faster than the external supply being tracked so that

TRACK input have no effect. the tracking signal will not drive the device into VIN

dropout as VOUT ramps up. The preferred method to

sequence the tracking device is to have VIN, VBIAS,

and VEN above the minimum required voltages before

enabling the master supply to initiate the startup

sequence. This method is illustrated in Figure 32.

Resistors R3and R4disable the master supply until

the input voltage is above 3.52V (typical).

If the TRACK pin is not needed it should be

connected to VIN. Configured in this way, the device

starts up typically within 40ms, which may result in

large inrush current that could cause the input supply

to droop. If soft-start is needed, consider the

TPS742xx or TPS744xx devices.

NOTE: When VBIAS and VEN are present and VIN is

not supplied, this device outputs approximately 50mA

of current from OUT. Although this condition will not

cause any damage to the device, the output current

may charge up the OUT node if total resistance

between OUT and GND (including external feedback

resistors) is greater than 10kΩ.

Figure 32. Various Sequencing Methods Using

the TRACK Pin

TPS743xx

www.ti.com

SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

ENABLE/SHUTDOWN current during a short-circuit fault. Recovery from a

short-circuit condition is well-controlled and results in

The enable (EN) pin is active high and is compatible very little output overshoot when the load is removed.

with standard digital signaling levels. VEN below 0.4V See Figure 27 in the Typical Characteristics section

turns the regulator off, while VEN above 1.1V turns the for output short-circuit recovery performance.

regulator on. Unlike many regulators, the enable

circuitry has hysteresis and deglitching for use with The internal current limit protection circuitry of the

relatively slow-ramping analog signals. This TPS743xx is designed to protect against overload

configuration allows the TPS743xx to be enabled by conditions. It is not intended to allow operation above

connecting the output of another supply to the EN the rated current of the device. Continuously running

pin. The enable circuitry typically has 50mV of the TPS743xx above the rated current degrades

hysteresis and a deglitch circuit to help avoid on-off device reliability.

cycling because of small glitches in the VEN signal. THERMAL PROTECTION

The enable threshold is typically 0.8V and varies with

temperature and process variations. Temperature Thermal protection disables the output when the

variation is approximately –1mV/°C; therefore, junction temperature rises to approximately +155°C,

process variation accounts for most of the variation in allowing the device to cool. When the junction

the enable threshold. If precise turn-on timing is temperature cools to approximately +140°C, the

required, a fast rise-time signal should be used to output circuitry is enabled. Depending on power

enable the TPS743xx. dissipation, thermal resistance, and ambient

temperature the thermal protection circuit may cycle

If not used, EN can be connected to either IN or on and off. This cycling limits the dissipation of the

BIAS. If EN is connected to IN, it should be regulator, protecting it from damage as a result of

connected as close as possible to the largest overheating.

capacitance on the input to prevent voltage droops on

that line from triggering the enable circuit. Activation of the thermal protection circuit indicates

excessive power dissipation or inadequate

POWER-GOOD (QFN Package Only) heatsinking. For reliable operation, junction

temperature should be limited to +125°C maximum.

The power-good (PG) pin is an open-drain output and To estimate the margin of safety in a complete design

can be connected to any 5.5V or lower rail through an (including heatsink), increase the ambient

external pull-up resistor. This pin requires at least temperature until thermal protection is triggered; use

1.1V on VBIAS in order to have a valid output. The PG worst-case loads and signal conditions. For good

output is high-impedance when VOUT is greater than reliability, thermal protection should trigger at least

VIT + VHYS. If VOUT drops below VIT or if VBIAS drops +30°C above the maximum expected ambient

below 1.9V, the open-drain output turns on and pulls condition of the application. This condition produces a

the PG output low. The PG pin also asserts when the worst-case junction temperature of +125°C at the

device is disabled. The recommended operating highest expected ambient temperature and

condition of PG pin sink current is up to 1mA, so the worst-case load.

pull-up resistor for PG should be in the range of 10kΩ

to 1MΩ. PG is only provided on the QFN package. If The internal protection circuitry of the TPS743xx is

output voltage monitoring is not needed, the PG pin designed to protect against overload conditions. It is

can be left floating. not intended to replace proper heatsinking.

Continuously running the TPS743xx into thermal

shutdown degrades device reliability.

INTERNAL CURRENT LIMIT

The TPS743xx features a factory-trimmed, accurate

current limit that is flat over temperature and supply

voltage. The current limit allows the device to supply

surges of up to 1.8A and maintain regulation. The

current limit responds in about 10ms to reduce the

RqJA +()125OC*TA)

PD+ǒVIN *VOUTǓ IOUT

120

100

qJA ( C/W)

0 1 2 3 4 5 678 9 10

BoardCopperArea(in )

qJA (KTW)

qJA (RGW)

TPS743xx

SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

www.ti.com

LAYOUT RECOMMENDATIONS AND POWER The maximum junction-to-ambient thermal resistance

DISSIPATION depends on the maximum ambient temperature,

maximum device junction temperature, and power

An optimal layout can greatly improve transient dissipation of the device and can be calculated using

performance, PSRR, and noise. To minimize the Equation 2:

voltage droop on the input of the device during load

transients, the capacitance on IN and BIAS should be

connected as close as possible to the device. This (2)

capacitance also minimizes the effects of parasitic white space

inductance and resistance of the input source and

can therefore improve stability. To achieve optimal Knowing the maximum RqJA, the minimum amount of

transient performance and accuracy, the top side of PCB copper area needed for appropriate heatsinking

R1in Figure 28 should be connected as close as can be estimated using Figure 33.

possible to the load. If BIAS is connected to IN, it is

recommended to connect BIAS as close to the sense

point of the input supply as possible. This connection

minimizes the voltage droop on BIAS during transient

conditions and can improve the turn-on response.

Knowing the device power dissipation and proper

sizing of the thermal plane that is connected to the

tab or pad is critical to avoiding thermal shutdown

and ensuring reliable operation. Power dissipation of

the device depends on input voltage and load

conditions, and can be calculated using Equation 1:

(1)

Power dissipation can be minimized and greater

efficiency can be achieved by using the lowest

possible input voltage necessary to achieve the

required output voltage regulation. Note: qJA value at board size of 9in2(that is, 3in ×

3in) is a JEDEC standard.

On the QFN (RGW) package, the primary conduction Figure 33. qJA vs Board Size

path for heat is through the exposed pad to the

printed circuit board (PCB). The pad can be

connected to ground or be left floating; however, it Figure 33 shows the variation of qJA as a function of

should be attached to an appropriate amount of ground plane copper area in the board. It is intended

copper PCB area to ensure the device will not only as a guideline to demonstrate the effects of heat

overheat. On the DDPAK (KTW) package, the spreading in the ground plane and should not be

primary conduction path for heat is through the tab to used to estimate actual thermal performance in real

the PCB. That tab should be connected to ground. application environments.

NOTE: When the device is mounted on an

application PCB, it is strongly recommended to use

ΨJT and ΨJB, as explained in the Estimating Junction

Temperature section.

Y Y

JT J T JT D

:T =T + P·

Y Y

JB J B JB D

:T =T + P·

T on PCB

BT on of ICtop

1mm

(a) Example RGW (QFN) Package Measurement (b) Example KTW (DDPAK) Package Measurement

1mm

T on of IC

Ttop (1)

T on PCB

surface

(2)

TPS743xx

www.ti.com

SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

ESTIMATING JUNCTION TEMPERATURE Where PDis the power dissipation shown by

Equation 1, TTis the temperature at the center-top of

Using the thermal metrics ΨJT and ΨJB, shown in the the IC package, and TBis the PCB temperature

Thermal Information table, the junction temperature measured 1mm away from the IC package on the

can be estimated with corresponding formulas (given PCB surface (as Figure 34 shows).

in Equation 3). For backwards compatibility, an older

qJC,Top parameter is listed as well. NOTE: Both TTand TBcan be measured on actual

application boards using a thermo-gun (an infrared

thermometer).

For more information about measuring TTand TB, see

the application note Using New Thermal Metrics

(3) (SBVA025), available for download at www.ti.com.

(1) TTis measured at the center of both the X- and Y-dimensional axes.

(2) TBis measured below the package lead on the PCB surface.

Figure 34. Measuring Points for TTand TB

Y Yand ( C/W)

JT JB °

0 2 46 8 10

BoardCopperArea(in )

YJT (KTW)

YJT (RGW)

YJB (RGW)

YJB (KTW)

TPS743xx

SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

www.ti.com

Compared with qJA, the thermal metrics ΨJT and ΨJB

are less independent of board size, but they do have

a small dependency. Figure 35 shows characteristic

performance of ΨJT and ΨJB versus board size.

Looking at Figure 35, the RGW package thermal

performance has negligible dependency on board

size. The KTW package, however, does have a

measurable dependency on board size. This

dependency exists because the package shape is not

point-symmetric to an IC center. In the KTW package,

for example (see Figure 34), silicon is not beneath

the measuring point of TTwhich is the center of the X

and Y dimension, so that ΨJT has a dependency.

Also, because of that non-point-symmetry, device

heat distribution on the PCB is not point-symmetric,

either, so that ΨJB has a dependency. Figure 35. ΨJT and ΨJB vs Board Size

space For a more detailed discussion of why TI does not

recommend using qJC,Top to determine thermal

characteristics, refer to the application note Using

New Thermal Metrics (SBVA025), available for

download at www.ti.com. Also, refer to the application

note IC Package Thermal Metrics (SPRA953) (also

available on the TI web site) for further information.

TPS743xx

www.ti.com

SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision J (December, 2009) to Revision K Page

• Replaced the Dissipation Ratings table with the Thermal Information table ........................................................................ 3

• Revised Layout Recommendations and Power Dissipation section ................................................................................... 16

• Revised Estimating Junction Temperature section ............................................................................................................. 17

Changes from Revision I (August, 2009) to Revision J Page

• Changed last sentence of Layout Recommendations and Power Dissipation section; added Figure 33 .......................... 16

• Added Estimating Junction Temperature section ............................................................................................................... 17

• Deleted (previously numbered) Figure 33 through Figure 37 ............................................................................................. 18

PACKAGE OPTION ADDENDUM

www.ti.com 7-Aug-2010

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TPS74301KTWR ACTIVE DDPAK KTW 7 500 Green (RoHS

& no Sb/Br) CU SN Level-3-245C-168 HR

TPS74301KTWRG3 ACTIVE DDPAK KTW 7 500 Green (RoHS

& no Sb/Br) CU SN Level-3-245C-168 HR

TPS74301KTWT ACTIVE DDPAK KTW 7 50 Green (RoHS

& no Sb/Br) CU SN Level-3-245C-168 HR

TPS74301KTWTG3 ACTIVE DDPAK KTW 7 50 Green (RoHS

& no Sb/Br) CU SN Level-3-245C-168 HR

TPS74301RGWR ACTIVE VQFN RGW 20 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TPS74301RGWRG4 ACTIVE VQFN RGW 20 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TPS74301RGWT ACTIVE VQFN RGW 20 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TPS74301RGWTG4 ACTIVE VQFN RGW 20 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

PACKAGE OPTION ADDENDUM

www.ti.com 7-Aug-2010

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS74301KTWR DDPAK KTW 7 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2

TPS74301KTWT DDPAK KTW 7 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2

TPS74301RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

TPS74301RGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS74301KTWR DDPAK KTW 7 500 367.0 367.0 45.0

TPS74301KTWT DDPAK KTW 7 50 367.0 367.0 45.0

TPS74301RGWR VQFN RGW 20 3000 367.0 367.0 35.0

TPS74301RGWT VQFN RGW 20 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

MECHANICAL DATA

MPSF015 – AUGUST 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT

0.010 (0,25) AM

4201284/A 08/01

0.385 (9,78)

0.410 (10,41)

–A– 0.006

–B–

0.170 (4,32)

0.183 (4,65)

0.000 (0,00)

0.012 (0,305)

0.104 (2,64)

0.096 (2,44)

0.034 (0,86)

0.022 (0,57)

0.050 (1,27)

0.055 (1,40)

0.045 (1,14)

0.014 (0,36)

0.026 (0,66)

0.330 (8,38)

0.370 (9,40)

0.297 (7,54)

0.303 (7,70)

0.0585 (1,485)

0.0625 (1,587)

0.595 (15,1 1)

0.605 (15,37)

0.019 (0,48)

0.017 (0,43)

0°~3°

0.179 (4,55)

0.187 (4,75)

0.056 (1,42)

0.064 (1,63)

0.296 (7,52)

0.304 (7,72)

0.300 (7,62)

0.252 (6,40)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Lead width and height dimensions apply to the

plated lead.

D. Leads are not allowed above the Datum B.

E. Stand–off height is measured from lead tip

with reference to Datum B.

F. Lead width dimension does not include dambar

protrusion. Allowable dambar protrusion shall not

cause the lead width to exceed the maximum

dimension by more than 0.003”.

G. Cross–hatch indicates exposed metal surface.

H. Falls within JEDEC MO–169 with the exception

of the dimensions indicated.

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anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

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regulatory requirements in connection with such use.

TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

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