Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V,
Single-Supply TTL/CMOS Comparator
ADCMP609
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007–2008 Analog Devices, Inc. All rights reserved.
FEATURES
Fully specified rail-to-rail at VCC = 2.5 V to 5.5 V
Input common-mode voltage from −0.2 V to VCC + 0.2 V
Low glitch TTL-/CMOS-compatible output stage
40 ns propagation delay
Low power 1 mW at 2.5 V
Shutdown pin
Programmable hysteresis
Power supply rejection > 60 dB
−40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
FUNCTIONAL BLOCK DIAGRAM
06918-001
ADCMP609
NONINVERTING
INPUT
INVERTING
INPUT
Q OUTPUT
+
–
S
DN
Figure 1.
GENERAL DESCRIPTION
The ADCMP609 is a fast comparator fabricated on XFCB2, an
Analog Devices, Inc., proprietary process. These comparators
are exceptionally versatile and easy to use. Features include an
input range from VEE − 0.2 V to VCC + 0.2 V, low noise, TTL-
/CMOS-compatible output drivers, and adjustable hysteresis
and/or shutdown inputs.
The device offers 40 ns propagation delay driving a 15 pF load
with 10 mV overdrive on 500 μA typical supply current.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a −0.2 V to +3.0 V
input signal range up to a +5.5 V positive supply with a −0.2 V
to +5.7 V input signal range.
The TTL-/CMOS-compatible output stage is designed to drive
up to 15 pF with full rated timing specifications and to degrade
in a graceful and linear fashion as additional capacitance is added.
The input stage of the comparator offers robust protection against
large input overdrive, and the outputs do not phase reverse when
the valid input signal range is exceeded. A programmable hysteresis
feature is also provided.
The ADCMP609, available in an 8-lead MSOP package, features
a shutdown pin and hysteresis control.
ADCMP609
Rev. A | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applicat ions ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ............................................. 6
Applications Information .................................................................8
Power/Ground Layout and Bypassing ........................................8
TTL-/CMOS-Compatible Output Stage ....................................8
Optimizing Performance ..............................................................8
Comparator Propagation Delay Dispersion ..................................8
Comparator Hysteresis .................................................................9
Crossover Bias Point .....................................................................9
Minimum Input Slew Rate Requirement ................................ 10
Typical Applications Circuits ........................................................ 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
8/08—Rev. 0 to Rev. A
Changes to Table 4 ............................................................................ 5
Changes to Ordering Guide .......................................................... 12
7/07—Revision 0: Initial Version
ADCMP609
Rev. A | Page 3 of 12
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCC = 2.5 V, TA = −40°C to +125°C; typical value is TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DC INPUT CHARACTERISTICS
Voltage Range VP, VN V
CC = 2.5 V to 5.5 V −0.2 VCC + 0.2 V V
Common-Mode Range VCC = 2.5 V to 5.5 V −0.2 VCC + 0.2 V V
Differential Voltage VCC = 2.5 V to 5.5 V VCC V
Offset Voltage VOS −5.0 ±3 +5.0 mV
Bias Current IP, IN −0.4 +0.4 µA
Offset Current −1.0 +1.0 µA
Capacitance CP, CN 1 pF
Resistance, Differential Mode −0.5 V to VCC + 0.5 V 200 7000 kΩ
Resistance, Common Mode −0.5 V to VCC + 0.5 V 100 4000 kΩ
Active Gain AV 80 dB
Common-Mode Rejection Ratio CMRR VCC = 2.5 V 50 dB
V
CM = −0.2 V to +2.7 V
V
CC = 5.5 V 50 dB
Hysteresis RHYS = ∞ 0.1 mV
HYSTERESIS MODE AND TIMING
Hysteresis Mode Bias Voltage Current − 1 A 1.145 1.25 1.35 V
Minimum Resistor Value Hysteresis = 120 mV 30 120 kΩ
SHUTDOWN PIN CHARACTERISTICS1
VIH Comparator is operating 2.0 VCC V
VIL Shutdown guaranteed −0.2 +0.4 +0.4 V
IIH V
IH = VCC −6 +6 µA
Sleep Time tSD l
CC < 100 µA 300 ns
Wake-Up Time tH V
PP = 10 mV, output valid 150 ns
DC OUTPUT CHARACTERISTICS VCC = 2.5 V to 5.5 V
Output Voltage High Level VOH I
OH = 0.8 mA, VCC = 2.5 V VCC − 0.4 V
Output Voltage Low Level VOL IOL = 0.8 mA, VCC = 2.5 V 0.4 V
AC PERFORMANCE2 V
CC = 2.5 V to 5.5 V
Rise Time/Fall Time tR/tF 10% to 90%, VCC = 2.5 V 25 to 50 ns
10% to 90%, VCC = 5.5 V 45 to 75 ns
Propagation Delay tPD V
OD = 10 mV, VCC = 2.5 V 30 to 50 ns
V
OD = 50 mV, VCC = 5.5 V 35 to 60 ns
Propagation Delay Skew, Rising to Falling Transition VCC = 2.5 V 4.5 ns
VCC = 5.5 V 8 ns
Propagation Delay Skew, Q to Q VCC = 2.5 V 3 ns
VCC = 5.5 V 4 ns
Overdrive Dispersion 10 mV < VOD < 125 mV 12 ns
Common-Mode Dispersion −0.2 V < VCM < VCC + 0.2 V 1.5 ns
POWER SUPPLY
Supply Voltage Range VCC 2.5 5.5 V
Positive Supply Current IVCC V
CC = 2.5 V 550 650 A
V
CC = 5.5 V 800 1100 A
Power Dissipation PD VCC = 2.5 V 1.4 1.7 mW
V
CC = 5.5 V 4.5 7 mW
Power Supply Rejection Ratio PSRR VCC = 2.5 V to 5.5 V −50 dB
Shutdown Current ISD V
CC = 2.5 V to 5.5 V 150 260 A
1 The output is a high impedance mode when the device is in shutdown mode. Note that this feature is to be used with care since the enable/disable time is much
longer than with a true tristate output.
2 VIN = 100 mV square input at 1 MHz, VCM = 0 V, CL = 15 pF, VCCI = 2.5 V, unless otherwise noted.
ADCMP609
Rev. A | Page 4 of 12
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltages
Supply Voltage (VCC to Ground) −0.5 V to +6.0 V
Supply Differential −6.0 V to +6.0 V
Input Voltages
Input Voltage −0.5 V to VCC + 0.5 V
Differential Input Voltage ±(VCC + 0.5 V)
Maximum Input/Output Current ±50 mA
Shutdown Pin
Applied Voltage (SDN to Ground) −0.5 V to VCC + 0.5 V
Maximum Input/Output Current ±50 mA
Hysteresis Control Pin
Applied Voltage (HYS to Ground) −0.5 V to VCC + 0.5 V
Maximum Input/Output Current ±50 mA
Output Current ±50 mA
Operating Temperature
Ambient Temperature Range −40°C to +125°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3.
Package Type θJA1 Unit
ADCMP609 8-Lead MSOP 130 °C/W
1 Measurement in still air.
ESD CAUTION
ADCMP609
Rev. A | Page 5 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADCMP609
TOP VIEW
(Not to Scale)
VCC 1Q8
VP2Q
7
VN3VEE
6
SDN 4HYS
5
06918-002
Figure 2. ADCMP609 Pin Configuration
Table 4. ADCMP609 Pin Function Descriptions
Pin No. Mnemonic Description
1 VCC V
CC Supply.
2 VP Noninverting Analog Input.
3 VN Inverting Analog Input.
4 SDN Shutdown. Drive this pin low to shut down the device.
5 HYS Hysteresis Control. Bias with resistor or current source for hysteresis.
6 VEE Negative Supply Voltage.
7 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input (VP) is greater than the
analog voltage at the inverting input (VN), provided the comparator is in compare mode.
8 QInverting Output. Q is at logic low if the analog voltage at the noninverting input (VP) is greater than the analog
voltage at the inverting input (VN), provided the comparator is in compare mode.
ADCMP609
Rev. A | Page 6 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 2.5 V, TA = 25°C, unless otherwise noted.
06918-003
76543210–1
HYSPINVOLTAGE(V)
400
300
200
100
0
–100
–200
–300
–400
CU
R
R
ENT (µA)
V
CC
= 2.5V V
CC
= 5.5V
Figure 3. HYS Pin Current (μA) vs. Voltage (V)
06918-004
3.53.02.52.01.51.00.50–0.5–1.0
5
4
3
2
1
0
–1
–2
–3
–4
–5
+125°C
–40°C
+25°C
V
CM
AT V
CC
(2.5V)
I
B
(µA)
Figure 4. Input Bias Current vs. Input Common-Mode Voltage (V)
150100500
OD (mV)
60
55
50
45
40
35
30
25
20
PROPAGATION DELAY (ns)
V
CC
= 5.5V
FALL DELAY
V
CC
= 2.5V
RISE DELAY
V
CC
= 5.5V
RISE DELAY
V
CC
= 2.5V
FALL DELAY
06918-005
Figure 5. Propagation Delay vs. Input Overdrive at VCC = 2.5 V and 5.5 V
06918-006
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
HYSTERESIS (
m
V)
13001200110010009008007006005004003002001000
HYS RESISTOR (k)
V
CC
= 5.5
V
CC
= 2.5
Figure 6. Hysteresis vs. HYS Resistor
06918-007
4.0–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
1.5
1.0
0.5
0
–0.5
–1.0
LOAD CU
R
R
ENT (
m
A)
SINK
SOURCE
VOUT (V)
Figure 7. Load Current vs. VOH/VOL
06918-008
0.5 1.0 1.5 2.0 2.5 3.0
38.0
37.8
37.6
37.4
37.2
37.0
36.8
36.6
36.4
36.2
36.0
PROPAGATION DELAY (ns)
V
CM
AT V
CC
(2.5V)
PROPAGATION DELAY RISE
PROPAGATION DELAY FALL
Figure 8. Propagation Delay vs. Input Common-Mode Voltage (V)
ADCMP609
Rev. A | Page 7 of 12
06918-009
Q
Q
10ns/DIV0.5V/DIV
Figure 9. 1 MHz Output Voltage Waveform at VCC = 2.5 V
06918-010
Q
Q
10ns/DIV1V/DIV
Figure 10. 1 MHz Output Voltage Waveform at VCC = 5.5 V
ADCMP609
Rev. A | Page 8 of 12
APPLICATIONS INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP609 comparator is a high speed device. Despite the
low noise output stage, it is essential to use proper high speed
design techniques to achieve the specified performance. Because
comparators are uncompensated amplifiers, feedback in any
phase relationship is likely to cause oscillations or undesired
hysteresis. Of critical importance is the use of low impedance
supply planes, particularly the output supply plane (VCC) and
the ground plane. Individual supply planes are recommended as
part of a multilayer board. Providing the lowest inductance return
path for switching currents ensures the best possible performance
in the target application.
It is also important to adequately bypass the input and output
supplies. Place a 0.1 μF bypass capacitor as close as possible to
each VCC supply pin. The capacitor should be connected to the
ground plane with redundant vias placed to provide a physically
short return path for output currents flowing back from ground
to the VCC pin. Carefully select high frequency bypass capacitors
for minimum inductance and effective series resistance (ESR).
Parasitic layout inductance should also be strictly controlled to
maximize the effectiveness of the bypass at high frequencies.
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
To achieve specified propagation delay performance, keep the
capacitive load at or below the specified minimums. The
outputs of the ADCMP609 are designed to directly drive one
Schottky TTL or three low power Schottky TTL loads (or an
equivalent). For large fan outputs, buses, or transmission lines,
use an appropriate buffer to maintain the excellent speed and
stability of the comparator.
With the rated 15 pF load capacitance applied, more than half
of the total device propagation delay is output stage slew time.
Because of this, the total propagation delay decreases as VCC
decreases, and instability in the power supply may appear as
excess delay dispersion.
Delay is measured to the 50% point for whatever supply is in
use; therefore, the fastest times are observed with the VCC supply at
2.5 V, and larger values are observed when driving loads that
switch at other levels.
Overdrive and input slew rate dispersions are not significantly
affected by output loading and VCC variations.
The TTL-/CMOS-compatible output stage is shown in the
simplified schematic diagram (Figure 11). Because of its inherent
symmetry and generally good behavior, this output stage is readily
adaptable for driving various filters and other unusual loads.
OUTPUT
Q2
Q1
+IN
–IN
OUTPUT STAGE
V
LOGIC
GAIN STAGE
A2
A1
A
V
06918-011
Figure 11. Simplified Schematic Diagram of
TTL-/CMOS-Compatible Output Stage
OPTIMIZING PERFORMANCE
As with any high speed comparator, proper design and layout tech-
niques are essential for obtaining the specified performance. Stray
capacitance, inductance, common power and ground impedances,
or other layout issues can severely limit performance and often
cause oscillation. The source impedance should be minimized as
much as is practicable. High source impedance, in combination
with the parasitic input capacitance of the comparator, causes an
undesirable degradation in bandwidth at the input, therefore
degrading the overall response. Higher impedances encourage
undesired coupling.
COMPARATOR PROPAGATION DELAY DISPERSION
The ADCMP609 comparator is designed to reduce propagation
delay dispersion over a wide input overdrive range of 10 mV to
VCC − 1 V. Propagation delay dispersion is the variation in propa-
gation delay that results from a change in the degree of overdrive
or slew rate, which is how far or how fast the input signal
exceeds the switching threshold.
Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications, such as data
communication, automatic test and measurement, and instru-
mentation. It is also important in event-driven applications, such as
pulse spectroscopy, nuclear instrumentation, and medical imaging.
Dispersion is the variation in propagation delay as the input over-
drive conditions are changed (see Figure 12 and Figure 13).
ADCMP609 dispersion is typically <12 ns as the overdrive varies
from 10 mV to 125 mV. This specification applies to both positive
and negative signals because the device has very closely matched
delays for both positive-going and negative-going inputs, and very
low output skews. Note that for repeatable dispersion measure-
ments the actual device offset is added to the overdrive.
ADCMP609
Rev. A | Page 9 of 12
Q/Q OUTPUT
INPUT VOLTAGE
500mV OVERDRIVE
10mV OVERDRIVE
DISPERSION
V
N
± V
OS
06918-012
Figure 12. Propagation Delay—Overdrive Dispersion
Q/Q OUTPUT
INPUT VOLTAGE
10V/ns
1V/ns
DISPERSION
V
N
± V
OS
06918-013
Figure 13. Propagation Delay—Slew Rate Dispersion
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a
noisy environment, or when the differential input amplitudes
are relatively small or slow moving. The transfer function for a
comparator with hysteresis is shown in Figure 14. As the input
voltage approaches the threshold (0.0 V, in Figure 14) from below
the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +VH/2. The
new switching threshold becomes −VH/2. The comparator remains
in the high state until the threshold, −VH/2, is crossed from below
the threshold region in a negative direction. In this manner, noise
or feedback output signals centered on 0.0 V input cannot cause
the comparator to switch states unless it exceeds the region
bounded by ±VH/2.
OUTPUT
INPUT
0.0V
V
OL
V
OH
+V
H
2
–V
H
2
0
6918-014
Figure 14. Comparator Hysteresis Transfer Function
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. One limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance and can even
induce oscillation in some cases.
The ADCMP609 comparator offers a programmable hysteresis
feature that significantly improves accuracy and stability.
Connecting an external pull-down resistor or a current source
from the HYS pin to ground varies the amount of hysteresis in a
predictable, stable manner. Leaving the HYS pin disconnected
or driving it high removes the hysteresis. The maximum
hysteresis that can be applied using this pin is approximately
160 mV. Figure 15 illustrates the amount of hysteresis applied as
a function of the external resistor value.
06918-006
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
HYSTERESIS (
m
V)
13001200110010009008007006005004003002001000
HYS RESISTOR (k)
V
CC
= 5.5
V
CC
= 2.5
Figure 15. Hysteresis vs. HYS Resistor
The HYS pin appears as a 1.25 V bias voltage seen through a
series resistance of 7 kΩ ± 20% throughout the hysteresis control
range. The advantages of applying hysteresis in this manner are
improved accuracy, improved stability, reduced component
count, and maximum versatility. An external bypass capacitor is
not recommended on the HYS pin because it impairs the latch
function and often degrades the jitter performance of the device.
With the pin driven low, hysteresis may become large, but in this
device, the effect is not reliable or intended as a latch function.
CROSSOVER BIAS POINT
Rail-to-rail inputs of this type, in both op amps and comparators,
have a dual front-end design. Certain devices are active near the
VCC rail, and others are active near the VEE rail. At some predeter-
mined point in the common-mode range, a crossover occurs. At
this point, normally VCC/2, the direction of the bias current reverses
and there are changes in measured offset voltages and currents.
The ADCMP609 slightly elaborates on this scheme. The
crossover points are at approximately 0.8 V and 1.6 V.
ADCMP609
Rev. A | Page 10 of 12
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PCB design
practice (as discussed in the Optimizing Performance section),
these comparators should be stable at any input slew rate with
no hysteresis. Broadband noise from the input stage is observed
in place of the violent chatter seen with most other high speed
comparators. With additional capacitive loading or poor bypassing,
oscillation may be encountered. These oscillations are due to the
high gain bandwidth of the comparator in combination with
feedback through parasitics in the package and PCB. In many
applications, chatter is not harmful.
ADCMP609
Rev. A | Page 11 of 12
TYPICAL APPLICATIONS CIRCUITS
HYS
ADCMP609
5
V
150k150k
CONTROL
VOLTAGE
0V TO 2.5
V
OUTPUT
39k
39k
470pF
20k
06918-016
Figure 16. Voltage-Controlled Oscillator
ADCMP609
OUTPUT
+
–
5
V
0.1µF
10k
10k
INPUT
V
REF
0.02µF
HYS
06918-017
Figure 17. Duty Cycle to Differential Voltage Converter
CMOS
PWM
OUTPUT
ADCMP608
2.5
V
INPUT
1.25V
REF
INPUT
1.25V
±50mV
HYS
ADCMP609
220pF
10k
10k
100k
10k
0
6918-018
Figure 18. Oscillator and Pulse-Width Modulator
ADCMP609
Rev. A | Page 12 of 12
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
8°
0°
4
8
1
5
PIN 1
0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0.95
0.85
0.75
Figure19. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature
Range Package Description
Package
Option Branding
ADCMP609BRMZ1−40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 GW
ADCMP609BRMZ-REEL1
−40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 GW
ADCMP609BRMZ-REEL71
−40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 GW
EVAL-ADCMP609BRMZ1
Evaluation Board
1 Z = RoHS Compliant Part.
©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06918-0-8/08(A)
