MGA-81563 0.1-6 GHz 3 V, 14 dBm Amplifier Data Sheet Description Features Avago's MGA-81563 is an economical, easy-to-use GaAs MMIC amplifier that offers excellent power and low noise figure for applications from 0.1 to 6 GHz. Packaged in an ultra-miniature SOT-363 package, it requires half the board space of a SOT-143 package. x Lead-free Option Available The output of the amplifier is matched to 50 (better than 2.1:1 VSWR) across the entire bandwidth. The input is partially matched to 50 (better than 2.5:1 VSWR) below 4 GHz and fully matched to 50 (better than 2:1 VSWR) above. A simple series inductor can be added to the input to improve the input match below 4 GHz. The amplifier allows a wide dynamic range by offering a 2.7 dB NF coupled with a +27 dBm Output IP3. x 2.8 dB Noise Figure at 2.0 GHz The circuit uses state-of-the-art PHEMT technology with proven reliability. On-chip bias circuitry allows operation from a single +3 V power supply, while resistive feedback ensures stability (K>1) over all frequencies and temperatures. x +14.8 dBm P1dB at 2.0 GHz +17 dBm Psat at 2.0 GHz x Single +3V Supply x 12.4 dB Gain at 2.0 GHz x Ultra-miniature Package x Unconditionally Stable Applications x Buffer or Driver Amp for PCS, PHS, ISM, SATCOM and WLL Applications x High Dynamic Range LNA Simplified Schematic OUTPUT and Vd Surface Mount Package: SOT-363 (SC-70) 6 INPUT 3 BIAS BIAS Pin Connections and Package Marking GND 2 INPUT 3 81x GND 1 OUTPUT 6 and V d GND 1, 2, 4, 5 5 GND 4 GND Note: Package marking provides orientation and identification. "81" = Device Code "x" = Date code character identifies month of manufacture Attention: Observe precautions for handling electrostatic sensitive devices. ESD Human Body Model (Class 0) Refer to Avago Application Note A004R: Electrostatic Discharge Damage and Control. MGA-81563 Absolute Maximum Ratings Units Absolute Maximum[1] Vd Device Voltage, RF Output to Ground V 6.0 Vgd Device Voltage, Gate to Drain V -6.0 Vin Range of RF Input Voltage to Ground V +0.5 to -1.0 Symbol Parameter Pin CW RF Input Power dBm +13 Tch Channel Temperature C 165 TSTG Storage Temperature C -65 to 150 Thermal Resistance [2]: Tch-c = 220C/W Notes: 1. Permanent damage may occur if any of these limits are exceeded. 2. TC = 25C (TC is defined to be the temperature at the package pins where contact is made to the circuit board.) MGA-81563 Electrical Specifications, TC = 25C, ZO = 50 , Vd = 3 V Symbol Parameters and Test Conditions Gtest Gain in test circuit[1] Units f = 2.0 GHz Min. Typ. Max. Std Dev[2] 10.5 12.4 14.5 0.44 2.8 3.8 0.21 NFtest [1] Noise Figure in test circuit f = 2.0 GHz NF50 Noise Figure in 50 system f = 0.5 GHz f = 1.0 GHz f = 2.0 GHz f = 3.0 GHz f = 4.0 GHz f = 6.0 GHz dB 3.1 3.0 2.7 2.7 2.8 3.5 0.21 |S21|2 Gain in 50 system f = 0.5 GHz f = 1.0 GHz f = 2.0 GHz = 3.0 GHz f = 4.0 GHz f = 6.0 GHz dB 12.5 12.5 12.3 11.8 11.4 10.2 0.44 P1 dB Output Power at 1 dB Gain Compression f = 0.5 GHz f = 1.0 GHz f = 2.0 GHz f = 3.0 GHz f = 4.0 GHz f = 6.0 GHz dBm 15.1 14.8 14.8 14.8 14.8 14.7 0.86 IP3 Output Third Order Intercept Point f = 2.0 GHz dBm +27 1.0 VSWRin Input VSWR f = 2.0 GHz 2.7:1 VSWRout Output VSWR f = 2.0 GHz 2.0:1 Id Device Current mA 31 42 51 Notes: 1. Guaranteed specifications are 100% tested in the circuit in Figure 10 in the Applications Information section. 2. Standard deviation number is based on measurement of at least 500 parts from three non-consecutive wafer lots during the initial characterization of this product, and is intended to be used as an estimate for distribution of the typical specification. 2 MGA-81563 Typical Performance, TC = 25 C, Vd = 3 V 16 5 16 4 15 NOISE FIGURE (dB) GAIN (dB) 12 10 8 6 4 TA = +85C TA = +25C TA = -40C 2 P1 dB (dBm) 14 3 2 13 TA = +85C TA = +25C TA = -40C 1 0 14 0 0 1 2 3 4 5 6 TA = +85C TA = +25C TA = -40C 12 11 0 1 2 FREQUENCY (GHz) 3 4 5 6 0 1 Figure 1. Power Gain vs. Frequency and Temperature. Figure 2. Noise Figure vs. Frequency and Temperature. 16 2 3 4 5 6 5 6 FREQUENCY (GHz) FREQUENCY (GHz) Figure 3. Output Power @ 1 dB Gain Compression 5 16 4 15 NOISE FIGURE (dB) 10 8 6 Vd = 2.7V Vd = 3.0V Vd = 3.3V 4 2 3 2 1 2 3 4 5 6 11 0 1 2 FREQUENCY (GHz) 60 3.5 50 DEVICE CURRENT (mA) 4 VSWR (n:1) 3 2.5 Output 2 2 3 4 FREQUENCY (GHz) Figure 7. Input and Output VSWR vs. Frequency. 5 6 0 1 5 6 2 3 4 FREQUENCY (GHz) Figure 6. Output Power @ 1 dB Gain Compression vs. Frequency and Voltage 16 14 Gain 40 30 TA = +85C TA = +25C TA = -40C 20 10 1.5 1 4 Figure 5. Noise Figure vs. Frequency and Voltage. Input 3 3 FREQUENCY (GHz) Figure 4. Power Gain vs. Frequency and Voltage. 0 Vd = 2.7V Vd = 3.0V Vd = 3.3V 12 0 0 1 13 Vd = 2.7V Vd = 3.0V Vd = 3.3V 1 0 14 GAIN and NF (dB) GAIN (dB) 12 P1 dB (dBm) 14 12 10 8 6 4 NF 2 0 0 0 1 2 3 4 DEVICE VOLTAGE (V) Figure 8. Device Current vs. Voltage and Temperature. 5 0 1 2 3 4 5 FREQUENCY (GHz) Figure 9. Minimum Noise Figure and Associated Gain vs. Frequency. 6 MGA-81563 Typical Scattering Parameters[1], TC = 25C, Z O = 50 , Vd = 3 V Freq. S11 S21 S12 K Mag Ang dB Mag Ang dB Mag Ang Mag Ang Factor 0.1 0.2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 0.57 0.52 0.49 0.48 0.47 0.45 0.43 0.39 0.35 0.32 0.28 0.25 0.22 0.20 0.18 0.17 -16 -13 -16 -28 -40 -52 -63 -75 -87 -100 -114 -130 -146 -166 174 150 13.02 12.58 12.35 12.18 12.00 11.82 11.63 11.37 11.11 10.85 10.58 10.30 10.02 9.75 9.46 9.12 4.48 4.258 4.15 4.06 3.98 3.90 3.81 3.70 3.59 3.49 3.38 3.27 3.17 3.07 2.97 2.86 172 171 164 152 140 128 116 104 93 81 70 59 49 38 27 16 -25 -25 -25 -25 -25 -24 -24 -24 -22 -22 -22 -21 -21 -21 -21 -21 0.051 0.057 0.059 0.061 0.063 0.067 0.070 0.074 0.077 0.081 0.083 0.087 0.09 0.091 0.093 0.094 312 17 8 5 5 4 2 -1 -4 -7 -11 -15 -20 -25 -30 -36 0.43 0.38 0.35 0.35 0.34 0.34 0.32 0.31 0.29 0.27 0.25 0.23 0.21 0.19 0.17 0.14 -14 -13 -9 -15 -22 -30 -39 -46 -53 -60 -67 -74 -81 -90 -96 -100 1.47 1.58 1.64 1.65 1.65 1.65 1.66 1.69 1.73 1.77 1.82 1.85 1.91 1.93 1.98 2.05 MGA-81563 Typical Noise Parameters[1] TC = 25C, ZO = 50 , Vd = 3 V Frequency NFO Gopt Rn / 50 GHz dB Mag. Ang. -- 0.5 2.90 0.16 1 1.57 1.0 2.80 0.15 17 0.96 1.5 2.70 0.14 28 0.75 2.0 2.69 0.14 37 0.41 2.5 2.68 0.13 44 0.39 3.0 2.68 0.11 50 0.38 3.5 2.68 0.09 56 0.36 4.0 2.69 0.06 65 0.34 4.5 2.69 0.03 76 0.33 5.0 2.68 0.01 137 0.32 5.5 2.67 0.02 -135 0.32 6.0 2.67 0.05 -109 0.32 6.5 2.71 0.07 -95 0.33 7.0 2.77 0.09 -78 0.36 Note: 1. Reference plane per Figure 11 in Applications Information section. 4 S22 GHz MGA-81563 Applications Information Introduction Phase Reference Planes This high performance GaAs MMIC amplifier was developed for commercial wireless applications from 100 MHz to 6 GHz. The positions of the reference planes used to specify the S-Parameters and Noise Parameters for this device are shown in Figure 11. As seen in the illustration, the reference planes are located at the point where the package leads contact the test circuit. The MGA-81563 runs on only 3 volts and typically requires only 42 mA to deliver 14.8 dBm of output power at 1 dB gain compression. An innovative internal bias circuit regulates the device's internal current to enable the MGA-81563 to operate over a wide temperature range with a single, positive power supply of 3 volts. The MGA-81563 will operate with reduced performance with voltages as low as 1.5 volts. The MGA-81563 uses resistive feedback to simultaneously achieve flat gain over a wide bandwidth and match the input and output impedances to 50. The MGA-81563 is unconditionally stable (K>1) over its entire frequency range, making it both very easy to use and yielding consistent performance in the manufacture of high volume wireless products. With a combination of high linearity (+27 dBm output IP3) and low noise figure (3 dB), the MGA-81563 offers outstanding performance for applications requiring a high dynamic range, such as receivers operating in dense signal environments. A wide dynamic range amplifier such as the MGA-81563 can often be used to relieve the requirements of bulky, lossy filters at a receiver's input. The 14.8 dBm output power (P1dB) also makes the MGA81563 extremely useful for pre-driver, driver and buffer stages. For transmitter gain stage applications that require higher output power, the MGA-81563 can provide 50 mW (17 dBm) of saturated output power with a high power added efficiency of 45%. Test Circuit The circuit shown in Figure 10 is used for 100% RF testing of Noise Figure and Gain. The 3.9 nH inductor at the input fix-tunes the circuit to 2 GHz. The only purpose of the RFC at the output is to apply DC bias to the device under test. Tests in this circuit are used to guarantee the NFtest and Gtest parameters shown in the table of Electrical Specifications. 100 pF 81 RF INPUT 3.9 nH RF OUTPUT 22 nH RFC Vd 100 pF Figure 10. Test Circuit. 5 REFERENCE PLANES TEST CIRCUIT Figure 11. Phase Reference Planes. Specifications and Statistical Parameters Several categories of parameters appear within this data sheet. Parameters may be described with values that are either "minimum or maximum," "typical," or "standard deviations." The values for parameters are based on comprehensive product characterization data, in which automated measurements are made on of a minimum of 500 parts taken from 3 non-consecutive process lots of semiconductor wafers. The data derived from product characterization tends to be normally distributed, e.g., fits the standard "bell curve." Parameters considered to be the most important to system performance are bounded by minimum or maximum values. For the MGA-81563, these parameters are: Gain (Gtest), Noise Figure (NFtest), and Device Current (Id). Each of these guaranteed parameters is 100% tested. Values for most of the parameters in the table of Electrical Specifications that are described by typical data are the mathematical mean (P), of the normal distribution taken from the characterization data. For parameters where measurements or mathematical averaging may not be practical, such as the Noise and S-parameter tables or performance curves, the data represents a nominal part taken from the "center" of the characterization distribution. Typical values are intended to be used as a basis for electrical design. To assist designers in optimizing not only the immediate circuit using the MGA-81563, but to also optimize and evaluate trade-offs that affect a complete wireless system, the standard deviation (V) is provided for many of the Electrical Specifications parameters (at 25) in addition to the mean. The standard deviation is a measure of the variability about the mean. It will be recalled that a normal distribution is completely described by the mean and standard deviation. Standard statistics tables or calculations provide the probability of a parameter falling between any two values, usually symmetrically located about the mean. Referring to Figure 12 for example, the probability of a parameter being between 1V is 68.3%; between 2V is 95.4%; and between 3V is 99.7%. 68% 95% 99% -3 -2 -1 Mean () +1 +2 (typical) +3 Parameter Value Figure 12. Normal Distribution. RF Layout The RF layout in Figure 13 is suggested as a starting point for microstripline designs using the MGA-81563 amplifier. Adequate grounding is needed to obtain optimum performance and to maintain stability. All of the ground pins of the MMIC should be connected to the RF groundplane on the backside of the PCB by means of plated through holes (vias) that are placed near the package terminals. As a minimum, one via should be located next to each ground pin to ensure good RF grounding. It is a good practice to use multiple vias to further minimize ground path inductance. line on FR-4, for example, has approximately 0.3 dB loss at 4 GHz. This loss will add directly to the noise figure of the MGA-81563. Biasing The MGA-81563 is a voltage-biased device and is designed to operate from a single, +3 volt power supply with a typical current drain of 42 mA. The internal current regulation circuit allows the amplifier to be operated with voltages as high +5 volts or as low as +1.5 volt. Refer to the section titled "Operation at Bias Voltages Other than 3 Volts" for information on performance and precautions when using other voltages. Typical Application Example The printed circuit layout in Figure 14 can serve as a design guide. This layout is a microstripline design (solid groundplane on the backside of the circuit board) with a 50 input and output. The circuit is fabricated on 0.031inch thick FR-4 dielectric material. Plated through holes (vias) are used to bring the ground to the top side of the circuit where needed. Multiple vias are used to reduce the inductance of the paths to ground. OUT IN +V MGA-8-A 50 81 RF Input RF Output and Vd 50 Figure 13. RF Layout. It is recommended that the PCB pads for the ground pins not be connected together underneath the body of the package. PCB traces hidden under the package cannot be adequately inspected for SMT solder quality. Figure 14. PCB Layout. A schematic diagram of the application circuit is shown in Figure 15. DC blocking capacitors (C1 and C2) are used at the input and output of the MMIC to isolate the device from adjacent circuits. Although the input terminal of the MGA-81563 is at ground potential, it is not a current sink. If the input is connected to a preceding stage that has a voltage present, the use of the DC blocking capacitor (C1) is required. C2 Vd PCB Material FR-4 or G-10 printed circuit board materials are a good choice for most low cost wireless applications. Typical board thickness is 0.020 to 0.031 inches. The width of the 50: microstriplines on PC boards in this thickness range is also very convenient for mounting chip components such as the series inductor at the input or DC blocking and bypass capacitors. For higher frequencies or for noise figure critical applications, the additional cost of PTFE/glass dielectric materials may be warranted to minimize transmission line loss at the amplifier's input. A 0.5 inch length of 50 microstrip6 C4 RFC RF Input C1 L1 C2 RF Output Figure 15. Schematic Diagram. DC bias is applied to the MGA-81563 through the RF Output pin. An inductor (RFC), or length of high impedance transmission line (preferably O/4 at the band center), is used to isolate the RF from the DC supply. The power supply is bypassed to ground with capacitor C3 to keep RF off of the DC lines and to prevent gain dips or peaks in the response of the amplifier. An additional bypass capacitor, C4, may be added to the bias line near the Vd connection to eliminate unwanted feedback through bias lines that could cause oscillation. C4 will not normally be needed unless several stages are cascaded using a common power supply. When multiple bypass capacitors are used, consideration should be given to potential resonances. It is important to ensure that the capacitors when combined with additional parasitic L's and C's on the circuit board do not form resonant circuits. The addition of a small value resistor in the bias supply line between bypass capacitors will often "de-Q" the bias circuit and eliminate the effect of a resonance. The value of the DC blocking and RF bypass capacitors (C1 - C3) should be chosen to provide a small reactance (typically < 5 ohms) at the lowest operating frequency. The reactance of the RF choke (RFC) should be high (e.g., several hundred ohms) at the lowest frequency of operation. The MGA-81563's response at low frequencies is limited to approximately 100 MHz by the size of capacitors integrated on the MMIC chip. The input of the MGA-81563 is partially matched internally to 50 . Without external matching elements, the input VSWR of the MGA-81563 is 3.0:1 at 300 MHz and decreases to 1.5:1 at 6 GHz. This will be adequate for many applications. If a better input VSWR is required, the use of a series inductor, L1 in the applications example, (or, alternatively a length of high impedance transmission line) is all that is needed to improve the match. The table in Figure 16 shows suggested values for L1 for various wireless frequency bands. Frequency (GHz) 0.9 1.5 1.9 2.4 4.0 5.8 Inductor, L1 (nH) 10 6.8 3.9 2.7 0.5 0 Figure 16. Values for L1. These values for L1 take into account the short length of 50 transmission line between the inductor and the input pin of the device. 7 For applications requiring minimum noise figure (NFo), some improvement over a 50 match is possible by matching the signal input to the optimum noise match impedance, *o, as specified in the "Typical Noise Parameters" table. For most applications, as shown in the example circuit, the output of the MGA-81563 is already sufficiently well matched to 50 and no additional matching is needed. The nominal device output VSWR is 2.2:1 from 300 MHz through 6 GHz. The completed application amplifier with all components and SMA connectors is shown in Figure 17. C1 OUT L1 C2 IN RFC C3 +V MGA-8-A C4 Figure 17. Complete Application Circuit. Operation in Saturation for Higher Output Power For applications such as pre-driver and driver stages in transmitters, the MGA-81563 can be operated in saturation to deliver up to 50 mW (17 dBm) of output power. The power added efficiency increases to 45% at these power levels. There are several design considerations related to reliability and performance that should be taken into account when operating the amplifier in saturation. First of all, it is important that the stage preceding the MGA-81563 not overdrive the device. Referring to the "Absolute Maximum Ratings" table, the maximum allowable input power is +13 dBm. This should be regarded as the input power level above which the device could be permanently damaged. Driving the amplifier into saturation will also affect electrical performance. Figure 18 presents the Output Power, Third Order Intercept Point (Output IP3), and Power Added Efficiency (PAE) as a function of Input Power. This data represents performance into a 50: load. Since the output impedance of the device changes when driven into saturation, it is possible to obtain even more output power with a "power match." The optimum impedance match for maximum output power is dependent on frequency and actual output power level and can be arrived at empirically. Operation at Bias Voltages Other than 3 Volts 50 PAE While the MGA-81563 is designed primarily for use in +3 volt applications, the internal bias regulation circuitry allows it to be operated with any power supply voltage from +1.5 to +5 volts. Performance of Gain, Noise Figure, and Output Power over a wide range of bias voltage is shown in Figure 20. As can be seen, the gain and NF are fairly flat, but an increase in output power is possible by using higher voltages. The use of +5 volts increases the P1dB by 2 dBm. Pout and IP3 (dBm), PAE (%) 40 IP3 30 20 Power 10 0 -10 -20 -15 -10 -5 0 5 10 18 POWER IN (dBm) Power 16 As the input power is increased beyond the linear range of the amplifier, the gain becomes more compressed. Gain as a function of either input or output power may be derived from Figure 18. Gain compression renders the amplifier less sensitive to variations in the power level from the preceding stage. This can be a benefit in systems requiring fairly constant output power levels from the MGA-81563. Increased efficiency (45% at full output power) is another benefit of saturated operation. At high output power levels, the bias supply current drops by about 15%. This is normal and is taken into account for the PAE data in Figure 18. Noise figure and input impedance are also affected by saturated power operation. As a guideline, the input impedance is lowered, resulting in an improvement in input VSWR of approximately 20%. Like other active devices, the intermodulation products of the MGA-81563 increase as the device is driven further into nonlinear operation. The 3rd, 5th, and 7th order intermodulation products of the MGA-81563 are shown in Figure 19 along with the fundamental response. This data was measured in the test circuit in Figure 10. 30 Pout, 3rd, 5th, 7th HARMONICS (dBm) 20 NF, GAIN, P1 dB (dB) Figure 18. Output Power, IP3, and Power-Added-Efficiency vs. Input Power. (Vd = 3.0 V) 14 12 Gain 10 8 6 4 NF 2 0 0 1 2 3 4 5 SUPPLY VOLTAGE (V) Figure 20. Gain, Noise Figure, and Output Power vs. Supply Voltage. Some thermal precautions must be observed for operation at higher bias voltages. For reliable operation, the channel temperature should be kept within the 165C indicated in the "Absolute Maximum Ratings" table. As a guideline, operating life tests have established a MTTF in excess of 106 hours for channel temperatures up to 150C. There are several means of biasing the MGA-81563 at 3 volts in systems that use higher power supply voltages. The simplest method, shown in Figure 21a, is to use a series resistor to drop the device voltage to 3 volts. For example, a 47 resistor will drop a 5-volt supply to 3 volts at the nominal current of 42 mA. Some variation in performance could be expected for this method due to variations in current within the specified 31 to 51 mA min/max range. +5 V 10 +5 V +5 V Pout 0 47 -10 3rd -20 Silicon Diodes Zener Diode (b) (c) -30 -40 5th 7th -50 (a) -60 -30 -15 -10 -5 0 5 10 15 FREQUENCY (GHz) Figure 19. Intermodulation Products vs. Input Power. (Vd = 3.0V) 8 Figure 21. Biasing From Higher Supply Voltages. A second method illustrated in Figure 21b, is to use forward-biased diodes in series with the power supply. For example, three silicon diodes connected in series will drop a 5-volt supply to approximately 3 volts. The use of the series diode approach has the advantage of less dependency on current variation in the amplifiers since the forward voltage drop of a diode is somewhat current independent. Reverse breakdown diodes (e.g., Zener diodes) could also be used as in Figure 21c. However, care should be taken to ensure that the noise generated by diodes in either Zener or reverse breakdown is adequately filtered (e.g., bypassed to ground) such that the diode's noise is not added to the amplifier's signal. SOT-363 PCB Footprint A recommended PCB pad layout for the miniature SOT363 (SC-70) package used by the MGA-81563 is shown in Figure 22 (dimensions are in inches). This layout provides ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the high frequency RF performance of the MGA81563. The layout is shown with a nominal SOT-363 package footprint superimposed on the PCB pads. 0.026 0.079 0.039 0.018 Dimensions in inches. Figure 22. Recommended PCB Pad Layout for Avago's SC70 6L/SOT-363 Products. 9 Package Dimensions Outline 63 (SOT-363/SC-70) HE E e D Q1 A2 A c A1 L b DIMENSIONS (mm) SYMBOL E D HE A A2 A1 Q1 e b c L MAX. 1.35 2.25 2.40 1.10 1.00 0.10 0.40 MIN. 1.15 1.80 1.80 0.80 0.80 0.00 0.10 NOTES: 1. All dimensions are in mm. 2. Dimensions are inclusive of plating. 3. Dimensions are exclusive of mold flash & metal burr. 4. All specifications comply to EIAJ SC70. 5. Die is facing up for mold and facing down for trim/form, ie: reverse trim/form. 6. Package surface to be mirror finish. 0.650 BCS 0.15 0.10 0.10 0.30 0.20 0.30 Part Number Ordering Information 10 Part Number No. of Devices Container MGA-81563-TR1G 3000 7" Reel MGA-81563-TR2G 10000 13" Reel MGA-81563-BLKG 100 antistatic bag Device Orientation REEL TOP VIEW END VIEW 4 mm 8 mm CARRIER TAPE 81 81 81 81 USER FEED DIRECTION COVER TAPE Tape Dimensions and Product Orientation for Outline 63 P P2 D P0 E F W C D1 t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS) K0 10 MAX. A0 DESCRIPTION 10 MAX. B0 SYMBOL SIZE (mm) SIZE (INCHES) CAVITY LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A0 B0 K0 P D1 2.40 0.10 2.40 0.10 1.20 0.10 4.00 0.10 1.00 + 0.25 0.094 0.004 0.094 0.004 0.047 0.004 0.157 0.004 0.039 + 0.010 PERFORATION DIAMETER PITCH POSITION D P0 E 1.55 0.10 4.00 0.10 1.75 0.10 0.061 + 0.002 0.157 0.004 0.069 0.004 CARRIER TAPE WIDTH THICKNESS W t1 8.00 + 0.30 - 0.10 0.254 0.02 0.315 + 0.012 0.0100 0.0008 COVER TAPE WIDTH TAPE THICKNESS C Tt 5.40 0.10 0.062 0.001 0.205 + 0.004 0.0025 0.0004 DISTANCE CAVITY TO PERFORATION (WIDTH DIRECTION) F 3.50 0.05 0.138 0.002 CAVITY TO PERFORATION (LENGTH DIRECTION) P2 2.00 0.05 0.079 0.002 For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright (c) 2005-2010 Avago Technologies. All rights reserved. Obsoletes AV01-0190EN AV02-0966EN - May 22, 2010