MGA-81563
0.1–6 GHz 3 V, 14 dBm Amplier
Data Sheet
Features
x Lead-free Option Available
x +14.8 dBm P1dB at 2.0 GHz
+17 dBm Psat at 2.0 GHz
x Single +3V Supply
x 2.8 dB Noise Figure at 2.0 GHz
x 12.4 dB Gain at 2.0 GHz
x Ultra-miniature Package
x Unconditionally Stable
Applications
x Buer or Driver Amp for PCS, PHS, ISM, SATCOM and
WLL Applications
x High Dynamic Range LNA
Simplied Schematic
Description
Avago’s MGA-81563 is an economical, easy-to-use GaAs
MMIC amplier that oers excellent power and low noise
gure for applications from 0.1 to 6 GHz. Packaged in
an ultra-miniature SOT-363 package, it requires half the
board space of a SOT-143 package.
The output of the amplier is matched to 50Ω (better
than 2.1:1 VSWR) across the entire bandwidth. The input is
partially matched to 50Ω (better than 2.5:1 VSWR) below
4 GHz and fully matched to 50Ω (better than 2:1 VSWR)
above. A simple series inductor can be added to the in-
put to improve the input match below 4 GHz. The ampli-
er allows a wide dynamic range by oering a 2.7 dB NF
coupled with a +27 dBm Output IP3.
The circuit uses state-of-the-art PHEMT technology
with proven reliability. On-chip bias circuitry allows op-
eration from a single +3 V power supply, while resistive
feedback ensures stability (K>1) over all frequencies and
temperatures.
Surface Mount Package: SOT-363 (SC-70)
INPUT
3
OUTPUT
and V
d
6
GND
BIAS
1, 2, 4, 5
BIAS
Pin Connections and Package Marking
OUTPUT
and V
d
GND
81x
GND
GND
INPUT
1
2
3
6
5
4 GND
Note: Package marking provides orientation and identication.
"81" = Device Code
"x" = Date code character identies month of manufacture
Attention:
Observe precautions for
handling electrostatic sensitive devices.
ESD Human Body Model (Class 0)
Refer to Avago Application Note A004R:
Electrostatic Discharge Damage and Control.
2
Thermal Resistance[2]:
Tch-c = 220°C/W
Notes:
1. Permanent damage may occur if any of
these limits are exceeded.
2. TC = 25°C (TC is dened to be the
temperature at the package pins where
contact is made to the circuit board.)
MGA-81563 Electrical Specications, TC = 25°C, ZO = 50 Ω, Vd = 3 V
Symbol Parameters and Test Conditions Units Min. Typ. Max. Std Dev[2]
Gtest Gain in test circuit[1] f = 2.0 GHz 10.5 12.4 14.5 0.44
NFtest Noise Figure in test circuit[1] f = 2.0 GHz 2.8 3.8 0.21
NF50 Noise Figure in 50 system f = 0.5 GHz
f = 1.0 GHz
f = 2.0 GHz
f = 3.0 GHz
f = 4.0 GHz
f = 6.0 GHz
dB 3.1
3.0
2.7
2.7
2.8
3.5
0.21
|S21|2 Gain in 50 system f = 0.5 GHz
f = 1.0 GHz
f = 2.0 GHz
= 3.0 GHz
f = 4.0 GHz
f = 6.0 GHz
dB 12.5
12.5
12.3
11.8
11.4
10.2
0.44
P1 dB Output Power at 1 dB Gain Compression f = 0.5 GHz
f = 1.0 GHz
f = 2.0 GHz
f = 3.0 GHz
f = 4.0 GHz
f = 6.0 GHz
dBm 15.1
14.8
14.8
14.8
14.8
14.7
0.86
IP3 Output Third Order Intercept Point f = 2.0 GHz dBm +27 1.0
VSWRin Input VSWR f = 2.0 GHz 2.7:1
VSWRout Output VSWR f = 2.0 GHz 2.0:1
I d Device Current mA 31 42 51
Notes:
1. Guaranteed specications are 100% tested in the circuit in Figure 10 in the Applications Information section.
2. Standard deviation number is based on measurement of at least 500 parts from three non-consecutive wafer lots during the initial characterization
of this product, and is intended to be used as an estimate for distribution of the typical specication.
MGA-81563 Absolute Maximum Ratings
Absolute
Symbol Parameter Units Maximum[1]
V
d Device Voltage, RF Output V 6.0
to Ground
V
gd Device Voltage, Gate V -6.0
to Drain
V
in Range of RF Input Voltage V +0.5 to -1.0
to Ground
P
in CW RF Input Power dBm +13
T
ch Channel Temperature °C 165
T
STG Storage Temperature °C -65 to 150
3
MGA-81563 Typical Performance, TC = 25° C, Vd = 3 V
034512 6 0 34512 6
FREQUENCY (GHz) FREQUENCY (GHz)
Figure 2. Noise Figure vs. Frequency and
Temperature.
T
A
= +85C
T
A
= +25C
T
A
= –40C
0
2
4
6
8
16
12
14
10
GAIN
(dB)
0
1
2
3
4
5
NOISE FIGURE
(dB)
T
A
= +85C
T
A
= +25C
T
A
= –40C
Figure 1. Power Gain vs. Frequency and
Temperature.
034512 6
FREQUENCY (GHz)
Figure 3. Output Power @ 1 dB Gain
Compression
P
1 dB
(dBm)
11
12
13
14
15
16
T
A
= +85C
T
A
= +25C
T
A
= –40C
0
1
2
3
4
5
034512 6
NOISE FIGURE
(dB)
FREQUENCY (GHz)
Figure 5. Noise Figure vs. Frequency and
Voltage.
V
d
= 2.7V
V
d
= 3.0V
V
d
= 3.3V
11
12
13
14
15
16
034512 6
FREQUENCY (GHz)
Figure 6. Output Power @ 1 dB Gain
Compression vs. Frequency and Voltage
P
1 dB
(dBm)
V
d
= 2.7V
V
d
= 3.0V
V
d
= 3.3V
0
2
4
6
8
16
12
14
10
034512 6
GAIN
(dB)
FREQUENCY (GHz)
Figure 4. Power Gain vs. Frequency and
Voltage.
V
d
= 2.7V
V
d
= 3.0V
V
d
= 3.3V
034512 6
VSWR (n:1)
FREQUENCY (GHz)
Figure 7. Input and Output VSWR vs.
Frequency.
1
1.5
2
3
2.5
4
3.5
034512
0
10
20
40
30
60
50
DEVICE CURRENT
(mA)
DEVICE VOLTAGE (V)
Figure 8. Device Current vs. Voltage and
Temperature.
FREQUENCY (GHz)
Figure 9. Minimum Noise Figure and
Associated Gain vs. Frequency.
GAIN and NF
(dB)
T
A
= +85C
T
A
= +25C
T
A
= -40C NF
Gain
034512 6
0
2
4
6
8
16
12
14
10
Input
Output
4
MGA-81563 Typical Scattering Parameters[1], TC = 25°C, ZO = 50 Ω, Vd = 3 V
Freq. S11 S
21 S12 S22 K
GHz Mag Ang dB Mag Ang dB Mag Ang Mag Ang Factor
0.1 0.57 -16 13.02 4.48 172 -25 0.051 312 0.43 -14 1.47
0.2 0.52 -13 12.58 4.258 171 -25 0.057 17 0.38 -13 1.58
0.5 0.49 -16 12.35 4.15 164 -25 0.059 8 0.35 -9 1.64
1.0 0.48 -28 12.18 4.06 152 -25 0.061 5 0.35 -15 1.65
1.5 0.47 -40 12.00 3.98 140 -25 0.063 5 0.34 -22 1.65
2.0 0.45 -52 11.82 3.90 128 -24 0.067 4 0.34 -30 1.65
2.5 0.43 -63 11.63 3.81 116 -24 0.070 2 0.32 -39 1.66
3.0 0.39 -75 11.37 3.70 104 -24 0.074 -1 0.31 -46 1.69
3.5 0.35 -87 11.11 3.59 93 -22 0.077 -4 0.29 -53 1.73
4.0 0.32 -100 10.85 3.49 81 -22 0.081 -7 0.27 -60 1.77
4.5 0.28 -114 10.58 3.38 70 -22 0.083 -11 0.25 -67 1.82
5.0 0.25 -130 10.30 3.27 59 -21 0.087 -15 0.23 -74 1.85
5.5 0.22 -146 10.02 3.17 49 -21 0.09 -20 0.21 -81 1.91
6.0 0.20 -166 9.75 3.07 38 -21 0.091 -25 0.19 -90 1.93
6.5 0.18 174 9.46 2.97 27 -21 0.093 -30 0.17 -96 1.98
7.0 0.17 150 9.12 2.86 16 -21 0.094 -36 0.14 -100 2.05
MGA-81563 Typical Noise Parameters[1] TC = 25°C, ZO = 50 Ω, Vd = 3 V
Frequency NFO G
opt R
n/ 50 Ω
GHz dB Mag. Ang. —
0.5 2.90 0.16 1 1.57
1.0 2.80 0.15 17 0.96
1.5 2.70 0.14 28 0.75
2.0 2.69 0.14 37 0.41
2.5 2.68 0.13 44 0.39
3.0 2.68 0.11 50 0.38
3.5 2.68 0.09 56 0.36
4.0 2.69 0.06 65 0.34
4.5 2.69 0.03 76 0.33
5.0 2.68 0.01 137 0.32
5.5 2.67 0.02 -135 0.32
6.0 2.67 0.05 -109 0.32
6.5 2.71 0.07 -95 0.33
7.0 2.77 0.09 -78 0.36
Note:
1. Reference plane per Figure 11 in Applications Information section.
5
MGA-81563 Applications Information
Introduction
This high performance GaAs MMIC amplier was
developed for commercial wireless applications from
100 MHz to 6 GHz.
The MGA-81563 runs on only 3 volts and typically requires
only 42 mA to deliver 14.8 dBm of output power at 1 dB
gain compression.
An innovative internal bias circuit regulates the device’s
internal current to enable the MGA-81563 to operate over
a wide temperature range with a single, positive power
supply of 3 volts. The MGA-81563 will operate with re-
duced performance with voltages as low as 1.5 volts.
The MGA-81563 uses resistive feedback to simultaneously
achieve at gain over a wide bandwidth and match the in-
put and output impedances to 50Ω. The MGA-81563 is un-
conditionally stable (K>1) over its entire frequency range,
making it both very easy to use and yielding consistent
performance in the manufacture of high volume wireless
products.
With a combination of high linearity (+27 dBm output IP3)
and low noise gure (3 dB), the MGA-81563 oers out-
standing performance for applications requiring a high
dynamic range, such as receivers operating in dense sig-
nal environments. A wide dynamic range amplier such as
the MGA-81563 can often be used to relieve the require-
ments of bulky, lossy lters at a receiver’s input.
The 14.8 dBm output power (P1dB) also makes the MGA-
81563 extremely useful for pre-driver, driver and buer
stages. For transmitter gain stage applications that re-
quire higher output power, the MGA-81563 can provide
50 mW (17 dBm) of saturated output power with a high
power added eciency of 45%.
Test Circuit
The circuit shown in Figure 10 is used for 100% RF testing
of Noise Figure and Gain. The 3.9 nH inductor at the input
x-tunes the circuit to 2 GHz. The only purpose of the RFC
at the output is to apply DC bias to the device under test.
Tests in this circuit are used to guarantee the NFtest and Gtest
parameters shown in the table of Electrical Specications.
Phase Reference Planes
The positions of the reference planes used to specify the
S-Parameters and Noise Parameters for this device are
shown in Figure 11. As seen in the illustration, the refer-
ence planes are located at the point where the package
leads contact the test circuit.
RF
INPUT
3.9 nH
22 nH
RFC
100 pF
100 pF
Vd
RF
OUTPUT
81
TEST CIRCUIT
REFERENCE
PLANES
Figure 10. Test Circuit.
Figure 11. Phase Reference Planes.
Specications and Statistical Parameters
Several categories of parameters appear within this data
sheet. Parameters may be described with values that are
either “minimum or maximum,” “typical,” or “standard de-
viations.”
The values for parameters are based on comprehensive
product characterization data, in which automated mea-
surements are made on of a minimum of 500 parts taken
from 3 non-consecutive process lots of semiconductor
wafers. The data derived from product characterization
tends to be normally distributed, e.g., ts the standard
“bell curve.”
Parameters considered to be the most important to sys-
tem performance are bounded by minimum or maximum
values. For the MGA-81563, these parameters are: Gain
(Gtest), Noise Figure (NFtest), and Device Current (Id). Each of
these guaranteed parameters is 100% tested.
Values for most of the parameters in the table of Electrical
Specications that are described by typical data are the
mathematical mean (P), of the normal distribution taken
from the characterization data. For parameters where
measurements or mathematical averaging may not be
practical, such as the Noise and S-parameter tables or
performance curves, the data represents a nominal part
taken from the “center” of the characterization distribu-
tion. Typical values are intended to be used as a basis for
electrical design.
To assist designers in optimizing not only the immediate
circuit using the MGA-81563, but to also optimize and
evaluate trade-os that aect a complete wireless system,
the standard deviation (V) is provided for many of the
Electrical Specications parameters (at 25°) in addition
to the mean. The standard deviation is a measure of the
variability about the mean. It will be recalled that a nor-
mal distribution is completely described by the mean and
standard deviation.
6
Standard statistics tables or calculations provide the prob-
ability of a parameter falling between any two values,
usually symmetrically located about the mean. Referring
to Figure 12 for example, the probability of a parameter
being between ±1V is 68.3%; between ±2V is 95.4%; and
between ±3V is 99.7%.
line on FR-4, for example, has approximately 0.3 dB loss at
4 GHz. This loss will add directly to the noise gure of the
MGA-81563.
Biasing
The MGA-81563 is a voltage-biased device and is designed
to operate from a single, +3 volt power supply with a typi-
cal current drain of 42 mA. The internal current regulation
circuit allows the amplier to be operated with voltages
as high +5 volts or as low as +1.5 volt. Refer to the section
titled “Operation at Bias Voltages Other than 3 Volts” for
information on performance and precautions when using
other voltages.
Typical Application Example
The printed circuit layout in Figure 14 can serve as a de-
sign guide. This layout is a microstripline design (solid
groundplane on the backside of the circuit board) with a
50Ω input and output. The circuit is fabricated on 0.031-
inch thick FR-4 dielectric material. Plated through holes
(vias) are used to bring the ground to the top side of the
circuit where needed. Multiple vias are used to reduce the
inductance of the paths to ground.
68%
95%
99%
Parameter Value
Mean (μ)
(typical)
-3σ-2σ-1σ+1σ+2σ+3σ
81
50 Ω
50 Ω
RF Input
RF Output
and Vd
IN
OUT
+V
MGA-8-A
C2
C2
C4
C1 L1
RFC
V
d
RF
Output
RF
Input
Figure 12. Normal Distribution.
RF Layout
The RF layout in Figure 13 is suggested as a starting point
for microstripline designs using the MGA-81563 amplier.
Adequate grounding is needed to obtain optimum per-
formance and to maintain stability. All of the ground pins
of the MMIC should be connected to the RF groundplane
on the backside of the PCB by means of plated through
holes (vias) that are placed near the package terminals.
As a minimum, one via should be located next to each
ground pin to ensure good RF grounding. It is a good
practice to use multiple vias to further minimize ground
path inductance.
Figure 13. RF Layout.
It is recommended that the PCB pads for the ground pins
not be connected together underneath the body of the
package. PCB traces hidden under the package cannot be
adequately inspected for SMT solder quality.
PCB Material
FR-4 or G-10 printed circuit board materials are a good
choice for most low cost wireless applications. Typical
board thickness is 0.020 to 0.031 inches. The width of the
50: microstriplines on PC boards in this thickness range is
also very convenient for mounting chip components such
as the series inductor at the input or DC blocking and by-
pass capacitors.
For higher frequencies or for noise gure critical applica-
tions, the additional cost of PTFE/glass dielectric materials
may be warranted to minimize transmission line loss at
the amplier’s input. A 0.5 inch length of 50Ω microstrip-
Figure 14. PCB Layout.
A schematic diagram of the application circuit is shown
in Figure 15. DC blocking capacitors (C1 and C2) are used
at the input and output of the MMIC to isolate the device
from adjacent circuits. Although the input terminal of the
MGA-81563 is at ground potential, it is not a current sink.
If the input is connected to a preceding stage that has a
voltage present, the use of the DC blocking capacitor (C1)
is required.
Figure 15. Schematic Diagram.
DC bias is applied to the MGA-81563 through the
RF Output pin. An inductor (RFC), or length of high
impedance transmission line (preferably O/4 at the band
center), is used to isolate the RF from the DC supply.
7
The power supply is bypassed to ground with capacitor
C3 to keep RF o of the DC lines and to prevent gain dips
or peaks in the response of the amplier.
An additional bypass capacitor, C4, may be added to the
bias line near the Vd connection to eliminate unwanted
feedback through bias lines that could cause oscillation.
C4 will not normally be needed unless several stages are
cascaded using a common power supply.
When multiple bypass capacitors are used, consideration
should be given to potential resonances. It is important
to ensure that the capacitors when combined with addi-
tional parasitic L’s and C’s on the circuit board do not form
resonant circuits. The addition of a small value resistor in
the bias supply line between bypass capacitors will often
“de-Q” the bias circuit and eliminate the eect of a reso-
nance.
The value of the DC blocking and RF bypass capacitors
(C1 – C3) should be chosen to provide a small reactance
(typically < 5 ohms) at the lowest operating frequency.
The reactance of the RF choke (RFC) should be high (e.g.,
several hundred ohms) at the lowest frequency of opera-
tion.
The MGA-81563’s response at low frequencies is limited
to approximately 100 MHz by the size of capacitors inte-
grated on the MMIC chip.
The input of the MGA-81563 is partially matched inter-
nally to 50 Ω. Without external matching elements, the
input VSWR of the MGA-81563 is 3.0:1 at 300 MHz and de-
creases to 1.5:1 at 6 GHz. This will be adequate for many
applications. If a better input VSWR is required, the use of
a series inductor, L1 in the applications example, (or, alter-
natively a length of high impedance transmission line) is
all that is needed to improve the match. The table in Fig-
ure 16 shows suggested values for L1 for various wireless
frequency bands.
Frequency Inductor, L1
(GHz) (nH)
0.9 10
1.5 6.8
1.9 3.9
2.4 2.7
4.0 0.5
5.8 0
Figure 16. Values for L1.
These values for L1 take into account the short length of
50Ω transmission line between the inductor and the input
pin of the device.
For applications requiring minimum noise gure (NFo),
some improvement over a 50Ω match is possible by
matching the signal input to the optimum noise match
impedance, *o, as specied in the “Typical Noise Param-
eters” table.
For most applications, as shown in the example circuit,
the output of the MGA-81563 is already suciently well
matched to 50Ω and no additional matching is needed.
The nominal device output VSWR is ≤ 2.2:1 from 300 MHz
through 6 GHz.
The completed application amplier with all components
and SMA connectors is shown in Figure 17.
Figure 17. Complete Application Circuit.
Operation in Saturation for Higher Output Power
For applications such as pre-driver and driver stages in
transmitters, the MGA-81563 can be operated in satura-
tion to deliver up to 50 mW (17 dBm) of output power. The
power added eciency increases to 45% at these power
levels.
There are several design considerations related to reliabil-
ity and performance that should be taken into account
when operating the amplier in saturation.
First of all, it is important that the stage preceding the
MGA-81563 not overdrive the device. Referring to the “Ab-
solute Maximum Ratings” table, the maximum allowable
input power is +13 dBm. This should be regarded as the
input power level above which the device could be per-
manently damaged.
Driving the amplier into saturation will also aect elec-
trical performance. Figure 18 presents the Output Power,
Third Order Intercept Point (Output IP3), and Power Added
Eciency (PAE) as a function of Input Power. This data
represents performance into a 50: load. Since the output
impedance of the device changes when driven into satu-
ration, it is possible to obtain even more output power
with a “power match.” The optimum impedance match for
maximum output power is dependent on frequency and
actual output power level and can be arrived at empiri-
cally.
IN
OUT
+V
C4
C3
RFC
C2
L1
C1
MGA-8-A
8
Figure 18. Output Power, IP3, and Power-Added-Eciency vs. Input Power.
(Vd = 3.0 V)
As the input power is increased beyond the linear range
of the amplier, the gain becomes more compressed. Gain
as a function of either input or output power may be de-
rived from Figure 18. Gain compression renders the ampli-
er less sensitive to variations in the power level from the
preceding stage. This can be a benet in systems requiring
fairly constant output power levels from the MGA-81563.
Increased eciency (45% at full output power) is another
benet of saturated operation. At high output power lev-
els, the bias supply current drops by about 15%. This is
normal and is taken into account for the PAE data in Fig-
ure 18.
Noise gure and input impedance are also aected by
saturated power operation. As a guideline, the input im-
pedance is lowered, resulting in an improvement in input
VSWR of approximately 20%.
Like other active devices, the intermodulation products
of the MGA-81563 increase as the device is driven further
into nonlinear operation. The 3rd, 5th, and 7th order in-
termodulation products of the MGA-81563 are shown in
Figure 19 along with the fundamental response. This data
was measured in the test circuit in Figure 10.
Operation at Bias Voltages Other than 3 Volts
While the MGA-81563 is designed primarily for use in +3
volt applications, the internal bias regulation circuitry al-
lows it to be operated with any power supply voltage from
+1.5 to +5 volts. Performance of Gain, Noise Figure, and
Output Power over a wide range of bias voltage is shown
in Figure 20. As can be seen, the gain and NF are fairly
at, but an increase in output power is possible by using
higher voltages. The use of +5 volts increases the P1dB by
2 dBm.
-30 -50510-15-1015
Pout, 3rd, 5th, 7th HARMONICS (dBm)
FREQUENCY (GHz)
-60
-50
-40
-20
-30
30
-10
0
10
20
7th5th
3rd
Pout
-20 -505-15-1010
Pout and IP3 (dBm), PAE (%)
POWER IN (dBm)
-10
0
10
30
20
50
40
Power
PAE
IP3
NF, GAIN, P1 dB (dB)
SUPPLY VOLTAGE (V)
0
2
4
8
6
18
10
12
14
16
NF
Gain
Power
034512
Figure 20. Gain, Noise Figure, and Output Power vs. Supply Voltage.
Some thermal precautions must be observed for operation
at higher bias voltages. For reliable operation, the channel
temperature should be kept within the 165°C indicated in
the “Absolute Maximum Ratings” table. As a guideline, op-
erating life tests have established a MTTF in excess of 106
hours for channel temperatures up to 150°C.
There are several means of biasing the MGA-81563 at
3 volts in systems that use higher power supply voltages.
The simplest method, shown in Figure 21a, is to use a se-
ries resistor to drop the device voltage to 3 volts. For ex-
ample, a 47Ω resistor will drop a 5-volt supply to 3 volts
at the nominal current of 42 mA. Some variation in per-
formance could be expected for this method due to varia-
tions in current within the specied 31 to 51 mA min/max
range.
Figure 19. Intermodulation Products vs. Input Power.
(Vd = 3.0V)
Figure 21. Biasing From Higher Supply Voltages.
47 Ω
(a)
+5 V
Silicon
Diodes
(b)
+5 V
Zener
Diode
(c)
+5 V
9
A second method illustrated in Figure 21b, is to use for-
ward-biased diodes in series with the power supply. For
example, three silicon diodes connected in series will drop
a 5-volt supply to approximately 3 volts.
The use of the series diode approach has the advantage
of less dependency on current variation in the ampliers
since the forward voltage drop of a diode is somewhat
current independent.
Reverse breakdown diodes (e.g., Zener diodes) could also
be used as in Figure 21c. However, care should be taken
to ensure that the noise generated by diodes in either Ze-
ner or reverse breakdown is adequately ltered (e.g., by-
passed to ground) such that the diode’s noise is not added
to the amplier’s signal.
SOT-363 PCB Footprint
A recommended PCB pad layout for the miniature SOT-
363 (SC-70) package used by the MGA-81563 is shown in
Figure 22 (dimensions are in inches). This layout provides
ample allowance for package placement by automated
assembly equipment without adding parasitics that could
impair the high frequency RF performance of the MGA-
81563. The layout is shown with a nominal SOT-363 pack-
age footprint superimposed on the PCB pads.
0.026
0.079
0.018
0.039
Dimensions in inches.
Figure 22. Recommended PCB Pad Layout for Avago’s SC70 6L/SOT-363
Products.
10
Package Dimensions
Outline 63 (SOT-363/SC-70)
Part Number Ordering Information
No. of
Part Number Devices Container
MGA-81563-TR1G 3000 7" Reel
MGA-81563-TR2G 10000 13" Reel
MGA-81563-BLKG 100 antistatic bag
E
HE
D
e
A1
b
A
A2
Q1
L
c
DIMENSIONS (mm)
MIN.
1.15
1.80
1.80
0.80
0.80
0.00
0.10
0.15
0.10
0.10
MAX.
1.35
2.25
2.40
1.10
1.00
0.10
0.40
0.30
0.20
0.30
SYMBOL
E
D
HE
A
A2
A1
Q1
e
b
c
L
NOTES:
1. All dimensions are in mm.
2. Dimensions are inclusive of plating.
3. Dimensions are exclusive of mold flash & metal burr.
4. All specifications comply to EIAJ SC70.
5. Die is facing up for mold and facing down for trim/form,
ie: reverse trim/form.
6. Package surface to be mirror finish.
0.650 BCS
Tape Dimensions and Product Orientation for Outline 63
Device Orientation
P
P
0
P
2
F
W
C
D
1
D
E
A
0
10° MAX.
t
1
(CARRIER TAPE THICKNESS) T
t
(COVER TAPE THICKNESS)
10° MAX.
B
0
K
0
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A
0
B
0
K
0
P
D
1
2.40 ± 0.10
2.40 ± 0.10
1.20 ± 0.10
4.00 ± 0.10
1.00 + 0.25
0.094 ± 0.004
0.094 ± 0.004
0.047 ± 0.004
0.157 ± 0.004
0.039 + 0.010
CAVITY
DIAMETER
PITCH
POSITION
D
P
0
E
1.55 ± 0.10
4.00 ± 0.10
1.75 ± 0.10
0.061 + 0.002
0.157 ± 0.004
0.069 ± 0.004
PERFORATION
WIDTH
THICKNESS
W
t
1
8.00 + 0.30 - 0.10
0.254 ± 0.02
0.315 + 0.012
0.0100 ± 0.0008
CARRIER TAPE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
P
2
3.50 ± 0.05
2.00 ± 0.05
0.138 ± 0.002
0.079 ± 0.002
DISTANCE
WIDTH
TAPE THICKNESS
C
T
t
5.40 ± 0.10
0.062 ± 0.001
0.205 + 0.004
0.0025 ± 0.0004
COVER TAPE
USER
FEED
DIRECTION
COVER TAPE
CARRIER
TAPE
REEL END VIEW
8 mm
4 mm
TOP VIEW
81 81 81 81
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. Obsoletes AV01-0190EN
AV02-0966EN - May 22, 2010
