 
   
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DOperating Range 2-V to 5.5-V VCC
DSchmitt-Trigger Circuitry On A, B, and CLR
Inputs for Slow Input Transition Rates
DEdge Triggered From Active-High or
Active-Low Gated Logic Inputs
DRetriggerable for Very Long Output Pulses
DOverriding Clear Terminates Output Pulse
DGlitch-Free Power-Up Reset On Outputs
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
The ’AHC123A devices are dual retriggerable
monostable multivibrators designed for 2-V to
5.5-V VCC operation.
These edge-triggered multivibrators feature
output pulse-duration control by three methods. In
the first method, the A input is low, and the B input
goes high. In the second method, the B input is
high, and the A input goes low. In the third method,
the A input is low, the B input is high, and the clear
(CLR) input goes high.
ORDERING INFORMATION
TAPACKAGEORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N Tube SN74AHC123AN SN74AHC123AN
SOIC − D
Tube SN74AHC123AD
AHC123A
−40°C to 85°C
SOIC − D Tape and reel SN74AHC123ADR AHC123A
−40°C to 85°CSSOP − DB Tape and reel SN74AHC123ADBR HA123A
TSSOP − PW Tape and reel SN74AHC123APWR HA123A
TVSOP − DGV Tape and reel SN74AHC123ADGVR HA123A
CDIP − J Tube SNJ54AHC123AJ SNJ54AHC123AJ
−55°C to 125°CCFP − W Tube SNJ54AHC123AW SNJ54AHC123AW
−55 C to 125 C
LCCC − FK Tube SNJ54AHC123AFK SNJ54AHC123AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54AHC123A ...J OR W PACKAGE
SN74AHC123A . . . D, DB, DGV, N, OR PW PACKAGE
(TOP VIEW)
SN54AHC123A . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1B
1CLR
1Q
2Q
2Cext
2Rext/Cext
GND
VCC
1Rext/Cext
1Cext
1Q
2Q
2CLR
2B
2A
3212019
910111213
4
5
6
7
8
18
17
16
15
14
1Cext
1Q
NC
2Q
2CLR
1CLR
1Q
NC
2Q
2Cext
1B
1A
NC
2A
2B V
1R
2R GND
NC CC
NC − No internal connection
ext/Cext
ext/Cext
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SCLS352H − JULY 1997 − REVISED OCTOBER 2005
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description/ordering information (continued)
The output pulse duration is programmed by selecting external resistance and capacitance values. The external
timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected
between R ext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between
Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. CLR input can be used to override
A or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early
clearing.
The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing
components. An e xample of this distribution for the ’AHC123A is shown in Figure 10. Variations in output pulse
duration versus supply voltage and temperature are shown in Figure 6.
During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free,
without applying a reset pulse.
For additional application information on multivibrators, see the application report Designing With the
SN74AHC123A and SN74AHCT123A, literature number SCLA014.
FUNCTION TABLE
(each multivibrator)
INPUTS OUTPUTS
CLR A B Q Q
L X X L H
XHXL
H
XXLL
H
H L
H#H
L H
These outputs are based on the
assumption that the indicated
steady-state conditions at the A and
B inputs have been set up long enough to
complete any pulse started before the
setup.
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SCLS352H − JULY 1997 − REVISED OCTOBER 2005
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram, each multivibrator (positive logic)
CLR
Cext
Rext/Cext
R
B
A
Q
Q
input/output timing diagram
A
B
CLR
Q
Q
twtwtw + trr
trr
Rext/Cext
 
   
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VCC (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 2) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range in high or low state, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . .
Output voltage range in power-off state, VO (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to the network ground terminal.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN54AHC123A SN74AHC123A
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
V
IH
High-level input voltage VCC = 3 V 2.1 2.1 V
VIH
High-level input voltage
VCC = 5.5 V 3.85 3.85
V
VCC = 2 V 0.5 0.5
V
IL
Low-level input voltage VCC = 3 V 0.9 0.9 V
VIL
Low-level input voltage
VCC = 5.5 V 1.65 1.65
V
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V −50 −50 mA
I
OH
High-level output current VCC = 3.3 V ± 0.3 V −4 −4
mA
IOH
High-level output current
VCC = 5 V ± 0.5 V −8 −8 mA
VCC = 2 V 50 50 mA
I
OL
Low-level output current VCC = 3.3 V ± 0.3 V 4 4
mA
IOL
Low-level output current
VCC = 5 V ± 0.5 V 8 8 mA
Rext
External timing resistance
VCC = 2 V 5k 5k
Rext External timing resistance VCC > 3 V 1k 1k
t/VCC Power-up ramp rate 1 1 ms/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 4: Unused Rext/Cext terminals should be left unconnected. All remaining unused inputs of the device must be held at VCC or GND to ensure
proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
 
   
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VCC
TA = 25°C SN54AHC123A SN74AHC123A
UNIT
PARAMETER
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 2 1.9 1.9
I
= −50 mA3 V 2.9 3 2.9 2.9
V
OH
4.5 V 4.4 4.5 4.4 4.4 V
VOH
IOH = −4 mA 3 V 2.58 2.48 2.48
V
IOH = −8 mA 4.5 V 3.94 3.8 3.8
2 V 0.1 0.1 0.1
I
= 50 mA3 V 0.1 0.1 0.1
V
OL
4.5 V 0.1 0.1 0.1 V
VOL
IOL = 4 mA 3 V 0.36 0.5 0.44
V
IOL = 8 mA 4.5 V 0.36 0.5 0.44
II
Rext/CextVI = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5
A
IIA, B, and CLR VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1mA
ICC Quiescent VI = VCC or GND, IO = 0 5.5 V 4 40 40 mA
Active state
3 V 160 250 280 280
I
CC
Active state
(per circuit)
VI = VCC or GND,
4.5 V 280 500 650 650 mA
ICC
(per circuit)
5.5 V 360 750 975 975
mA
CiVI = VCC or GND 5 V 1.9 10 10 pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
This test is performed with the terminal in the off-state condition.
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TEST CONDITIONS
TA = 25°C SN54AHC123A SN74AHC123A
UNIT
TEST CONDITIONS
MIN TYP MAX MIN MAX MIN MAX
UNIT
tw
Pulse
CLR 5 5 5
ns
tw
Pulse
duration A or B trigger 5 5 5 ns
trr
Pulse retrigger time
Rext = 1 k, Cext = 100 pF 76 ns
trr
Pulse retrigger time
Rext = 1 k, Cext = 0.01 mF1.8 ms
See retriggering data in the application information section.
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TEST CONDITIONS
TA = 25°C SN54AHC123A SN74AHC123A
UNIT
TEST CONDITIONS
MIN TYP MAX MIN MAX MIN MAX
UNIT
tw
Pulse
CLR 5 5 5
ns
tw
Pulse
duration A or B trigger 5 5 5 ns
trr
Pulse retrigger time
Rext = 1 k, Cext = 100 pF 59 ns
trr
Pulse retrigger time
Rext = 1 k, Cext = 0.01 mF1.5 ms
See retriggering data in the application information section.
 
   
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TEST
TA = 25°C SN54AHC123A SN74AHC123A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS MIN TYP MAX MIN MAX MIN MAX
UNIT
tPLH
A or B
Q or Q
CL = 15 pF
9.5* 20.6* 1* 24* 1 24
ns
tPHL A or B Q or Q CL = 15 pF 10.2* 20.6* 1* 24* 1 24 ns
tPLH
CLR
Q or Q
CL = 15 pF
7.5* 15.8* 1* 18.5* 1 18.5
ns
tPHL CLR Q or Q CL = 15 pF 9.3* 15.8* 1* 18.5* 1 18.5 ns
tPLH
CLR trigger
Q or Q
CL = 15 pF
10* 22.4* 1* 26* 1 26
ns
tPHL CLR trigger Q or Q CL = 15 pF 10.6* 22.4* 1* 26* 1 26 ns
tPLH
A or B
Q or Q
CL = 50 pF
10.5 24.1 1 27.5 1 27.5
ns
tPHL A or B Q or Q CL = 50 pF 11.8 24.1 1 27.5 1 27.5 ns
tPLH
CLR
Q or Q
CL = 50 pF
8.9 19.3 1 22 1 22
ns
tPHL CLR Q or Q CL = 50 pF 10.5 19.3 1 22 1 22 ns
tPLH
CLR trigger
Q or Q
CL = 50 pF
11 25.9 1 29.5 1 29.5
ns
tPHL CLR trigger Q or Q CL = 50 pF 12.3 25.9 1 29.5 1 29.5 ns
CL = 50 pF,
Cext = 28 pF,
Rext = 2 k182 240 300 300 ns
twQ or Q CL = 50 pF,
Cext = 0.01 µF,
Rext = 10 k90 100 110 90 110 90 110 ms
CL = 50 pF,
Cext = 0.1 µF,
Rext = 10 k0.9 1 1.1 0.9 1.1 0.9 1.1 ms
tw±1 %
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
tw = Pulse duration at Q and Q outputs
tw = Output pulse-duration variation (Q and Q) between circuits in same package
 
   
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TEST
TA = 25°C SN54AHC123A SN74AHC123A
UNIT
PARAMETER
FROM
(NPUT)
TO
(OUTPUT)
TEST
CONDITIONS MIN TYP MAX MIN MAX MIN MAX
UNIT
tPLH
A or B
Q or Q
CL = 15 pF
6.5* 12* 1* 14* 1 14
ns
tPHL A or B Q or Q CL = 15 pF 7.1* 12* 1* 14* 1 14 ns
tPLH
CLR
Q or Q
CL = 15 pF
5.3* 9.4* 1* 11* 111
ns
tPHL CLR Q or Q CL = 15 pF 6.5* 9.4* 1* 11* 111 ns
tPLH
CLR trigger
Q or Q
CL = 15 pF
6.9* 12.9* 1* 15* 1 15
ns
tPHL CLR trigger Q or Q CL = 15 pF 7.4* 12.9* 1* 15* 1 15 ns
tPLH
A or B
Q or Q
CL = 50 pF
7.3 14 1 16 1 16
ns
tPHL A or B Q or Q CL = 50 pF 8.3 14 1 16 1 16 ns
tPLH
CLR
Q or Q
CL = 50 pF
6.3 11.4 1 13 1 13
ns
tPHL CLR Q or Q CL = 50 pF 7.4 11.4 1 13 1 13 ns
tPLH
CLR trigger
Q or Q
CL = 50 pF
7.6 14.9 1 17 1 17
ns
tPHL CLR trigger Q or Q CL = 50 pF 8.7 14.9 1 17 1 17 ns
CL = 50 pF,
Cext = 28 pF,
Rext = 2 k167 200 240 240 ns
twQ or Q CL = 50 pF,
Cext = 0.01 µF,
Rext = 10 k90 100 110 90 110 90 110 ms
CL = 50 pF,
Cext = 0.1 µF,
Rext = 10 k0.9 1 1.1 0.9 1.1 0.9 1.1 ms
tw±1 %
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
tw = Pulse duration at Q and Q outputs
tw = Output pulse-duration variation (Q and Q) between circuits in same package
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 29 pF
 
   
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: ZO = 50 , tr +3 ns, tf + 3 ns.
C. The outputs are measured one at a time, with one input transition per measurement.
50% VCC
tPLH
tPHL
VOH
VOL
VCC
50% VCC
50% VCC
VCC
Input A
(see Note B) 50% VCC 0 V
0 V
In-Phase
Output
Out-of-Phase
Output
VOLTAGE WAVEFORMS
DELAY TIMES
Input B
(see Note B)
VOL
VOH
LOAD CIRCUIT
Test
Point
CL
(see Note A)
From Output
Under Test
50% VCC
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
Input CLR
(see Note B)
Out-of-Phase
Output
In-Phase
Output
VOLTAGE WAVEFORMS
DELAY TIMES
50% VCC
50% VCC
50% VCC 50% VCC
VCC
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Inputs or
Outputs 50% VCC
50% VCC
Figure 1. Load Circuit and Voltage Waveforms
 
   
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
caution in use
To prevent malfunctions due to noise, connect a high-frequency capacitor between VCC and GND, and keep
the wiring between the external components and Cext and Rext/Cext terminals as short as possible.
power-down considerations
Large values of Cext can cause problems when powering down the ’AHC123A devices because of the amount
of energy stored in the capacitor. When a system containing this device is powered down, the capacitor can
discharge from VCC through the protection diodes at pin 2 or pin 14. Current through the input protection diodes
must be limited to 30 mA; therefore, the turn-off time of the VCC power supply must not be faster than
t = VCC × Cext/30 mA. For example, if V CC = 5 V and Cext = 15 pF, the VCC supply must turn off no faster than
t = (5 V) × (15 pF)/30 mA = 2.5 ns. Usually, this is not a problem because power supplies are heavily filtered
and cannot discharge at this rate. When a more rapid decrease of VCC to zero occurs, the ’AHC123A devices
can sustain damage. To avoid this possibility, use external clamping diodes.
output pulse duration
The output pulse duration, tw, is determined primarily by the values of the external capacitance (CT) and timing
resistance (RT). The timing components are connected as shown in Figure 2.
VCC
RT
CT
To Rext/Cext
Terminal To Cext
Terminal
Figure 2. Timing-Component Connections
The pulse duration is given by:
tw+K RT CT
if CT is 1000 pF, K = 1.0 or
if CT is <1000 pF, K can be determined from Figure 9
where:
tw= pulse duration in ns
RT= external timing resistance in k
CT= external capacitance in pF
K = multiplier factor
Equation 1 and Figure 3 can be used to determine values for pulse duration, external resistance, and external
capacitance.
(1)
 
   
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
retriggering data
The minimum input retriggering time (tMIR) is the minimum time required after the initial signal before retriggering
the input. After tMIR, the device retriggers the output. Experimentally, it also can be shown that to retrigger the
output pulse, the two adjacent input signals should be tMIR apart, where tMIR = 0.30 × tw. The retrigger pulse
duration is calculated as shown in Figure 3.
tMIR
tRT
tPLH tw
Input
Output
tRT = tw + tPLH = (K × RT × CT) + tPLH
Where:
tMIR = Minimum Input Retriggering Time
tPLH = Propagation Delay
tRT = Retrigger Time
tw= Output Pulse Duration Before Retriggering
Figure 3. Retrigger Pulse Duration
The minimum value from the end of the input pulse to the beginning of the retriggered output should be
approximately 15 ns to ensure a retriggered output (see Figure 4).
Input
Output
tMRT= Minimum Time Between the End of the Second Input Pulse and the Beginning of the Retriggered Output
tMRT= 15 ns
tMRT
Figure 4. Input/Output Requirements
 
   
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
11010
2103104105106107
1.00E+00
1.00E+01
1.00E+02
1.00E+03
1.00E+04
1.00E+05
1.00E+06
1.00E+07
1.00E+08
1.00E+09
RT = 1k
RT = 5k
RT = 10k
RT = 80k
RT = 150k
RT = 200k
VCC = 5 V
TA = 25°C
Output Pulse Duration − ns
w
t
CT − External Timing Capacitance − pF
Figure 5. Output Pulse Duration vs External Timing Capacitance
tw = 866 ns at:
VCC = 5 V
RT = 10 k
CT = 50 pF
TA = 25°C
−60 −40 −20 0 20 40 60 80 100 120 140 160
VCC = 2.5 V
VCC = 3 V
VCC = 3.5 V
VCC = 4 V
VCC = 5 V
VCC = 6 V
VCC = 7 V
180
−6%
−4%
−2%
0%
2%
4%
6%
8%
10%
12%
14%
Temperature − °C
Variation in Output Pulse Duration
Figure 6. Variations in Output Pulse Duration vs Temperature
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
 
   
SCLS352H − JULY 1997 − REVISED OCTOBER 2005
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 7
MINIMUM TRIGGER TIME
vs
VCC CHARACTERISTICS
RT = 1 k
TA = 25°C
10.00
0
1.00
0.10
0.01 123456
CT = 0.01 µF
CT = 1000 pF
CT = 100 pF
VCC − Supply Voltage − V
Minimum Retrigger Timeµs
rr t
Figure 8
1.20
1.15
1.10
1.05
1.00
0.95
0.901.5 2 2.5 3 3.5 4 4.5 5 5.5 6
RT = 10 k
TA = 25°C
tW = K ×CT ×RT
VCC − Supply Voltage − V
OUTPUT PULSE-DURATION CONSTANT
vs
SUPPLY VOLTAGE
Output Pulse-Duration Constant − K
CT = 1000 pF
CT = 0.01 µF
CT = 0.1 µF
Figure 9
1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50
0.00001
0.0001
0.001
TA = 25°C
VCC = 5 V
For Capacitor Values of
0.001 µF or Greater,
K = 1.0
(K is Independent of R)
Multiplier Factor − K
EXTERNAL CAPACITANCE
vs
MULTIPLIER FACTOR
CT− External Capacitor Value − µF
Figure 10
tw − Output Pulse Duration
Relative Frequency of Occurance
DISTRIBUTION OF UNITS
vs
OUTPUT PULSE DURATION
Mean = 856 ns
Median = 856 ns
Std. Dev. = 3.5 ns
VCC = 5 V
TA = 25°C
CT = 50 pF
RT = 10 kW
−3 Std. Dev. +3 Std. Dev.
Median
99% of Data Units
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-9860801Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9860801QEA ACTIVE CDIP J 16 1 TBD Call TI Call TI
5962-9860801QFA ACTIVE CFP W 16 1 TBD Call TI Call TI
SN74AHC123AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC123ADBR ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC123ADBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC123ADBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC123ADE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC123ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC123ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC123ADGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC123ADGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC123ADR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC123ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC123ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC123AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74AHC123ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74AHC123APWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC123APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74AHC123APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SNJ54AHC123AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54AHC123AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SNJ54AHC123AW ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AHC123A, SN74AHC123A :
Catalog: SN74AHC123A
Enhanced Product: SN74AHC123A-EP
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 3
Military: SN54AHC123A
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Enhanced Product - Supports Defense, Aerospace and Medical Applications
Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AHC123ADBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74AHC123ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74AHC123ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74AHC123APWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
SN74AHC123APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AHC123APWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHC123ADBR SSOP DB 16 2000 367.0 367.0 38.0
SN74AHC123ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0
SN74AHC123ADR SOIC D 16 2500 333.2 345.9 28.6
SN74AHC123APWR TSSOP PW 16 2000 364.0 364.0 27.0
SN74AHC123APWR TSSOP PW 16 2000 367.0 367.0 35.0
SN74AHC123APWRG4 TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2