LT1765ES8 - Linear Technology - Datasheet.Directory

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

TYPICAL APPLICATION

DESCRIPTION

Monolithic 3A, 1.25MHz

Step-Down Switching Regulator

The LT

1765 is a 1.25MHz monolithic buck switching

regulator. A high efﬁ ciency 3A, 0.09Ω switch is included

on the die together with all the control circuitry required

to construct a high frequency, current mode switching

regulator. Current mode control provides fast transient

response and excellent loop stability.

New design techniques achieve high efﬁ ciency at high

switching frequencies over a wide operating voltage

range. A low dropout internal regulator maintains con-

sistent performance over a wide range of inputs from

24V systems to Li-Ion batteries. An operating supply

current of 1mA improves efﬁ ciency, especially at lower

output currents. Shutdown reduces quiescent current to

15μA. Maximum switch current remains constant at all

duty cycles. Synchronization allows an external logic level

signal to increase the internal oscillator into the range of

1.6MHz to 2MHz.

Full cycle-by-cycle current control and thermal shutdown

are provided. High frequency operation allows the reduc-

tion of input and output ﬁ ltering components and permits

the use of chip inductors.

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

*Patent Pending

5V to 3.3V Step-Down Converter

FEATURES

APPLICATIONS

n DSL Modems

n Portable Computers

n Regulated Wall Adapters

n Battery-Powered Systems

n Distributed Power

n 3A Switch in a Thermally Enhanced 16-Lead

TSSOP or 8-Lead SO Package

n Constant 1.25MHz Switching Frequency

n Wide Operating Voltage Range: 3V to 25V

n High Efﬁ ciency 0.09Ω Switch

n 1.2V Feedback Reference Voltage

n Uses Low Proﬁ le Surface Mount Components

n Low Shutdown Current: 15μA

n Synchronizable to 2MHz

n Current Mode Loop Control

n Constant Maximum Switch Current Rating at

All Duty Cycles*

n Available in 8-Lead SO and 16-Lead Thermally

Enhanced TSSOP Packages

BOOST

LT1765-3.3

VIN

OUTPUT

3.3V

2.5A

INPUT

1765 TA01

0.18μF

2.2nF UPS120

4.7μF

CERAMIC

2.2μF

CERAMIC

CMDSH-3

1.5μH

VSW

FBSHDN

ONOFF

GND VC

SYNC

Efﬁ ciency vs Load Current

SWITCH CURRENT (A)

EFFICIENCY (%)

2.0

1765 • TAO1a

70 0.5 1.0 1.5

90 VIN = 10V

VOUT = 5V

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

ABSOLUTE MAXIMUM RATINGS

Input Voltage ........................................................... 25V

BOOST Pin Above SW ............................................. 20V

Max BOOST Pin Voltage ............................................35V

SHDN Pin ................................................................. 25V

FB Pin Current ......................................................... 1mA

(Note 1)

FE PACKAGE

16-LEAD PLASTIC TSSOP

TOP VIEW

GND

BOOST

VIN

GND

SYNC

SHDN

GND

θJA = 45°C/W, θJC(PAD) = 10°C/W

EXPOSED PAD (PIN 17) SOLDERED TO LARGE COPPER PLANE

TOP VIEW

SYNC

SHDN

BOOST

VIN

GND

S8 PACKAGE

8-LEAD PLASTIC SO

TJMAX = 125°C, θJA = 90°C/W, θJC(PIN 4) = 30°C/W

GROUND PIN CONNECTED TO LARGE COPPER AREA

PIN CONFIGURATION

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LT1765EFE#PBF LT1765EFE#TRPBF 1765EFE 16-Lead Plastic TSSOP –40°C to 125°C

LT1765EFE-1.8#PBF LT1765EFE-1.8#TRPBF 1765EFE-1.8 16-Lead Plastic TSSOP –40°C to 125°C

LT1765EFE-2.5#PBF LT1765EFE-2.5#TRPBF 1765EFE-2.5 16-Lead Plastic TSSOP –40°C to 125°C

LT1765EFE-3.3#PBF LT1765EFE-3.3#TRPBF 1765EFE-3.3 16-Lead Plastic TSSOP –40°C to 125°C

LT1765EFE-5#PBF LT1765EFE-5#TRPBF 1765EFE-5 16-Lead Plastic TSSOP –40°C to 125°C

LT1765ES8#PBF LT1765ES8#TRPBF 1765 8-Lead Plastic SO –40°C to 125°C

LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LT1765EFE LT1765EFE#TR 1765EFE 16-Lead Plastic TSSOP –40°C to 125°C

LT1765EFE-1.8 LT1765EFE-1.8#TR 1765EFE-1.8 16-Lead Plastic TSSOP –40°C to 125°C

LT1765EFE-2.5 LT1765EFE-2.5#TR 1765EFE-2.5 16-Lead Plastic TSSOP –40°C to 125°C

LT1765EFE-3.3 LT1765EFE-3.3#TR 1765EFE-3.3 16-Lead Plastic TSSOP –40°C to 125°C

LT1765EFE-5 LT1765EFE-5#TR 1765EFE-5 16-Lead Plastic TSSOP –40°C to 125°C

LT1765ES8 LT1765ES8#TR 1765 8-Lead Plastic SO –40°C to 125°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

SYNC Pin Current ................................................... 1mA

Operating Junction Temperature Range

(Note 2) ................................................. –40°C to 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ................ 300°C

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LT1765E is guaranteed to meet performance speciﬁ cations

from 0°C to 125°C. Speciﬁ cations over the –40°C to 125°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Maximum Switch Current Limit 346 A

Oscillator Frequency 3.3V < VIN < 25V l1.1 1.25 1.6 MHz

Switch On Voltage Drop I = 3A l270 430 mV

VIN Undervoltage Lockout (Note 3) l2.47 2.6 2.73 V

VIN Supply Current l1 1.3 mA

Shutdown Supply Current VSHDN = 0V, VIN = 25V, VSW = 0V

15 35

μA

Feedback Voltage 3V < VIN < 25V, 0.4V < VC < 0.9V

(Note 3)

LT1765 (Adj)

1.182

1.176

1.2 1.218

1.224

LT1765-1.8 l1.764 1.8 1.836 V

LT1765-2.5 l2.45 2.5 2.55 V

LT1765-3.3 l3.234 3.3 3.366 V

LT1765-5 l4.9 5 5.1 V

FB Input Current LT1765 (Adj) l–0.25 –0.5 μA

FB Input Resistance LT1765-1.8

LT1765-2.5

LT1765-3.3

LT1765-5

10.5

14.7

27.5

kΩ

FB Error Amp Voltage Gain 0.4V < VC < 0.9V 150 350

FB Error Amp Transconductance ΔIVC = ±10μA l500 850 1300 μMho

VC Pin Source Current VFB = VNOM – 17% l80 120 160 μA

VC Pin Sink Current VFB = VNOM + 17% l70 110 180 μA

VC Pin to Switch Current Transconductance 5A/V

VC Pin Minimum Switching Threshold Duty Cycle = 0% 0.4 V

VC Pin 3A ISW Threshold 0.9 V

Maximum Switch Duty Cycle VC = 1.2V, ISW = 800mA, VIN = 6V

90 %

Minimum Boost Voltage Above Switch ISW = 3A l1.8 2.7 V

Boost Current ISW = 1A (Note 4)

ISW = 3A (Note 4)

140

SHDN Threshold Voltage l1.27 1.33 1.40 V

SHDN Threshold Current Hysteresis l4710 μA

SHDN Input Current (Shutting Down) SHDN = 60mV Above Threshold l–7 –10 –13 μA

SYNC Threshold Voltage 1.5 2.2 V

SYNC Input Frequency 1.6 2 MHz

SYNC Pin Resistance ISYNC = 1mA 20 kΩ

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

VIN = 15V, VC = 0.8V, Boost = VIN + 5V, SHDN, SYNC and switch open unless otherwise noted.

Note 3: Minimum input voltage is deﬁ ned as the voltage where the internal

regulator enters lockout. Actual minimum input voltage to maintain a

regulated output will depend on output voltage and load current. See

Applications Information.

Note 4: Current ﬂ ows into the BOOST pin only during the on period of the

switch cycle.

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

TYPICAL PERFORMANCE CHARACTERISTICS

TEMPERATURE (°C)

–50

FB VOLTAGE (V)

100

1765 G01

050

1.220

1.215

1.210

1.205

1.200

1.195

1.190

1.185

1.180

–25 25 75 125

SWITCH CURRENT (A)

350

300

250

200

150

100

1765 G02

SWITCH VOLTAGE (mV)

TA = 125°C

TA = –40°C

TA = 25°C

TEMPERATURE (°C)

–50 –25 0 25 50 75 100 125

FREQUENCY (MHz)

1765 G03

1.50

1.45

1.40

1.35

1.30

1.25

1.20

1.15

1.10

TEMPERATURE (°C)

–50 –25 0 25 50 75 100 125

SHDN THRESHOLD (V)

1765 G04

1.40

1.38

1.36

1.34

1.32

1.30

VIN (V)

0 5 10 15 20 25 30

VIN CURRENT (μA)

1765 G05

SHDN = 0V

VIN (V)

0 5 10 15 20 25 30

VIN CURRENT (μA)

1765 G05

SHDN = 0V

SHDN Threshold vs Temperature

SHDN Supply Current vs VIN SHDN IP Current vs Temperature

FB vs Temperature (Adj) Switch On Voltage Drop

Oscillator Frequency

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

TYPICAL PERFORMANCE CHARACTERISTICS

LOAD CURRENT (A)

0.001 0.01 0.1 1

INPUT VOLTAGE (V)

1765 G07

3.5

3.3

3.1

2.9

2.7

2.5

SHUTDOWN VOLTAGE (V)

00.2 0.4 0.6 0.8 1 1.2 1.4

VIN CURRENT (μA)

1765 G08

300

250

200

150

100

VIN = 15V

INPUT VOLTAGE (V)

0 5 10 15 20 25 30

VIN CURRENT (μA)

1765 G09

1200

1000

800

600

400

200

UNDERVOLTAGE

LOCKOUT

FEEDBACK VOLTAGE (V)

0 0.2 0.4 0.6 0.8 1 1.2

SWITCH PEAK CURRENT (A)

1765 G10

FB INPUT CURRENT (μA)

FB CURRENT

SWITCH CURRENT

1765 G11

INPUT VOLTAGE (V)

0 5 10 15 20 25

OUTPUT CURRENT (A)

3.0

2.8

2.6

2.4

2.2

2.0

L = 4.7μH

L = 2.2μH

L = 1.5μH

INPUT VOLTAGE (V)

0510 15 20 25

OUTPUT CURRENT (A)

1765 G12

3.0

2.8

2.6

2.4

2.2

L = 4.7μH

L = 2.2μH

L = 1.5μH

Current Limit Foldback

Maximum Load Current,

VOUT = 5V

Maximum Load Current,

VOUT = 2.5V

Minimum Input Voltage for

2.5V Out SHDN Supply Current

Input Supply Current

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

PIN FUNCTIONS

FB: The feedback pin is used to set output voltage using

an external voltage divider (adjustable version) that gener-

ates 1.2V at the pin when connected to the desired output

voltage. The ﬁ xed voltage 1.8V, 2.5V, 3.3V and 5V versions

have the divider network included internally and the FB pin

is connected directly to the output. If required, the current

limit can be reduced during start up or short-circuit when

the FB pin is below 0.5V (see the Current Limit Foldback

graph in the Typical Performance Characteristics section).

An impedance of less than 5kΩ on the adjustable version

at the FB pin is needed for this feature to operate.

BOOST: The BOOST pin is used to provide a drive voltage,

higher than the input voltage, to the internal bipolar NPN

power switch.

VIN: This is the collector of the on-chip power NPN switch.

This pin powers the internal circuitry and internal regulator.

At NPN switch on and off, high di/dt edges occur on this

pin. Keep the external bypass capacitor and catch diode

close to this pin. All trace inductance on this path will

create a voltage spike at switch off, adding to the VCE volt-

age across the internal NPN. Both VIN pins of the TSSOP

package must be shorted together on the PC board.

GND: The GND pin acts as the reference for the regulated

output, so load regulation will suffer if the “ground” end of

the load is not at the same voltage as the GND pin of the

IC. This condition will occur when load current or other

currents ﬂ ow through metal paths between the GND pin

and the load ground point. Keep the ground path short

between the GND pin and the load and use a ground plane

when possible. Keep the path between the input bypass

and the GND pin short. The exposed GND pad and/or GND

pins of the package are directly attached to the internal

tab. These pins/pad should be attached to a large copper

area to reduce thermal resistance.

VSW: The switch pin is the emitter of the on-chip power

NPN switch. This pin is driven up to the input pin voltage

during switch on time. Inductor current drives the switch

pin negative during switch off time. Negative voltage must

be clamped with an external catch diode with a VBR <0.8V.

Both VSW pins of the TSSOP package must be shorted

together on the PC board.

SYNC: The sync pin is used to synchronize the internal

oscillator to an external signal. It is directly logic compat-

ible and can be driven with any signal between 20% and

80% duty cycle. The synchronizing range is from 1.6MHz

to 2MHz. See Synchronization section in Applications

Information for details. When not in use, this pin should

be grounded.

SHDN: The shutdown pin is used to turn off the regula-

tor and to reduce input drain current to a few microam-

peres. The 1.33V threshold can function as an accurate

undervoltage lockout (UVLO), preventing the regulator

from operating until the input voltage has reached a pre-

determined level. Float or pull high to put the regulator in

the operating mode.

VC: The VC pin is the output of the error ampliﬁ er and the

input of the peak switch current comparator. It is normally

used for frequency compensation, but can do double duty

as a current clamp or control loop override. This pin sits

at about 0.4V for very light loads and 0.9V at maximum

load. It can be driven to ground to shut off the output.

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

BLOCK DIAGRAM

–

∑

INPUT

2.5V BIAS

REGULATOR

1.25MHz

OSCILLATOR

VSW

GND

1765 F01

SLOPE COMP

0.005Ω

INTERNAL

VCC

CURRENT

SENSE

AMPLIFIER

VOLTAGE GAIN = 40

SYNC

SHDN

SHUTDOWN

COMPARATOR

CURRENT

COMPARATOR

ERROR

AMPLIFIER

gm = 850μMho

BOOST

FLIP-FLOP

DRIVER

CIRCUITRY

0.4V

POWER

SWITCH

PARASITIC DIODES

DO NOT FORWARD BIAS

1.2V

–

1.33V

3μA

7μA

INTERNAL

VCC

The LT1765 is a constant frequency, current mode buck

converter. This means that there is an internal clock and

two feedback loops that control the duty cycle of the power

switch. In addition to the normal error ampliﬁ er, there is a

current sense ampliﬁ er that monitors switch current on a

cycle-by-cycle basis. A switch cycle starts with an oscillator

pulse which sets the RS ﬂ ip-ﬂ op to turn the switch on. When

switch current reaches a level set by the inverting input of

the comparator, the ﬂ ip-ﬂ op is reset and the switch turns

off. Output voltage control is obtained by using the output

of the error ampliﬁ er to set the switch current trip point.

This technique means that the error ampliﬁ er commands

current to be delivered to the output rather than voltage.

A voltage fed system will have low phase shift up to the

resonant frequency of the inductor and output capacitor,

then an abrupt 180° shift will occur. The current fed system

will have 90° phase shift at a much lower frequency, but

will not have the additional 90° shift until well beyond

the LC resonant frequency. This makes it much easier to

frequency compensate the feedback loop and also gives

much quicker transient response.

High switch efﬁ ciency is attained by using the BOOST pin

to provide a voltage to the switch driver which is higher

than the input voltage, allowing the switch to be saturated.

This boosted voltage is generated with an external capacitor

and diode. A comparator connected to the shutdown pin

disables the internal regulator, reducing supply current.

Figure 1. Block Diagram

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

Figure 2. Feedback Network

–

1.2V

VSW

VCGND

1765 F02

10k

OUTPUT

ERROR

AMPLIFIER

LT1765 (ADJ)

FB RESISTOR NETWORK

If an output voltage of 1.8V, 2.5V, 3.3V or 5V is required,

the respective ﬁ xed option part, -1.8, -2.5, -3.3 or -5,

should be used. The FB pin is tied directly to the output;

the necessary resistive divider is already included on

the part. For other voltage outputs, the adjustable part

should be used and an external resistor divider added.

The suggested resistor (R2) from FB to ground is 10k.

This reduces the contribution of FB input bias current to

output voltage to less than 0.25%. The formula for the

resistor (R1) from VOUT to FB is:

RRV

OUT

1212

12 2025

=μ

(–.)

.– (. )

APPLICATIONS INFORMATION APPLICATIONS INFORMATION

rating and turn-on surge problems. Y5V or similar type

ceramics can be used since the absolute value of capaci-

tance is less important and has no signiﬁ cant effect on

loop stability. If operation is required close to the minimum

input required by the output or the LT1765, a larger value

may be required. This is to prevent excessive ripple caus-

ing dips below the minimum operating voltage resulting

in erratic operation.

If tantalum capacitors are used, values in the 22μF to 470μF

range are generally needed to minimize ESR and meet

ripple current and surge ratings. Care should be taken to

ensure the ripple and surge ratings are not exceeded. The

AVX TPS and Kemet T495 series tantalum capacitors are

surge rated. AVX recommends derating capacitor operating

voltage by 2:1 for high surge applications.

OUTPUT CAPACITOR

Unlike the input capacitor, RMS ripple current in the output

capacitor is normally low enough that ripple current rating

is not an issue. The current waveform is triangular, with

an RMS value given by:

IVVV

LfV

RIPPLE RMS

OUT IN OUT

()

−

()

()()

(

029.

))

The LT1765 will operate with both ceramic and tantalum

output capacitors. Ceramic capacitors are generally cho-

sen for their small size, very low ESR (effective series

resistance), and good high frequency operation. Ceramic

output capacitors in the 1μF to 10μF range, X7R or X5R

type are recommended.

Tantalum capacitors are usually chosen for their bulk

capacitance properties, useful in high transient load ap-

plications. ESR rather than absolute value deﬁ nes output

ripple at 1.25MHz. Typical LT1765 applications require a

tantalum capacitor with less than 0.3Ω ESR at 22μF to

500μF, see Table 2. This ESR provides a useful zero in the

frequency response. Ceramic output capacitors with low

ESR usually require a larger VC capacitor or an additional

series R to compensate for this.

INPUT CAPACITOR

Step-down regulators draw current from the input supply

in pulses. The rise and fall times of these pulses are very

fast. The input capacitor is required to reduce the voltage

ripple at the input of LT1765 and to force the switching

current into a tight local loop, thereby minimizing EMI.

The RMS ripple current can be calculated from:

IIVVVV

RIPPLE RMS OUT OUT IN OUT IN

()

=−

()

Ceramic capacitors are ideal for input bypassing. At higher

switching frequency, the energy storage requirement of

the input capacitor is reduced so values in the range of

1μF to 4.7μF are suitable for most applications. Their high

frequency capacitive nature removes most ripple current

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

Table 2. Surface Mount Solid Tantalum Capacitor ESR

and Ripple Current

E Case Size ESR (Max, Ω) Ripple Current (A)

AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1

AVX TAJ 0.7 to 0.9 0.4

D Case Size

AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1

C Case Size

AVX TPS 0.2 (typ) 0.5 (typ)

Figure 3 shows a comparison of output ripple for a ceramic

and tantalum capacitor at 200mA ripple current.

APPLICATIONS INFORMATION

IOUT MAX

()

Continuous Mode

IVVV

LfV

OUT IN OUT

–()(– )

()()( )2

For VIN = 8V, VOUT = 5V and L = 3.3μH,

IOUT MAX() .• . •

=−

()

−

()

()()

(

−

3585

2 3 3 10 1 25 10 8

))

=− =3 0 23 2 77..A

Note that the worst case (minimum output current avail-

able) condition is at the maximum input voltage. For the

same circuit at 15V, maximum output current would be

only 2.6A.

Inductor Selection

The output inductor should have a saturation current rating

greater than the peak inductor current set by the current

comparator of the LT1765. The peak inductor current will

depend on the output current, input and output voltages

and the inductor value:

VVV

LfV

PEAK OUT OUT IN OUT

=+ −

()

()()

()

IN = Maximum input voltage

f = Switching frequency, 1.25MHz

If an inductor with a peak current lower than the maximum

switch current of the LT1765 is chosen a soft-start circuit

in Figure 10 should be used. Also, short-circuit conditions

should not be allowed because the inductor may saturate

resulting in excessive power dissipation.

Also, consideration should be given to the resistance

of the inductor. Inductor conduction loses are directly

proportional to the DC resistance of inductor. Sometime,

the manufacturers will also provide maximum current

rating based on the allowable losses in the inductor. Care

should be taken, however. At high input voltages and low

DCR, excessive switch current could ﬂ ow during shorted

output condition.

Suitable inductors are available from Coilcraft, Coiltronics,

Dale, Sumida, Toko, Murata, Panasonic and other

manufacturers.

Figure 3. Output Ripple Voltage Waveform

VSW

(5V/DIV)

VOUT USING 2.2μF

CERAMIC CAPACITOR

(10mV/DIV)

VOUT USING 47μF, 0.1Ω

TANTALUM CAPACITOR

(10mV/DIV)

0.2μs/DIV 1765 F03

INDUCTOR CHOICE AND MAXIMUM OUTPUT

CURRENT

Maximum output current for an LT1765 buck converter is

equal to the maximum switch rating (IP) minus one half

peak to peak inductor ripple current. The LT1765 main-

tains a constant switch current rating at all duty cycles.

(Patent Pending)

For most applications, the output inductor will be in the

1μH to 10μH range. Lower values are chosen to reduce

the physical size of the inductor, higher values allow higher

output currents due to reduced peak to peak ripple current.

The following formula gives maximum output current for

continuous mode operation, implying that the peak to peak

ripple (2x the term on the right) is less than the maximum

switch current.

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

APPLICATIONS INFORMATION APPLICATIONS INFORMATION

Table 3

PART NUMBER

VALUE

(μH)

IRMS

(Amps)

DCR

(Ω)

HEIGHT

(mm)

Coiltcraft

DO1608C-222 2.2 2.4 0.07 2.9

Sumida

CDRH3D16-1R5 1.5 1.6 0.043 1.8

CDRH4D18-1R0 1.0 1.7 0.035 2.0

CDC5D23-2R2 2.2 2.2 0.03 2.5

CR43-1R4 1.4 2.5 0.056 3.5

CDRH5D28-2R6 2.6 2.6 0.013 3.0

Toko

(D62F)847FY-2R4M 2.4 2.5 0.037 2.7

(D73LF)817FY-2R2M 2.2 2.7 0.03 3.0

CATCH DIODE

The diode D1 conducts current only during switch off

time. Peak reverse voltage is equal to regulator input

voltage. Average forward current in normal operation can

be calculated from:

IIVV

D AVG

OUT IN OUT

()

−

()

The only reason to consider a larger than 3A diode is the

worst-case condition of a high input voltage and shorted

output. With a shorted condition, diode current will increase to

a typical value of 4A, determined by peak switch current limit

of the LT1765. A higher forward voltage will also limit switch

current. This is safe for short periods of time, but it would be

prudent to check with the diode manufacturer if continuous

operation under these conditions must be tolerated.

BOOST PIN

For most applications, the boost components are a 0.18μF

capacitor and a CMDSH-3 diode. The anode is typically

connected to the regulated output voltage to generate a

voltage approximately VOUT above VIN to drive the output

stage. The output driver requires at least 2.7V of headroom

throughout the on period to keep the switch fully saturated.

However, the output stage discharges the boost capacitor

during this on time. If the output voltage is less than 3.3V,

it is recommended that an alternate boost supply is used.

The boost diode can be connected to the input, although,

care must be taken to prevent the 2x VIN boost voltage from

exceeding the BOOST pin absolute maximum rating. The

additional voltage across the switch driver also increases

power loss, reducing efﬁ ciency. If available, an independent

supply can be used with a local bypass capacitor.

A 0.18μF boost capacitor is recommended for most ap-

plications. Almost any type of ﬁ lm or ceramic capacitor

is suitable, but the ESR should be <1Ω to ensure it can

be fully recharged during the off time of the switch. The

capacitor value is derived from worst-case conditions of

700ns on-time, 90mA boost current, and 0.7V discharge

ripple. This value is then guard banded by 2x for secondary

factors such as capacitor tolerance, ESR and temperature

effects. The boost capacitor value could be reduced under

less demanding conditions, but this will not improve cir-

cuit operation or efﬁ ciency. Under low input voltage and

low load conditions, a higher value capacitor will reduce

discharge ripple and improve start up operation.

SHUTDOWN AND UNDERVOLTAGE LOCKOUT

Figure 4 shows how to add undervoltage lockout (UVLO)

to the LT1765. Typically, UVLO is used in situations where

the input supply is current limited, or has a relatively high

source resistance. A switching regulator draws constant

power from the source, so source current increases as

source voltage drops. This looks like a negative resistance

load to the source and can cause the source to current limit

or latch low under low source voltage conditions. UVLO

prevents the regulator from operating at source voltages

where these problems might occur.

Figure 4. Undervoltage Lockout

1.33V

GND

VSW

INPUT

1765 F04

OUTPUT

SHDN

VCC

LT1765

3μA

C1 +

7μA

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

APPLICATIONS INFORMATION

An internal comparator will force the part into shutdown

below the minimum VIN of 2.6V. This feature can be used

to prevent excessive discharge of battery-operated sys-

tems. If an adjustable UVLO threshold is required, the

shutdown pin can be used. The threshold voltage of the

shutdown pin comparator is 1.33V. A 3μA internal current

source defaults the open pin condition to be operating (see

Typical Performance Graphs). Current hysteresis is added

above the SHDN threshold. This can be used to set voltage

hysteresis of the UVLO using the following:

RVV

2133

133

=−

()

+μ

H – Turn-on threshold

L – Turn-off threshold

Example: switching should not start until the input is above

4.75V and is to stop if the input falls below 3.75V.

H = 4.75V

L = 3.75V

RVV

1475 375

7143

2133

475 133

143 3

49 4

=−

μ=

=−

()

+μ

.. .

Keep the connections from the resistors to the SHDN

pin short and make sure that the interplane or surface

capacitance to the switching nodes are minimized. If high

resistor values are used, the SHDN pin should be bypassed

with a 1nF capacitor to prevent coupling problems from

the switch node.

SYNCHRONIZATION

The SYNC pin is used to synchronize the internal oscilla-

tor to an external signal. The SYNC input must pass from

a logic level low, through the maximum synchronization

threshold with a duty cycle between 20% and 80%. The

input can be driven directly from a logic level output. The

synchronizing range is equal to initial operating frequency

up to 2MHz. This means that minimum practical sync

frequency is equal to the worst-case high self-oscillating

frequency (1.6MHz), not the typical operating frequency

of 1.25MHz. Caution should be used when synchronizing

above 1.8MHz because at higher sync frequencies the

amplitude of the internal slope compensation used to

prevent subharmonic switching is reduced. This type of

subharmonic switching only occurs at input voltages less

than twice output voltage. Higher inductor values will tend

to eliminate this problem. See Frequency Compensation

section for a discussion of an entirely different cause of

subharmonic switching before assuming that the cause is

insufﬁ cient slope compensation. Application Note 19 has

more details on the theory of slope compensation.

LAYOUT CONSIDERATIONS

As with all high frequency switchers, when considering

layout, care must be taken in order to achieve optimal

electrical, thermal and noise performance. For maximum

efﬁ ciency, switch rise and fall times are typically in the

nanosecond range. To prevent noise both radiated and

conducted, the high speed switching current path, shown

in Figure 5, must be kept as short as possible. Shortening

this path will also reduce the parasitic trace inductance

of approximately 25nH/inch. At switch off, this parasitic

inductance produces a ﬂ yback spike across the LT1765

switch. When operating at higher currents and input volt-

ages, with poor layout, this spike can generate voltages

across the LT1765 that may exceed its absolute maximum

Figure 5. High Speed Switching Path

1765 F05

VIN

LT1765

D1 C1C3

VIN

HIGH

FREQUENCY

CIRCULATING

PATH

LOAD

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

APPLICATIONS INFORMATION APPLICATIONS INFORMATION

rating. A ground plane should always be used under the

switcher circuitry to prevent interplane coupling and

overall noise.

The VC and FB components should be kept as far away as

possible from the switch and boost nodes. The LT1765

pinout has been designed to aid in this. The ground for

these components should be separated from the switch

current path. Failure to do so will result in poor stability

or subharmonic like oscillation.

Board layout also has a signiﬁ cant effect on thermal

resistance. The exposed pad or GND pin is a continuous

copper plate that runs under the LT1765 die. This is the

best thermal path for heat out of the package as can be

seen by the low θJC of the exposed pad package. Reduc-

ing the thermal resistance from Pin 4 or exposed pad

onto the board will reduce die temperature and increase

the power capability of the LT1765. This is achieved by

providing as much copper area as possible around this

pin/pad. Also, having multiple solder ﬁ lled feedthroughs

to a continuous copper plane under LT1765 will help in

reducing thermal resistance. Ground plane is usually suit-

able for this purpose. In multilayer PCB designs, placing a

ground plane next to the layer with the LT1765 will reduce

thermal resistance to a minimum.

THERMAL CALCULATIONS

Power dissipation in the LT1765 chip comes from four

sources: switch DC loss, switch AC loss, boost circuit cur-

rent, and input quiescent current. The following formulas

show how to calculate each of these losses. These formulas

assume continuous mode operation, so they should not

be used for calculating efﬁ ciency at light load currents.

Switch loss:

PRI V

Vns I V f

SW SW OUT OUT

IN OUT IN

()( )

()()()

Boost current loss for VBOOST = VOUT:

PVI

BOOST OUT OUT

()

250/

Quiescent current loss:

QIN

()

0 001.

RSW = Switch resistance (≈0.13Ω at hot)

17ns = Equivalent switch current/voltage overlap time

f = Switch frequency

Figure 6. Typical Application and Layout (Topside Only Shown)

BOOST

LT1765-33

VIN

OUTPUT

3.3V

2.5A

INPUT

15V

1765 F06

0.18μF

2.2nF

B220A

4.7μF

CERAMIC

4.7μF

CERAMIC

CMDSH-3

2.7μH

VSW

FBSHDN

ONOFF

GND VC

SYNC

GND

KEEP FB AND VC

COMPONENTS AND

TRACES AWAY FROM

HIGH FREQUENCY,

HIGH INPUT

COMPONENTS

PLACE FEEDTHROUGHS

UNDER AND AROUND

GROUND PAD FOR

GOOD THERMAL

CONDUCTIVITY

1765 F6a

GND

MINIMIZE D1, C3

LT1765 LOOP

KELVIN

SENSE

VOUT

VIN

VOUT

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

APPLICATIONS INFORMATION

Example: with VIN = 10V, VOUT = 5V and IOUT = 2A:

BOOST

( )()()

()

()( )

()

=+ =

()( )

()

−

013 2 5

10 17 10 2 10 1 25 10

026 043 069

5250

10 01

10 0 001 0 01

.•.•

...

Total power dissipation, PTOT, is 0.69 + 0.1 + 0.01 = 0.8W.

Thermal resistance for the LT1765 16-lead TSSOP exposed

pad package is inﬂ uenced by the presence of internal or

backside planes. With a full plane under the package,

thermal resistance will be about 45°C/W. With no plane

under the package, thermal resistance will increase to

about 110°C/W. For the exposed pad package θJC(PAD) =

10°C/W. Thermal resistance is dominated by board perfor-

mance. To calculate die temperature, use the appropriate

thermal resistance number and add in worst-case ambient

temperature:

J = TA + θJA (PTOT)

When estimating ambient, remember the nearby catch

diode will also be dissipating power.

PVV V I

DIODE F IN OUT LOAD

()

−

()()

F = Forward voltage of diode (assume 0.5V at 2A)

DIODE =

()

−

()()

05 10 5 2

10 05

Notice that the catch diode’s forward voltage contributes

a signiﬁ cant loss in the overall system efﬁ ciency. A larger,

lower VF diode can improve efﬁ ciency by several percent.

Typical thermal resistance of the board θB is 35°C/W. At

an ambient temperature of 25°C,

J = TA + θJA(PTOT) + θB(PDIODE)

J = 25 + 45 (0.8) + 35 (0.5) = 79°C

DIE TEMPERATURE MEASUREMENT

If a true die temperature is required, a measurement of the

SYNC to GND pin resistance can be used. The SYNC pin

resistance across temperature must ﬁ rst be calibrated, with

no signiﬁ cant output load, in an oven. An initial value of

40k with a temperature coefﬁ cient of 0.16%/°C is typical.

The same measurement can then be used in operation to

indicate the die temperature.

FREQUENCY COMPENSATION

Before starting on the theoretical analysis of frequency

response, the following should be remembered—the worse

the board layout, the more difﬁ cult the circuit will be to

stabilize. This is true of almost all high frequency analog

circuits, read the ‘LAYOUT CONSIDERATIONS’ section ﬁ rst.

Common layout errors that appear as stability problems

are distant placement of input decoupling capacitor and/or

catch diode, and connecting the VC compensation to a

ground track carrying signiﬁ cant switch current. In addition,

the theoretical analysis considers only ﬁ rst order ideal

component behavior. For these reasons, it is important

that a ﬁ nal stability check is made with production layout

and components.

The LT1765 uses current mode control. This alleviates many

of the phase shift problems associated with the inductor.

The basic regulator loop is shown in Figure 7, with both

tantalum and ceramic capacitor equivalent circuits. The

LT1765 can be considered as two gm blocks, the error

ampliﬁ er and the power stage.

Figure 7. Model for Loop Response

–

1.2V

VSW

LT1765

GND

1765 F07

OUTPUT

ESR

500k

ERROR

AMPLIFIER

CURRENT MODE

POWER STAGE

gm = 5mho

gm =

850μmho

ESL

CERAMICTANTALUM

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

APPLICATIONS INFORMATION APPLICATIONS INFORMATION

Figure 8 shows the overall loop response with a 330pF VC

capacitor and a typical 100μF tantalum output capacitor.

The response is set by the following terms:

Error ampliﬁ er:

DC gain set by gm and RL = 850μ • 500k = 425.

Pole set by CF and RL = (2π • 500k • 330p)–1 = 965Hz.

Unity-gain set by CF and gm = (2π • 330p • 850μ–1)–1 =

410kHz.

Power stage:

DC gain set by gm and RL (assume 5Ω) = 5 • 5 = 25.

Pole set by COUT and RL = (2π • 100μ • 10)–1 = 159Hz.

Unity-gain set by COUT and gm = (2π • 100μ • 5–1)–1 =

8kHz.

Tantalum output capacitor:

Zero set by COUT and CESR = (2π • 100μ • 0.1)–1 = 15.9kHz.

The zero produced by the ESR of the tantalum output capaci-

tor is very useful in maintaining stability. Ceramic output

capacitors do not have a zero due to very low ESR, but are

dominated by their ESL. They form a notch in the 1MHz to

10MHz range. Without this zero, the VC pole must be made

dominant. A typical value of 2.2nF will achieve this.

If better transient response is required, a zero can be

added to the loop using a resistor (RC) in series with the

compensation capacitor. As the value of RC is increased,

transient response will generally improve, but two effects

limit its value. First, the combination of output capacitor

ESR and a large RC may stop loop gain rolling off altogether.

Second, if the loop gain is not rolled sufﬁ ciently at the

switching frequency, output ripple will perturb the VC pin

enough to cause unstable duty cycle switching similar

to subharmonic oscillation. This may not be apparent

at the output. Small signal analysis will not show this

since a continuous time system is assumed. If needed,

an additional capacitor (CF) can be added to the VC pin to

form a pole at typically one ﬁ fth the switching frequency

(If RC = ~ 5k, CF = ~ 100pF)

When checking loop stability, the circuit should be operated

over the application’s full voltage, current and temperature

range. Any transient loads should be applied and the output

voltage monitored for a well-damped behavior.

CONVERTER WITH BACKUP OUTPUT REGULATOR

In systems with a primary and backup supply, for example,

a battery powered device with a wall adapter input, the

output of the LT1765 can be held up by the backup supply

with its input disconnected. In this condition, the SW pin

will source current into the VIN pin. If the SHDN pin is held

at ground, only the shutdown current of 6μA will be pulled

via the SW pin from the second supply. With the SHDN pin

ﬂ oating, the LT1765 will consume its quiescent operating

current of 1mA. The VIN pin will also source current to

any other components connected to the input line. If this

load is greater than 10mA or the input could be shorted to

ground, a series Schottky diode must be added, as shown

in Figure 9. With these safeguards, the output can be held

at voltages up to the VIN absolute maximum rating.

BUCK CONVERTER WITH ADJUSTABLE SOFT-START

Large capacitive loads or high input voltages can cause

high input currents at start-up. Figure 10 shows a circuit

that limits the dv/dt of the output at start-up, controlling

the capacitor charge rate. The buck converter is a typical

conﬁ guration with the addition of R3, R4, CSS and Q1. As

the output starts to rise, Q1 turns on, regulating switch

current via the VC pin to maintain a constant dv/dt at the

output. Output rise time is controlled by the current through

CSS deﬁ ned by R4 and Q1’s VBE. Once the output is in

regulation, Q1 turns off and the circuit operates normally.

R3 is transient protection for the base of Q1.

Figure 8. Overall Loop Response

FREQUENCY (Hz)

GAIN (dB)

–20

–40

PHASE (DEG)

180

150

120

1765 F08

GAIN

PHASE

VOUT = 5V

COUT = 100μF, 0.1Ω

CC = 330pF

RC/CF = 0

ILOAD = 1A

10 1k 10k 1M100 100k

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

APPLICATIONS INFORMATION

Figure 10. Buck Converter with Adjustable Soft Start

BOOST

LT1765-5

VIN

OUTPUT

2.5A

INPUT

12V

1765 F10

0.18μF

100μF

CSS

15nF

330pF

2.2μF

CMDSH-3

5μH

VSW

SHDN

GND VC

SYNC

47k

D1: B220A

Q1: 2N3904

RiseTime RC V

SS OUT

=()( )( )

()

Using the values shown in Figure 10,

RiseTime ms==

(• )(• )()

–

47 10 15 10 5

07 5

The ramp is linear and rise times in the order of 100ms are

possible. Since the circuit is voltage controlled, the ramp

rate is unaffected by load characteristics and maximum

output current is unchanged. Variants of this circuit can

be used for sequencing multiple regulator outputs.

Dual Output Converter

The circuit in Figure 11 generates both positive and negative

5V outputs with a single piece of magnetics. The two induc-

tors shown are actually just two windings on a standard

B H Electronics inductor. The topology for the 5V output

is a standard buck converter. The –5V topology would be

a simple ﬂ yback winding coupled to the buck converter

if C4 were not present. C4 creates a SEPIC (single-ended

primary inductance converter) topology which improves

regulation and reduces ripple current in L1. Without C4,

the voltage swing on L1B compared to L1A would vary

due to relative loading and coupling losses. C4 provides a

low impedance path to maintain an equal voltage swing in

L1B, improving regulation. In a ﬂ yback converter, during

switch on time, all the converter’s energy is stored in L1A

only, since no current ﬂ ows in L1B. At switch off, energy

is transferred by magnetic coupling into L1B, powering

the –5V rail. C4 pulls L1B positive during switch on time,

causing current to ﬂ ow, and energy to build in L1B and

C4. At switch off, the energy stored in both L1B and C4

supply the –5V rail. This reduces the current in L1A and

changes L1B current waveform from square to triangular.

For details on this circuit, including maximum output cur-

rents, see Design Note 100

Figure 9. Dual Source Supply with 6μA Reverse Leakage

3.3V, 2A

* ONLY REQUIRED IF ADDITIONAL LOADS ON THE INPUT CAN SINK >10mA

REMOVABLE

INPUT

0.18μF

2.2nF

83k

B220A

1765 F09

2.2μF

MBRS330T3*

CMDSH-3

5μH

4.7μF

BOOST

LT1765-3.3

VIN VSW

FBSHDN

GND VC

SYNC

ALTERNATE

SUPPLY

28.5k

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

APPLICATIONS INFORMATION

Figure 11a. Dual Output Converter

OUTPUT

5V AT 1.5A

OUTPUT

–5V† AT 1.1A

* L1 IS A SINGLE CORE WITH TWO WINDINGS

COILTRONICS CTX5-1A

†

IF LOAD CAN GO TO ZERO, AN OPTIONAL

PRELOAD OF 1k TO 5k MAY BE USED TO

IMPROVE LOAD REGULATION

D1, D3: B220A

INPUT

12V

GND

1765 F11a

0.18μF

4700pF

3.3k D1

4.7μF

6.3V

CERAMIC

4.7mF

6.3V

CERAMIC

2.2μF

25V

CERAMIC

4.7μF

16V

CERAMIC

CMDSH-3

L1A*

L1B*

BOOST

LT1765-5

VIN VSW

FBSHDN

GND VC

SYNC

Figure 11b. Dual Output Converter (Output Currents)

5V LOAD CURRENT (mA)

10 100 1000 10000

MAX –5V LOAD (mA)

1765 F11b

1200

1000

800

600

400

200

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

APPLICATIONS INFORMATION

Figure 12. Positive-to-Negative Low Output Ripple Converter

1800pF

2.4k

100pF

OUTPUT

–5V AT 1A

L1: CDRH6D28-3R0

INPUT

1765 F12

0.22μF

B220A

10μF

6.3V X5R

CERAMIC

2.2μF

16V X5R

CERAMIC

CMDSH-3

3μH

B220A

BOOST

LT1765-5

VIN

22μF

VSW

SYNC

SHDN

GND VC

Figure 13. Negative Boost Converter

INPUT

–5V

L1: CDRH5D28-2R5

BOLD LINES INDICATE HIGH CURRENT PATHS

OUTPUT

–9V AT 1A

1765 F13

0.22μF

4700pF

6.8k

UPS120 C1

2.2μF

6.3V X5R

22μF

16V X5R

CERAMIC

CMDSH-3

2.5μH

BOOST

LT1765FE

VIN VSW

SYNC

SHDN

GND VC

10k

100pF

64.9k

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

PACKAGE DESCRIPTION

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation BB

FE16 (BB) TSSOP 0204

0.09 – 0.20

(.0035 – .0079)

0° – 8°

0.25

REF

0.50 – 0.75

(.020 – .030)

4.30 – 4.50*

(.169 – .177)

134

5678

10 9

4.90 – 5.10*

(.193 – .201)

16 1514 13 12 11

1.10

(.0433)

MAX

0.05 – 0.15

(.002 – .006)

0.65

(.0256)

BSC

2.94

(.116)

0.195 – 0.30

(.0077 – .0118)

TYP

RECOMMENDED SOLDER PAD LAYOUT

0.45 p0.05

0.65 BSC

4.50 p0.10

6.60 p0.10

1.05 p0.10

2.94

(.116)

3.58

(.141)

3.58

(.141)

MILLIMETERS

(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

6.40

(.252)

BSC

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

S8 Package

8-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610)

.016 – .050

(0.406 – 1.270)

.010 – .020

(0.254 – 0.508) × 45°

0°– 8° TYP

.008 – .010

(0.203 – 0.254)

SO8 0303

.053 – .069

(1.346 – 1.752)

.014 – .019

(0.355 – 0.483)

TYP

.004 – .010

(0.101 – 0.254)

.050

(1.270)

BSC

1234

.150 – .157

(3.810 – 3.988)

NOTE 3

8765

.189 – .197

(4.801 – 5.004)

NOTE 3

.228 – .244

(5.791 – 6.197)

.245

MIN .160 p.005

RECOMMENDED SOLDER PAD LAYOUT

.045 p.005

.050 BSC

.030 p.005

TYP

INCHES

(MILLIMETERS)

NOTE:

1. DIMENSIONS IN

2. DRAWING NOT TO SCALE

3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

LT1765/LT1765-1.8/LT1765-2.5/

LT1765-3.3/LT1765-5

1765fd

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0608 REV D • PRINTED IN USA

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LTC3407 Dual 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC

Converter

VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA,

ISD < 1μA, MS10E

LTC3412 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA,

ISD < 1μA, TSSOP16E

LTC3414 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter VIN: 2.3V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA,

ISD < 1μA, TSSOP20E

LT3430/LT3431 60V, 2.75A (IOUT), 200kHz/500kHz, High Efﬁ ciency Step-Down

DC/DC Converter

VIN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA,

ISD = 30μA, TSSOP16E

LT3433 60V, 400mA (IOUT), 200kHz, High Efﬁ ciency Step-Up/Step-Down

DC/DC Converter with Burst Mode Operation

VIN: 4V to 60V, VOUT(MIN) = 3.3V to 20V, IQ = 100μA,

ISD < 1μA, TSSOP16E

LTC3727/LTC3727-1 36V, 500kHz, High Efﬁ ciency Step-Down DC/DC Converter VIN: 4V to 36V, VOUT(MIN) = 0.8V, IQ = 670μA,

ISD < 20μA, QFN32, SSOP28

Burst Mode is a registered trademark of Linear Technology Corporation.