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Wh y is Ph y sic al
Synthesis
Necessary?
In the domain of deep submicron (DSM) and nanomet er ASIC technolo gies (180 nm and
below), the traditional separation between logical (synthesis) and physical (place and route )
design methods often causes a problem—designs cannot meet their realistic timing objectives;
creating the well known “timing closure prob lem.” Timing closure is now considered the biggest
area of difficulty for ASIC performanc e-oriented designs. The underl ying reaso n is that circuit
dela ys are dominated by net delays , which are influenced by the placement of the cells. The
traditional fanout-based wireload mod els, for estimating interconnect delay during synthesi s,
are considered inaccurate and are the key factor causing the lack of timing predictability
between post synthesis and post layout results. It is evident that synthesis and placeme nt
technologies must merge to cr eate properly placed and routa ble designs that meet realistic
perfor m ance goal s.
What is
Physical
Synthesis?
Ph ysical Synthesis refers to the ability of creating a properly placed-and-routed circuit from the
RTL code; a circuit that m eets the realistic perfor m ance goals of the design in one pass. In
cases where there are very aggressive performance goals or tight ph ysical constraints , a
second pass ma y be needed to achie ve the desired perf ormance goals. A properly placed-and-
routed des ign me ets the design rules of the target silic on te chnology and is routable by a
detailed router. The silicon technology determines the realistic performance goals of the
design.
What Does It Do
in an ASIC
Environment?
Physical Synthesis tools, such as Physical Compiler from Synopsys or PKS from Cadence
(Physically Knowledgeable Synthesis) replaces the typical Synthesis tools (such as Design
Compil e r fro m Syn o psys) that m any ASIC designers a re using today. Use rs typica lly start wi th
a design-planning tool such as the Synopsys Chip Architect or the Cadence LDP and decide
on:
• Physical area allocated to each synthesizable mod ule in the design
• Physical location of each synthesizable module
• Physical locations of RAM, ROM, hard IP, and other non-synthesizable bloc ks in the
design
• Pad (I/O) locations
The next step is to perf orm the top-lev el routing and the timing analysis, based on the chip-le vel
timing constraints. Based on the analysis result, users adjust the physical port location on
synthesiza ble modules, and adjust the location and orientation of non-synthesi zable blocks to
deriv e a realistic timing budget for each synthesizable module in the design.
At this point, all the necessary information is available fo r ever y synthes izable module in the
design so the user can proceed with the p hysical synthesis step. For each synthesizable
module, th e Physical Compiler ta kes in :
• RTL code
• Timing constraints that are derived from the design planning step
• Physical constraints (area, por t location s, etc.) that are derived from the design planning
step
• Synthesis and physical libraries
Ap pl ic a tio n N ot e: FP GAs
XAPP140 (v1.0) Februar y 26, 2001
Physi cal Synthe sis
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The Physic al Compiler produces a netlist and physi cal infor m ation (such as the proper
placement of all the cells) that meets the timing goal of the parti cular module. The next step is
to perfor m the detailed rout ing on the circuit a nd timing ana lysis to insure that the fu lly placed-
and-routed module meets its performance goal. Cadence and Av ant! are the only ED A vendors
that offer pro ven detailed routers that are trusted by major ASIC vendors (such as NEC, LSI, TI,
etc.)
Physical synthesis requires thousands of strategies to be eval uated by the software while the
circuit is being properly placed-and-routed and timed. Detailed routing takes a ver y long time
and it is not suitable during the synthesis process. Theref ore, f ollowing placement, the Physical
Compiler performs an estimated routing to assess the net delay and the impact on the module’s
timing objectives. It must also decide on the next synthesis strategy if the timing goal is n ot
being met. The single most important step is the correlation between routability analysis
(obtained from the congestion map) of the Physical Synthesis tool and the final detailed router .
Without such a correlation, the placement that is created by the Physical Synthesis tool may be
unusable by the detailed router, nullifying the result of th e Physical Synt hesis to ol.
What Are the
Pitfalls? Cost: Synopsys currently charges $200K f or a single l icense of its Physical Compiler . A design
planner or fl oorpla nner (such as the Synopsys Chi p Architect) is needed to create the
necessary inf ormation for the Physical Compiler and costs about $150K. The total cost of
setting up the Physical Syn thesis environment is about $350K .
Intero perability: The success of a physical synthesis tool is highly dependent on the routability
of the p laced circuits that it produces. If the Physical Synthesis vendor also pro vides a proven
detailed router, then there is high degree of certainty that placed circuit can be routed by the
vendor’s detailed router . Synopsys’ Ph ysic al Compil er is t he most s uccessful ph ys ical com piler
so far, but it relies on Cadence and Avant! detaile d routers to complete the phys ical
implementation of the design. Synopsys d oes not yet provide a proven detailed router. If
Cadence and A v ant! change the algorithms of t heir r outers the y may not work properly with the
Synopsys tools.
Layout Expertis e: The users require extensive training to becom e comfort able with physical
design concepts and this uses additional resource at additional cost.
How Does Xilinx
Addre ss th e
Timing Closure
Prob lem for
Virtex and
Spartan II
FPGAs?
Xilinx addresses the timing closure issue for Virtex™ and Spartan™-II architectures b y using a
three-step process of "Predict, Control and Improv e" t o implement designs that can meet their
realistic timing objectives with a minimum number of iterations.
Predict: I n the Xilinx FPGA architectures, the interconnect timing is less variable than an ASIC.
This characteristic makes it possib le to create interconnect models that are not based on
fano ut. The models can be used dur ing the synthesis proc ess to estimate the interconnect
timing with a high degree of pred ictability with respect to the placed and rout ed design. Xi linx
has par t nered with leading FP GA EDA vendors to offer synthesis tools that are aware of th e
Xilinx FP GA ar chit ec tural det ails. They use our accurat e interconnec t mo deling to produce
netlists with timing within 20% of placed-and-routed designs. The ne xt two steps close the
remaining performance gap.
Control: Guiding the Xilinx timing driven implementation tools with realistic timing constraints,
high quality netlists, and accurate physical constraint a re the keys to closing the performa nce
gap that may exist betwe en the synthe sized netlist and the placed and routed design. Xilinx
worked closely with Sy npl icity to develo p Amplify, a design planner and physical optimizat ion
tool f or FPGAs. Amplify can improve the netlist quality through physical optimization techniques
such as moving registers across physical boundaries to increase perfor mance. It can also
provi de accurate area constraints and critical path physical grouping to the Xilinx
imp lemen t a t ion tools. It is still po ssib le to have fa ilin g pa ths r emain in g a f te r t he pla c e- a nd -
route. T he next step address es the remaini ng failing path s.
Improve: Xilinx, in partnership with leading FPGA EDA vendors, has dev el oped a tight
interface between the synthe sis tools and the Xilinx implementation tools that allows re-
Physical Synthesis
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optimization of failing paths and ECO ing new circuits into th e Xilinx implementa tion tools. In a
major ity of cases this capability can enable tim ing closure in two passes.
Conclusion Physical Synth esis is ra pidly becom ing a requirement to close the timing gap for DSM (0.18µ
and below) ASIC designs. The key reason is inaccurate timing estimation during synthesis due
to unpredictable interconnect timing. Xilinx has successfully applied the three-step process of
"Predict, Control and Improv e" to close the timing f or Virtex and Spartan-II architectures (0.22µ
to 0.18µ). The key success factors are accurate timing estimation during synthesis, true timing
driven place-and-route, and re-optimization of failing paths. Proc ess technology continues to
shrink for upcoming Xilinx architectures enabli ng designers to implement more comple x and
higher performance designs. Xilinx will continue to provide the right solution to the timing
closure issue for future generations of FPGA architectures.
Revisi on
History The following table shows the revision histor y for this docum ent.
Date Version Revision
02/26/01 1.0 Initial Xilinx release.
