3
2
4
6
1
RSTSENSE
GND
RESET
HSENSE
VDD
TPS3806I33-Q1
DBV PACKAGE
(TOP VIEW)
LSENSE
5
VDD
LSENSE
HSENSE
RESET
RSTSENSE
GND
R4 R5
R1
R2
R3
3.6 V
Li-lon
Cell
TPS3806I33-Q1
Typical Operating Circuit
TPS3806I33-Q1
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SLVSBW8A MARCH 2013REVISED MARCH 2013
Dual Voltage Detector With Adjustable Hysteresis
Check for Samples: TPS3806I33-Q1
1FEATURES DESCRIPTION
Qualified for Automotive Applications The TPS3806I33-Q1 integrates two independent
AEC-Q100 Qualified With the Following voltage detectors for battery voltage monitoring.
Results: During power on, the device asserts RESET and
Device Temperature Grade 1: –40°C to RSTSENSE when supply voltage VDD or the voltage
125°C Ambient Operating Temperature at the LSENSE input becomes higher than 0.8 V.
Thereafter, the supervisory circuit monitors VDD and
Range LSENSE, keeping RESET and RSTSENSE active as
Device HBM ESD Classification Level H2 long as VDD and LSENSE remain below the threshold
Device CDM ESD Classification Level C4B voltage, VIT. As soon as VDD or LSENSE rises above
Dual Voltage Detector With Adjustable the threshold voltage VIT, the device deasserts
RESET or RSTSENSE, respectively. The
Hysteresis, 3.3-V Adjustable and 2-V TPS3806I33-Q1 device has a fixed-sense threshold
Adjustable voltage VIT set by an internal voltage divider at VDD
Assured Reset at VDD = 0.8 V and an adjustable second-LSENSE input. In addition,
Supply Current: 3 µA Typical at VDD = 3.3 V one can set an upper voltage threshold at HSENSE
to allow a wide adjustable
Independent Open-Drain Reset Outputs hysteresis window.
6-Pin SOT-23 Package The devices are available in a 6-pin SOT-23
package. Characterization of the TPS3806I33-Q1
APPLICATIONS device is for operation over a temperature range of
Voltage Supervisor –40°C to 125°C.
Voltage Detector
Battery Monitor
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS380 6 I 33 DBV R
Reel
Package
Nominal Supply Voltage
Nominal Threshold Voltage
Functionality
Family
TPS3806I33-Q1
SLVSBW8A MARCH 2013REVISED MARCH 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION(1)
TAPACKAGE QUANTITY PART NUMBER TOP-SIDE SYMBOL STATUS
–40°C to DBV (SOT-23) Reel of 3000 TPS3806I33QDBVRQ1 PZHQ Active
125°C
(1) For the most-current package and ordering information, see the Package Option Addendum located at the end of this data sheet or refer
to the TI Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
TPS3806I33-Q1 UNIT
Supply voltage, VDD (2) 7 V
All other pins(2) –0.3 to 7 V
Maximum low-output current, IOL 5 mA
Maximum high-output current, IOH –5 mA
Input clamp current, IIK (VI< 0 or VI> VDD) ±10 mA
Output clamp current, IOK (VO< 0 or VO> VDD) ±10 mA
Operating free-air temperature range, TA–40 to 125 °C
Storage temperature range, Tstg –65 to 150 °C
Human-body model (HBM) AEC-Q100 2 kV
Classification Level H2
Electrostatic discharge rating, ESD Charged-device model (CDM) AEC-Q100 750 V
Classification Level C4B
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND. For reliable operation, the device must not be continuously operated at 7 V for more than
t = 1000 h.
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SLVSBW8A MARCH 2013REVISED MARCH 2013
THERMAL INFORMATION TPS3806I33-Q1
THERMAL METRIC(1) DBV UNIT
6 PINS
θJA Junction-to-ambient thermal resistance(2) 188.9 °C/W
θJCtop Junction-to-case (top) thermal resistance(3) 130.9 °C/W
θJB Junction-to-board thermal resistance(4) 34.2 °C/W
ψJT Junction-to-top characterization parameter(5) 25.4 °C/W
ψJB Junction-to-board characterization parameter(6) 33.8 °C/W
θJCbot Junction-to-case (bottom) thermal resistance(7) N/A °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
Supply voltage, VDD 1.3 6 V
Input voltage, VI0 VDD + 0.3 V
Operating free-air temperature range, TA–40 125 °C
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD = 1.5 V, IOL = 1 mA
VOL Low-level output voltage VDD = 3.3 V, IOL = 2 mA 0.3 V
VDD = 6 V, IOL = 3 mA
Power-up reset voltage(1) VDD 0.8 V, IOL = 50 µA 0.2 V
LSENSE 1.198 1.207 1.216
TA= 25°C
TPS3806I33-Q1 2.978 3 3.022
LSENSE 1.188 1.207 1.226
Negative-going
VIT TA= 0°C to 70°C V
input threshold voltage(2) TPS3806I33-Q1 2.952 3 3.048
LSENSE 1.183 1.207 1.231
TA= –40°C to 125°C
TPS3806I33-Q1 2.94 3 3.06
1.2 V < VIT < 2.5 V 60
Vhys Hysteresis mV
2.5 V < VIT < 3.5 V 90
IIInput current LSENSE, HSENSE –25 25 nA
IOH High-level output current VDD = VIT + 0.2 V, VOH = VDD 300 nA
VDD = 3.3 V, output unconnected 3 5
IDD Supply current µA
VDD = 6 V, output unconnected 4 6
CiInput capacitance VI= 0 V to VDD 1 pF
(1) The lowest supply voltage at which RESET becomes active. tr,VDD 15 µs/V
(2) To ensure best stability of the threshold voltage, place a bypass capacitor (ceramic, 0.1 µF) near the supply terminals.
SWITCHING CHARACTERISTICS
at RL= 1 M, CL= 50 pF, TA= –40°C to 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD to RESET delay
Propagation (delay) time,
tPHL 5 100 µs
high-to-low-level output LSENSE to RSTSENSE delay VIH = 1.05 x VIT,
VIL = 0.95 x VIT
VDD to RESET delay
Propagation (delay) time,
tPLH 5 100 µs
low-to-high-level output HSENSE to RSTSENSE delay
TIMING REQUIREMENTS
at RL= 1 M, CL= 50 pF, TA= –40°C to 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
At VDD
twPulse duration VIH = 1.05 x VIT, VIL = 0.95 x VIT 5.5 µs
At SENSE
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VDD
VIT(HSENSE)
VIT(LSENSE)
VIT,VDD+Vhys
VIT(VDD)
0.8 V
RSTSENSE
RESET
= Undefined
TPS3806I33-Q1
www.ti.com
SLVSBW8A MARCH 2013REVISED MARCH 2013
Table 2. TERMINAL FUNCTIONS
TERMINAL I/O DESCRIPTION
NAME NO.
GND 2 I Ground
HSENSE 6 I Adjustable hysteresis input
LSENSE 5 I Adjustable sense input
RESET 3 O Active-low open-drain reset output (from VDD)
RSTSENSE 1 O Active-low open-drain reset output (from LSENSE)
VDD 4 I Input supply voltage and fixed sense input
FUNCTION AND TRUTH TABLE
TPS3806I33-Q1
VDD > VIT RESET LSENSE > VIT RSTSENSE
0 L 0 L
1 H 1 H
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V(HSENSE) +VrefǒR1 )R2 )R3
R3 Ǔ
V(LSENSE) +VrefǒR1 )R2 )R3
R2 )R3 Ǔ
_
+
_
+
R1
R2
Reference
Voltage of
1.207 V
RSTSENSE
RESET
LSENSE
HSENSE
VDD
GND
TPS3806
TPS3806I33-Q1
SLVSBW8A MARCH 2013REVISED MARCH 2013
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
Detailed Description
Operation
The TPS3806I33-Q1 monitors battery voltage and asserts RESET when a battery becomes discharged below a
certain threshold voltage. A comparator monitors the battery voltage via an external resistor divider. When the
voltage at the LSENSE input drops below the internal reference voltage, the RSTSENSE output pulls low. The
output remains low until the battery is replaced, or recharged above a second higher trip-point, set at HSENSE.
One can monitor a second voltage at VDD. The independent RESET output pulls low when the voltage at VDD
drops below the fixed threshold voltage. Because the TPS3806I33-Q1 outputs are open-drain MOSFETs, most
applications may require a pullup resistor.
Programming the Threshold Voltage Levels
Calculate the low-voltage threshold at LSENSE according to Equation 1:
(1)
where Vref = 1.207 V
Calculate the high-voltage threshold at HSENSE as shown in Equation 2:
(2)
where Vref = 1.207 V
To minimize battery current draw, TI recommends using 1 Mas the total resistor value R(tot), with
R(tot) = R1 + R2 + R3.
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Product Folder Links: TPS3806I33-Q1
0.35
0.30
0.25
0.20
0 1 2 3
0.40
0.45
0.50
0.15
0.10
0.05
0
OL
V− Low-Level Output Voltage − V
IOL − Low-Level Output Current − mA
85°C
0°C
25°C
−40°C
VDD = 1.5 V
V(SENSE) = Low
0.5 1.5 2.5
Expanded View
2
1.5
1
0.5
0 5 10 15 20 25 30
2.5
3
3.5
35 40 45 50
OL
V− Low-Level Output Voltage − V
IOL − Low-Level Output Current − mA
85°C
0°C
25°C
−40°C
VDD = 6 V
V(SENSE) = Low
0
3
2
1
00 0.5 1 1.5 2 2.5 3
4
5
6
3.5 4 4.5 5 5.5 6
DD
ISupply Current − Aµ
VDD − Supply Voltage − V
V(HSENSE) < V(LSENSE)
RESET = Open
RSTSENSE = Open
85°C
0°C
25°C
−40°C
TPS3806I33-Q1
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SLVSBW8A MARCH 2013REVISED MARCH 2013
TYPICAL CHARACTERISTICS
SUPPLY CURRENT LOW-LEVEL OUTPUT VOLTAGE
versus versus
SUPPLY VOLTAGE LOW-LEVEL OUTPUT CURRENT
Figure 1. Figure 2.
LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
versus versus
LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
Figure 3. Figure 4.
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: TPS3806I33-Q1
1
0.999
0.998
0.997
−40 −20 0 20
1.001
1.002
1.003
TA − Free-Air Temperature at VDD°C
0.996
0.995
RESET = 100 k to VDD1.004
1.005
40 60 80
VIT − Normalized Input Threshold Voltage VIT(TA) / VIT(25°C)
0.7
0.6
0.5
0.4
0 2 4 6 8 10 12
0.8
0.9
1
14 16 18 20
OL
V− Low-Level Output Voltage − V
IOL − Low-Level Output Current − mA
85°C
0°C
25°C
−40°C
VDD = 6 V
V(SENSE) = Low
0.3
0.2
0.1
0
Expanded View
TPS3806I33-Q1
SLVSBW8A MARCH 2013REVISED MARCH 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
LOW-LEVEL OUTPUT VOLTAGE NORMALIZED INPUT THRESHOLD VOLTAGE
versus versus
LOW-LEVEL OUTPUT CURRENT FREE-AIR TEMPERATURE AT VDD
Figure 5. Figure 6.
MINIMUM PULSE DURATION AT VDD MINIMUM PULSE DURATION AT LSENSE
versus versus
VDD THRESHOLD OVERDRIVE VOLTAGE LSENSE THRESHOLD OVERDRIVE VOLTAGE
Figure 7. Figure 8.
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PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
TPS3806I33QDBVRQ1 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PZHQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS3806I33-Q1 :
Catalog: TPS3806I33
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS3806I33QDBVRQ1 SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS3806I33QDBVRQ1 SOT-23 DBV 6 3000 180.0 180.0 18.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 2
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