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AD9152 Data Sheet
Rev. B | Page 56 of 103
Programmable Modulus DDS
The programmable modulus is a modification of the typical
accumulator-based DDS architecture (NCO). The frequency
ratio for the programmable modulus DDS is very similar to that
of the typical accumulator-based DDS. The only difference is
that N is not required to be a power of two for the programmable
modulus, but can be an arbitrary integer. In practice, hardware
constraints place limits on the range of values for N. As a result,
it extends the use of DDS to applications that require exact rational
frequency synthesis. The underlying function of the programmable
modulus technique is to alter the accumulator modulus.
Implementation of the programmable modulus function within
the AD9152 is such that the fraction, M/N, is expressible per the
equation below. Note that the form of the equation implies a
compound frequency tuning word with X representing the
integer part and A/B representing the fractional part.
where:
X is programmed in Register 0x114 to Register 0x119.
A is programmed in Register 0x158 to Register 0x15D.
B is programmed in Register 0x152 to Register 0x157.
Programmable Modulus Example
Consider the case in which fDAC = 250 MHz and the desired value of
fCARRIER is 25 MHz. This scenario synthesizes an output frequency
that is not a power of two submultiple of the sample rate, namely
fCARRIER = (1/10) fDAC, which is not possible with a typical accumula-
tor-based DDS. The frequency ratio, fCARRIER/fDAC, leads directly
to M and N, which are determined by reducing the fraction
(25,000,000/250,000,000) to its lowest terms. That is,
M/N = 25,000,000/250,000,000 = 1/10
Therefore, M = 1 and N = 10. After calculation, X = 429,496,729;
A = 3; and B = 5. Programming these values into the registers
causes the modulus DDS to produce an output frequency of
exactly 25 MHz, given a 250 MHz sampling clock. For more
details, see the AN-953 Application Note.
NCO ALIGNMENT
The NCO alignment block phase aligns the NCO output from
multiple converters. Two NCO alignment modes are supported
by the AD9152. The first is a SYSREF± alignment mode that
phase aligns the NCO outputs to the rising edge of a SYSREF±
pulse. The second alignment mode is a data key alignment;
when this mode is enabled, the AD9152 aligns the NCO outputs
when a user specified data pattern arrives at the DAC input.
SYSREF± NCO Alignment
As with the LMFC alignment, in Subclass 1, a SYSREF± pulse
phase aligns the NCO outputs of multiple devices in a system
and multiple channels on the same device. Note that in Subclass 0,
this alignment mode can be used to align the NCO outputs
within a device to an internal processing clock edge. No
SYSREF± edge is needed in Subclass 0, but multichip alignment
cannot be achieved. The steps to achieve a SYSREF± NCO
alignment are as follows:
1. Set NCO_ALIGN_MODE (Register 0x050, Bits[1:0] =
0b01) for SYSREF± NCO alignment mode.
2. Set NCO_ALIGN_ARM (Register 0x050, Bit 7) to 1.
3. Perform an LMFC alignment to force the NCO phase align
(see the Syncing LMFC Signals section). The phase
alignment occurs on the next SYSREF± edge.
Note that if in one shot sync mode, the LMFC alignment
block must be armed by setting Register 0x03A, Bit 6 = 1. If
in continuous mode or one shot then monitor mode, the
LMFC align block does not need to be armed; the NCO
align automatically trips on the next SYSREF± edge.
4. Check the alignment status. If NCO phase alignment was
successful, NCO_ALIGN_PASS (Register 0x050, Bit 4) = 1.
If phase alignment failed, NCO_ALIGN_FAIL
(Register 0x050, Bit 3) = 1.
Data Key NCO Alignment
In addition to supporting the SYSREF± alignment mode, the
AD9152 supports a mode in which the NCO phase alignment
occurs when a user-specified pattern is seen at the DAC input.
The steps to achieve a data key NCO alignment are as follows:
1. Set NCO_ALIGN_MODE (Register 0x050, Bits[1:0]) to 0b10.
2. Write the expected 16-bit data key for the I and Q datapath
into NCOKEYI[15:0] (Register 0x051 to Register 0x052) and
NCOKEYQ[15:0] (Register 0x053 to Register 0x054),
respectively.
3. Set NCO_ALIGN_ARM (Register 0x050, Bit 7) to 1.
4. Send the expected 16-bit I and Q data keys to the device to
achieve NCO alignment.
5. Check the alignment status. If the expected data key was
seen at the DAC input, NCO_ALIGN_MTCH
(Register 0x050, Bit 5) = 1. If NCO phase alignment was
successful, NCO_ALIGN_PASS (Register 0x050, Bit 4) = 1.
If phase alignment failed, NCO_ALIGN_FAIL
(Register 0x050, Bit 3) = 1.
Multiple device NCO alignment can be achieved with the data
key alignment mode. To achieve multichip NCO alignment,
program the same expected data key on all devices, arm all
devices, and then send the data key to all devices/channels at
the same time.
NCO Alignment IRQ
An IRQ event showing whether the NCO align was tripped is
available. Use Register 0x021, Bit 4 to enable the IRQ and then
use Register 0x025, Bit 4 to read back its status and reset the
IRQ signal. See the Interrupt Request Operation section for details.