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XILINX XC1700L Series High Density Serial Configuration PROMs including XQ1701L QPRO Series January 27, 1999 (Version 2.2) Product Specification Features * Serial Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices * Simple interface to the FPGA; requires only one user I/O pin * Cascadable for storing longer or multiple bitstreams * Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions * Supports XC4000EX/XL/XLA/XV fast configuration mode (15.0 MHz) * Low-power CMOS Floating Gate process * XC1704L, XC1702L, XC1701L, XQ1701L and the XC17512L are 3.3 V devices * XC1701 is a5 V device only * Available in compact plastic packages: 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44-pin PLCC or 44-pin VQFP. * QPRO parts available in 44-pin ceramic LCC and 20-pin SOIC. * Programming support by leading programmer manufacturers. * Design support using the Xilinx Alliance and Foundation series software packages. Vec Vpp GND Description The XC1704L, XC1702L, XC1701L, and the XC17512L are Xilinxs 3.3V series of high density serial configuration PROMs (SPROMs). Included within this family are the XC1701 (5V) and the XQ1701L (3.3V) SPROMs to provide an easy-to-use, cost-effective method for storing large Xil- inx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the SPROM. A short access time after the rising clock edge, data appears on the SPROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once contig- ured, it disables the SPROM. When the FPGA is in Slave Serial mode, the SPROM and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all SPROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or Foun- dation series development system compiles the FPGA design file into a standard Hex format, which is then trans- ferred to most commercial PROM programmers. [p> 0 CEL q RESET/L> ) = OE or , | 8 OE/ RESET . CLKID POH Address Counter VY EPROM Matrix > DATA X3185 Figure 1: Simplified Block Diagram (does not show programming circuit) January 27, 1999 (Version 2.2)XC1700L Series High Density Serial Configuration PROMs $= XILINX Pin Description DATA Data output, 3-stated when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low. CLK Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active. RESET/OE When High, this input holds the address counter reset and 3-states the DATA output. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the DATA output is 3-stated. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGAs INIT pin. The polarity of this pin is controlled in the programmer inter- face. This input pin is easily inverted using the Xilinx HW-130 Programmer. Third-party programmers have dif- ferent methods to invert this pin. CE When High, this pin disables the internal address counter, 3-states the DATA output, and forces the device into low-loc standby mode. CEO Chip Enable output, to be connected to the CE input of the next SPROM in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low. Vpp Programming voltage. No overshoot above the specified max voltage is permitted on this pin. For normal read oper- ation, this pin must be connected to Vec. Failure to do so may lead to unpredictable, temperature-dependent opera- tion and severe problems in circuit debugging. Do not leave VPP floating! Vec and GND Positive supply and ground pins. Serial PROM Pinouts Pin Name | Pin |20-Pin] 20-Pin | 44-Pin whee PDIP | SOIC | PLCC | VOFP | 4 oc DATA 1 1 2 40 2 CLK 2 3 4 43 5 RESET/OE 3 8 6 13 19 (OE/RESET) CE 4 10 8 15 21 GND 5 11 10 18&41|] 248&3 CEO 6 13 14 21 27 Vpp 7 18 17 35 44 Voc 8 20 20 38 44 Capacity Devices Configuration Bits XC1704L 4,194,304 XC1702L 2,097,152 XC1701L 1,048,576 XC1701 1,048,576 XC17512L 524,288 Xilinx FPGAs and Compatible SPROMs. Device Configuration Bits SPROM XC4010XL 283,424 X017512L XC4013XL/XLA 393,632 X017512L XC4020E 329,312 XC1701 XC4020XL/XLA 521,880 X017512L XC4025E 422,176 XC1701 XC4028XL/XLA 668,184 XC1701L XC4028EX 668,184 XC1701 XC4036EX 832,528 XC1701 XC4036XL/XLA 832,528 XC1701L XC4044XL/XLA 1,014,928 XC1701L XC4052XL/XLA 1,215,368 XC1702L XC4062XL/XLA 1,433,864 XC1702L XC4085XL/XLA 1,924,992 XC1702L XC40110XV 2,686,136 XC1704L XC40150XV 3,373,448 XC1704L XC40200XV 4,551,056 XC1704L + X017512L XC40250XV 5,433,888 XC1704L + XC1702L XCV50 559,232 XC1701L XCV100 781,248 XC1701L XCV150 1,041,128 XC1701L XCV200 1,335,872 XC1702L XCV300 1,751,840 XC1702L XCV400 2,546,080 XC1704L XCV600 3,608,000 XC1704L XCV800 4,715,648 XC1704L + XC1701L XCV1000 6,127,776 XC1704L + XC1702L January 27, 1999 (Version 2.2)$2 XILINX XC1700L Series High Density Serial Configuration PROMs Controlling Serial PROMs Connecting the FPGA device with the SPROM. * The DATA output(s) of the of the SPROM(s) drives the DIN input of the lead FPGA device. * The Master FPGA CCLK output drives the CLK input(s) of the SPROM(s). * The CEO output of a SPROM drives the CE input of the next SPROM in a daisy chain (if any). * The RESET/OE input of all SPROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the SPROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a Vcc glitch. Other methods such as driving RESET/OE from LDC or system reset assume the SPROM internal power-on-reset is always in step with the FPGAs internal power-on-reset. This may not be a safe assumption. __ * The SPROM CE input can be driven from either the LDC or DONE pins. Using LDC avoids potential contention on the DIN pin. * The CE input of the lead (or only) SPROM is driven by the DONE output of the lead FPGA device, provided that DONE is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum. FPGA Master Serial Mode Summary The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are estab- lished by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the con- figuration program from an external memory. The Xilinx SPROMs have been designed for compatibility with the Master Serial mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select pins are Low (MO0=0, M1=0, M2=0). Data is read from the SPROM sequentially on a single data line. Synchronization is provided by the rising edge of the tem- porary signal CCLK, which is generated during configura- tion. Master Serial Mode provides a simple configuration inter- face. Only a serial data line and two control lines are required to configure an FPGA. Data from the SPROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an on-chip default pull-up resistor. Programming the FPGA With Counters Unchanged Upon Completion When multiple FPGA-configurations for a single FPGA are stored in a SPROM, the OE pin should be tied Low. Upon power-up, the internal address counters are reset and con- figuration begins with the first program stored in memory. Since the OE pin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the FPGA with another program, the DONE line is pulled Low and configuration begins at the last value of the address counters. This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and then restarts a new configuration, as intended, but the Serial PROM does not reset its address counter, since it never saw a High level on its OE input. The new configura- tion, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the FPGA is the master, it issues the necessary number of CCLK pulses, up to 16 million (224) and DONE goes High. How- ever, the FPGA configuration will be completely wrong, with potential contentions inside the FPGA and on its output pins. This method must, therefore, never be used when there is any chance of external reset during configuration. Cascading Serial Configuration PROMs For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cas- caded SPROMs provide additional memory. After the last bit from the first SPROM is read, the next clock signal to the SPROM asserts its CEO output Low and disables its DATA line. The second SPROM recognizes the Low level on its CE input and enables its DATA output. See Figure 2. After configuration is complete, the address counters of all cascaded SPROMs are reset if the FPGA RESET pin goes Low, assuming the SPROM reset polarity option has been inverted. To reprogram the FPGA with another program, the DONE line goes Low and configuration begins where the address counters had stopped. In this case, avoid contention between DATA and the configured I/O use of DIN. January 27, 1999 (Version 2.2)XC1700L Series High Density Serial Configuration PROMs $= XILINX _ RESET9 DOouT FPGA MODES RESET OPTIONAL Daisy-chained FPGAs with - Different Configurations OPTIONAL Slave FPGAs with Identical Configurations Vec Vec Vpp DATA DIN CCLK| CLK DONE;/}-~ CE CE iNT SPROM CCLK (OUTPUT) DIN DOUT (OUTPUT) (Low Resets the Address Pointer) VS NS a. X x X bol CE I | DATA |! CLK Cascaded I Serial Memory SY X X X8256_01 Figure 2: Master Serial Mode. The one-time-programmable SPROM supports automatic loading of configuration programs. Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK cycle before the FPGA I/Os become active. 8-6 January 27, 1999 (Version 2.2)>: XILINX XC1700L Series High Density Serial Configuration PROMs Standby Mode Programming The PROM enters a low-power standby mode whenever The devices can be programmed on programmers supplied CE is asserted High. The output remains in a high imped- by Xilinx or qualified third-party vendors. The user must ance state regardless of the state of the OE input. ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device. Table 1: Truth Table for XC1700 Control Inputs Control Inputs Outputs Internal Address RESET CE DATA CEO lee Inactive Low if address < TC: increment active High active if address > TC: dont change 3-state Low reduced Active Low Held reset 3-state High active Inactive High Not changing 3-state High standby Active High Held reset 3-state High standby Notes: 1. The XC1700 RESET input has programmable polarity 2. TC = Terminal Count = highest address value. TC+1 = address 0. IMPORTANT: Always tie the Vpp pin to Voc in your application. Never leave Vpp floating. January 27, 1999 (Version 2.2) 8-7XC1700L Series High Density Serial Configuration PROMs 3 XILINX XC1701 Absolute Maximum Ratings Symbol Description Units Voc Supply voltage relative to GND -0.5 to +7.0 Vv Vpp Supply voltage relative to GND -0.5 to +12.5 Vv VIN Input voltage relative to GND -0.5 to Voc +0.5 Vv Vrs Voltage applied to 3-state output -0.5 to Voc +0.5 Vv Tsta Storage temperature (ambient) -65 to +150 C Tsoi Maximum soldering temperature (10 s @ 1/16 in.) +260 C Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol Description Min Max Units Voc Commercial Supply voltage relative to GND (Tag = 0C to +70C) 4.75 5.25 Vv Industrial Supply voltage relative to GND (Ta = -40C to +85C) 4.50 5.50 Vv Note: During normal read operation Vpp must be connect to Voc DC Characteristics Over Operating Condition Symbol Description Min Max Units Vin High-level input voltage 2.0 Veco ViL Low-level input voltage 0 0.8 Vv Vou High-level output voltage (loy = -4 MA) Commercial 3.86 Vv VoL Low-level output voltage (lop = +4 mA) 0.32 Vv Vou High-level output voltage (loy = -4 MA) Industrial 3.76 Vv VoL Low-level output voltage (Io, = +4 mA) 0.37 Vv loca Supply current, active mode (at maximum frequency) 10.0 mA locs Supply current, standby mode 100.0 HA IL Input or output leakage current -10.0 10.0 LA Cin Input Capacitance (Vij = GND, f = 1.0 MHZ) 10.0 pF Court Output Capacitance (Viy = GND, f = 1.0 MHZ) 10.0 pF 8-8 January 27, 1999 (Version 2.2)>: XILINX XC1700L Series High Density Serial Configuration PROMs XC1704L, XC1702L, XC1701L, XQI701L, & XC17512L Absolute Maximum Ratings Symbol Description Units Voc Supply voltage relative to GND -0.5 to +4.0 Vv Vpp Supply voltage relative to GND -0.5 to +12.5 Vv VIN Input voltage with respect to GND -0.5 to Voc +0.5 Vv Vrs Voltage applied to 3-state output -0.5 to Voc +0.5 Vv Tsta Storage temperature (ambient) -65 to +150 C Tsoi Maximum soldering temperature (10 s @ 1/16 in.) +260 C Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol Description Min Max Units Voc Commercial Supply voltage relative to GND (Tag = 0C to +70C) 3.0 3.6 Vv Industrial Supply voltage relative to GND (Ta = -40C to +85C) 3.0 3.6 Vv Supply voltage relative to GND 3.0 3.6 Vv Ceramic Package (Tc = -55C to +125C) Military Supply voltage relative to GND 3.0 3.6 Vv Plastic Package (Ty = -55C to +125C) Note: During normal read operation Vpp must be connected to Voc DC Characteristics Over Operating Condition Symbol Description Min Max Units Vin High-level input voltage 2.0 Vec Vv ViL Low-level input voltage 0 0.8 Vv Vou High-level output voltage (loy = -3 MA) 2.4 Vv VoL Low-level output voltage (Io, = +3 mA) 0.4 Vv loca Supply current, active mode (at maximum frequency) 10.0 mA locs Supply current, standby mode Commercial/Industrial 50.0 HA Military 100.0 LA IL Input or output leakage current -10.0 10.0 LA Cin Input Capacitance (Vij = GND, f = 1.0 MHZ) 10.0 pF Court Output Capacitance (Vij = GND, f = 1.0 MHZ) 10.0 pF January 27, 1999 (Version 2.2) 8-9XC1700L Series High Density Serial Configuration PROMs 3 XILINX AC Characteristics Over Operating Condition CE \ RESET/OE CLK DATA X2634 XC1704L, XC1702L, XC1701 XC1701L, Symbol Description XQ1701L & Units XC17512L Min Max Min Max 1 Toe OE to Data Delay 25 30 ns 2 Tce CE to Data Delay 45 45 ns 3 Teac CLK to Data Delay 45 45 ns 4 Tou Data Hold From CE, OE, or CLK 0 0 ns 5 Tor CE or OE to Data Float Delay? 50 50 ns 6 Teyc Clock Periods 67 67 ns 7 Tie CLK Low Time? 20 25 ns 8 THC CLK High Time? 20 25 ns 9 TSCE CE Setup Time to CLK (to guarantee proper counting) 20 25 ns 10 |Tuce CE Hold Time to CLK (to guarantee proper counting) 0 0 ns 11 |TyoE OE Hold Time (guarantees counters are reset) 20 25 ns Notes: 1. AC test load = 50 pF 2. Float delays are measured with 5 pF AC loads. Transition is measured at +/- 200mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with V)|, = 0.0 V and Vj = 3.0 V. 8-10 January 27, 1999 (Version 2.2)>: XILINX XC1700L Series High Density Serial Configuration PROMs AC Characteristics Over Operating Condition When Cascading RESET/OE fo \ CE # \ CLK / \ + (Toor L ; / oe a DATA x Last Bit + \ First Bit (Tock >| > (Toor CEO (Toce > > (9 Toce xate3 Symbol Description Min Max Units 12 |Tepr CLK to Data Float Delay? ? 50 ns 13. | Tock CLK to CEO Delay? 30 ns 14 |Toce CE to CEO Delay 35 ns 15 |Tooe RESET/OE to CEO Delay? 30 ns Notes: 1. AC test load = 50 pF 2. Float delays are measured with 5 pF AC loads. Transition is measured at +/- 200mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with V)|, = 0.0 V and Vj = 3.0 V. January 27, 1999 (Version 2.2) 8-11XC1700L Series High Density Serial Configuration PROMs $= XILINX Ordering Information XC 1701L PC20 Device Type =__ _ XC Commercial XQ QPRO Operating Range/Processing C = Commercial (T, = 0 to +70C) Device Number_! Package Type | = Industrial (Ta =40 to +85C) 1704L PD8 = 8-Pin Plastic DIP Ne UU ete eg 1702L $020 = 20-Pin Plastic Small-Outline Package Mee, (To = a eee 1701L PC20 = 20-Pin Plastic Leaded Chip Carrier = OMI & (s dt MIL-PRE aedas 1701 VQ44 = 44-Pin Plastic Quad Flat Package centile to WET 17512L PC44 = 44-Pin Plastic Chip Carrier CC44 = 44-Pin Ceramic Chip Carrier Valid Ordering Combinations XC1704LVQ44C XC1702LVQ44C XC1701LPD8C XC1701PD8C XC17512LPD8C XC1704LPC44C XC1702LPC44C XC1701LSO20C XC1701SO20C XC17512LSO20C XC1701LPC20C XC1701PC20C XC17512LPC20C XC1704LVQ44I XC1702LVQ44I XC1701LPD8I XC1701PD8I XC17512LPD8! XC1704LPC441 XC1702LPC44I XC1701LSO201 XC1701S0201 XC17512LS0201 XC1701PC201 XC1701PC201 XC17512LPC201 XQ1701LCC44M XQ1701LCC44B XQ1701LS020N Marking Information Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. The XQ CC44 packages are marked as ordered. Device marking on the commercial and military plastic packages is as follows: 1701L JC Device Number | | Operating Range/Processing XC1704L C = Commercial (T, = 0 to +70C) XC1702L Package Type | = Industrial (T, = 40 to +85C) XC1701L P = 8-Pin Plastic DIP N = Military Plastic (Ty = 55 to +125C) XQ1701L S = 20-Pin Plastic Small-Outline Package M = Military (Te =55 to +125C) XC1701 J = 20-Pin Plastic Leaded Chip Carrier B = Military (To = 55 to +125C) XC017512L VQ44 = 44-Pin Plastic Quad Flat Package QML certified to MIL-PRF-38535 PC44 = 44-Pin Plastic Chip Carrier CC44 = 44-Pin Ceramic Chip Carrier 8-12 January 27, 1999 (Version 2.2)>: XILINX XC1700L Series High Density Serial Configuration PROMs Revision Control Date Revision 7/14/98 Major revisions to include the XC1704L, XC1702L, and the XQ1701L devices, packages and op- erating conditions. Also revised the timing specifications on page 16. 9/8/98 Revised the marking information on page 12 for the VQ44. Updated DC Characteristics Over Op- erating Condition on page &. and page 8. Added references to the XC4000XLA and XC4000XV families in Xilinx FPGAs and Gompatible SPROMs. on page 4. and Figure 2 on page 6. 12/18/98 Added Virtex FPGAs to Xilinx FPGAs and Cornpatible SPROMs. on page 4. Added the PC44 package for the XC1702L & XC1704L products. 1/27/99 Changed Military Iecg on page 3. January 27, 1999 (Version 2.2) 8-13